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asix-sigma: Squash yoda-condition in upload_firmware()
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CommitLineData
28a35d8a 1/*
50985c20 2 * This file is part of the libsigrok project.
28a35d8a 3 *
868501fa 4 * Copyright (C) 2010-2012 Håvard Espeland <gus@ping.uio.no>,
911f1834
UH
5 * Copyright (C) 2010 Martin Stensgård <mastensg@ping.uio.no>
6 * Copyright (C) 2010 Carl Henrik Lunde <chlunde@ping.uio.no>
28a35d8a
HE
7 *
8 * This program is free software: you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation, either version 3 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program. If not, see <http://www.gnu.org/licenses/>.
20 */
21
911f1834 22/*
6352d030 23 * ASIX SIGMA/SIGMA2 logic analyzer driver
911f1834
UH
24 */
25
3bbd9849
UH
26#include <glib.h>
27#include <glib/gstdio.h>
28a35d8a
HE
28#include <ftdi.h>
29#include <string.h>
45c59c8b
BV
30#include "libsigrok.h"
31#include "libsigrok-internal.h"
28a35d8a
HE
32#include "asix-sigma.h"
33
34#define USB_VENDOR 0xa600
35#define USB_PRODUCT 0xa000
36#define USB_DESCRIPTION "ASIX SIGMA"
37#define USB_VENDOR_NAME "ASIX"
38#define USB_MODEL_NAME "SIGMA"
c50277a6 39#define TRIGGER_TYPE "rf10"
28a35d8a 40
ed300b9f 41SR_PRIV struct sr_dev_driver asix_sigma_driver_info;
a873c594 42static struct sr_dev_driver *di = &asix_sigma_driver_info;
6078d2c9 43static int dev_acquisition_stop(struct sr_dev_inst *sdi, void *cb_data);
28a35d8a 44
b1648dea
MV
45/*
46 * The ASIX Sigma supports arbitrary integer frequency divider in
47 * the 50MHz mode. The divider is in range 1...256 , allowing for
48 * very precise sampling rate selection. This driver supports only
49 * a subset of the sampling rates.
50 */
2c9c0df8 51static const uint64_t samplerates[] = {
b1648dea
MV
52 SR_KHZ(200), /* div=250 */
53 SR_KHZ(250), /* div=200 */
54 SR_KHZ(500), /* div=100 */
55 SR_MHZ(1), /* div=50 */
56 SR_MHZ(5), /* div=10 */
57 SR_MHZ(10), /* div=5 */
58 SR_MHZ(25), /* div=2 */
59 SR_MHZ(50), /* div=1 */
60 SR_MHZ(100), /* Special FW needed */
61 SR_MHZ(200), /* Special FW needed */
28a35d8a
HE
62};
63
d261dbbf 64/*
ba7dd8bb 65 * Channel numbers seem to go from 1-16, according to this image:
d261dbbf
UH
66 * http://tools.asix.net/img/sigma_sigmacab_pins_720.jpg
67 * (the cable has two additional GND pins, and a TI and TO pin)
68 */
790c7ccc 69static const char *channel_names[] = {
78693401
UH
70 "1", "2", "3", "4", "5", "6", "7", "8",
71 "9", "10", "11", "12", "13", "14", "15", "16",
464d12c7
KS
72};
73
2c9c0df8 74static const int32_t hwcaps[] = {
1953564a
BV
75 SR_CONF_LOGIC_ANALYZER,
76 SR_CONF_SAMPLERATE,
38d32464 77 SR_CONF_TRIGGER_TYPE,
1953564a 78 SR_CONF_CAPTURE_RATIO,
1953564a 79 SR_CONF_LIMIT_MSEC,
6868626b 80 SR_CONF_LIMIT_SAMPLES,
28a35d8a
HE
81};
82
fefa1800
UH
83/* Initialize the logic analyzer mode. */
84static uint8_t logic_mode_start[] = {
85 0x00, 0x40, 0x0f, 0x25, 0x35, 0x40,
86 0x2a, 0x3a, 0x40, 0x03, 0x20, 0x38,
87};
88
499b17e9
MV
89static const char *sigma_firmware_files[] = {
90 /* 50 MHz, supports 8 bit fractions */
91 FIRMWARE_DIR "/asix-sigma-50.fw",
92 /* 100 MHz */
93 FIRMWARE_DIR "/asix-sigma-100.fw",
94 /* 200 MHz */
95 FIRMWARE_DIR "/asix-sigma-200.fw",
96 /* Synchronous clock from pin */
97 FIRMWARE_DIR "/asix-sigma-50sync.fw",
98 /* Frequency counter */
99 FIRMWARE_DIR "/asix-sigma-phasor.fw",
f6564c8d
HE
100};
101
0e1357e8 102static int sigma_read(void *buf, size_t size, struct dev_context *devc)
28a35d8a
HE
103{
104 int ret;
fefa1800 105
0e1357e8 106 ret = ftdi_read_data(&devc->ftdic, (unsigned char *)buf, size);
28a35d8a 107 if (ret < 0) {
47f4f073 108 sr_err("ftdi_read_data failed: %s",
0e1357e8 109 ftdi_get_error_string(&devc->ftdic));
28a35d8a
HE
110 }
111
112 return ret;
113}
114
0e1357e8 115static int sigma_write(void *buf, size_t size, struct dev_context *devc)
28a35d8a
HE
116{
117 int ret;
fefa1800 118
0e1357e8 119 ret = ftdi_write_data(&devc->ftdic, (unsigned char *)buf, size);
28a35d8a 120 if (ret < 0) {
47f4f073 121 sr_err("ftdi_write_data failed: %s",
0e1357e8 122 ftdi_get_error_string(&devc->ftdic));
fefa1800 123 } else if ((size_t) ret != size) {
47f4f073 124 sr_err("ftdi_write_data did not complete write.");
28a35d8a
HE
125 }
126
127 return ret;
128}
129
99965709 130static int sigma_write_register(uint8_t reg, uint8_t *data, size_t len,
0e1357e8 131 struct dev_context *devc)
28a35d8a
HE
132{
133 size_t i;
134 uint8_t buf[len + 2];
135 int idx = 0;
136
137 buf[idx++] = REG_ADDR_LOW | (reg & 0xf);
138 buf[idx++] = REG_ADDR_HIGH | (reg >> 4);
139
fefa1800 140 for (i = 0; i < len; ++i) {
28a35d8a
HE
141 buf[idx++] = REG_DATA_LOW | (data[i] & 0xf);
142 buf[idx++] = REG_DATA_HIGH_WRITE | (data[i] >> 4);
143 }
144
0e1357e8 145 return sigma_write(buf, idx, devc);
28a35d8a
HE
146}
147
0e1357e8 148static int sigma_set_register(uint8_t reg, uint8_t value, struct dev_context *devc)
28a35d8a 149{
0e1357e8 150 return sigma_write_register(reg, &value, 1, devc);
28a35d8a
HE
151}
152
99965709 153static int sigma_read_register(uint8_t reg, uint8_t *data, size_t len,
0e1357e8 154 struct dev_context *devc)
28a35d8a
HE
155{
156 uint8_t buf[3];
fefa1800 157
28a35d8a
HE
158 buf[0] = REG_ADDR_LOW | (reg & 0xf);
159 buf[1] = REG_ADDR_HIGH | (reg >> 4);
28a35d8a
HE
160 buf[2] = REG_READ_ADDR;
161
0e1357e8 162 sigma_write(buf, sizeof(buf), devc);
28a35d8a 163
0e1357e8 164 return sigma_read(data, len, devc);
28a35d8a
HE
165}
166
0e1357e8 167static uint8_t sigma_get_register(uint8_t reg, struct dev_context *devc)
28a35d8a
HE
168{
169 uint8_t value;
fefa1800 170
0e1357e8 171 if (1 != sigma_read_register(reg, &value, 1, devc)) {
47f4f073 172 sr_err("sigma_get_register: 1 byte expected");
28a35d8a
HE
173 return 0;
174 }
175
176 return value;
177}
178
99965709 179static int sigma_read_pos(uint32_t *stoppos, uint32_t *triggerpos,
0e1357e8 180 struct dev_context *devc)
28a35d8a
HE
181{
182 uint8_t buf[] = {
183 REG_ADDR_LOW | READ_TRIGGER_POS_LOW,
184
185 REG_READ_ADDR | NEXT_REG,
186 REG_READ_ADDR | NEXT_REG,
187 REG_READ_ADDR | NEXT_REG,
188 REG_READ_ADDR | NEXT_REG,
189 REG_READ_ADDR | NEXT_REG,
190 REG_READ_ADDR | NEXT_REG,
191 };
28a35d8a
HE
192 uint8_t result[6];
193
0e1357e8 194 sigma_write(buf, sizeof(buf), devc);
28a35d8a 195
0e1357e8 196 sigma_read(result, sizeof(result), devc);
28a35d8a
HE
197
198 *triggerpos = result[0] | (result[1] << 8) | (result[2] << 16);
199 *stoppos = result[3] | (result[4] << 8) | (result[5] << 16);
200
57bbf56b
HE
201 /* Not really sure why this must be done, but according to spec. */
202 if ((--*stoppos & 0x1ff) == 0x1ff)
203 stoppos -= 64;
204
205 if ((*--triggerpos & 0x1ff) == 0x1ff)
206 triggerpos -= 64;
207
28a35d8a
HE
208 return 1;
209}
210
99965709 211static int sigma_read_dram(uint16_t startchunk, size_t numchunks,
0e1357e8 212 uint8_t *data, struct dev_context *devc)
28a35d8a
HE
213{
214 size_t i;
215 uint8_t buf[4096];
216 int idx = 0;
217
fefa1800 218 /* Send the startchunk. Index start with 1. */
28a35d8a
HE
219 buf[0] = startchunk >> 8;
220 buf[1] = startchunk & 0xff;
0e1357e8 221 sigma_write_register(WRITE_MEMROW, buf, 2, devc);
28a35d8a 222
fefa1800 223 /* Read the DRAM. */
28a35d8a
HE
224 buf[idx++] = REG_DRAM_BLOCK;
225 buf[idx++] = REG_DRAM_WAIT_ACK;
226
227 for (i = 0; i < numchunks; ++i) {
fefa1800
UH
228 /* Alternate bit to copy from DRAM to cache. */
229 if (i != (numchunks - 1))
230 buf[idx++] = REG_DRAM_BLOCK | (((i + 1) % 2) << 4);
28a35d8a
HE
231
232 buf[idx++] = REG_DRAM_BLOCK_DATA | ((i % 2) << 4);
233
fefa1800 234 if (i != (numchunks - 1))
28a35d8a
HE
235 buf[idx++] = REG_DRAM_WAIT_ACK;
236 }
237
0e1357e8 238 sigma_write(buf, idx, devc);
28a35d8a 239
0e1357e8 240 return sigma_read(data, numchunks * CHUNK_SIZE, devc);
28a35d8a
HE
241}
242
4ae1f451 243/* Upload trigger look-up tables to Sigma. */
0e1357e8 244static int sigma_write_trigger_lut(struct triggerlut *lut, struct dev_context *devc)
ee492173
HE
245{
246 int i;
247 uint8_t tmp[2];
248 uint16_t bit;
249
250 /* Transpose the table and send to Sigma. */
251 for (i = 0; i < 16; ++i) {
252 bit = 1 << i;
253
254 tmp[0] = tmp[1] = 0;
255
256 if (lut->m2d[0] & bit)
257 tmp[0] |= 0x01;
258 if (lut->m2d[1] & bit)
259 tmp[0] |= 0x02;
260 if (lut->m2d[2] & bit)
261 tmp[0] |= 0x04;
262 if (lut->m2d[3] & bit)
263 tmp[0] |= 0x08;
264
265 if (lut->m3 & bit)
266 tmp[0] |= 0x10;
267 if (lut->m3s & bit)
268 tmp[0] |= 0x20;
269 if (lut->m4 & bit)
270 tmp[0] |= 0x40;
271
272 if (lut->m0d[0] & bit)
273 tmp[1] |= 0x01;
274 if (lut->m0d[1] & bit)
275 tmp[1] |= 0x02;
276 if (lut->m0d[2] & bit)
277 tmp[1] |= 0x04;
278 if (lut->m0d[3] & bit)
279 tmp[1] |= 0x08;
280
281 if (lut->m1d[0] & bit)
282 tmp[1] |= 0x10;
283 if (lut->m1d[1] & bit)
284 tmp[1] |= 0x20;
285 if (lut->m1d[2] & bit)
286 tmp[1] |= 0x40;
287 if (lut->m1d[3] & bit)
288 tmp[1] |= 0x80;
289
99965709 290 sigma_write_register(WRITE_TRIGGER_SELECT0, tmp, sizeof(tmp),
0e1357e8
BV
291 devc);
292 sigma_set_register(WRITE_TRIGGER_SELECT1, 0x30 | i, devc);
ee492173
HE
293 }
294
295 /* Send the parameters */
296 sigma_write_register(WRITE_TRIGGER_SELECT0, (uint8_t *) &lut->params,
0e1357e8 297 sizeof(lut->params), devc);
ee492173 298
e46b8fb1 299 return SR_OK;
ee492173
HE
300}
301
3678cf73 302static void clear_helper(void *priv)
0448d110 303{
0e1357e8 304 struct dev_context *devc;
ce4d26dd 305
3678cf73 306 devc = priv;
0e1357e8 307
3678cf73
UH
308 ftdi_deinit(&devc->ftdic);
309}
0448d110 310
3b412e3a 311static int dev_clear(void)
3678cf73
UH
312{
313 return std_dev_clear(di, clear_helper);
0448d110
BV
314}
315
6078d2c9 316static int init(struct sr_context *sr_ctx)
61136ea6 317{
f6beaac5 318 return std_init(sr_ctx, di, LOG_PREFIX);
61136ea6
BV
319}
320
6078d2c9 321static GSList *scan(GSList *options)
28a35d8a 322{
d68e2d1a 323 struct sr_dev_inst *sdi;
ba7dd8bb 324 struct sr_channel *ch;
0e1357e8
BV
325 struct drv_context *drvc;
326 struct dev_context *devc;
0448d110 327 GSList *devices;
e3fff420
HE
328 struct ftdi_device_list *devlist;
329 char serial_txt[10];
330 uint32_t serial;
790c7ccc
MV
331 int ret;
332 unsigned int i;
28a35d8a 333
0448d110 334 (void)options;
64d33dc2 335
a873c594 336 drvc = di->priv;
4b97c74e 337
0448d110 338 devices = NULL;
4b97c74e 339
0e1357e8 340 if (!(devc = g_try_malloc(sizeof(struct dev_context)))) {
47f4f073 341 sr_err("%s: devc malloc failed", __func__);
0448d110 342 return NULL;
b53738ba 343 }
99965709 344
0e1357e8 345 ftdi_init(&devc->ftdic);
28a35d8a 346
fefa1800 347 /* Look for SIGMAs. */
e3fff420 348
0e1357e8 349 if ((ret = ftdi_usb_find_all(&devc->ftdic, &devlist,
eec944c5
BV
350 USB_VENDOR, USB_PRODUCT)) <= 0) {
351 if (ret < 0)
352 sr_err("ftdi_usb_find_all(): %d", ret);
99965709 353 goto free;
eec944c5 354 }
99965709 355
e3fff420 356 /* Make sure it's a version 1 or 2 SIGMA. */
0e1357e8 357 ftdi_usb_get_strings(&devc->ftdic, devlist->dev, NULL, 0, NULL, 0,
6352d030 358 serial_txt, sizeof(serial_txt));
e3fff420
HE
359 sscanf(serial_txt, "%x", &serial);
360
6352d030 361 if (serial < 0xa6010000 || serial > 0xa602ffff) {
47f4f073
UH
362 sr_err("Only SIGMA and SIGMA2 are supported "
363 "in this version of libsigrok.");
e3fff420
HE
364 goto free;
365 }
366
367 sr_info("Found ASIX SIGMA - Serial: %s", serial_txt);
368
0e1357e8
BV
369 devc->cur_samplerate = 0;
370 devc->period_ps = 0;
371 devc->limit_msec = 0;
372 devc->cur_firmware = -1;
ba7dd8bb 373 devc->num_channels = 0;
0e1357e8
BV
374 devc->samples_per_event = 0;
375 devc->capture_ratio = 50;
376 devc->use_triggers = 0;
28a35d8a 377
fefa1800 378 /* Register SIGMA device. */
d68e2d1a 379 if (!(sdi = sr_dev_inst_new(0, SR_ST_INITIALIZING, USB_VENDOR_NAME,
55f98c65 380 USB_MODEL_NAME, NULL))) {
47f4f073 381 sr_err("%s: sdi was NULL", __func__);
99965709 382 goto free;
d68e2d1a 383 }
a873c594 384 sdi->driver = di;
87ca93c5 385
790c7ccc
MV
386 for (i = 0; i < ARRAY_SIZE(channel_names); i++) {
387 ch = sr_channel_new(i, SR_CHANNEL_LOGIC, TRUE,
388 channel_names[i]);
389 if (!ch)
87ca93c5 390 return NULL;
ba7dd8bb 391 sdi->channels = g_slist_append(sdi->channels, ch);
87ca93c5
BV
392 }
393
0448d110 394 devices = g_slist_append(devices, sdi);
0e1357e8
BV
395 drvc->instances = g_slist_append(drvc->instances, sdi);
396 sdi->priv = devc;
28a35d8a 397
fefa1800 398 /* We will open the device again when we need it. */
e3fff420 399 ftdi_list_free(&devlist);
28a35d8a 400
0448d110 401 return devices;
ea9cfed7 402
99965709 403free:
0e1357e8
BV
404 ftdi_deinit(&devc->ftdic);
405 g_free(devc);
0448d110 406 return NULL;
28a35d8a
HE
407}
408
6078d2c9 409static GSList *dev_list(void)
811deee4 410{
0e94d524 411 return ((struct drv_context *)(di->priv))->instances;
811deee4
BV
412}
413
d5fa188a
MV
414/*
415 * Configure the FPGA for bitbang mode.
416 * This sequence is documented in section 2. of the ASIX Sigma programming
417 * manual. This sequence is necessary to configure the FPGA in the Sigma
418 * into Bitbang mode, in which it can be programmed with the firmware.
419 */
420static int sigma_fpga_init_bitbang(struct dev_context *devc)
421{
422 uint8_t suicide[] = {
423 0x84, 0x84, 0x88, 0x84, 0x88, 0x84, 0x88, 0x84,
424 };
425 uint8_t init_array[] = {
426 0x01, 0x03, 0x03, 0x01, 0x01, 0x01, 0x01, 0x01,
427 0x01, 0x01,
428 };
429 int i, ret, timeout = 10000;
430 uint8_t data;
431
432 /* Section 2. part 1), do the FPGA suicide. */
433 sigma_write(suicide, sizeof(suicide), devc);
434 sigma_write(suicide, sizeof(suicide), devc);
435 sigma_write(suicide, sizeof(suicide), devc);
436 sigma_write(suicide, sizeof(suicide), devc);
437
438 /* Section 2. part 2), do pulse on D1. */
439 sigma_write(init_array, sizeof(init_array), devc);
440 ftdi_usb_purge_buffers(&devc->ftdic);
441
442 /* Wait until the FPGA asserts D6/INIT_B. */
443 for (i = 0; i < timeout; i++) {
444 ret = sigma_read(&data, 1, devc);
445 if (ret < 0)
446 return ret;
447 /* Test if pin D6 got asserted. */
448 if (data & (1 << 5))
449 return 0;
450 /* The D6 was not asserted yet, wait a bit. */
451 usleep(10000);
452 }
453
454 return SR_ERR_TIMEOUT;
455}
456
a80226bb
MV
457/*
458 * Read the firmware from a file and transform it into a series of bitbang
459 * pulses used to program the FPGA. Note that the *bb_cmd must be free()'d
460 * by the caller of this function.
461 */
462static int sigma_fw_2_bitbang(const char *filename,
463 uint8_t **bb_cmd, gsize *bb_cmd_size)
464{
465 GMappedFile *file;
466 GError *error;
467 gsize i, file_size, bb_size;
468 gchar *firmware;
469 uint8_t *bb_stream, *bbs;
470 uint32_t imm;
471 int bit, v;
472 int ret = SR_OK;
473
474 /*
475 * Map the file and make the mapped buffer writable.
476 * NOTE: Using writable=TRUE does _NOT_ mean that file that is mapped
477 * will be modified. It will not be modified until someone uses
478 * g_file_set_contents() on it.
479 */
480 error = NULL;
481 file = g_mapped_file_new(filename, TRUE, &error);
482 g_assert_no_error(error);
483
484 file_size = g_mapped_file_get_length(file);
485 firmware = g_mapped_file_get_contents(file);
486 g_assert(firmware);
487
488 /* Weird magic transformation below, I have no idea what it does. */
489 imm = 0x3f6df2ab;
490 for (i = 0; i < file_size; i++) {
491 imm = (imm + 0xa853753) % 177 + (imm * 0x8034052);
492 firmware[i] ^= imm & 0xff;
493 }
494
495 /*
496 * Now that the firmware is "transformed", we will transcribe the
497 * firmware blob into a sequence of toggles of the Dx wires. This
498 * sequence will be fed directly into the Sigma, which must be in
499 * the FPGA bitbang programming mode.
500 */
501
502 /* Each bit of firmware is transcribed as two toggles of Dx wires. */
503 bb_size = file_size * 8 * 2;
504 bb_stream = (uint8_t *)g_try_malloc(bb_size);
505 if (!bb_stream) {
506 sr_err("%s: Failed to allocate bitbang stream", __func__);
507 ret = SR_ERR_MALLOC;
508 goto exit;
509 }
510
511 bbs = bb_stream;
512 for (i = 0; i < file_size; i++) {
513 for (bit = 7; bit >= 0; bit--) {
514 v = (firmware[i] & (1 << bit)) ? 0x40 : 0x00;
515 *bbs++ = v | 0x01;
516 *bbs++ = v;
517 }
518 }
519
520 /* The transformation completed successfully, return the result. */
521 *bb_cmd = bb_stream;
522 *bb_cmd_size = bb_size;
523
524exit:
525 g_mapped_file_unref(file);
526 return ret;
527}
528
0e1357e8 529static int upload_firmware(int firmware_idx, struct dev_context *devc)
28a35d8a
HE
530{
531 int ret;
532 unsigned char *buf;
533 unsigned char pins;
534 size_t buf_size;
28a35d8a 535 unsigned char result[32];
499b17e9 536 const char *firmware = sigma_firmware_files[firmware_idx];
8bbf7627 537 struct ftdi_context *ftdic = &devc->ftdic;
28a35d8a 538
fefa1800 539 /* Make sure it's an ASIX SIGMA. */
8bbf7627
MV
540 ret = ftdi_usb_open_desc(ftdic, USB_VENDOR, USB_PRODUCT,
541 USB_DESCRIPTION, NULL);
542 if (ret < 0) {
47f4f073 543 sr_err("ftdi_usb_open failed: %s",
8bbf7627 544 ftdi_get_error_string(ftdic));
28a35d8a
HE
545 return 0;
546 }
547
8bbf7627
MV
548 ret = ftdi_set_bitmode(ftdic, 0xdf, BITMODE_BITBANG);
549 if (ret < 0) {
47f4f073 550 sr_err("ftdi_set_bitmode failed: %s",
8bbf7627 551 ftdi_get_error_string(ftdic));
28a35d8a
HE
552 return 0;
553 }
554
fefa1800 555 /* Four times the speed of sigmalogan - Works well. */
8bbf7627
MV
556 ret = ftdi_set_baudrate(ftdic, 750000);
557 if (ret < 0) {
47f4f073 558 sr_err("ftdi_set_baudrate failed: %s",
8bbf7627 559 ftdi_get_error_string(ftdic));
28a35d8a
HE
560 return 0;
561 }
562
d5fa188a
MV
563 /* Initialize the FPGA for firmware upload. */
564 ret = sigma_fpga_init_bitbang(devc);
565 if (ret)
566 return ret;
28a35d8a 567
9ddb2a12 568 /* Prepare firmware. */
d485d443 569 ret = sigma_fw_2_bitbang(firmware, &buf, &buf_size);
8bbf7627 570 if (ret != SR_OK) {
47f4f073 571 sr_err("An error occured while reading the firmware: %s",
499b17e9 572 firmware);
b53738ba 573 return ret;
28a35d8a
HE
574 }
575
fefa1800 576 /* Upload firmare. */
499b17e9 577 sr_info("Uploading firmware file '%s'.", firmware);
0e1357e8 578 sigma_write(buf, buf_size, devc);
28a35d8a
HE
579
580 g_free(buf);
581
8bbf7627
MV
582 ret = ftdi_set_bitmode(ftdic, 0x00, BITMODE_RESET);
583 if (ret < 0) {
47f4f073 584 sr_err("ftdi_set_bitmode failed: %s",
8bbf7627 585 ftdi_get_error_string(ftdic));
e46b8fb1 586 return SR_ERR;
28a35d8a
HE
587 }
588
8bbf7627 589 ftdi_usb_purge_buffers(ftdic);
28a35d8a 590
fefa1800 591 /* Discard garbage. */
29b66a2e 592 while (sigma_read(&pins, 1, devc) == 1)
28a35d8a
HE
593 ;
594
fefa1800 595 /* Initialize the logic analyzer mode. */
0e1357e8 596 sigma_write(logic_mode_start, sizeof(logic_mode_start), devc);
28a35d8a 597
fefa1800 598 /* Expect a 3 byte reply. */
0e1357e8 599 ret = sigma_read(result, 3, devc);
28a35d8a
HE
600 if (ret != 3 ||
601 result[0] != 0xa6 || result[1] != 0x55 || result[2] != 0xaa) {
47f4f073 602 sr_err("Configuration failed. Invalid reply received.");
e46b8fb1 603 return SR_ERR;
28a35d8a
HE
604 }
605
0e1357e8 606 devc->cur_firmware = firmware_idx;
f6564c8d 607
47f4f073 608 sr_info("Firmware uploaded.");
e3fff420 609
e46b8fb1 610 return SR_OK;
f6564c8d
HE
611}
612
6078d2c9 613static int dev_open(struct sr_dev_inst *sdi)
f6564c8d 614{
0e1357e8 615 struct dev_context *devc;
f6564c8d
HE
616 int ret;
617
0e1357e8 618 devc = sdi->priv;
99965709 619
9ddb2a12 620 /* Make sure it's an ASIX SIGMA. */
0e1357e8 621 if ((ret = ftdi_usb_open_desc(&devc->ftdic,
f6564c8d
HE
622 USB_VENDOR, USB_PRODUCT, USB_DESCRIPTION, NULL)) < 0) {
623
47f4f073 624 sr_err("ftdi_usb_open failed: %s",
0e1357e8 625 ftdi_get_error_string(&devc->ftdic));
f6564c8d
HE
626
627 return 0;
628 }
28a35d8a 629
5a2326a7 630 sdi->status = SR_ST_ACTIVE;
28a35d8a 631
e46b8fb1 632 return SR_OK;
f6564c8d
HE
633}
634
6f4b1868 635static int set_samplerate(const struct sr_dev_inst *sdi, uint64_t samplerate)
f6564c8d 636{
2c9c0df8
BV
637 struct dev_context *devc;
638 unsigned int i;
639 int ret;
f6564c8d 640
2c9c0df8 641 devc = sdi->priv;
f4abaa9f
UH
642 ret = SR_OK;
643
2c9c0df8
BV
644 for (i = 0; i < ARRAY_SIZE(samplerates); i++) {
645 if (samplerates[i] == samplerate)
f6564c8d
HE
646 break;
647 }
2c9c0df8 648 if (samplerates[i] == 0)
e46b8fb1 649 return SR_ERR_SAMPLERATE;
f6564c8d 650
59df0c77 651 if (samplerate <= SR_MHZ(50)) {
0e1357e8 652 ret = upload_firmware(0, devc);
ba7dd8bb 653 devc->num_channels = 16;
e8397563 654 }
59df0c77 655 if (samplerate == SR_MHZ(100)) {
0e1357e8 656 ret = upload_firmware(1, devc);
ba7dd8bb 657 devc->num_channels = 8;
f78898e9 658 }
59df0c77 659 else if (samplerate == SR_MHZ(200)) {
0e1357e8 660 ret = upload_firmware(2, devc);
ba7dd8bb 661 devc->num_channels = 4;
f78898e9 662 }
f6564c8d 663
0e1357e8 664 devc->cur_samplerate = samplerate;
5edc02c7 665 devc->period_ps = 1000000000000ULL / samplerate;
ba7dd8bb 666 devc->samples_per_event = 16 / devc->num_channels;
0e1357e8 667 devc->state.state = SIGMA_IDLE;
f6564c8d 668
e8397563 669 return ret;
28a35d8a
HE
670}
671
c53d793f
HE
672/*
673 * In 100 and 200 MHz mode, only a single pin rising/falling can be
674 * set as trigger. In other modes, two rising/falling triggers can be set,
ba7dd8bb 675 * in addition to value/mask trigger for any number of channels.
c53d793f
HE
676 *
677 * The Sigma supports complex triggers using boolean expressions, but this
678 * has not been implemented yet.
679 */
ba7dd8bb 680static int configure_channels(const struct sr_dev_inst *sdi)
57bbf56b 681{
0e1357e8 682 struct dev_context *devc = sdi->priv;
ba7dd8bb 683 const struct sr_channel *ch;
1b79df2f 684 const GSList *l;
57bbf56b 685 int trigger_set = 0;
ba7dd8bb 686 int channelbit;
57bbf56b 687
0e1357e8 688 memset(&devc->trigger, 0, sizeof(struct sigma_trigger));
eec5275e 689
ba7dd8bb
UH
690 for (l = sdi->channels; l; l = l->next) {
691 ch = (struct sr_channel *)l->data;
692 channelbit = 1 << (ch->index);
57bbf56b 693
ba7dd8bb 694 if (!ch->enabled || !ch->trigger)
57bbf56b
HE
695 continue;
696
0e1357e8 697 if (devc->cur_samplerate >= SR_MHZ(100)) {
c53d793f 698 /* Fast trigger support. */
ee492173 699 if (trigger_set) {
47f4f073
UH
700 sr_err("Only a single pin trigger in 100 and "
701 "200MHz mode is supported.");
e46b8fb1 702 return SR_ERR;
ee492173 703 }
ba7dd8bb
UH
704 if (ch->trigger[0] == 'f')
705 devc->trigger.fallingmask |= channelbit;
706 else if (ch->trigger[0] == 'r')
707 devc->trigger.risingmask |= channelbit;
ee492173 708 else {
47f4f073
UH
709 sr_err("Only rising/falling trigger in 100 "
710 "and 200MHz mode is supported.");
e46b8fb1 711 return SR_ERR;
ee492173 712 }
57bbf56b 713
c53d793f 714 ++trigger_set;
ee492173 715 } else {
c53d793f 716 /* Simple trigger support (event). */
ba7dd8bb
UH
717 if (ch->trigger[0] == '1') {
718 devc->trigger.simplevalue |= channelbit;
719 devc->trigger.simplemask |= channelbit;
c53d793f 720 }
ba7dd8bb
UH
721 else if (ch->trigger[0] == '0') {
722 devc->trigger.simplevalue &= ~channelbit;
723 devc->trigger.simplemask |= channelbit;
c53d793f 724 }
ba7dd8bb
UH
725 else if (ch->trigger[0] == 'f') {
726 devc->trigger.fallingmask |= channelbit;
c53d793f
HE
727 ++trigger_set;
728 }
ba7dd8bb
UH
729 else if (ch->trigger[0] == 'r') {
730 devc->trigger.risingmask |= channelbit;
c53d793f
HE
731 ++trigger_set;
732 }
ee492173 733
ea9cfed7
UH
734 /*
735 * Actually, Sigma supports 2 rising/falling triggers,
736 * but they are ORed and the current trigger syntax
737 * does not permit ORed triggers.
738 */
98b8cbc1 739 if (trigger_set > 1) {
47f4f073
UH
740 sr_err("Only 1 rising/falling trigger "
741 "is supported.");
e46b8fb1 742 return SR_ERR;
ee492173 743 }
ee492173 744 }
5b5ea7c6
HE
745
746 if (trigger_set)
0e1357e8 747 devc->use_triggers = 1;
57bbf56b
HE
748 }
749
e46b8fb1 750 return SR_OK;
57bbf56b
HE
751}
752
6078d2c9 753static int dev_close(struct sr_dev_inst *sdi)
28a35d8a 754{
0e1357e8 755 struct dev_context *devc;
28a35d8a 756
961009b0 757 devc = sdi->priv;
697785d1
UH
758
759 /* TODO */
760 if (sdi->status == SR_ST_ACTIVE)
0e1357e8 761 ftdi_usb_close(&devc->ftdic);
697785d1
UH
762
763 sdi->status = SR_ST_INACTIVE;
764
765 return SR_OK;
28a35d8a
HE
766}
767
6078d2c9 768static int cleanup(void)
28a35d8a 769{
3b412e3a 770 return dev_clear();
28a35d8a
HE
771}
772
8f996b89 773static int config_get(int id, GVariant **data, const struct sr_dev_inst *sdi,
53b4680f 774 const struct sr_channel_group *cg)
28a35d8a 775{
0e1357e8 776 struct dev_context *devc;
99965709 777
53b4680f 778 (void)cg;
8f996b89 779
035a1078 780 switch (id) {
123e1313 781 case SR_CONF_SAMPLERATE:
41479605 782 if (sdi) {
0e1357e8 783 devc = sdi->priv;
2c9c0df8 784 *data = g_variant_new_uint64(devc->cur_samplerate);
41479605
BV
785 } else
786 return SR_ERR;
28a35d8a 787 break;
d7bbecfd 788 default:
bd6fbf62 789 return SR_ERR_NA;
28a35d8a
HE
790 }
791
41479605 792 return SR_OK;
28a35d8a
HE
793}
794
8f996b89 795static int config_set(int id, GVariant *data, const struct sr_dev_inst *sdi,
53b4680f 796 const struct sr_channel_group *cg)
28a35d8a 797{
0e1357e8 798 struct dev_context *devc;
6868626b 799 uint64_t num_samples;
28a35d8a 800 int ret;
f6564c8d 801
53b4680f 802 (void)cg;
8f996b89 803
e73ffd42
BV
804 if (sdi->status != SR_ST_ACTIVE)
805 return SR_ERR_DEV_CLOSED;
806
0e1357e8 807 devc = sdi->priv;
99965709 808
6868626b
BV
809 switch (id) {
810 case SR_CONF_SAMPLERATE:
2c9c0df8 811 ret = set_samplerate(sdi, g_variant_get_uint64(data));
6868626b
BV
812 break;
813 case SR_CONF_LIMIT_MSEC:
2c9c0df8 814 devc->limit_msec = g_variant_get_uint64(data);
0e1357e8 815 if (devc->limit_msec > 0)
e46b8fb1 816 ret = SR_OK;
94ba4bd6 817 else
e46b8fb1 818 ret = SR_ERR;
6868626b
BV
819 break;
820 case SR_CONF_LIMIT_SAMPLES:
821 num_samples = g_variant_get_uint64(data);
822 devc->limit_msec = num_samples * 1000 / devc->cur_samplerate;
823 break;
824 case SR_CONF_CAPTURE_RATIO:
2c9c0df8 825 devc->capture_ratio = g_variant_get_uint64(data);
0e1357e8 826 if (devc->capture_ratio < 0 || devc->capture_ratio > 100)
e46b8fb1 827 ret = SR_ERR;
94ba4bd6 828 else
e46b8fb1 829 ret = SR_OK;
6868626b
BV
830 break;
831 default:
bd6fbf62 832 ret = SR_ERR_NA;
28a35d8a
HE
833 }
834
835 return ret;
836}
837
8f996b89 838static int config_list(int key, GVariant **data, const struct sr_dev_inst *sdi,
53b4680f 839 const struct sr_channel_group *cg)
a1c743fc 840{
2c9c0df8
BV
841 GVariant *gvar;
842 GVariantBuilder gvb;
a1c743fc
BV
843
844 (void)sdi;
53b4680f 845 (void)cg;
a1c743fc
BV
846
847 switch (key) {
9a6517d1 848 case SR_CONF_DEVICE_OPTIONS:
2c9c0df8
BV
849 *data = g_variant_new_fixed_array(G_VARIANT_TYPE_INT32,
850 hwcaps, ARRAY_SIZE(hwcaps), sizeof(int32_t));
9a6517d1 851 break;
a1c743fc 852 case SR_CONF_SAMPLERATE:
2c9c0df8
BV
853 g_variant_builder_init(&gvb, G_VARIANT_TYPE("a{sv}"));
854 gvar = g_variant_new_fixed_array(G_VARIANT_TYPE("t"), samplerates,
855 ARRAY_SIZE(samplerates), sizeof(uint64_t));
856 g_variant_builder_add(&gvb, "{sv}", "samplerates", gvar);
857 *data = g_variant_builder_end(&gvb);
a1c743fc 858 break;
c50277a6 859 case SR_CONF_TRIGGER_TYPE:
2c9c0df8 860 *data = g_variant_new_string(TRIGGER_TYPE);
c50277a6 861 break;
a1c743fc 862 default:
bd6fbf62 863 return SR_ERR_NA;
a1c743fc
BV
864 }
865
866 return SR_OK;
867}
868
36b1c8e6
HE
869/* Software trigger to determine exact trigger position. */
870static int get_trigger_offset(uint16_t *samples, uint16_t last_sample,
871 struct sigma_trigger *t)
872{
873 int i;
874
875 for (i = 0; i < 8; ++i) {
876 if (i > 0)
877 last_sample = samples[i-1];
878
879 /* Simple triggers. */
880 if ((samples[i] & t->simplemask) != t->simplevalue)
881 continue;
882
883 /* Rising edge. */
884 if ((last_sample & t->risingmask) != 0 || (samples[i] &
885 t->risingmask) != t->risingmask)
886 continue;
887
888 /* Falling edge. */
bdfc7a89
HE
889 if ((last_sample & t->fallingmask) != t->fallingmask ||
890 (samples[i] & t->fallingmask) != 0)
36b1c8e6
HE
891 continue;
892
893 break;
894 }
895
896 /* If we did not match, return original trigger pos. */
897 return i & 0x7;
898}
899
28a35d8a 900/*
fefa1800
UH
901 * Decode chunk of 1024 bytes, 64 clusters, 7 events per cluster.
902 * Each event is 20ns apart, and can contain multiple samples.
f78898e9
HE
903 *
904 * For 200 MHz, events contain 4 samples for each channel, spread 5 ns apart.
905 * For 100 MHz, events contain 2 samples for each channel, spread 10 ns apart.
906 * For 50 MHz and below, events contain one sample for each channel,
907 * spread 20 ns apart.
28a35d8a
HE
908 */
909static int decode_chunk_ts(uint8_t *buf, uint16_t *lastts,
88c51afe 910 uint16_t *lastsample, int triggerpos,
3cd3a20b 911 uint16_t limit_chunk, void *cb_data)
28a35d8a 912{
3cd3a20b 913 struct sr_dev_inst *sdi = cb_data;
0e1357e8 914 struct dev_context *devc = sdi->priv;
fefa1800 915 uint16_t tsdiff, ts;
0e1357e8 916 uint16_t samples[65536 * devc->samples_per_event];
b9c735a2 917 struct sr_datafeed_packet packet;
9c939c51 918 struct sr_datafeed_logic logic;
f78898e9 919 int i, j, k, l, numpad, tosend;
fefa1800 920 size_t n = 0, sent = 0;
0e1357e8 921 int clustersize = EVENTS_PER_CLUSTER * devc->samples_per_event;
fefa1800 922 uint16_t *event;
f78898e9 923 uint16_t cur_sample;
57bbf56b 924 int triggerts = -1;
ee492173 925
4ae1f451 926 /* Check if trigger is in this chunk. */
ee492173 927 if (triggerpos != -1) {
0e1357e8 928 if (devc->cur_samplerate <= SR_MHZ(50))
36b1c8e6 929 triggerpos -= EVENTS_PER_CLUSTER - 1;
ee492173
HE
930
931 if (triggerpos < 0)
932 triggerpos = 0;
57bbf56b 933
ee492173
HE
934 /* Find in which cluster the trigger occured. */
935 triggerts = triggerpos / 7;
936 }
28a35d8a 937
eec5275e 938 /* For each ts. */
28a35d8a 939 for (i = 0; i < 64; ++i) {
fefa1800 940 ts = *(uint16_t *) &buf[i * 16];
28a35d8a
HE
941 tsdiff = ts - *lastts;
942 *lastts = ts;
943
88c51afe
HE
944 /* Decode partial chunk. */
945 if (limit_chunk && ts > limit_chunk)
e46b8fb1 946 return SR_OK;
88c51afe 947
fefa1800 948 /* Pad last sample up to current point. */
0e1357e8 949 numpad = tsdiff * devc->samples_per_event - clustersize;
28a35d8a 950 if (numpad > 0) {
f78898e9
HE
951 for (j = 0; j < numpad; ++j)
952 samples[j] = *lastsample;
953
954 n = numpad;
28a35d8a
HE
955 }
956
57bbf56b
HE
957 /* Send samples between previous and this timestamp to sigrok. */
958 sent = 0;
959 while (sent < n) {
960 tosend = MIN(2048, n - sent);
961
5a2326a7 962 packet.type = SR_DF_LOGIC;
9c939c51
BV
963 packet.payload = &logic;
964 logic.length = tosend * sizeof(uint16_t);
965 logic.unitsize = 2;
966 logic.data = samples + sent;
3e9b7f9c 967 sr_session_send(devc->cb_data, &packet);
28a35d8a 968
57bbf56b
HE
969 sent += tosend;
970 }
971 n = 0;
972
973 event = (uint16_t *) &buf[i * 16 + 2];
f78898e9
HE
974 cur_sample = 0;
975
976 /* For each event in cluster. */
28a35d8a 977 for (j = 0; j < 7; ++j) {
f78898e9
HE
978
979 /* For each sample in event. */
0e1357e8 980 for (k = 0; k < devc->samples_per_event; ++k) {
f78898e9
HE
981 cur_sample = 0;
982
ba7dd8bb
UH
983 /* For each channel. */
984 for (l = 0; l < devc->num_channels; ++l)
edca2c5c 985 cur_sample |= (!!(event[j] & (1 << (l *
0e1357e8 986 devc->samples_per_event + k)))) << l;
f78898e9
HE
987
988 samples[n++] = cur_sample;
28a35d8a
HE
989 }
990 }
991
eec5275e 992 /* Send data up to trigger point (if triggered). */
fefa1800 993 sent = 0;
57bbf56b
HE
994 if (i == triggerts) {
995 /*
36b1c8e6
HE
996 * Trigger is not always accurate to sample because of
997 * pipeline delay. However, it always triggers before
998 * the actual event. We therefore look at the next
999 * samples to pinpoint the exact position of the trigger.
57bbf56b 1000 */
bdfc7a89 1001 tosend = get_trigger_offset(samples, *lastsample,
0e1357e8 1002 &devc->trigger);
57bbf56b
HE
1003
1004 if (tosend > 0) {
5a2326a7 1005 packet.type = SR_DF_LOGIC;
9c939c51
BV
1006 packet.payload = &logic;
1007 logic.length = tosend * sizeof(uint16_t);
1008 logic.unitsize = 2;
1009 logic.data = samples;
3e9b7f9c 1010 sr_session_send(devc->cb_data, &packet);
57bbf56b
HE
1011
1012 sent += tosend;
1013 }
28a35d8a 1014
5b5ea7c6 1015 /* Only send trigger if explicitly enabled. */
0e1357e8 1016 if (devc->use_triggers) {
5a2326a7 1017 packet.type = SR_DF_TRIGGER;
3e9b7f9c 1018 sr_session_send(devc->cb_data, &packet);
5b5ea7c6 1019 }
28a35d8a 1020 }
57bbf56b 1021
eec5275e 1022 /* Send rest of the chunk to sigrok. */
57bbf56b
HE
1023 tosend = n - sent;
1024
abda62ce 1025 if (tosend > 0) {
5a2326a7 1026 packet.type = SR_DF_LOGIC;
9c939c51
BV
1027 packet.payload = &logic;
1028 logic.length = tosend * sizeof(uint16_t);
1029 logic.unitsize = 2;
1030 logic.data = samples + sent;
3e9b7f9c 1031 sr_session_send(devc->cb_data, &packet);
abda62ce 1032 }
ee492173
HE
1033
1034 *lastsample = samples[n - 1];
28a35d8a
HE
1035 }
1036
e46b8fb1 1037 return SR_OK;
28a35d8a
HE
1038}
1039
6868626b 1040static void download_capture(struct sr_dev_inst *sdi)
28a35d8a 1041{
6868626b 1042 struct dev_context *devc;
28a35d8a
HE
1043 const int chunks_per_read = 32;
1044 unsigned char buf[chunks_per_read * CHUNK_SIZE];
6868626b
BV
1045 int bufsz, i, numchunks, newchunks;
1046
1047 sr_info("Downloading sample data.");
1048
1049 devc = sdi->priv;
1050 devc->state.chunks_downloaded = 0;
1051 numchunks = (devc->state.stoppos + 511) / 512;
1052 newchunks = MIN(chunks_per_read, numchunks - devc->state.chunks_downloaded);
1053
1054 bufsz = sigma_read_dram(devc->state.chunks_downloaded, newchunks, buf, devc);
1055 /* TODO: Check bufsz. For now, just avoid compiler warnings. */
1056 (void)bufsz;
1057
1058 /* Find first ts. */
1059 if (devc->state.chunks_downloaded == 0) {
1060 devc->state.lastts = RL16(buf) - 1;
1061 devc->state.lastsample = 0;
1062 }
1063
1064 /* Decode chunks and send them to sigrok. */
1065 for (i = 0; i < newchunks; ++i) {
1066 int limit_chunk = 0;
1067
1068 /* The last chunk may potentially be only in part. */
1069 if (devc->state.chunks_downloaded == numchunks - 1) {
1070 /* Find the last valid timestamp */
1071 limit_chunk = devc->state.stoppos % 512 + devc->state.lastts;
1072 }
1073
1074 if (devc->state.chunks_downloaded + i == devc->state.triggerchunk)
1075 decode_chunk_ts(buf + (i * CHUNK_SIZE),
1076 &devc->state.lastts,
1077 &devc->state.lastsample,
1078 devc->state.triggerpos & 0x1ff,
1079 limit_chunk, sdi);
1080 else
1081 decode_chunk_ts(buf + (i * CHUNK_SIZE),
1082 &devc->state.lastts,
1083 &devc->state.lastsample,
1084 -1, limit_chunk, sdi);
1085
1086 ++devc->state.chunks_downloaded;
1087 }
1088
1089}
1090
1091static int receive_data(int fd, int revents, void *cb_data)
1092{
1093 struct sr_dev_inst *sdi;
1094 struct dev_context *devc;
1095 struct sr_datafeed_packet packet;
94ba4bd6 1096 uint64_t running_msec;
28a35d8a 1097 struct timeval tv;
6868626b
BV
1098 int numchunks;
1099 uint8_t modestatus;
28a35d8a 1100
cb93f8a9
UH
1101 (void)fd;
1102 (void)revents;
28a35d8a 1103
6868626b
BV
1104 sdi = cb_data;
1105 devc = sdi->priv;
1106
805919b0 1107 /* Get the current position. */
0e1357e8 1108 sigma_read_pos(&devc->state.stoppos, &devc->state.triggerpos, devc);
805919b0 1109
0e1357e8 1110 if (devc->state.state == SIGMA_IDLE)
805919b0 1111 return TRUE;
28a35d8a 1112
0e1357e8 1113 if (devc->state.state == SIGMA_CAPTURE) {
6868626b
BV
1114 numchunks = (devc->state.stoppos + 511) / 512;
1115
6aac7737
HE
1116 /* Check if the timer has expired, or memory is full. */
1117 gettimeofday(&tv, 0);
0e1357e8
BV
1118 running_msec = (tv.tv_sec - devc->start_tv.tv_sec) * 1000 +
1119 (tv.tv_usec - devc->start_tv.tv_usec) / 1000;
28a35d8a 1120
0e1357e8 1121 if (running_msec < devc->limit_msec && numchunks < 32767)
6868626b 1122 /* Still capturing. */
6aac7737 1123 return TRUE;
6aac7737 1124
6868626b
BV
1125 /* Stop acquisition. */
1126 sigma_set_register(WRITE_MODE, 0x11, devc);
28a35d8a 1127
6868626b
BV
1128 /* Set SDRAM Read Enable. */
1129 sigma_set_register(WRITE_MODE, 0x02, devc);
28a35d8a 1130
6868626b
BV
1131 /* Get the current position. */
1132 sigma_read_pos(&devc->state.stoppos, &devc->state.triggerpos, devc);
28a35d8a 1133
6868626b
BV
1134 /* Check if trigger has fired. */
1135 modestatus = sigma_get_register(READ_MODE, devc);
1136 if (modestatus & 0x20)
1137 devc->state.triggerchunk = devc->state.triggerpos / 512;
1138 else
1139 devc->state.triggerchunk = -1;
28a35d8a 1140
6868626b
BV
1141 /* Transfer captured data from device. */
1142 download_capture(sdi);
88c51afe 1143
6868626b
BV
1144 /* All done. */
1145 packet.type = SR_DF_END;
1146 sr_session_send(sdi, &packet);
88c51afe 1147
6868626b 1148 dev_acquisition_stop(sdi, sdi);
28a35d8a
HE
1149 }
1150
28a35d8a
HE
1151 return TRUE;
1152}
1153
c53d793f
HE
1154/* Build a LUT entry used by the trigger functions. */
1155static void build_lut_entry(uint16_t value, uint16_t mask, uint16_t *entry)
ee492173
HE
1156{
1157 int i, j, k, bit;
1158
ba7dd8bb 1159 /* For each quad channel. */
ee492173 1160 for (i = 0; i < 4; ++i) {
c53d793f 1161 entry[i] = 0xffff;
ee492173 1162
f758d074 1163 /* For each bit in LUT. */
ee492173
HE
1164 for (j = 0; j < 16; ++j)
1165
ba7dd8bb 1166 /* For each channel in quad. */
ee492173
HE
1167 for (k = 0; k < 4; ++k) {
1168 bit = 1 << (i * 4 + k);
1169
c53d793f
HE
1170 /* Set bit in entry */
1171 if ((mask & bit) &&
1172 ((!(value & bit)) !=
4ae1f451 1173 (!(j & (1 << k)))))
c53d793f 1174 entry[i] &= ~(1 << j);
ee492173
HE
1175 }
1176 }
c53d793f 1177}
ee492173 1178
c53d793f
HE
1179/* Add a logical function to LUT mask. */
1180static void add_trigger_function(enum triggerop oper, enum triggerfunc func,
1181 int index, int neg, uint16_t *mask)
1182{
1183 int i, j;
1184 int x[2][2], tmp, a, b, aset, bset, rset;
1185
1186 memset(x, 0, 4 * sizeof(int));
1187
1188 /* Trigger detect condition. */
1189 switch (oper) {
1190 case OP_LEVEL:
1191 x[0][1] = 1;
1192 x[1][1] = 1;
1193 break;
1194 case OP_NOT:
1195 x[0][0] = 1;
1196 x[1][0] = 1;
1197 break;
1198 case OP_RISE:
1199 x[0][1] = 1;
1200 break;
1201 case OP_FALL:
1202 x[1][0] = 1;
1203 break;
1204 case OP_RISEFALL:
1205 x[0][1] = 1;
1206 x[1][0] = 1;
1207 break;
1208 case OP_NOTRISE:
1209 x[1][1] = 1;
1210 x[0][0] = 1;
1211 x[1][0] = 1;
1212 break;
1213 case OP_NOTFALL:
1214 x[1][1] = 1;
1215 x[0][0] = 1;
1216 x[0][1] = 1;
1217 break;
1218 case OP_NOTRISEFALL:
1219 x[1][1] = 1;
1220 x[0][0] = 1;
1221 break;
1222 }
1223
1224 /* Transpose if neg is set. */
1225 if (neg) {
ea9cfed7 1226 for (i = 0; i < 2; ++i) {
c53d793f
HE
1227 for (j = 0; j < 2; ++j) {
1228 tmp = x[i][j];
1229 x[i][j] = x[1-i][1-j];
1230 x[1-i][1-j] = tmp;
1231 }
ea9cfed7 1232 }
c53d793f
HE
1233 }
1234
1235 /* Update mask with function. */
1236 for (i = 0; i < 16; ++i) {
1237 a = (i >> (2 * index + 0)) & 1;
1238 b = (i >> (2 * index + 1)) & 1;
1239
1240 aset = (*mask >> i) & 1;
1241 bset = x[b][a];
1242
1243 if (func == FUNC_AND || func == FUNC_NAND)
1244 rset = aset & bset;
1245 else if (func == FUNC_OR || func == FUNC_NOR)
1246 rset = aset | bset;
1247 else if (func == FUNC_XOR || func == FUNC_NXOR)
1248 rset = aset ^ bset;
1249
1250 if (func == FUNC_NAND || func == FUNC_NOR || func == FUNC_NXOR)
1251 rset = !rset;
1252
1253 *mask &= ~(1 << i);
1254
1255 if (rset)
1256 *mask |= 1 << i;
1257 }
1258}
1259
1260/*
1261 * Build trigger LUTs used by 50 MHz and lower sample rates for supporting
1262 * simple pin change and state triggers. Only two transitions (rise/fall) can be
1263 * set at any time, but a full mask and value can be set (0/1).
1264 */
0e1357e8 1265static int build_basic_trigger(struct triggerlut *lut, struct dev_context *devc)
c53d793f
HE
1266{
1267 int i,j;
4ae1f451 1268 uint16_t masks[2] = { 0, 0 };
c53d793f
HE
1269
1270 memset(lut, 0, sizeof(struct triggerlut));
1271
1272 /* Contant for simple triggers. */
1273 lut->m4 = 0xa000;
1274
1275 /* Value/mask trigger support. */
0e1357e8 1276 build_lut_entry(devc->trigger.simplevalue, devc->trigger.simplemask,
99965709 1277 lut->m2d);
c53d793f
HE
1278
1279 /* Rise/fall trigger support. */
1280 for (i = 0, j = 0; i < 16; ++i) {
0e1357e8
BV
1281 if (devc->trigger.risingmask & (1 << i) ||
1282 devc->trigger.fallingmask & (1 << i))
c53d793f
HE
1283 masks[j++] = 1 << i;
1284 }
1285
1286 build_lut_entry(masks[0], masks[0], lut->m0d);
1287 build_lut_entry(masks[1], masks[1], lut->m1d);
1288
1289 /* Add glue logic */
1290 if (masks[0] || masks[1]) {
1291 /* Transition trigger. */
0e1357e8 1292 if (masks[0] & devc->trigger.risingmask)
c53d793f 1293 add_trigger_function(OP_RISE, FUNC_OR, 0, 0, &lut->m3);
0e1357e8 1294 if (masks[0] & devc->trigger.fallingmask)
c53d793f 1295 add_trigger_function(OP_FALL, FUNC_OR, 0, 0, &lut->m3);
0e1357e8 1296 if (masks[1] & devc->trigger.risingmask)
c53d793f 1297 add_trigger_function(OP_RISE, FUNC_OR, 1, 0, &lut->m3);
0e1357e8 1298 if (masks[1] & devc->trigger.fallingmask)
c53d793f
HE
1299 add_trigger_function(OP_FALL, FUNC_OR, 1, 0, &lut->m3);
1300 } else {
1301 /* Only value/mask trigger. */
1302 lut->m3 = 0xffff;
1303 }
ee492173 1304
c53d793f 1305 /* Triggertype: event. */
ee492173
HE
1306 lut->params.selres = 3;
1307
e46b8fb1 1308 return SR_OK;
ee492173
HE
1309}
1310
6078d2c9 1311static int dev_acquisition_start(const struct sr_dev_inst *sdi, void *cb_data)
28a35d8a 1312{
0e1357e8 1313 struct dev_context *devc;
9ddb2a12 1314 struct clockselect_50 clockselect;
82957b65 1315 int frac, triggerpin, ret;
f4abaa9f 1316 uint8_t triggerselect = 0;
57bbf56b 1317 struct triggerinout triggerinout_conf;
ee492173 1318 struct triggerlut lut;
28a35d8a 1319
e73ffd42
BV
1320 if (sdi->status != SR_ST_ACTIVE)
1321 return SR_ERR_DEV_CLOSED;
1322
0e1357e8 1323 devc = sdi->priv;
28a35d8a 1324
ba7dd8bb
UH
1325 if (configure_channels(sdi) != SR_OK) {
1326 sr_err("Failed to configure channels.");
014359e3
BV
1327 return SR_ERR;
1328 }
1329
ea9cfed7 1330 /* If the samplerate has not been set, default to 200 kHz. */
0e1357e8 1331 if (devc->cur_firmware == -1) {
82957b65
UH
1332 if ((ret = set_samplerate(sdi, SR_KHZ(200))) != SR_OK)
1333 return ret;
1334 }
e8397563 1335
eec5275e 1336 /* Enter trigger programming mode. */
0e1357e8 1337 sigma_set_register(WRITE_TRIGGER_SELECT1, 0x20, devc);
28a35d8a 1338
eec5275e 1339 /* 100 and 200 MHz mode. */
0e1357e8
BV
1340 if (devc->cur_samplerate >= SR_MHZ(100)) {
1341 sigma_set_register(WRITE_TRIGGER_SELECT1, 0x81, devc);
57bbf56b 1342
a42aec7f
HE
1343 /* Find which pin to trigger on from mask. */
1344 for (triggerpin = 0; triggerpin < 8; ++triggerpin)
0e1357e8 1345 if ((devc->trigger.risingmask | devc->trigger.fallingmask) &
a42aec7f
HE
1346 (1 << triggerpin))
1347 break;
1348
1349 /* Set trigger pin and light LED on trigger. */
1350 triggerselect = (1 << LEDSEL1) | (triggerpin & 0x7);
1351
1352 /* Default rising edge. */
0e1357e8 1353 if (devc->trigger.fallingmask)
a42aec7f 1354 triggerselect |= 1 << 3;
57bbf56b 1355
eec5275e 1356 /* All other modes. */
0e1357e8
BV
1357 } else if (devc->cur_samplerate <= SR_MHZ(50)) {
1358 build_basic_trigger(&lut, devc);
ee492173 1359
0e1357e8 1360 sigma_write_trigger_lut(&lut, devc);
57bbf56b
HE
1361
1362 triggerselect = (1 << LEDSEL1) | (1 << LEDSEL0);
1363 }
1364
eec5275e 1365 /* Setup trigger in and out pins to default values. */
57bbf56b
HE
1366 memset(&triggerinout_conf, 0, sizeof(struct triggerinout));
1367 triggerinout_conf.trgout_bytrigger = 1;
1368 triggerinout_conf.trgout_enable = 1;
1369
28a35d8a 1370 sigma_write_register(WRITE_TRIGGER_OPTION,
57bbf56b 1371 (uint8_t *) &triggerinout_conf,
0e1357e8 1372 sizeof(struct triggerinout), devc);
28a35d8a 1373
eec5275e 1374 /* Go back to normal mode. */
0e1357e8 1375 sigma_set_register(WRITE_TRIGGER_SELECT1, triggerselect, devc);
28a35d8a 1376
edca2c5c 1377 /* Set clock select register. */
0e1357e8 1378 if (devc->cur_samplerate == SR_MHZ(200))
ba7dd8bb 1379 /* Enable 4 channels. */
0e1357e8
BV
1380 sigma_set_register(WRITE_CLOCK_SELECT, 0xf0, devc);
1381 else if (devc->cur_samplerate == SR_MHZ(100))
ba7dd8bb 1382 /* Enable 8 channels. */
0e1357e8 1383 sigma_set_register(WRITE_CLOCK_SELECT, 0x00, devc);
edca2c5c
HE
1384 else {
1385 /*
9ddb2a12 1386 * 50 MHz mode (or fraction thereof). Any fraction down to
eec5275e 1387 * 50 MHz / 256 can be used, but is not supported by sigrok API.
edca2c5c 1388 */
0e1357e8 1389 frac = SR_MHZ(50) / devc->cur_samplerate - 1;
edca2c5c 1390
9ddb2a12
UH
1391 clockselect.async = 0;
1392 clockselect.fraction = frac;
ba7dd8bb 1393 clockselect.disabled_channels = 0;
edca2c5c
HE
1394
1395 sigma_write_register(WRITE_CLOCK_SELECT,
9ddb2a12 1396 (uint8_t *) &clockselect,
0e1357e8 1397 sizeof(clockselect), devc);
edca2c5c
HE
1398 }
1399
fefa1800 1400 /* Setup maximum post trigger time. */
99965709 1401 sigma_set_register(WRITE_POST_TRIGGER,
0e1357e8 1402 (devc->capture_ratio * 255) / 100, devc);
28a35d8a 1403
eec5275e 1404 /* Start acqusition. */
0e1357e8
BV
1405 gettimeofday(&devc->start_tv, 0);
1406 sigma_set_register(WRITE_MODE, 0x0d, devc);
99965709 1407
3e9b7f9c 1408 devc->cb_data = cb_data;
28a35d8a 1409
3c36c403 1410 /* Send header packet to the session bus. */
29a27196 1411 std_session_send_df_header(cb_data, LOG_PREFIX);
f366e86c 1412
f366e86c 1413 /* Add capture source. */
3ffb6964 1414 sr_source_add(0, G_IO_IN, 10, receive_data, (void *)sdi);
f366e86c 1415
0e1357e8 1416 devc->state.state = SIGMA_CAPTURE;
6aac7737 1417
e46b8fb1 1418 return SR_OK;
28a35d8a
HE
1419}
1420
6078d2c9 1421static int dev_acquisition_stop(struct sr_dev_inst *sdi, void *cb_data)
28a35d8a 1422{
0e1357e8 1423 struct dev_context *devc;
6aac7737 1424
3cd3a20b 1425 (void)cb_data;
28a35d8a 1426
6868626b
BV
1427 devc = sdi->priv;
1428 devc->state.state = SIGMA_IDLE;
6aac7737 1429
6868626b 1430 sr_source_remove(0);
3010f21c
UH
1431
1432 return SR_OK;
28a35d8a
HE
1433}
1434
c09f0b57 1435SR_PRIV struct sr_dev_driver asix_sigma_driver_info = {
e519ba86 1436 .name = "asix-sigma",
6352d030 1437 .longname = "ASIX SIGMA/SIGMA2",
e519ba86 1438 .api_version = 1,
6078d2c9
UH
1439 .init = init,
1440 .cleanup = cleanup,
1441 .scan = scan,
1442 .dev_list = dev_list,
3b412e3a 1443 .dev_clear = dev_clear,
035a1078
BV
1444 .config_get = config_get,
1445 .config_set = config_set,
a1c743fc 1446 .config_list = config_list,
6078d2c9
UH
1447 .dev_open = dev_open,
1448 .dev_close = dev_close,
1449 .dev_acquisition_start = dev_acquisition_start,
1450 .dev_acquisition_stop = dev_acquisition_stop,
0e1357e8 1451 .priv = NULL,
28a35d8a 1452};