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Commit | Line | Data |
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28a35d8a HE |
1 | /* |
2 | * This file is part of the sigrok project. | |
3 | * | |
911f1834 UH |
4 | * Copyright (C) 2010 Håvard Espeland <gus@ping.uio.no>, |
5 | * Copyright (C) 2010 Martin Stensgård <mastensg@ping.uio.no> | |
6 | * Copyright (C) 2010 Carl Henrik Lunde <chlunde@ping.uio.no> | |
28a35d8a HE |
7 | * |
8 | * This program is free software: you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation, either version 3 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
20 | */ | |
21 | ||
911f1834 UH |
22 | /* |
23 | * ASIX Sigma Logic Analyzer Driver | |
24 | */ | |
25 | ||
28a35d8a HE |
26 | #include <ftdi.h> |
27 | #include <string.h> | |
28 | #include <zlib.h> | |
fefa1800 | 29 | #include <sigrok.h> |
28a35d8a HE |
30 | #include "asix-sigma.h" |
31 | ||
32 | #define USB_VENDOR 0xa600 | |
33 | #define USB_PRODUCT 0xa000 | |
34 | #define USB_DESCRIPTION "ASIX SIGMA" | |
35 | #define USB_VENDOR_NAME "ASIX" | |
36 | #define USB_MODEL_NAME "SIGMA" | |
37 | #define USB_MODEL_VERSION "" | |
28a35d8a HE |
38 | |
39 | static GSList *device_instances = NULL; | |
40 | ||
41 | // XXX These should be per device | |
42 | static struct ftdi_context ftdic; | |
f78898e9 | 43 | static uint64_t cur_samplerate = 0; |
28a35d8a HE |
44 | static uint32_t limit_msec = 0; |
45 | static struct timeval start_tv; | |
f6564c8d | 46 | static int cur_firmware = -1; |
f78898e9 HE |
47 | static int num_probes = 0; |
48 | static int samples_per_event = 0; | |
28a35d8a HE |
49 | |
50 | static uint64_t supported_samplerates[] = { | |
edca2c5c HE |
51 | KHZ(250), |
52 | MHZ(1), | |
53 | MHZ(10), | |
54 | MHZ(25), | |
e8397563 HE |
55 | MHZ(50), |
56 | MHZ(100), | |
28a35d8a HE |
57 | MHZ(200), |
58 | 0, | |
59 | }; | |
60 | ||
61 | static struct samplerates samplerates = { | |
edca2c5c | 62 | KHZ(250), |
28a35d8a HE |
63 | MHZ(200), |
64 | 0, | |
65 | supported_samplerates, | |
66 | }; | |
67 | ||
68 | static int capabilities[] = { | |
69 | HWCAP_LOGIC_ANALYZER, | |
70 | HWCAP_SAMPLERATE, | |
71 | ||
72 | /* These are really implemented in the driver, not the hardware. */ | |
73 | HWCAP_LIMIT_MSEC, | |
74 | 0, | |
75 | }; | |
76 | ||
fefa1800 UH |
77 | /* Force the FPGA to reboot. */ |
78 | static uint8_t suicide[] = { | |
79 | 0x84, 0x84, 0x88, 0x84, 0x88, 0x84, 0x88, 0x84, | |
80 | }; | |
81 | ||
82 | /* Prepare to upload firmware (FPGA specific). */ | |
83 | static uint8_t init[] = { | |
84 | 0x03, 0x03, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, | |
85 | }; | |
86 | ||
87 | /* Initialize the logic analyzer mode. */ | |
88 | static uint8_t logic_mode_start[] = { | |
89 | 0x00, 0x40, 0x0f, 0x25, 0x35, 0x40, | |
90 | 0x2a, 0x3a, 0x40, 0x03, 0x20, 0x38, | |
91 | }; | |
92 | ||
f6564c8d HE |
93 | static const char *firmware_files[] = |
94 | { | |
a8116d76 HE |
95 | "asix-sigma-50.fw", /* 50 MHz, supports 8 bit fractions */ |
96 | "asix-sigma-100.fw", /* 100 MHz */ | |
97 | "asix-sigma-200.fw", /* 200 MHz */ | |
98 | "asix-sigma-50sync.fw", /* Asynchronous sampling */ | |
99 | "asix-sigma-phasor.fw", /* Frequency counter */ | |
f6564c8d HE |
100 | }; |
101 | ||
102 | static int sigma_read(void* buf, size_t size) | |
28a35d8a HE |
103 | { |
104 | int ret; | |
fefa1800 UH |
105 | |
106 | ret = ftdi_read_data(&ftdic, (unsigned char *)buf, size); | |
28a35d8a HE |
107 | if (ret < 0) { |
108 | g_warning("ftdi_read_data failed: %s", | |
fefa1800 | 109 | ftdi_get_error_string(&ftdic)); |
28a35d8a HE |
110 | } |
111 | ||
112 | return ret; | |
113 | } | |
114 | ||
fefa1800 | 115 | static int sigma_write(void *buf, size_t size) |
28a35d8a HE |
116 | { |
117 | int ret; | |
fefa1800 UH |
118 | |
119 | ret = ftdi_write_data(&ftdic, (unsigned char *)buf, size); | |
28a35d8a HE |
120 | if (ret < 0) { |
121 | g_warning("ftdi_write_data failed: %s", | |
fefa1800 UH |
122 | ftdi_get_error_string(&ftdic)); |
123 | } else if ((size_t) ret != size) { | |
28a35d8a HE |
124 | g_warning("ftdi_write_data did not complete write\n"); |
125 | } | |
126 | ||
127 | return ret; | |
128 | } | |
129 | ||
130 | static int sigma_write_register(uint8_t reg, uint8_t *data, size_t len) | |
131 | { | |
132 | size_t i; | |
133 | uint8_t buf[len + 2]; | |
134 | int idx = 0; | |
135 | ||
136 | buf[idx++] = REG_ADDR_LOW | (reg & 0xf); | |
137 | buf[idx++] = REG_ADDR_HIGH | (reg >> 4); | |
138 | ||
fefa1800 | 139 | for (i = 0; i < len; ++i) { |
28a35d8a HE |
140 | buf[idx++] = REG_DATA_LOW | (data[i] & 0xf); |
141 | buf[idx++] = REG_DATA_HIGH_WRITE | (data[i] >> 4); | |
142 | } | |
143 | ||
144 | return sigma_write(buf, idx); | |
145 | } | |
146 | ||
147 | static int sigma_set_register(uint8_t reg, uint8_t value) | |
148 | { | |
149 | return sigma_write_register(reg, &value, 1); | |
150 | } | |
151 | ||
152 | static int sigma_read_register(uint8_t reg, uint8_t *data, size_t len) | |
153 | { | |
154 | uint8_t buf[3]; | |
fefa1800 | 155 | |
28a35d8a HE |
156 | buf[0] = REG_ADDR_LOW | (reg & 0xf); |
157 | buf[1] = REG_ADDR_HIGH | (reg >> 4); | |
28a35d8a HE |
158 | buf[2] = REG_READ_ADDR; |
159 | ||
160 | sigma_write(buf, sizeof(buf)); | |
161 | ||
162 | return sigma_read(data, len); | |
163 | } | |
164 | ||
165 | static uint8_t sigma_get_register(uint8_t reg) | |
166 | { | |
167 | uint8_t value; | |
fefa1800 | 168 | |
28a35d8a HE |
169 | if (1 != sigma_read_register(reg, &value, 1)) { |
170 | g_warning("Sigma_get_register: 1 byte expected"); | |
171 | return 0; | |
172 | } | |
173 | ||
174 | return value; | |
175 | } | |
176 | ||
177 | static int sigma_read_pos(uint32_t *stoppos, uint32_t *triggerpos) | |
178 | { | |
179 | uint8_t buf[] = { | |
180 | REG_ADDR_LOW | READ_TRIGGER_POS_LOW, | |
181 | ||
182 | REG_READ_ADDR | NEXT_REG, | |
183 | REG_READ_ADDR | NEXT_REG, | |
184 | REG_READ_ADDR | NEXT_REG, | |
185 | REG_READ_ADDR | NEXT_REG, | |
186 | REG_READ_ADDR | NEXT_REG, | |
187 | REG_READ_ADDR | NEXT_REG, | |
188 | }; | |
28a35d8a HE |
189 | uint8_t result[6]; |
190 | ||
191 | sigma_write(buf, sizeof(buf)); | |
192 | ||
193 | sigma_read(result, sizeof(result)); | |
194 | ||
195 | *triggerpos = result[0] | (result[1] << 8) | (result[2] << 16); | |
196 | *stoppos = result[3] | (result[4] << 8) | (result[5] << 16); | |
197 | ||
198 | return 1; | |
199 | } | |
200 | ||
201 | static int sigma_read_dram(uint16_t startchunk, size_t numchunks, uint8_t *data) | |
202 | { | |
203 | size_t i; | |
204 | uint8_t buf[4096]; | |
205 | int idx = 0; | |
206 | ||
fefa1800 | 207 | /* Send the startchunk. Index start with 1. */ |
28a35d8a HE |
208 | buf[0] = startchunk >> 8; |
209 | buf[1] = startchunk & 0xff; | |
210 | sigma_write_register(WRITE_MEMROW, buf, 2); | |
211 | ||
fefa1800 | 212 | /* Read the DRAM. */ |
28a35d8a HE |
213 | buf[idx++] = REG_DRAM_BLOCK; |
214 | buf[idx++] = REG_DRAM_WAIT_ACK; | |
215 | ||
216 | for (i = 0; i < numchunks; ++i) { | |
fefa1800 UH |
217 | /* Alternate bit to copy from DRAM to cache. */ |
218 | if (i != (numchunks - 1)) | |
219 | buf[idx++] = REG_DRAM_BLOCK | (((i + 1) % 2) << 4); | |
28a35d8a HE |
220 | |
221 | buf[idx++] = REG_DRAM_BLOCK_DATA | ((i % 2) << 4); | |
222 | ||
fefa1800 | 223 | if (i != (numchunks - 1)) |
28a35d8a HE |
224 | buf[idx++] = REG_DRAM_WAIT_ACK; |
225 | } | |
226 | ||
227 | sigma_write(buf, idx); | |
228 | ||
229 | return sigma_read(data, numchunks * CHUNK_SIZE); | |
230 | } | |
231 | ||
fefa1800 | 232 | /* Generate the bitbang stream for programming the FPGA. */ |
28a35d8a | 233 | static int bin2bitbang(const char *filename, |
fefa1800 | 234 | unsigned char **buf, size_t *buf_size) |
28a35d8a | 235 | { |
fefa1800 | 236 | FILE *f; |
28a35d8a HE |
237 | long file_size; |
238 | unsigned long offset = 0; | |
239 | unsigned char *p; | |
240 | uint8_t *compressed_buf, *firmware; | |
241 | uLongf csize, fwsize; | |
242 | const int buffer_size = 65536; | |
243 | size_t i; | |
fefa1800 UH |
244 | int c, ret, bit, v; |
245 | uint32_t imm = 0x3f6df2ab; | |
28a35d8a | 246 | |
fefa1800 | 247 | f = fopen(filename, "r"); |
28a35d8a HE |
248 | if (!f) { |
249 | g_warning("fopen(\"%s\", \"r\")", filename); | |
250 | return -1; | |
251 | } | |
252 | ||
253 | if (-1 == fseek(f, 0, SEEK_END)) { | |
254 | g_warning("fseek on %s failed", filename); | |
255 | fclose(f); | |
256 | return -1; | |
257 | } | |
258 | ||
259 | file_size = ftell(f); | |
260 | ||
261 | fseek(f, 0, SEEK_SET); | |
262 | ||
28a35d8a HE |
263 | compressed_buf = g_malloc(file_size); |
264 | firmware = g_malloc(buffer_size); | |
265 | ||
266 | if (!compressed_buf || !firmware) { | |
267 | g_warning("Error allocating buffers"); | |
268 | return -1; | |
269 | } | |
270 | ||
28a35d8a HE |
271 | csize = 0; |
272 | while ((c = getc(f)) != EOF) { | |
273 | imm = (imm + 0xa853753) % 177 + (imm * 0x8034052); | |
274 | compressed_buf[csize++] = c ^ imm; | |
275 | } | |
276 | fclose(f); | |
277 | ||
278 | fwsize = buffer_size; | |
279 | ret = uncompress(firmware, &fwsize, compressed_buf, csize); | |
280 | if (ret < 0) { | |
281 | g_free(compressed_buf); | |
282 | g_free(firmware); | |
283 | g_warning("Could not unpack Sigma firmware. (Error %d)\n", ret); | |
284 | return -1; | |
285 | } | |
286 | ||
287 | g_free(compressed_buf); | |
288 | ||
289 | *buf_size = fwsize * 2 * 8; | |
290 | ||
fefa1800 | 291 | *buf = p = (unsigned char *)g_malloc(*buf_size); |
28a35d8a HE |
292 | |
293 | if (!p) { | |
294 | g_warning("Error allocating buffers"); | |
295 | return -1; | |
296 | } | |
297 | ||
298 | for (i = 0; i < fwsize; ++i) { | |
28a35d8a | 299 | for (bit = 7; bit >= 0; --bit) { |
fefa1800 | 300 | v = firmware[i] & 1 << bit ? 0x40 : 0x00; |
28a35d8a HE |
301 | p[offset++] = v | 0x01; |
302 | p[offset++] = v; | |
303 | } | |
304 | } | |
305 | ||
306 | g_free(firmware); | |
307 | ||
308 | if (offset != *buf_size) { | |
309 | g_free(*buf); | |
310 | g_warning("Error reading firmware %s " | |
fefa1800 UH |
311 | "offset=%ld, file_size=%ld, buf_size=%zd\n", |
312 | filename, offset, file_size, *buf_size); | |
28a35d8a HE |
313 | |
314 | return -1; | |
315 | } | |
316 | ||
317 | return 0; | |
318 | } | |
319 | ||
320 | static int hw_init(char *deviceinfo) | |
321 | { | |
322 | struct sigrok_device_instance *sdi; | |
323 | ||
324 | deviceinfo = deviceinfo; | |
325 | ||
326 | ftdi_init(&ftdic); | |
327 | ||
fefa1800 UH |
328 | /* Look for SIGMAs. */ |
329 | if (ftdi_usb_open_desc(&ftdic, USB_VENDOR, USB_PRODUCT, | |
330 | USB_DESCRIPTION, NULL) < 0) | |
28a35d8a HE |
331 | return 0; |
332 | ||
fefa1800 | 333 | /* Register SIGMA device. */ |
28a35d8a HE |
334 | sdi = sigrok_device_instance_new(0, ST_INITIALIZING, |
335 | USB_VENDOR_NAME, USB_MODEL_NAME, USB_MODEL_VERSION); | |
336 | if (!sdi) | |
337 | return 0; | |
338 | ||
339 | device_instances = g_slist_append(device_instances, sdi); | |
340 | ||
fefa1800 | 341 | /* We will open the device again when we need it. */ |
28a35d8a HE |
342 | ftdi_usb_close(&ftdic); |
343 | ||
344 | return 1; | |
345 | } | |
346 | ||
f6564c8d | 347 | static int upload_firmware(int firmware_idx) |
28a35d8a HE |
348 | { |
349 | int ret; | |
350 | unsigned char *buf; | |
351 | unsigned char pins; | |
352 | size_t buf_size; | |
28a35d8a | 353 | unsigned char result[32]; |
e8397563 | 354 | char firmware_path[128]; |
28a35d8a | 355 | |
fefa1800 | 356 | /* Make sure it's an ASIX SIGMA. */ |
28a35d8a HE |
357 | if ((ret = ftdi_usb_open_desc(&ftdic, |
358 | USB_VENDOR, USB_PRODUCT, USB_DESCRIPTION, NULL)) < 0) { | |
28a35d8a | 359 | g_warning("ftdi_usb_open failed: %s", |
fefa1800 | 360 | ftdi_get_error_string(&ftdic)); |
28a35d8a HE |
361 | return 0; |
362 | } | |
363 | ||
364 | if ((ret = ftdi_set_bitmode(&ftdic, 0xdf, BITMODE_BITBANG)) < 0) { | |
365 | g_warning("ftdi_set_bitmode failed: %s", | |
fefa1800 | 366 | ftdi_get_error_string(&ftdic)); |
28a35d8a HE |
367 | return 0; |
368 | } | |
369 | ||
fefa1800 | 370 | /* Four times the speed of sigmalogan - Works well. */ |
28a35d8a HE |
371 | if ((ret = ftdi_set_baudrate(&ftdic, 750000)) < 0) { |
372 | g_warning("ftdi_set_baudrate failed: %s", | |
fefa1800 | 373 | ftdi_get_error_string(&ftdic)); |
28a35d8a HE |
374 | return 0; |
375 | } | |
376 | ||
fefa1800 | 377 | /* Force the FPGA to reboot. */ |
28a35d8a HE |
378 | sigma_write(suicide, sizeof(suicide)); |
379 | sigma_write(suicide, sizeof(suicide)); | |
380 | sigma_write(suicide, sizeof(suicide)); | |
381 | sigma_write(suicide, sizeof(suicide)); | |
382 | ||
fefa1800 | 383 | /* Prepare to upload firmware (FPGA specific). */ |
28a35d8a HE |
384 | sigma_write(init, sizeof(init)); |
385 | ||
386 | ftdi_usb_purge_buffers(&ftdic); | |
387 | ||
fefa1800 | 388 | /* Wait until the FPGA asserts INIT_B. */ |
28a35d8a HE |
389 | while (1) { |
390 | ret = sigma_read(result, 1); | |
391 | if (result[0] & 0x20) | |
392 | break; | |
393 | } | |
394 | ||
f6564c8d | 395 | /* Prepare firmware */ |
e8397563 | 396 | snprintf(firmware_path, sizeof(firmware_path), "%s/%s", FIRMWARE_DIR, |
f6564c8d HE |
397 | firmware_files[firmware_idx]); |
398 | ||
e8397563 | 399 | if (-1 == bin2bitbang(firmware_path, &buf, &buf_size)) { |
28a35d8a | 400 | g_warning("An error occured while reading the firmware: %s", |
e8397563 | 401 | firmware_path); |
28a35d8a HE |
402 | return SIGROK_ERR; |
403 | } | |
404 | ||
fefa1800 | 405 | /* Upload firmare. */ |
28a35d8a HE |
406 | sigma_write(buf, buf_size); |
407 | ||
408 | g_free(buf); | |
409 | ||
410 | if ((ret = ftdi_set_bitmode(&ftdic, 0x00, BITMODE_RESET)) < 0) { | |
f6564c8d | 411 | g_warning("ftdi_set_bitmode failed: %s", |
fefa1800 | 412 | ftdi_get_error_string(&ftdic)); |
28a35d8a HE |
413 | return SIGROK_ERR; |
414 | } | |
415 | ||
416 | ftdi_usb_purge_buffers(&ftdic); | |
417 | ||
fefa1800 | 418 | /* Discard garbage. */ |
28a35d8a HE |
419 | while (1 == sigma_read(&pins, 1)) |
420 | ; | |
421 | ||
fefa1800 | 422 | /* Initialize the logic analyzer mode. */ |
28a35d8a HE |
423 | sigma_write(logic_mode_start, sizeof(logic_mode_start)); |
424 | ||
fefa1800 | 425 | /* Expect a 3 byte reply. */ |
28a35d8a HE |
426 | ret = sigma_read(result, 3); |
427 | if (ret != 3 || | |
428 | result[0] != 0xa6 || result[1] != 0x55 || result[2] != 0xaa) { | |
fefa1800 | 429 | g_warning("Configuration failed. Invalid reply received."); |
28a35d8a HE |
430 | return SIGROK_ERR; |
431 | } | |
432 | ||
f6564c8d HE |
433 | cur_firmware = firmware_idx; |
434 | ||
435 | return SIGROK_OK; | |
436 | } | |
437 | ||
438 | static int hw_opendev(int device_index) | |
439 | { | |
440 | struct sigrok_device_instance *sdi; | |
441 | int ret; | |
442 | ||
443 | /* Make sure it's an ASIX SIGMA */ | |
444 | if ((ret = ftdi_usb_open_desc(&ftdic, | |
445 | USB_VENDOR, USB_PRODUCT, USB_DESCRIPTION, NULL)) < 0) { | |
446 | ||
447 | g_warning("ftdi_usb_open failed: %s", | |
448 | ftdi_get_error_string(&ftdic)); | |
449 | ||
450 | return 0; | |
451 | } | |
28a35d8a HE |
452 | |
453 | if (!(sdi = get_sigrok_device_instance(device_instances, device_index))) | |
454 | return SIGROK_ERR; | |
455 | ||
456 | sdi->status = ST_ACTIVE; | |
457 | ||
f6564c8d HE |
458 | return SIGROK_OK; |
459 | } | |
460 | ||
461 | static int set_samplerate(struct sigrok_device_instance *sdi, uint64_t samplerate) | |
462 | { | |
e8397563 | 463 | int i, ret; |
f6564c8d HE |
464 | |
465 | sdi = sdi; | |
466 | ||
467 | for (i = 0; supported_samplerates[i]; i++) { | |
468 | if (supported_samplerates[i] == samplerate) | |
469 | break; | |
470 | } | |
471 | if (supported_samplerates[i] == 0) | |
472 | return SIGROK_ERR_SAMPLERATE; | |
473 | ||
e8397563 HE |
474 | if (samplerate <= MHZ(50)) { |
475 | ret = upload_firmware(0); | |
f78898e9 | 476 | num_probes = 16; |
edca2c5c | 477 | // XXX: Setup divider if < 50 MHz |
e8397563 | 478 | } |
f78898e9 | 479 | if (samplerate == MHZ(100)) { |
e8397563 | 480 | ret = upload_firmware(1); |
f78898e9 HE |
481 | num_probes = 8; |
482 | } | |
483 | else if (samplerate == MHZ(200)) { | |
e8397563 | 484 | ret = upload_firmware(2); |
f78898e9 HE |
485 | num_probes = 4; |
486 | } | |
f6564c8d | 487 | |
e8397563 | 488 | cur_samplerate = samplerate; |
f78898e9 | 489 | samples_per_event = 16 / num_probes; |
f6564c8d | 490 | |
28a35d8a HE |
491 | g_message("Firmware uploaded"); |
492 | ||
e8397563 | 493 | return ret; |
28a35d8a HE |
494 | } |
495 | ||
28a35d8a HE |
496 | static void hw_closedev(int device_index) |
497 | { | |
498 | device_index = device_index; | |
499 | ||
500 | ftdi_usb_close(&ftdic); | |
501 | } | |
502 | ||
28a35d8a HE |
503 | static void hw_cleanup(void) |
504 | { | |
505 | } | |
506 | ||
28a35d8a HE |
507 | static void *hw_get_device_info(int device_index, int device_info_id) |
508 | { | |
509 | struct sigrok_device_instance *sdi; | |
510 | void *info = NULL; | |
511 | ||
512 | if (!(sdi = get_sigrok_device_instance(device_instances, device_index))) { | |
513 | fprintf(stderr, "It's NULL.\n"); | |
514 | return NULL; | |
515 | } | |
516 | ||
517 | switch (device_info_id) { | |
518 | case DI_INSTANCE: | |
519 | info = sdi; | |
520 | break; | |
521 | case DI_NUM_PROBES: | |
edca2c5c | 522 | info = GINT_TO_POINTER(16); |
28a35d8a HE |
523 | break; |
524 | case DI_SAMPLERATES: | |
525 | info = &samplerates; | |
526 | break; | |
527 | case DI_TRIGGER_TYPES: | |
fefa1800 | 528 | info = 0; //TRIGGER_TYPES; |
28a35d8a HE |
529 | break; |
530 | case DI_CUR_SAMPLERATE: | |
531 | info = &cur_samplerate; | |
532 | break; | |
533 | } | |
534 | ||
535 | return info; | |
536 | } | |
537 | ||
28a35d8a HE |
538 | static int hw_get_status(int device_index) |
539 | { | |
540 | struct sigrok_device_instance *sdi; | |
541 | ||
542 | sdi = get_sigrok_device_instance(device_instances, device_index); | |
543 | if (sdi) | |
544 | return sdi->status; | |
545 | else | |
546 | return ST_NOT_FOUND; | |
547 | } | |
548 | ||
28a35d8a HE |
549 | static int *hw_get_capabilities(void) |
550 | { | |
551 | return capabilities; | |
552 | } | |
553 | ||
554 | static int hw_set_configuration(int device_index, int capability, void *value) | |
555 | { | |
556 | struct sigrok_device_instance *sdi; | |
557 | int ret; | |
f6564c8d | 558 | |
28a35d8a HE |
559 | if (!(sdi = get_sigrok_device_instance(device_instances, device_index))) |
560 | return SIGROK_ERR; | |
561 | ||
562 | if (capability == HWCAP_SAMPLERATE) { | |
f6564c8d | 563 | ret = set_samplerate(sdi, *(uint64_t*) value); |
28a35d8a HE |
564 | } else if (capability == HWCAP_PROBECONFIG) { |
565 | ret = SIGROK_OK; | |
566 | } else if (capability == HWCAP_LIMIT_MSEC) { | |
567 | limit_msec = strtoull(value, NULL, 10); | |
568 | ret = SIGROK_OK; | |
569 | } else { | |
570 | ret = SIGROK_ERR; | |
571 | } | |
572 | ||
573 | return ret; | |
574 | } | |
575 | ||
28a35d8a | 576 | /* |
fefa1800 UH |
577 | * Decode chunk of 1024 bytes, 64 clusters, 7 events per cluster. |
578 | * Each event is 20ns apart, and can contain multiple samples. | |
f78898e9 HE |
579 | * |
580 | * For 200 MHz, events contain 4 samples for each channel, spread 5 ns apart. | |
581 | * For 100 MHz, events contain 2 samples for each channel, spread 10 ns apart. | |
582 | * For 50 MHz and below, events contain one sample for each channel, | |
583 | * spread 20 ns apart. | |
28a35d8a HE |
584 | */ |
585 | static int decode_chunk_ts(uint8_t *buf, uint16_t *lastts, | |
f78898e9 | 586 | uint16_t *lastsample, void *user_data) |
28a35d8a | 587 | { |
fefa1800 | 588 | uint16_t tsdiff, ts; |
f78898e9 | 589 | uint16_t samples[65536 * samples_per_event]; |
28a35d8a | 590 | struct datafeed_packet packet; |
f78898e9 | 591 | int i, j, k, l, numpad, tosend; |
fefa1800 | 592 | size_t n = 0, sent = 0; |
f78898e9 | 593 | int clustersize = EVENTS_PER_CLUSTER * samples_per_event; |
fefa1800 | 594 | uint16_t *event; |
f78898e9 | 595 | uint16_t cur_sample; |
28a35d8a HE |
596 | |
597 | /* For each ts */ | |
598 | for (i = 0; i < 64; ++i) { | |
fefa1800 | 599 | ts = *(uint16_t *) &buf[i * 16]; |
28a35d8a HE |
600 | tsdiff = ts - *lastts; |
601 | *lastts = ts; | |
602 | ||
fefa1800 UH |
603 | /* Pad last sample up to current point. */ |
604 | numpad = tsdiff * samples_per_event - clustersize; | |
28a35d8a | 605 | if (numpad > 0) { |
f78898e9 HE |
606 | for (j = 0; j < numpad; ++j) |
607 | samples[j] = *lastsample; | |
608 | ||
609 | n = numpad; | |
28a35d8a HE |
610 | } |
611 | ||
fefa1800 | 612 | event = (uint16_t *) &buf[i * 16 + 2]; |
28a35d8a | 613 | |
f78898e9 HE |
614 | cur_sample = 0; |
615 | ||
616 | /* For each event in cluster. */ | |
28a35d8a | 617 | for (j = 0; j < 7; ++j) { |
f78898e9 HE |
618 | |
619 | /* For each sample in event. */ | |
28a35d8a | 620 | for (k = 0; k < samples_per_event; ++k) { |
f78898e9 HE |
621 | cur_sample = 0; |
622 | ||
623 | /* For each probe. */ | |
624 | for (l = 0; l < num_probes; ++l) | |
edca2c5c HE |
625 | cur_sample |= (!!(event[j] & (1 << (l * |
626 | samples_per_event + k)))) | |
627 | << l; | |
f78898e9 HE |
628 | |
629 | samples[n++] = cur_sample; | |
28a35d8a HE |
630 | } |
631 | } | |
632 | ||
fefa1800 | 633 | *lastsample = samples[n - 1]; |
28a35d8a | 634 | |
fefa1800 UH |
635 | /* Send to sigrok. */ |
636 | sent = 0; | |
28a35d8a | 637 | while (sent < n) { |
f78898e9 | 638 | tosend = MIN(2048, n - sent); |
28a35d8a | 639 | |
f78898e9 HE |
640 | packet.type = DF_LOGIC16; |
641 | packet.length = tosend * sizeof(uint16_t); | |
fefa1800 | 642 | packet.payload = samples + sent; |
28a35d8a HE |
643 | session_bus(user_data, &packet); |
644 | ||
645 | sent += tosend; | |
646 | } | |
647 | } | |
648 | ||
f78898e9 | 649 | return SIGROK_OK; |
28a35d8a HE |
650 | } |
651 | ||
652 | static int receive_data(int fd, int revents, void *user_data) | |
653 | { | |
654 | struct datafeed_packet packet; | |
28a35d8a HE |
655 | const int chunks_per_read = 32; |
656 | unsigned char buf[chunks_per_read * CHUNK_SIZE]; | |
fefa1800 UH |
657 | int bufsz, numchunks, curchunk, i, newchunks; |
658 | uint32_t triggerpos, stoppos, running_msec; | |
28a35d8a | 659 | struct timeval tv; |
28a35d8a | 660 | uint16_t lastts = 0; |
f78898e9 | 661 | uint16_t lastsample = 0; |
28a35d8a HE |
662 | |
663 | fd = fd; | |
664 | revents = revents; | |
665 | ||
fefa1800 | 666 | /* Get the current position. */ |
28a35d8a HE |
667 | sigma_read_pos(&stoppos, &triggerpos); |
668 | numchunks = stoppos / 512; | |
669 | ||
fefa1800 | 670 | /* Check if the has expired, or memory is full. */ |
28a35d8a HE |
671 | gettimeofday(&tv, 0); |
672 | running_msec = (tv.tv_sec - start_tv.tv_sec) * 1000 + | |
fefa1800 | 673 | (tv.tv_usec - start_tv.tv_usec) / 1000; |
28a35d8a HE |
674 | |
675 | if (running_msec < limit_msec && numchunks < 32767) | |
676 | return FALSE; | |
677 | ||
fefa1800 | 678 | /* Stop acqusition. */ |
28a35d8a HE |
679 | sigma_set_register(WRITE_MODE, 0x11); |
680 | ||
fefa1800 | 681 | /* Set SDRAM Read Enable. */ |
28a35d8a HE |
682 | sigma_set_register(WRITE_MODE, 0x02); |
683 | ||
fefa1800 | 684 | /* Get the current position. */ |
28a35d8a HE |
685 | sigma_read_pos(&stoppos, &triggerpos); |
686 | ||
f78898e9 HE |
687 | /* Read mode status. We will care for this later. */ |
688 | sigma_get_register(READ_MODE); | |
689 | ||
fefa1800 | 690 | /* Download sample data. */ |
28a35d8a | 691 | for (curchunk = 0; curchunk < numchunks;) { |
fefa1800 | 692 | newchunks = MIN(chunks_per_read, numchunks - curchunk); |
28a35d8a HE |
693 | |
694 | g_message("Downloading sample data: %.0f %%", | |
fefa1800 | 695 | 100.0 * curchunk / numchunks); |
28a35d8a HE |
696 | |
697 | bufsz = sigma_read_dram(curchunk, newchunks, buf); | |
698 | ||
fefa1800 UH |
699 | /* Find first ts. */ |
700 | if (curchunk == 0) | |
701 | lastts = *(uint16_t *) buf - 1; | |
28a35d8a | 702 | |
fefa1800 | 703 | /* Decode chunks and send them to sigrok. */ |
28a35d8a HE |
704 | for (i = 0; i < newchunks; ++i) { |
705 | decode_chunk_ts(buf + (i * CHUNK_SIZE), | |
706 | &lastts, &lastsample, user_data); | |
707 | } | |
708 | ||
709 | curchunk += newchunks; | |
710 | } | |
711 | ||
712 | /* End of data */ | |
713 | packet.type = DF_END; | |
714 | packet.length = 0; | |
715 | session_bus(user_data, &packet); | |
716 | ||
717 | return TRUE; | |
718 | } | |
719 | ||
720 | static int hw_start_acquisition(int device_index, gpointer session_device_id) | |
721 | { | |
722 | struct sigrok_device_instance *sdi; | |
723 | struct datafeed_packet packet; | |
724 | struct datafeed_header header; | |
fefa1800 | 725 | uint8_t trigger_option[2] = { 0x38, 0x00 }; |
28a35d8a HE |
726 | |
727 | session_device_id = session_device_id; | |
728 | ||
729 | if (!(sdi = get_sigrok_device_instance(device_instances, device_index))) | |
730 | return SIGROK_ERR; | |
731 | ||
732 | device_index = device_index; | |
733 | ||
e8397563 HE |
734 | if (cur_firmware == -1) { |
735 | /* Samplerate has not been set. Default to 200 MHz */ | |
736 | set_samplerate(sdi, 200); | |
737 | } | |
738 | ||
fefa1800 | 739 | /* Setup trigger (by trigger-in). */ |
28a35d8a HE |
740 | sigma_set_register(WRITE_TRIGGER_SELECT1, 0x20); |
741 | ||
fefa1800 | 742 | /* More trigger setup. */ |
28a35d8a | 743 | sigma_write_register(WRITE_TRIGGER_OPTION, |
fefa1800 | 744 | trigger_option, sizeof(trigger_option)); |
28a35d8a | 745 | |
fefa1800 | 746 | /* Trigger normal (falling edge). */ |
28a35d8a HE |
747 | sigma_set_register(WRITE_TRIGGER_SELECT1, 0x08); |
748 | ||
edca2c5c HE |
749 | /* Set clock select register. */ |
750 | if (cur_samplerate == MHZ(200)) | |
751 | /* Enable 4 probes. */ | |
752 | sigma_set_register(WRITE_CLOCK_SELECT, 0xf0); | |
753 | else if (cur_samplerate == MHZ(100)) | |
754 | /* Enable 8 probes. */ | |
755 | sigma_set_register(WRITE_CLOCK_SELECT, 0x00); | |
756 | else { | |
757 | /* | |
758 | * 50 MHz mode (or fraction thereof) | |
759 | * Any fraction down to 50 MHz / 256 can be used, | |
760 | * but is not suppoted by Sigrok API. | |
761 | */ | |
762 | ||
763 | int frac = MHZ(50) / cur_samplerate - 1; | |
764 | ||
765 | struct clockselect_50 clockselect = { | |
766 | .async = 0, | |
767 | .fraction = frac, | |
768 | .disabled_probes = 0, | |
769 | }; | |
770 | ||
771 | sigma_write_register(WRITE_CLOCK_SELECT, | |
772 | (uint8_t *) &clockselect, | |
773 | sizeof(clockselect)); | |
774 | } | |
775 | ||
28a35d8a | 776 | |
fefa1800 | 777 | /* Setup maximum post trigger time. */ |
28a35d8a HE |
778 | sigma_set_register(WRITE_POST_TRIGGER, 0xff); |
779 | ||
fefa1800 | 780 | /* Start acqusition (software trigger start). */ |
28a35d8a HE |
781 | gettimeofday(&start_tv, 0); |
782 | sigma_set_register(WRITE_MODE, 0x0d); | |
783 | ||
fefa1800 | 784 | /* Add capture source. */ |
28a35d8a HE |
785 | source_add(0, G_IO_IN, 10, receive_data, session_device_id); |
786 | ||
787 | receive_data(0, 1, session_device_id); | |
788 | ||
789 | /* Send header packet to the session bus. */ | |
790 | packet.type = DF_HEADER; | |
791 | packet.length = sizeof(struct datafeed_header); | |
792 | packet.payload = &header; | |
793 | header.feed_version = 1; | |
794 | gettimeofday(&header.starttime, NULL); | |
795 | header.samplerate = cur_samplerate; | |
796 | header.protocol_id = PROTO_RAW; | |
edca2c5c | 797 | header.num_probes = num_probes; |
28a35d8a HE |
798 | session_bus(session_device_id, &packet); |
799 | ||
800 | return SIGROK_OK; | |
801 | } | |
802 | ||
28a35d8a HE |
803 | static void hw_stop_acquisition(int device_index, gpointer session_device_id) |
804 | { | |
805 | device_index = device_index; | |
806 | session_device_id = session_device_id; | |
807 | ||
fefa1800 | 808 | /* Stop acquisition. */ |
28a35d8a HE |
809 | sigma_set_register(WRITE_MODE, 0x11); |
810 | ||
811 | // XXX Set some state to indicate that data should be sent to sigrok | |
812 | // Now, we just wait for timeout | |
813 | } | |
814 | ||
28a35d8a HE |
815 | struct device_plugin asix_sigma_plugin_info = { |
816 | "asix-sigma", | |
817 | 1, | |
818 | hw_init, | |
819 | hw_cleanup, | |
28a35d8a HE |
820 | hw_opendev, |
821 | hw_closedev, | |
822 | hw_get_device_info, | |
823 | hw_get_status, | |
824 | hw_get_capabilities, | |
825 | hw_set_configuration, | |
826 | hw_start_acquisition, | |
827 | hw_stop_acquisition | |
828 | }; |