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Commit | Line | Data |
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28a35d8a HE |
1 | /* |
2 | * This file is part of the sigrok project. | |
3 | * | |
868501fa | 4 | * Copyright (C) 2010-2012 Håvard Espeland <gus@ping.uio.no>, |
911f1834 UH |
5 | * Copyright (C) 2010 Martin Stensgård <mastensg@ping.uio.no> |
6 | * Copyright (C) 2010 Carl Henrik Lunde <chlunde@ping.uio.no> | |
28a35d8a HE |
7 | * |
8 | * This program is free software: you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation, either version 3 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
20 | */ | |
21 | ||
911f1834 | 22 | /* |
6352d030 | 23 | * ASIX SIGMA/SIGMA2 logic analyzer driver |
911f1834 UH |
24 | */ |
25 | ||
3bbd9849 UH |
26 | #include <glib.h> |
27 | #include <glib/gstdio.h> | |
28a35d8a HE |
28 | #include <ftdi.h> |
29 | #include <string.h> | |
45c59c8b BV |
30 | #include "libsigrok.h" |
31 | #include "libsigrok-internal.h" | |
28a35d8a HE |
32 | #include "asix-sigma.h" |
33 | ||
34 | #define USB_VENDOR 0xa600 | |
35 | #define USB_PRODUCT 0xa000 | |
36 | #define USB_DESCRIPTION "ASIX SIGMA" | |
37 | #define USB_VENDOR_NAME "ASIX" | |
38 | #define USB_MODEL_NAME "SIGMA" | |
39 | #define USB_MODEL_VERSION "" | |
ee492173 | 40 | #define TRIGGER_TYPES "rf10" |
464d12c7 | 41 | #define NUM_PROBES 16 |
28a35d8a | 42 | |
ed300b9f BV |
43 | SR_PRIV struct sr_dev_driver asix_sigma_driver_info; |
44 | static struct sr_dev_driver *adi = &asix_sigma_driver_info; | |
28a35d8a | 45 | |
a533743d | 46 | static const uint64_t supported_samplerates[] = { |
59df0c77 UH |
47 | SR_KHZ(200), |
48 | SR_KHZ(250), | |
49 | SR_KHZ(500), | |
50 | SR_MHZ(1), | |
51 | SR_MHZ(5), | |
52 | SR_MHZ(10), | |
53 | SR_MHZ(25), | |
54 | SR_MHZ(50), | |
55 | SR_MHZ(100), | |
56 | SR_MHZ(200), | |
28a35d8a HE |
57 | 0, |
58 | }; | |
59 | ||
d261dbbf UH |
60 | /* |
61 | * Probe numbers seem to go from 1-16, according to this image: | |
62 | * http://tools.asix.net/img/sigma_sigmacab_pins_720.jpg | |
63 | * (the cable has two additional GND pins, and a TI and TO pin) | |
64 | */ | |
c37d2b1b | 65 | static const char *probe_names[NUM_PROBES + 1] = { |
464d12c7 KS |
66 | "1", |
67 | "2", | |
68 | "3", | |
69 | "4", | |
70 | "5", | |
71 | "6", | |
72 | "7", | |
73 | "8", | |
74 | "9", | |
75 | "10", | |
76 | "11", | |
77 | "12", | |
78 | "13", | |
79 | "14", | |
80 | "15", | |
d261dbbf | 81 | "16", |
464d12c7 KS |
82 | NULL, |
83 | }; | |
84 | ||
a533743d | 85 | static const struct sr_samplerates samplerates = { |
590b9f9a UH |
86 | 0, |
87 | 0, | |
88 | 0, | |
28a35d8a HE |
89 | supported_samplerates, |
90 | }; | |
91 | ||
915f7cc8 | 92 | static const int hwcaps[] = { |
5a2326a7 UH |
93 | SR_HWCAP_LOGIC_ANALYZER, |
94 | SR_HWCAP_SAMPLERATE, | |
95 | SR_HWCAP_CAPTURE_RATIO, | |
96 | SR_HWCAP_PROBECONFIG, | |
28a35d8a | 97 | |
5a2326a7 | 98 | SR_HWCAP_LIMIT_MSEC, |
28a35d8a HE |
99 | 0, |
100 | }; | |
101 | ||
fefa1800 UH |
102 | /* Force the FPGA to reboot. */ |
103 | static uint8_t suicide[] = { | |
104 | 0x84, 0x84, 0x88, 0x84, 0x88, 0x84, 0x88, 0x84, | |
105 | }; | |
106 | ||
107 | /* Prepare to upload firmware (FPGA specific). */ | |
108 | static uint8_t init[] = { | |
109 | 0x03, 0x03, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, | |
110 | }; | |
111 | ||
112 | /* Initialize the logic analyzer mode. */ | |
113 | static uint8_t logic_mode_start[] = { | |
114 | 0x00, 0x40, 0x0f, 0x25, 0x35, 0x40, | |
115 | 0x2a, 0x3a, 0x40, 0x03, 0x20, 0x38, | |
116 | }; | |
117 | ||
eec5275e | 118 | static const char *firmware_files[] = { |
a8116d76 HE |
119 | "asix-sigma-50.fw", /* 50 MHz, supports 8 bit fractions */ |
120 | "asix-sigma-100.fw", /* 100 MHz */ | |
121 | "asix-sigma-200.fw", /* 200 MHz */ | |
ed09fd07 | 122 | "asix-sigma-50sync.fw", /* Synchronous clock from pin */ |
a8116d76 | 123 | "asix-sigma-phasor.fw", /* Frequency counter */ |
f6564c8d HE |
124 | }; |
125 | ||
3cd3a20b | 126 | static int hw_dev_acquisition_stop(int dev_index, void *cb_data); |
6aac7737 | 127 | |
ea9cfed7 | 128 | static int sigma_read(void *buf, size_t size, struct context *ctx) |
28a35d8a HE |
129 | { |
130 | int ret; | |
fefa1800 | 131 | |
ea9cfed7 | 132 | ret = ftdi_read_data(&ctx->ftdic, (unsigned char *)buf, size); |
28a35d8a | 133 | if (ret < 0) { |
7b48d6e1 | 134 | sr_err("sigma: ftdi_read_data failed: %s", |
ea9cfed7 | 135 | ftdi_get_error_string(&ctx->ftdic)); |
28a35d8a HE |
136 | } |
137 | ||
138 | return ret; | |
139 | } | |
140 | ||
ea9cfed7 | 141 | static int sigma_write(void *buf, size_t size, struct context *ctx) |
28a35d8a HE |
142 | { |
143 | int ret; | |
fefa1800 | 144 | |
ea9cfed7 | 145 | ret = ftdi_write_data(&ctx->ftdic, (unsigned char *)buf, size); |
28a35d8a | 146 | if (ret < 0) { |
7b48d6e1 | 147 | sr_err("sigma: ftdi_write_data failed: %s", |
ea9cfed7 | 148 | ftdi_get_error_string(&ctx->ftdic)); |
fefa1800 | 149 | } else if ((size_t) ret != size) { |
0aeb0ccd | 150 | sr_err("sigma: ftdi_write_data did not complete write."); |
28a35d8a HE |
151 | } |
152 | ||
153 | return ret; | |
154 | } | |
155 | ||
99965709 | 156 | static int sigma_write_register(uint8_t reg, uint8_t *data, size_t len, |
ea9cfed7 | 157 | struct context *ctx) |
28a35d8a HE |
158 | { |
159 | size_t i; | |
160 | uint8_t buf[len + 2]; | |
161 | int idx = 0; | |
162 | ||
163 | buf[idx++] = REG_ADDR_LOW | (reg & 0xf); | |
164 | buf[idx++] = REG_ADDR_HIGH | (reg >> 4); | |
165 | ||
fefa1800 | 166 | for (i = 0; i < len; ++i) { |
28a35d8a HE |
167 | buf[idx++] = REG_DATA_LOW | (data[i] & 0xf); |
168 | buf[idx++] = REG_DATA_HIGH_WRITE | (data[i] >> 4); | |
169 | } | |
170 | ||
ea9cfed7 | 171 | return sigma_write(buf, idx, ctx); |
28a35d8a HE |
172 | } |
173 | ||
ea9cfed7 | 174 | static int sigma_set_register(uint8_t reg, uint8_t value, struct context *ctx) |
28a35d8a | 175 | { |
ea9cfed7 | 176 | return sigma_write_register(reg, &value, 1, ctx); |
28a35d8a HE |
177 | } |
178 | ||
99965709 | 179 | static int sigma_read_register(uint8_t reg, uint8_t *data, size_t len, |
ea9cfed7 | 180 | struct context *ctx) |
28a35d8a HE |
181 | { |
182 | uint8_t buf[3]; | |
fefa1800 | 183 | |
28a35d8a HE |
184 | buf[0] = REG_ADDR_LOW | (reg & 0xf); |
185 | buf[1] = REG_ADDR_HIGH | (reg >> 4); | |
28a35d8a HE |
186 | buf[2] = REG_READ_ADDR; |
187 | ||
ea9cfed7 | 188 | sigma_write(buf, sizeof(buf), ctx); |
28a35d8a | 189 | |
ea9cfed7 | 190 | return sigma_read(data, len, ctx); |
28a35d8a HE |
191 | } |
192 | ||
ea9cfed7 | 193 | static uint8_t sigma_get_register(uint8_t reg, struct context *ctx) |
28a35d8a HE |
194 | { |
195 | uint8_t value; | |
fefa1800 | 196 | |
ea9cfed7 | 197 | if (1 != sigma_read_register(reg, &value, 1, ctx)) { |
7b48d6e1 | 198 | sr_err("sigma: sigma_get_register: 1 byte expected"); |
28a35d8a HE |
199 | return 0; |
200 | } | |
201 | ||
202 | return value; | |
203 | } | |
204 | ||
99965709 | 205 | static int sigma_read_pos(uint32_t *stoppos, uint32_t *triggerpos, |
ea9cfed7 | 206 | struct context *ctx) |
28a35d8a HE |
207 | { |
208 | uint8_t buf[] = { | |
209 | REG_ADDR_LOW | READ_TRIGGER_POS_LOW, | |
210 | ||
211 | REG_READ_ADDR | NEXT_REG, | |
212 | REG_READ_ADDR | NEXT_REG, | |
213 | REG_READ_ADDR | NEXT_REG, | |
214 | REG_READ_ADDR | NEXT_REG, | |
215 | REG_READ_ADDR | NEXT_REG, | |
216 | REG_READ_ADDR | NEXT_REG, | |
217 | }; | |
28a35d8a HE |
218 | uint8_t result[6]; |
219 | ||
ea9cfed7 | 220 | sigma_write(buf, sizeof(buf), ctx); |
28a35d8a | 221 | |
ea9cfed7 | 222 | sigma_read(result, sizeof(result), ctx); |
28a35d8a HE |
223 | |
224 | *triggerpos = result[0] | (result[1] << 8) | (result[2] << 16); | |
225 | *stoppos = result[3] | (result[4] << 8) | (result[5] << 16); | |
226 | ||
57bbf56b HE |
227 | /* Not really sure why this must be done, but according to spec. */ |
228 | if ((--*stoppos & 0x1ff) == 0x1ff) | |
229 | stoppos -= 64; | |
230 | ||
231 | if ((*--triggerpos & 0x1ff) == 0x1ff) | |
232 | triggerpos -= 64; | |
233 | ||
28a35d8a HE |
234 | return 1; |
235 | } | |
236 | ||
99965709 | 237 | static int sigma_read_dram(uint16_t startchunk, size_t numchunks, |
ea9cfed7 | 238 | uint8_t *data, struct context *ctx) |
28a35d8a HE |
239 | { |
240 | size_t i; | |
241 | uint8_t buf[4096]; | |
242 | int idx = 0; | |
243 | ||
fefa1800 | 244 | /* Send the startchunk. Index start with 1. */ |
28a35d8a HE |
245 | buf[0] = startchunk >> 8; |
246 | buf[1] = startchunk & 0xff; | |
ea9cfed7 | 247 | sigma_write_register(WRITE_MEMROW, buf, 2, ctx); |
28a35d8a | 248 | |
fefa1800 | 249 | /* Read the DRAM. */ |
28a35d8a HE |
250 | buf[idx++] = REG_DRAM_BLOCK; |
251 | buf[idx++] = REG_DRAM_WAIT_ACK; | |
252 | ||
253 | for (i = 0; i < numchunks; ++i) { | |
fefa1800 UH |
254 | /* Alternate bit to copy from DRAM to cache. */ |
255 | if (i != (numchunks - 1)) | |
256 | buf[idx++] = REG_DRAM_BLOCK | (((i + 1) % 2) << 4); | |
28a35d8a HE |
257 | |
258 | buf[idx++] = REG_DRAM_BLOCK_DATA | ((i % 2) << 4); | |
259 | ||
fefa1800 | 260 | if (i != (numchunks - 1)) |
28a35d8a HE |
261 | buf[idx++] = REG_DRAM_WAIT_ACK; |
262 | } | |
263 | ||
ea9cfed7 | 264 | sigma_write(buf, idx, ctx); |
28a35d8a | 265 | |
ea9cfed7 | 266 | return sigma_read(data, numchunks * CHUNK_SIZE, ctx); |
28a35d8a HE |
267 | } |
268 | ||
4ae1f451 | 269 | /* Upload trigger look-up tables to Sigma. */ |
ea9cfed7 | 270 | static int sigma_write_trigger_lut(struct triggerlut *lut, struct context *ctx) |
ee492173 HE |
271 | { |
272 | int i; | |
273 | uint8_t tmp[2]; | |
274 | uint16_t bit; | |
275 | ||
276 | /* Transpose the table and send to Sigma. */ | |
277 | for (i = 0; i < 16; ++i) { | |
278 | bit = 1 << i; | |
279 | ||
280 | tmp[0] = tmp[1] = 0; | |
281 | ||
282 | if (lut->m2d[0] & bit) | |
283 | tmp[0] |= 0x01; | |
284 | if (lut->m2d[1] & bit) | |
285 | tmp[0] |= 0x02; | |
286 | if (lut->m2d[2] & bit) | |
287 | tmp[0] |= 0x04; | |
288 | if (lut->m2d[3] & bit) | |
289 | tmp[0] |= 0x08; | |
290 | ||
291 | if (lut->m3 & bit) | |
292 | tmp[0] |= 0x10; | |
293 | if (lut->m3s & bit) | |
294 | tmp[0] |= 0x20; | |
295 | if (lut->m4 & bit) | |
296 | tmp[0] |= 0x40; | |
297 | ||
298 | if (lut->m0d[0] & bit) | |
299 | tmp[1] |= 0x01; | |
300 | if (lut->m0d[1] & bit) | |
301 | tmp[1] |= 0x02; | |
302 | if (lut->m0d[2] & bit) | |
303 | tmp[1] |= 0x04; | |
304 | if (lut->m0d[3] & bit) | |
305 | tmp[1] |= 0x08; | |
306 | ||
307 | if (lut->m1d[0] & bit) | |
308 | tmp[1] |= 0x10; | |
309 | if (lut->m1d[1] & bit) | |
310 | tmp[1] |= 0x20; | |
311 | if (lut->m1d[2] & bit) | |
312 | tmp[1] |= 0x40; | |
313 | if (lut->m1d[3] & bit) | |
314 | tmp[1] |= 0x80; | |
315 | ||
99965709 | 316 | sigma_write_register(WRITE_TRIGGER_SELECT0, tmp, sizeof(tmp), |
ea9cfed7 UH |
317 | ctx); |
318 | sigma_set_register(WRITE_TRIGGER_SELECT1, 0x30 | i, ctx); | |
ee492173 HE |
319 | } |
320 | ||
321 | /* Send the parameters */ | |
322 | sigma_write_register(WRITE_TRIGGER_SELECT0, (uint8_t *) &lut->params, | |
ea9cfed7 | 323 | sizeof(lut->params), ctx); |
ee492173 | 324 | |
e46b8fb1 | 325 | return SR_OK; |
ee492173 HE |
326 | } |
327 | ||
fefa1800 | 328 | /* Generate the bitbang stream for programming the FPGA. */ |
28a35d8a | 329 | static int bin2bitbang(const char *filename, |
fefa1800 | 330 | unsigned char **buf, size_t *buf_size) |
28a35d8a | 331 | { |
fefa1800 | 332 | FILE *f; |
e3fff420 | 333 | unsigned long file_size; |
28a35d8a HE |
334 | unsigned long offset = 0; |
335 | unsigned char *p; | |
e3fff420 HE |
336 | uint8_t *firmware; |
337 | unsigned long fwsize = 0; | |
28a35d8a HE |
338 | const int buffer_size = 65536; |
339 | size_t i; | |
e3fff420 | 340 | int c, bit, v; |
fefa1800 | 341 | uint32_t imm = 0x3f6df2ab; |
28a35d8a | 342 | |
868d8cef | 343 | f = g_fopen(filename, "rb"); |
28a35d8a | 344 | if (!f) { |
7b48d6e1 | 345 | sr_err("sigma: g_fopen(\"%s\", \"rb\")", filename); |
b53738ba | 346 | return SR_ERR; |
28a35d8a HE |
347 | } |
348 | ||
349 | if (-1 == fseek(f, 0, SEEK_END)) { | |
7b48d6e1 | 350 | sr_err("sigma: fseek on %s failed", filename); |
28a35d8a | 351 | fclose(f); |
b53738ba | 352 | return SR_ERR; |
28a35d8a HE |
353 | } |
354 | ||
355 | file_size = ftell(f); | |
356 | ||
357 | fseek(f, 0, SEEK_SET); | |
358 | ||
b53738ba | 359 | if (!(firmware = g_try_malloc(buffer_size))) { |
340cfac0 | 360 | sr_err("sigma: %s: firmware malloc failed", __func__); |
12ad53f5 | 361 | fclose(f); |
b53738ba | 362 | return SR_ERR_MALLOC; |
28a35d8a HE |
363 | } |
364 | ||
28a35d8a HE |
365 | while ((c = getc(f)) != EOF) { |
366 | imm = (imm + 0xa853753) % 177 + (imm * 0x8034052); | |
e3fff420 | 367 | firmware[fwsize++] = c ^ imm; |
28a35d8a HE |
368 | } |
369 | fclose(f); | |
370 | ||
e3fff420 HE |
371 | if(fwsize != file_size) { |
372 | sr_err("sigma: %s: Error reading firmware", filename); | |
373 | fclose(f); | |
374 | g_free(firmware); | |
375 | return SR_ERR; | |
28a35d8a HE |
376 | } |
377 | ||
28a35d8a HE |
378 | *buf_size = fwsize * 2 * 8; |
379 | ||
b53738ba | 380 | *buf = p = (unsigned char *)g_try_malloc(*buf_size); |
28a35d8a | 381 | if (!p) { |
340cfac0 | 382 | sr_err("sigma: %s: buf/p malloc failed", __func__); |
12ad53f5 | 383 | g_free(firmware); |
b53738ba | 384 | return SR_ERR_MALLOC; |
28a35d8a HE |
385 | } |
386 | ||
387 | for (i = 0; i < fwsize; ++i) { | |
28a35d8a | 388 | for (bit = 7; bit >= 0; --bit) { |
fefa1800 | 389 | v = firmware[i] & 1 << bit ? 0x40 : 0x00; |
28a35d8a HE |
390 | p[offset++] = v | 0x01; |
391 | p[offset++] = v; | |
392 | } | |
393 | } | |
394 | ||
395 | g_free(firmware); | |
396 | ||
397 | if (offset != *buf_size) { | |
398 | g_free(*buf); | |
7b48d6e1 | 399 | sr_err("sigma: Error reading firmware %s " |
0aeb0ccd | 400 | "offset=%ld, file_size=%ld, buf_size=%zd.", |
133a37bf | 401 | filename, offset, file_size, *buf_size); |
28a35d8a | 402 | |
b53738ba | 403 | return SR_ERR; |
28a35d8a HE |
404 | } |
405 | ||
b53738ba | 406 | return SR_OK; |
28a35d8a HE |
407 | } |
408 | ||
40dda2c3 | 409 | static int hw_init(void) |
61136ea6 BV |
410 | { |
411 | ||
412 | /* Nothing to do. */ | |
413 | ||
414 | return SR_OK; | |
415 | } | |
416 | ||
417 | static int hw_scan(void) | |
28a35d8a | 418 | { |
d68e2d1a | 419 | struct sr_dev_inst *sdi; |
ea9cfed7 | 420 | struct context *ctx; |
e3fff420 HE |
421 | struct ftdi_device_list *devlist; |
422 | char serial_txt[10]; | |
423 | uint32_t serial; | |
28a35d8a | 424 | |
ea9cfed7 UH |
425 | if (!(ctx = g_try_malloc(sizeof(struct context)))) { |
426 | sr_err("sigma: %s: ctx malloc failed", __func__); | |
e3fff420 | 427 | return SR_ERR_MALLOC; |
b53738ba | 428 | } |
99965709 | 429 | |
ea9cfed7 | 430 | ftdi_init(&ctx->ftdic); |
28a35d8a | 431 | |
fefa1800 | 432 | /* Look for SIGMAs. */ |
e3fff420 HE |
433 | |
434 | if (ftdi_usb_find_all(&ctx->ftdic, &devlist, | |
6352d030 | 435 | USB_VENDOR, USB_PRODUCT) <= 0) |
99965709 HE |
436 | goto free; |
437 | ||
e3fff420 HE |
438 | /* Make sure it's a version 1 or 2 SIGMA. */ |
439 | ftdi_usb_get_strings(&ctx->ftdic, devlist->dev, NULL, 0, NULL, 0, | |
6352d030 | 440 | serial_txt, sizeof(serial_txt)); |
e3fff420 HE |
441 | sscanf(serial_txt, "%x", &serial); |
442 | ||
6352d030 | 443 | if (serial < 0xa6010000 || serial > 0xa602ffff) { |
e3fff420 | 444 | sr_err("sigma: Only SIGMA and SIGMA2 are supported " |
6352d030 | 445 | "in this version of sigrok."); |
e3fff420 HE |
446 | goto free; |
447 | } | |
448 | ||
449 | sr_info("Found ASIX SIGMA - Serial: %s", serial_txt); | |
450 | ||
ea9cfed7 UH |
451 | ctx->cur_samplerate = 0; |
452 | ctx->period_ps = 0; | |
453 | ctx->limit_msec = 0; | |
454 | ctx->cur_firmware = -1; | |
455 | ctx->num_probes = 0; | |
456 | ctx->samples_per_event = 0; | |
457 | ctx->capture_ratio = 50; | |
458 | ctx->use_triggers = 0; | |
28a35d8a | 459 | |
fefa1800 | 460 | /* Register SIGMA device. */ |
d68e2d1a UH |
461 | if (!(sdi = sr_dev_inst_new(0, SR_ST_INITIALIZING, USB_VENDOR_NAME, |
462 | USB_MODEL_NAME, USB_MODEL_VERSION))) { | |
463 | sr_err("sigma: %s: sdi was NULL", __func__); | |
99965709 | 464 | goto free; |
d68e2d1a | 465 | } |
99965709 | 466 | |
ea9cfed7 | 467 | sdi->priv = ctx; |
28a35d8a | 468 | |
ed300b9f | 469 | adi->instances = g_slist_append(adi->instances, sdi); |
28a35d8a | 470 | |
fefa1800 | 471 | /* We will open the device again when we need it. */ |
e3fff420 | 472 | ftdi_list_free(&devlist); |
28a35d8a HE |
473 | |
474 | return 1; | |
ea9cfed7 | 475 | |
99965709 | 476 | free: |
ea9cfed7 | 477 | g_free(ctx); |
99965709 | 478 | return 0; |
28a35d8a HE |
479 | } |
480 | ||
ea9cfed7 | 481 | static int upload_firmware(int firmware_idx, struct context *ctx) |
28a35d8a HE |
482 | { |
483 | int ret; | |
484 | unsigned char *buf; | |
485 | unsigned char pins; | |
486 | size_t buf_size; | |
28a35d8a | 487 | unsigned char result[32]; |
e8397563 | 488 | char firmware_path[128]; |
28a35d8a | 489 | |
fefa1800 | 490 | /* Make sure it's an ASIX SIGMA. */ |
ea9cfed7 | 491 | if ((ret = ftdi_usb_open_desc(&ctx->ftdic, |
28a35d8a | 492 | USB_VENDOR, USB_PRODUCT, USB_DESCRIPTION, NULL)) < 0) { |
7b48d6e1 | 493 | sr_err("sigma: ftdi_usb_open failed: %s", |
ea9cfed7 | 494 | ftdi_get_error_string(&ctx->ftdic)); |
28a35d8a HE |
495 | return 0; |
496 | } | |
497 | ||
ea9cfed7 | 498 | if ((ret = ftdi_set_bitmode(&ctx->ftdic, 0xdf, BITMODE_BITBANG)) < 0) { |
7b48d6e1 | 499 | sr_err("sigma: ftdi_set_bitmode failed: %s", |
ea9cfed7 | 500 | ftdi_get_error_string(&ctx->ftdic)); |
28a35d8a HE |
501 | return 0; |
502 | } | |
503 | ||
fefa1800 | 504 | /* Four times the speed of sigmalogan - Works well. */ |
ea9cfed7 | 505 | if ((ret = ftdi_set_baudrate(&ctx->ftdic, 750000)) < 0) { |
7b48d6e1 | 506 | sr_err("sigma: ftdi_set_baudrate failed: %s", |
ea9cfed7 | 507 | ftdi_get_error_string(&ctx->ftdic)); |
28a35d8a HE |
508 | return 0; |
509 | } | |
510 | ||
fefa1800 | 511 | /* Force the FPGA to reboot. */ |
ea9cfed7 UH |
512 | sigma_write(suicide, sizeof(suicide), ctx); |
513 | sigma_write(suicide, sizeof(suicide), ctx); | |
514 | sigma_write(suicide, sizeof(suicide), ctx); | |
515 | sigma_write(suicide, sizeof(suicide), ctx); | |
28a35d8a | 516 | |
fefa1800 | 517 | /* Prepare to upload firmware (FPGA specific). */ |
ea9cfed7 | 518 | sigma_write(init, sizeof(init), ctx); |
28a35d8a | 519 | |
ea9cfed7 | 520 | ftdi_usb_purge_buffers(&ctx->ftdic); |
28a35d8a | 521 | |
fefa1800 | 522 | /* Wait until the FPGA asserts INIT_B. */ |
28a35d8a | 523 | while (1) { |
ea9cfed7 | 524 | ret = sigma_read(result, 1, ctx); |
28a35d8a HE |
525 | if (result[0] & 0x20) |
526 | break; | |
527 | } | |
528 | ||
9ddb2a12 | 529 | /* Prepare firmware. */ |
e8397563 | 530 | snprintf(firmware_path, sizeof(firmware_path), "%s/%s", FIRMWARE_DIR, |
f6564c8d HE |
531 | firmware_files[firmware_idx]); |
532 | ||
b53738ba | 533 | if ((ret = bin2bitbang(firmware_path, &buf, &buf_size)) != SR_OK) { |
7b48d6e1 | 534 | sr_err("sigma: An error occured while reading the firmware: %s", |
133a37bf | 535 | firmware_path); |
b53738ba | 536 | return ret; |
28a35d8a HE |
537 | } |
538 | ||
fefa1800 | 539 | /* Upload firmare. */ |
e3fff420 | 540 | sr_info("sigma: Uploading firmware %s", firmware_files[firmware_idx]); |
ea9cfed7 | 541 | sigma_write(buf, buf_size, ctx); |
28a35d8a HE |
542 | |
543 | g_free(buf); | |
544 | ||
ea9cfed7 | 545 | if ((ret = ftdi_set_bitmode(&ctx->ftdic, 0x00, BITMODE_RESET)) < 0) { |
7b48d6e1 | 546 | sr_err("sigma: ftdi_set_bitmode failed: %s", |
ea9cfed7 | 547 | ftdi_get_error_string(&ctx->ftdic)); |
e46b8fb1 | 548 | return SR_ERR; |
28a35d8a HE |
549 | } |
550 | ||
ea9cfed7 | 551 | ftdi_usb_purge_buffers(&ctx->ftdic); |
28a35d8a | 552 | |
fefa1800 | 553 | /* Discard garbage. */ |
ea9cfed7 | 554 | while (1 == sigma_read(&pins, 1, ctx)) |
28a35d8a HE |
555 | ; |
556 | ||
fefa1800 | 557 | /* Initialize the logic analyzer mode. */ |
ea9cfed7 | 558 | sigma_write(logic_mode_start, sizeof(logic_mode_start), ctx); |
28a35d8a | 559 | |
fefa1800 | 560 | /* Expect a 3 byte reply. */ |
ea9cfed7 | 561 | ret = sigma_read(result, 3, ctx); |
28a35d8a HE |
562 | if (ret != 3 || |
563 | result[0] != 0xa6 || result[1] != 0x55 || result[2] != 0xaa) { | |
7b48d6e1 | 564 | sr_err("sigma: Configuration failed. Invalid reply received."); |
e46b8fb1 | 565 | return SR_ERR; |
28a35d8a HE |
566 | } |
567 | ||
ea9cfed7 | 568 | ctx->cur_firmware = firmware_idx; |
f6564c8d | 569 | |
e3fff420 HE |
570 | sr_info("sigma: Firmware uploaded"); |
571 | ||
e46b8fb1 | 572 | return SR_OK; |
f6564c8d HE |
573 | } |
574 | ||
e7eb703f | 575 | static int hw_dev_open(int dev_index) |
f6564c8d | 576 | { |
d68e2d1a | 577 | struct sr_dev_inst *sdi; |
ea9cfed7 | 578 | struct context *ctx; |
f6564c8d HE |
579 | int ret; |
580 | ||
ed300b9f | 581 | if (!(sdi = sr_dev_inst_get(adi->instances, dev_index))) |
e46b8fb1 | 582 | return SR_ERR; |
99965709 | 583 | |
ea9cfed7 | 584 | ctx = sdi->priv; |
99965709 | 585 | |
9ddb2a12 | 586 | /* Make sure it's an ASIX SIGMA. */ |
ea9cfed7 | 587 | if ((ret = ftdi_usb_open_desc(&ctx->ftdic, |
f6564c8d HE |
588 | USB_VENDOR, USB_PRODUCT, USB_DESCRIPTION, NULL)) < 0) { |
589 | ||
7b48d6e1 | 590 | sr_err("sigma: ftdi_usb_open failed: %s", |
ea9cfed7 | 591 | ftdi_get_error_string(&ctx->ftdic)); |
f6564c8d HE |
592 | |
593 | return 0; | |
594 | } | |
28a35d8a | 595 | |
5a2326a7 | 596 | sdi->status = SR_ST_ACTIVE; |
28a35d8a | 597 | |
e46b8fb1 | 598 | return SR_OK; |
f6564c8d HE |
599 | } |
600 | ||
d68e2d1a | 601 | static int set_samplerate(struct sr_dev_inst *sdi, uint64_t samplerate) |
f6564c8d | 602 | { |
e8397563 | 603 | int i, ret; |
ea9cfed7 | 604 | struct context *ctx = sdi->priv; |
f6564c8d HE |
605 | |
606 | for (i = 0; supported_samplerates[i]; i++) { | |
607 | if (supported_samplerates[i] == samplerate) | |
608 | break; | |
609 | } | |
610 | if (supported_samplerates[i] == 0) | |
e46b8fb1 | 611 | return SR_ERR_SAMPLERATE; |
f6564c8d | 612 | |
59df0c77 | 613 | if (samplerate <= SR_MHZ(50)) { |
ea9cfed7 UH |
614 | ret = upload_firmware(0, ctx); |
615 | ctx->num_probes = 16; | |
e8397563 | 616 | } |
59df0c77 | 617 | if (samplerate == SR_MHZ(100)) { |
ea9cfed7 UH |
618 | ret = upload_firmware(1, ctx); |
619 | ctx->num_probes = 8; | |
f78898e9 | 620 | } |
59df0c77 | 621 | else if (samplerate == SR_MHZ(200)) { |
ea9cfed7 UH |
622 | ret = upload_firmware(2, ctx); |
623 | ctx->num_probes = 4; | |
f78898e9 | 624 | } |
f6564c8d | 625 | |
ea9cfed7 UH |
626 | ctx->cur_samplerate = samplerate; |
627 | ctx->period_ps = 1000000000000 / samplerate; | |
628 | ctx->samples_per_event = 16 / ctx->num_probes; | |
629 | ctx->state.state = SIGMA_IDLE; | |
f6564c8d | 630 | |
e8397563 | 631 | return ret; |
28a35d8a HE |
632 | } |
633 | ||
c53d793f HE |
634 | /* |
635 | * In 100 and 200 MHz mode, only a single pin rising/falling can be | |
636 | * set as trigger. In other modes, two rising/falling triggers can be set, | |
637 | * in addition to value/mask trigger for any number of probes. | |
638 | * | |
639 | * The Sigma supports complex triggers using boolean expressions, but this | |
640 | * has not been implemented yet. | |
641 | */ | |
1b79df2f | 642 | static int configure_probes(struct sr_dev_inst *sdi, const GSList *probes) |
57bbf56b | 643 | { |
ea9cfed7 | 644 | struct context *ctx = sdi->priv; |
1b79df2f JH |
645 | const struct sr_probe *probe; |
646 | const GSList *l; | |
57bbf56b | 647 | int trigger_set = 0; |
a42aec7f | 648 | int probebit; |
57bbf56b | 649 | |
ea9cfed7 | 650 | memset(&ctx->trigger, 0, sizeof(struct sigma_trigger)); |
eec5275e | 651 | |
57bbf56b | 652 | for (l = probes; l; l = l->next) { |
1afe8989 | 653 | probe = (struct sr_probe *)l->data; |
a42aec7f | 654 | probebit = 1 << (probe->index - 1); |
57bbf56b HE |
655 | |
656 | if (!probe->enabled || !probe->trigger) | |
657 | continue; | |
658 | ||
ea9cfed7 | 659 | if (ctx->cur_samplerate >= SR_MHZ(100)) { |
c53d793f | 660 | /* Fast trigger support. */ |
ee492173 | 661 | if (trigger_set) { |
7b48d6e1 | 662 | sr_err("sigma: ASIX SIGMA only supports a single " |
133a37bf | 663 | "pin trigger in 100 and 200MHz mode."); |
e46b8fb1 | 664 | return SR_ERR; |
ee492173 HE |
665 | } |
666 | if (probe->trigger[0] == 'f') | |
ea9cfed7 | 667 | ctx->trigger.fallingmask |= probebit; |
ee492173 | 668 | else if (probe->trigger[0] == 'r') |
ea9cfed7 | 669 | ctx->trigger.risingmask |= probebit; |
ee492173 | 670 | else { |
7b48d6e1 | 671 | sr_err("sigma: ASIX SIGMA only supports " |
133a37bf UH |
672 | "rising/falling trigger in 100 " |
673 | "and 200MHz mode."); | |
e46b8fb1 | 674 | return SR_ERR; |
ee492173 | 675 | } |
57bbf56b | 676 | |
c53d793f | 677 | ++trigger_set; |
ee492173 | 678 | } else { |
c53d793f HE |
679 | /* Simple trigger support (event). */ |
680 | if (probe->trigger[0] == '1') { | |
ea9cfed7 UH |
681 | ctx->trigger.simplevalue |= probebit; |
682 | ctx->trigger.simplemask |= probebit; | |
c53d793f HE |
683 | } |
684 | else if (probe->trigger[0] == '0') { | |
ea9cfed7 UH |
685 | ctx->trigger.simplevalue &= ~probebit; |
686 | ctx->trigger.simplemask |= probebit; | |
c53d793f HE |
687 | } |
688 | else if (probe->trigger[0] == 'f') { | |
ea9cfed7 | 689 | ctx->trigger.fallingmask |= probebit; |
c53d793f HE |
690 | ++trigger_set; |
691 | } | |
692 | else if (probe->trigger[0] == 'r') { | |
ea9cfed7 | 693 | ctx->trigger.risingmask |= probebit; |
c53d793f HE |
694 | ++trigger_set; |
695 | } | |
ee492173 | 696 | |
ea9cfed7 UH |
697 | /* |
698 | * Actually, Sigma supports 2 rising/falling triggers, | |
699 | * but they are ORed and the current trigger syntax | |
700 | * does not permit ORed triggers. | |
701 | */ | |
98b8cbc1 | 702 | if (trigger_set > 1) { |
7b48d6e1 UH |
703 | sr_err("sigma: ASIX SIGMA only supports 1 " |
704 | "rising/falling triggers."); | |
e46b8fb1 | 705 | return SR_ERR; |
ee492173 | 706 | } |
ee492173 | 707 | } |
5b5ea7c6 HE |
708 | |
709 | if (trigger_set) | |
ea9cfed7 | 710 | ctx->use_triggers = 1; |
57bbf56b HE |
711 | } |
712 | ||
e46b8fb1 | 713 | return SR_OK; |
57bbf56b HE |
714 | } |
715 | ||
e7eb703f | 716 | static int hw_dev_close(int dev_index) |
28a35d8a | 717 | { |
d68e2d1a | 718 | struct sr_dev_inst *sdi; |
ea9cfed7 | 719 | struct context *ctx; |
28a35d8a | 720 | |
ed300b9f | 721 | if (!(sdi = sr_dev_inst_get(adi->instances, dev_index))) { |
340cfac0 | 722 | sr_err("sigma: %s: sdi was NULL", __func__); |
0abee507 | 723 | return SR_ERR_BUG; |
697785d1 | 724 | } |
9be9893e | 725 | |
ea9cfed7 | 726 | if (!(ctx = sdi->priv)) { |
340cfac0 | 727 | sr_err("sigma: %s: sdi->priv was NULL", __func__); |
0abee507 | 728 | return SR_ERR_BUG; |
9be9893e | 729 | } |
697785d1 UH |
730 | |
731 | /* TODO */ | |
732 | if (sdi->status == SR_ST_ACTIVE) | |
ea9cfed7 | 733 | ftdi_usb_close(&ctx->ftdic); |
697785d1 UH |
734 | |
735 | sdi->status = SR_ST_INACTIVE; | |
736 | ||
737 | return SR_OK; | |
28a35d8a HE |
738 | } |
739 | ||
57ab7d9f | 740 | static int hw_cleanup(void) |
28a35d8a | 741 | { |
99965709 | 742 | GSList *l; |
d68e2d1a | 743 | struct sr_dev_inst *sdi; |
57ab7d9f | 744 | int ret = SR_OK; |
99965709 HE |
745 | |
746 | /* Properly close all devices. */ | |
ed300b9f | 747 | for (l = adi->instances; l; l = l->next) { |
57ab7d9f UH |
748 | if (!(sdi = l->data)) { |
749 | /* Log error, but continue cleaning up the rest. */ | |
7b48d6e1 | 750 | sr_err("sigma: %s: sdi was NULL, continuing", __func__); |
57ab7d9f UH |
751 | ret = SR_ERR_BUG; |
752 | continue; | |
753 | } | |
d3683c42 | 754 | sr_dev_inst_free(sdi); |
99965709 | 755 | } |
ed300b9f BV |
756 | g_slist_free(adi->instances); |
757 | adi->instances = NULL; | |
57ab7d9f UH |
758 | |
759 | return ret; | |
28a35d8a HE |
760 | } |
761 | ||
b7f578be | 762 | static const void *hw_dev_info_get(int dev_index, int dev_info_id) |
28a35d8a | 763 | { |
d68e2d1a | 764 | struct sr_dev_inst *sdi; |
ea9cfed7 | 765 | struct context *ctx; |
b7f578be | 766 | const void *info = NULL; |
28a35d8a | 767 | |
ed300b9f | 768 | if (!(sdi = sr_dev_inst_get(adi->instances, dev_index))) { |
7b48d6e1 | 769 | sr_err("sigma: %s: sdi was NULL", __func__); |
28a35d8a HE |
770 | return NULL; |
771 | } | |
772 | ||
ea9cfed7 | 773 | ctx = sdi->priv; |
99965709 | 774 | |
bb7ef793 | 775 | switch (dev_info_id) { |
1d9a8a5f | 776 | case SR_DI_INST: |
28a35d8a HE |
777 | info = sdi; |
778 | break; | |
5a2326a7 | 779 | case SR_DI_NUM_PROBES: |
464d12c7 KS |
780 | info = GINT_TO_POINTER(NUM_PROBES); |
781 | break; | |
782 | case SR_DI_PROBE_NAMES: | |
783 | info = probe_names; | |
28a35d8a | 784 | break; |
5a2326a7 | 785 | case SR_DI_SAMPLERATES: |
28a35d8a HE |
786 | info = &samplerates; |
787 | break; | |
5a2326a7 | 788 | case SR_DI_TRIGGER_TYPES: |
57bbf56b | 789 | info = (char *)TRIGGER_TYPES; |
28a35d8a | 790 | break; |
5a2326a7 | 791 | case SR_DI_CUR_SAMPLERATE: |
ea9cfed7 | 792 | info = &ctx->cur_samplerate; |
28a35d8a HE |
793 | break; |
794 | } | |
795 | ||
796 | return info; | |
797 | } | |
798 | ||
e7eb703f | 799 | static int hw_dev_status_get(int dev_index) |
28a35d8a | 800 | { |
d68e2d1a | 801 | struct sr_dev_inst *sdi; |
28a35d8a | 802 | |
ed300b9f | 803 | sdi = sr_dev_inst_get(adi->instances, dev_index); |
28a35d8a HE |
804 | if (sdi) |
805 | return sdi->status; | |
806 | else | |
5a2326a7 | 807 | return SR_ST_NOT_FOUND; |
28a35d8a HE |
808 | } |
809 | ||
915f7cc8 | 810 | static const int *hw_hwcap_get_all(void) |
28a35d8a | 811 | { |
ffedd0bf | 812 | return hwcaps; |
28a35d8a HE |
813 | } |
814 | ||
1b79df2f | 815 | static int hw_dev_config_set(int dev_index, int hwcap, const void *value) |
28a35d8a | 816 | { |
d68e2d1a | 817 | struct sr_dev_inst *sdi; |
ea9cfed7 | 818 | struct context *ctx; |
28a35d8a | 819 | int ret; |
f6564c8d | 820 | |
ed300b9f | 821 | if (!(sdi = sr_dev_inst_get(adi->instances, dev_index))) |
e46b8fb1 | 822 | return SR_ERR; |
28a35d8a | 823 | |
ea9cfed7 | 824 | ctx = sdi->priv; |
99965709 | 825 | |
ffedd0bf | 826 | if (hwcap == SR_HWCAP_SAMPLERATE) { |
1b79df2f | 827 | ret = set_samplerate(sdi, *(const uint64_t *)value); |
ffedd0bf | 828 | } else if (hwcap == SR_HWCAP_PROBECONFIG) { |
99965709 | 829 | ret = configure_probes(sdi, value); |
ffedd0bf | 830 | } else if (hwcap == SR_HWCAP_LIMIT_MSEC) { |
1b79df2f | 831 | ctx->limit_msec = *(const uint64_t *)value; |
ea9cfed7 | 832 | if (ctx->limit_msec > 0) |
e46b8fb1 | 833 | ret = SR_OK; |
94ba4bd6 | 834 | else |
e46b8fb1 | 835 | ret = SR_ERR; |
ffedd0bf | 836 | } else if (hwcap == SR_HWCAP_CAPTURE_RATIO) { |
1b79df2f | 837 | ctx->capture_ratio = *(const uint64_t *)value; |
ea9cfed7 | 838 | if (ctx->capture_ratio < 0 || ctx->capture_ratio > 100) |
e46b8fb1 | 839 | ret = SR_ERR; |
94ba4bd6 | 840 | else |
e46b8fb1 | 841 | ret = SR_OK; |
28a35d8a | 842 | } else { |
e46b8fb1 | 843 | ret = SR_ERR; |
28a35d8a HE |
844 | } |
845 | ||
846 | return ret; | |
847 | } | |
848 | ||
36b1c8e6 HE |
849 | /* Software trigger to determine exact trigger position. */ |
850 | static int get_trigger_offset(uint16_t *samples, uint16_t last_sample, | |
851 | struct sigma_trigger *t) | |
852 | { | |
853 | int i; | |
854 | ||
855 | for (i = 0; i < 8; ++i) { | |
856 | if (i > 0) | |
857 | last_sample = samples[i-1]; | |
858 | ||
859 | /* Simple triggers. */ | |
860 | if ((samples[i] & t->simplemask) != t->simplevalue) | |
861 | continue; | |
862 | ||
863 | /* Rising edge. */ | |
864 | if ((last_sample & t->risingmask) != 0 || (samples[i] & | |
865 | t->risingmask) != t->risingmask) | |
866 | continue; | |
867 | ||
868 | /* Falling edge. */ | |
bdfc7a89 HE |
869 | if ((last_sample & t->fallingmask) != t->fallingmask || |
870 | (samples[i] & t->fallingmask) != 0) | |
36b1c8e6 HE |
871 | continue; |
872 | ||
873 | break; | |
874 | } | |
875 | ||
876 | /* If we did not match, return original trigger pos. */ | |
877 | return i & 0x7; | |
878 | } | |
879 | ||
28a35d8a | 880 | /* |
fefa1800 UH |
881 | * Decode chunk of 1024 bytes, 64 clusters, 7 events per cluster. |
882 | * Each event is 20ns apart, and can contain multiple samples. | |
f78898e9 HE |
883 | * |
884 | * For 200 MHz, events contain 4 samples for each channel, spread 5 ns apart. | |
885 | * For 100 MHz, events contain 2 samples for each channel, spread 10 ns apart. | |
886 | * For 50 MHz and below, events contain one sample for each channel, | |
887 | * spread 20 ns apart. | |
28a35d8a HE |
888 | */ |
889 | static int decode_chunk_ts(uint8_t *buf, uint16_t *lastts, | |
88c51afe | 890 | uint16_t *lastsample, int triggerpos, |
3cd3a20b | 891 | uint16_t limit_chunk, void *cb_data) |
28a35d8a | 892 | { |
3cd3a20b | 893 | struct sr_dev_inst *sdi = cb_data; |
ea9cfed7 | 894 | struct context *ctx = sdi->priv; |
fefa1800 | 895 | uint16_t tsdiff, ts; |
ea9cfed7 | 896 | uint16_t samples[65536 * ctx->samples_per_event]; |
b9c735a2 | 897 | struct sr_datafeed_packet packet; |
9c939c51 | 898 | struct sr_datafeed_logic logic; |
f78898e9 | 899 | int i, j, k, l, numpad, tosend; |
fefa1800 | 900 | size_t n = 0, sent = 0; |
ea9cfed7 | 901 | int clustersize = EVENTS_PER_CLUSTER * ctx->samples_per_event; |
fefa1800 | 902 | uint16_t *event; |
f78898e9 | 903 | uint16_t cur_sample; |
57bbf56b | 904 | int triggerts = -1; |
ee492173 | 905 | |
4ae1f451 | 906 | /* Check if trigger is in this chunk. */ |
ee492173 | 907 | if (triggerpos != -1) { |
ea9cfed7 | 908 | if (ctx->cur_samplerate <= SR_MHZ(50)) |
36b1c8e6 | 909 | triggerpos -= EVENTS_PER_CLUSTER - 1; |
ee492173 HE |
910 | |
911 | if (triggerpos < 0) | |
912 | triggerpos = 0; | |
57bbf56b | 913 | |
ee492173 HE |
914 | /* Find in which cluster the trigger occured. */ |
915 | triggerts = triggerpos / 7; | |
916 | } | |
28a35d8a | 917 | |
eec5275e | 918 | /* For each ts. */ |
28a35d8a | 919 | for (i = 0; i < 64; ++i) { |
fefa1800 | 920 | ts = *(uint16_t *) &buf[i * 16]; |
28a35d8a HE |
921 | tsdiff = ts - *lastts; |
922 | *lastts = ts; | |
923 | ||
88c51afe HE |
924 | /* Decode partial chunk. */ |
925 | if (limit_chunk && ts > limit_chunk) | |
e46b8fb1 | 926 | return SR_OK; |
88c51afe | 927 | |
fefa1800 | 928 | /* Pad last sample up to current point. */ |
ea9cfed7 | 929 | numpad = tsdiff * ctx->samples_per_event - clustersize; |
28a35d8a | 930 | if (numpad > 0) { |
f78898e9 HE |
931 | for (j = 0; j < numpad; ++j) |
932 | samples[j] = *lastsample; | |
933 | ||
934 | n = numpad; | |
28a35d8a HE |
935 | } |
936 | ||
57bbf56b HE |
937 | /* Send samples between previous and this timestamp to sigrok. */ |
938 | sent = 0; | |
939 | while (sent < n) { | |
940 | tosend = MIN(2048, n - sent); | |
941 | ||
5a2326a7 | 942 | packet.type = SR_DF_LOGIC; |
9c939c51 BV |
943 | packet.payload = &logic; |
944 | logic.length = tosend * sizeof(uint16_t); | |
945 | logic.unitsize = 2; | |
946 | logic.data = samples + sent; | |
3cd3a20b | 947 | sr_session_send(ctx->session_dev_id, &packet); |
28a35d8a | 948 | |
57bbf56b HE |
949 | sent += tosend; |
950 | } | |
951 | n = 0; | |
952 | ||
953 | event = (uint16_t *) &buf[i * 16 + 2]; | |
f78898e9 HE |
954 | cur_sample = 0; |
955 | ||
956 | /* For each event in cluster. */ | |
28a35d8a | 957 | for (j = 0; j < 7; ++j) { |
f78898e9 HE |
958 | |
959 | /* For each sample in event. */ | |
ea9cfed7 | 960 | for (k = 0; k < ctx->samples_per_event; ++k) { |
f78898e9 HE |
961 | cur_sample = 0; |
962 | ||
963 | /* For each probe. */ | |
ea9cfed7 | 964 | for (l = 0; l < ctx->num_probes; ++l) |
edca2c5c | 965 | cur_sample |= (!!(event[j] & (1 << (l * |
ea9cfed7 | 966 | ctx->samples_per_event + k)))) << l; |
f78898e9 HE |
967 | |
968 | samples[n++] = cur_sample; | |
28a35d8a HE |
969 | } |
970 | } | |
971 | ||
eec5275e | 972 | /* Send data up to trigger point (if triggered). */ |
fefa1800 | 973 | sent = 0; |
57bbf56b HE |
974 | if (i == triggerts) { |
975 | /* | |
36b1c8e6 HE |
976 | * Trigger is not always accurate to sample because of |
977 | * pipeline delay. However, it always triggers before | |
978 | * the actual event. We therefore look at the next | |
979 | * samples to pinpoint the exact position of the trigger. | |
57bbf56b | 980 | */ |
bdfc7a89 | 981 | tosend = get_trigger_offset(samples, *lastsample, |
ea9cfed7 | 982 | &ctx->trigger); |
57bbf56b HE |
983 | |
984 | if (tosend > 0) { | |
5a2326a7 | 985 | packet.type = SR_DF_LOGIC; |
9c939c51 BV |
986 | packet.payload = &logic; |
987 | logic.length = tosend * sizeof(uint16_t); | |
988 | logic.unitsize = 2; | |
989 | logic.data = samples; | |
3cd3a20b | 990 | sr_session_send(ctx->session_dev_id, &packet); |
57bbf56b HE |
991 | |
992 | sent += tosend; | |
993 | } | |
28a35d8a | 994 | |
5b5ea7c6 | 995 | /* Only send trigger if explicitly enabled. */ |
ea9cfed7 | 996 | if (ctx->use_triggers) { |
5a2326a7 | 997 | packet.type = SR_DF_TRIGGER; |
3cd3a20b | 998 | sr_session_send(ctx->session_dev_id, &packet); |
5b5ea7c6 | 999 | } |
28a35d8a | 1000 | } |
57bbf56b | 1001 | |
eec5275e | 1002 | /* Send rest of the chunk to sigrok. */ |
57bbf56b HE |
1003 | tosend = n - sent; |
1004 | ||
abda62ce | 1005 | if (tosend > 0) { |
5a2326a7 | 1006 | packet.type = SR_DF_LOGIC; |
9c939c51 BV |
1007 | packet.payload = &logic; |
1008 | logic.length = tosend * sizeof(uint16_t); | |
1009 | logic.unitsize = 2; | |
1010 | logic.data = samples + sent; | |
3cd3a20b | 1011 | sr_session_send(ctx->session_dev_id, &packet); |
abda62ce | 1012 | } |
ee492173 HE |
1013 | |
1014 | *lastsample = samples[n - 1]; | |
28a35d8a HE |
1015 | } |
1016 | ||
e46b8fb1 | 1017 | return SR_OK; |
28a35d8a HE |
1018 | } |
1019 | ||
1f9813eb | 1020 | static int receive_data(int fd, int revents, void *cb_data) |
28a35d8a | 1021 | { |
1f9813eb | 1022 | struct sr_dev_inst *sdi = cb_data; |
ea9cfed7 | 1023 | struct context *ctx = sdi->priv; |
b9c735a2 | 1024 | struct sr_datafeed_packet packet; |
28a35d8a HE |
1025 | const int chunks_per_read = 32; |
1026 | unsigned char buf[chunks_per_read * CHUNK_SIZE]; | |
6aac7737 | 1027 | int bufsz, numchunks, i, newchunks; |
94ba4bd6 | 1028 | uint64_t running_msec; |
28a35d8a | 1029 | struct timeval tv; |
28a35d8a | 1030 | |
cb93f8a9 UH |
1031 | /* Avoid compiler warnings. */ |
1032 | (void)fd; | |
1033 | (void)revents; | |
28a35d8a | 1034 | |
805919b0 HE |
1035 | /* Get the current position. */ |
1036 | sigma_read_pos(&ctx->state.stoppos, &ctx->state.triggerpos, ctx); | |
1037 | ||
ea9cfed7 | 1038 | numchunks = (ctx->state.stoppos + 511) / 512; |
28a35d8a | 1039 | |
ea9cfed7 | 1040 | if (ctx->state.state == SIGMA_IDLE) |
805919b0 | 1041 | return TRUE; |
28a35d8a | 1042 | |
ea9cfed7 | 1043 | if (ctx->state.state == SIGMA_CAPTURE) { |
6aac7737 HE |
1044 | /* Check if the timer has expired, or memory is full. */ |
1045 | gettimeofday(&tv, 0); | |
ea9cfed7 UH |
1046 | running_msec = (tv.tv_sec - ctx->start_tv.tv_sec) * 1000 + |
1047 | (tv.tv_usec - ctx->start_tv.tv_usec) / 1000; | |
28a35d8a | 1048 | |
ea9cfed7 | 1049 | if (running_msec < ctx->limit_msec && numchunks < 32767) |
805919b0 | 1050 | return TRUE; /* While capturing... */ |
e3fff420 HE |
1051 | else |
1052 | hw_dev_acquisition_stop(sdi->index, sdi); | |
6aac7737 | 1053 | |
ea9cfed7 UH |
1054 | } else if (ctx->state.state == SIGMA_DOWNLOAD) { |
1055 | if (ctx->state.chunks_downloaded >= numchunks) { | |
6aac7737 | 1056 | /* End of samples. */ |
5a2326a7 | 1057 | packet.type = SR_DF_END; |
3cd3a20b | 1058 | sr_session_send(ctx->session_dev_id, &packet); |
6aac7737 | 1059 | |
ea9cfed7 | 1060 | ctx->state.state = SIGMA_IDLE; |
f78898e9 | 1061 | |
6aac7737 HE |
1062 | return TRUE; |
1063 | } | |
1064 | ||
1065 | newchunks = MIN(chunks_per_read, | |
ea9cfed7 | 1066 | numchunks - ctx->state.chunks_downloaded); |
28a35d8a | 1067 | |
7b48d6e1 | 1068 | sr_info("sigma: Downloading sample data: %.0f %%", |
ea9cfed7 | 1069 | 100.0 * ctx->state.chunks_downloaded / numchunks); |
28a35d8a | 1070 | |
ea9cfed7 UH |
1071 | bufsz = sigma_read_dram(ctx->state.chunks_downloaded, |
1072 | newchunks, buf, ctx); | |
719c5a93 UH |
1073 | /* TODO: Check bufsz. For now, just avoid compiler warnings. */ |
1074 | (void)bufsz; | |
28a35d8a | 1075 | |
fefa1800 | 1076 | /* Find first ts. */ |
ea9cfed7 UH |
1077 | if (ctx->state.chunks_downloaded == 0) { |
1078 | ctx->state.lastts = *(uint16_t *) buf - 1; | |
1079 | ctx->state.lastsample = 0; | |
6aac7737 | 1080 | } |
28a35d8a | 1081 | |
fefa1800 | 1082 | /* Decode chunks and send them to sigrok. */ |
28a35d8a | 1083 | for (i = 0; i < newchunks; ++i) { |
88c51afe HE |
1084 | int limit_chunk = 0; |
1085 | ||
1086 | /* The last chunk may potentially be only in part. */ | |
ea9cfed7 | 1087 | if (ctx->state.chunks_downloaded == numchunks - 1) { |
88c51afe | 1088 | /* Find the last valid timestamp */ |
ea9cfed7 | 1089 | limit_chunk = ctx->state.stoppos % 512 + ctx->state.lastts; |
88c51afe HE |
1090 | } |
1091 | ||
ea9cfed7 | 1092 | if (ctx->state.chunks_downloaded + i == ctx->state.triggerchunk) |
57bbf56b | 1093 | decode_chunk_ts(buf + (i * CHUNK_SIZE), |
ea9cfed7 UH |
1094 | &ctx->state.lastts, |
1095 | &ctx->state.lastsample, | |
1096 | ctx->state.triggerpos & 0x1ff, | |
1f9813eb | 1097 | limit_chunk, sdi); |
57bbf56b HE |
1098 | else |
1099 | decode_chunk_ts(buf + (i * CHUNK_SIZE), | |
ea9cfed7 UH |
1100 | &ctx->state.lastts, |
1101 | &ctx->state.lastsample, | |
1f9813eb | 1102 | -1, limit_chunk, sdi); |
28a35d8a | 1103 | |
ea9cfed7 | 1104 | ++ctx->state.chunks_downloaded; |
88c51afe | 1105 | } |
28a35d8a HE |
1106 | } |
1107 | ||
28a35d8a HE |
1108 | return TRUE; |
1109 | } | |
1110 | ||
c53d793f HE |
1111 | /* Build a LUT entry used by the trigger functions. */ |
1112 | static void build_lut_entry(uint16_t value, uint16_t mask, uint16_t *entry) | |
ee492173 HE |
1113 | { |
1114 | int i, j, k, bit; | |
1115 | ||
f758d074 | 1116 | /* For each quad probe. */ |
ee492173 | 1117 | for (i = 0; i < 4; ++i) { |
c53d793f | 1118 | entry[i] = 0xffff; |
ee492173 | 1119 | |
f758d074 | 1120 | /* For each bit in LUT. */ |
ee492173 HE |
1121 | for (j = 0; j < 16; ++j) |
1122 | ||
f758d074 | 1123 | /* For each probe in quad. */ |
ee492173 HE |
1124 | for (k = 0; k < 4; ++k) { |
1125 | bit = 1 << (i * 4 + k); | |
1126 | ||
c53d793f HE |
1127 | /* Set bit in entry */ |
1128 | if ((mask & bit) && | |
1129 | ((!(value & bit)) != | |
4ae1f451 | 1130 | (!(j & (1 << k))))) |
c53d793f | 1131 | entry[i] &= ~(1 << j); |
ee492173 HE |
1132 | } |
1133 | } | |
c53d793f | 1134 | } |
ee492173 | 1135 | |
c53d793f HE |
1136 | /* Add a logical function to LUT mask. */ |
1137 | static void add_trigger_function(enum triggerop oper, enum triggerfunc func, | |
1138 | int index, int neg, uint16_t *mask) | |
1139 | { | |
1140 | int i, j; | |
1141 | int x[2][2], tmp, a, b, aset, bset, rset; | |
1142 | ||
1143 | memset(x, 0, 4 * sizeof(int)); | |
1144 | ||
1145 | /* Trigger detect condition. */ | |
1146 | switch (oper) { | |
1147 | case OP_LEVEL: | |
1148 | x[0][1] = 1; | |
1149 | x[1][1] = 1; | |
1150 | break; | |
1151 | case OP_NOT: | |
1152 | x[0][0] = 1; | |
1153 | x[1][0] = 1; | |
1154 | break; | |
1155 | case OP_RISE: | |
1156 | x[0][1] = 1; | |
1157 | break; | |
1158 | case OP_FALL: | |
1159 | x[1][0] = 1; | |
1160 | break; | |
1161 | case OP_RISEFALL: | |
1162 | x[0][1] = 1; | |
1163 | x[1][0] = 1; | |
1164 | break; | |
1165 | case OP_NOTRISE: | |
1166 | x[1][1] = 1; | |
1167 | x[0][0] = 1; | |
1168 | x[1][0] = 1; | |
1169 | break; | |
1170 | case OP_NOTFALL: | |
1171 | x[1][1] = 1; | |
1172 | x[0][0] = 1; | |
1173 | x[0][1] = 1; | |
1174 | break; | |
1175 | case OP_NOTRISEFALL: | |
1176 | x[1][1] = 1; | |
1177 | x[0][0] = 1; | |
1178 | break; | |
1179 | } | |
1180 | ||
1181 | /* Transpose if neg is set. */ | |
1182 | if (neg) { | |
ea9cfed7 | 1183 | for (i = 0; i < 2; ++i) { |
c53d793f HE |
1184 | for (j = 0; j < 2; ++j) { |
1185 | tmp = x[i][j]; | |
1186 | x[i][j] = x[1-i][1-j]; | |
1187 | x[1-i][1-j] = tmp; | |
1188 | } | |
ea9cfed7 | 1189 | } |
c53d793f HE |
1190 | } |
1191 | ||
1192 | /* Update mask with function. */ | |
1193 | for (i = 0; i < 16; ++i) { | |
1194 | a = (i >> (2 * index + 0)) & 1; | |
1195 | b = (i >> (2 * index + 1)) & 1; | |
1196 | ||
1197 | aset = (*mask >> i) & 1; | |
1198 | bset = x[b][a]; | |
1199 | ||
1200 | if (func == FUNC_AND || func == FUNC_NAND) | |
1201 | rset = aset & bset; | |
1202 | else if (func == FUNC_OR || func == FUNC_NOR) | |
1203 | rset = aset | bset; | |
1204 | else if (func == FUNC_XOR || func == FUNC_NXOR) | |
1205 | rset = aset ^ bset; | |
1206 | ||
1207 | if (func == FUNC_NAND || func == FUNC_NOR || func == FUNC_NXOR) | |
1208 | rset = !rset; | |
1209 | ||
1210 | *mask &= ~(1 << i); | |
1211 | ||
1212 | if (rset) | |
1213 | *mask |= 1 << i; | |
1214 | } | |
1215 | } | |
1216 | ||
1217 | /* | |
1218 | * Build trigger LUTs used by 50 MHz and lower sample rates for supporting | |
1219 | * simple pin change and state triggers. Only two transitions (rise/fall) can be | |
1220 | * set at any time, but a full mask and value can be set (0/1). | |
1221 | */ | |
ea9cfed7 | 1222 | static int build_basic_trigger(struct triggerlut *lut, struct context *ctx) |
c53d793f HE |
1223 | { |
1224 | int i,j; | |
4ae1f451 | 1225 | uint16_t masks[2] = { 0, 0 }; |
c53d793f HE |
1226 | |
1227 | memset(lut, 0, sizeof(struct triggerlut)); | |
1228 | ||
1229 | /* Contant for simple triggers. */ | |
1230 | lut->m4 = 0xa000; | |
1231 | ||
1232 | /* Value/mask trigger support. */ | |
ea9cfed7 | 1233 | build_lut_entry(ctx->trigger.simplevalue, ctx->trigger.simplemask, |
99965709 | 1234 | lut->m2d); |
c53d793f HE |
1235 | |
1236 | /* Rise/fall trigger support. */ | |
1237 | for (i = 0, j = 0; i < 16; ++i) { | |
ea9cfed7 UH |
1238 | if (ctx->trigger.risingmask & (1 << i) || |
1239 | ctx->trigger.fallingmask & (1 << i)) | |
c53d793f HE |
1240 | masks[j++] = 1 << i; |
1241 | } | |
1242 | ||
1243 | build_lut_entry(masks[0], masks[0], lut->m0d); | |
1244 | build_lut_entry(masks[1], masks[1], lut->m1d); | |
1245 | ||
1246 | /* Add glue logic */ | |
1247 | if (masks[0] || masks[1]) { | |
1248 | /* Transition trigger. */ | |
ea9cfed7 | 1249 | if (masks[0] & ctx->trigger.risingmask) |
c53d793f | 1250 | add_trigger_function(OP_RISE, FUNC_OR, 0, 0, &lut->m3); |
ea9cfed7 | 1251 | if (masks[0] & ctx->trigger.fallingmask) |
c53d793f | 1252 | add_trigger_function(OP_FALL, FUNC_OR, 0, 0, &lut->m3); |
ea9cfed7 | 1253 | if (masks[1] & ctx->trigger.risingmask) |
c53d793f | 1254 | add_trigger_function(OP_RISE, FUNC_OR, 1, 0, &lut->m3); |
ea9cfed7 | 1255 | if (masks[1] & ctx->trigger.fallingmask) |
c53d793f HE |
1256 | add_trigger_function(OP_FALL, FUNC_OR, 1, 0, &lut->m3); |
1257 | } else { | |
1258 | /* Only value/mask trigger. */ | |
1259 | lut->m3 = 0xffff; | |
1260 | } | |
ee492173 | 1261 | |
c53d793f | 1262 | /* Triggertype: event. */ |
ee492173 HE |
1263 | lut->params.selres = 3; |
1264 | ||
e46b8fb1 | 1265 | return SR_OK; |
ee492173 HE |
1266 | } |
1267 | ||
3cd3a20b | 1268 | static int hw_dev_acquisition_start(int dev_index, void *cb_data) |
28a35d8a | 1269 | { |
d68e2d1a | 1270 | struct sr_dev_inst *sdi; |
ea9cfed7 | 1271 | struct context *ctx; |
3c36c403 HE |
1272 | struct sr_datafeed_packet *packet; |
1273 | struct sr_datafeed_header *header; | |
f366e86c | 1274 | struct sr_datafeed_meta_logic meta; |
9ddb2a12 | 1275 | struct clockselect_50 clockselect; |
82957b65 | 1276 | int frac, triggerpin, ret; |
57bbf56b HE |
1277 | uint8_t triggerselect; |
1278 | struct triggerinout triggerinout_conf; | |
ee492173 | 1279 | struct triggerlut lut; |
28a35d8a | 1280 | |
ed300b9f | 1281 | if (!(sdi = sr_dev_inst_get(adi->instances, dev_index))) |
e46b8fb1 | 1282 | return SR_ERR; |
28a35d8a | 1283 | |
ea9cfed7 | 1284 | ctx = sdi->priv; |
28a35d8a | 1285 | |
ea9cfed7 UH |
1286 | /* If the samplerate has not been set, default to 200 kHz. */ |
1287 | if (ctx->cur_firmware == -1) { | |
82957b65 UH |
1288 | if ((ret = set_samplerate(sdi, SR_KHZ(200))) != SR_OK) |
1289 | return ret; | |
1290 | } | |
e8397563 | 1291 | |
eec5275e | 1292 | /* Enter trigger programming mode. */ |
ea9cfed7 | 1293 | sigma_set_register(WRITE_TRIGGER_SELECT1, 0x20, ctx); |
28a35d8a | 1294 | |
eec5275e | 1295 | /* 100 and 200 MHz mode. */ |
ea9cfed7 UH |
1296 | if (ctx->cur_samplerate >= SR_MHZ(100)) { |
1297 | sigma_set_register(WRITE_TRIGGER_SELECT1, 0x81, ctx); | |
57bbf56b | 1298 | |
a42aec7f HE |
1299 | /* Find which pin to trigger on from mask. */ |
1300 | for (triggerpin = 0; triggerpin < 8; ++triggerpin) | |
ea9cfed7 | 1301 | if ((ctx->trigger.risingmask | ctx->trigger.fallingmask) & |
a42aec7f HE |
1302 | (1 << triggerpin)) |
1303 | break; | |
1304 | ||
1305 | /* Set trigger pin and light LED on trigger. */ | |
1306 | triggerselect = (1 << LEDSEL1) | (triggerpin & 0x7); | |
1307 | ||
1308 | /* Default rising edge. */ | |
ea9cfed7 | 1309 | if (ctx->trigger.fallingmask) |
a42aec7f | 1310 | triggerselect |= 1 << 3; |
57bbf56b | 1311 | |
eec5275e | 1312 | /* All other modes. */ |
ea9cfed7 UH |
1313 | } else if (ctx->cur_samplerate <= SR_MHZ(50)) { |
1314 | build_basic_trigger(&lut, ctx); | |
ee492173 | 1315 | |
ea9cfed7 | 1316 | sigma_write_trigger_lut(&lut, ctx); |
57bbf56b HE |
1317 | |
1318 | triggerselect = (1 << LEDSEL1) | (1 << LEDSEL0); | |
1319 | } | |
1320 | ||
eec5275e | 1321 | /* Setup trigger in and out pins to default values. */ |
57bbf56b HE |
1322 | memset(&triggerinout_conf, 0, sizeof(struct triggerinout)); |
1323 | triggerinout_conf.trgout_bytrigger = 1; | |
1324 | triggerinout_conf.trgout_enable = 1; | |
1325 | ||
28a35d8a | 1326 | sigma_write_register(WRITE_TRIGGER_OPTION, |
57bbf56b | 1327 | (uint8_t *) &triggerinout_conf, |
ea9cfed7 | 1328 | sizeof(struct triggerinout), ctx); |
28a35d8a | 1329 | |
eec5275e | 1330 | /* Go back to normal mode. */ |
ea9cfed7 | 1331 | sigma_set_register(WRITE_TRIGGER_SELECT1, triggerselect, ctx); |
28a35d8a | 1332 | |
edca2c5c | 1333 | /* Set clock select register. */ |
ea9cfed7 | 1334 | if (ctx->cur_samplerate == SR_MHZ(200)) |
edca2c5c | 1335 | /* Enable 4 probes. */ |
ea9cfed7 UH |
1336 | sigma_set_register(WRITE_CLOCK_SELECT, 0xf0, ctx); |
1337 | else if (ctx->cur_samplerate == SR_MHZ(100)) | |
edca2c5c | 1338 | /* Enable 8 probes. */ |
ea9cfed7 | 1339 | sigma_set_register(WRITE_CLOCK_SELECT, 0x00, ctx); |
edca2c5c HE |
1340 | else { |
1341 | /* | |
9ddb2a12 | 1342 | * 50 MHz mode (or fraction thereof). Any fraction down to |
eec5275e | 1343 | * 50 MHz / 256 can be used, but is not supported by sigrok API. |
edca2c5c | 1344 | */ |
ea9cfed7 | 1345 | frac = SR_MHZ(50) / ctx->cur_samplerate - 1; |
edca2c5c | 1346 | |
9ddb2a12 UH |
1347 | clockselect.async = 0; |
1348 | clockselect.fraction = frac; | |
1349 | clockselect.disabled_probes = 0; | |
edca2c5c HE |
1350 | |
1351 | sigma_write_register(WRITE_CLOCK_SELECT, | |
9ddb2a12 | 1352 | (uint8_t *) &clockselect, |
ea9cfed7 | 1353 | sizeof(clockselect), ctx); |
edca2c5c HE |
1354 | } |
1355 | ||
fefa1800 | 1356 | /* Setup maximum post trigger time. */ |
99965709 | 1357 | sigma_set_register(WRITE_POST_TRIGGER, |
6352d030 | 1358 | (ctx->capture_ratio * 255) / 100, ctx); |
28a35d8a | 1359 | |
eec5275e | 1360 | /* Start acqusition. */ |
ea9cfed7 UH |
1361 | gettimeofday(&ctx->start_tv, 0); |
1362 | sigma_set_register(WRITE_MODE, 0x0d, ctx); | |
99965709 | 1363 | |
3cd3a20b | 1364 | ctx->session_dev_id = cb_data; |
28a35d8a | 1365 | |
3c36c403 HE |
1366 | if (!(packet = g_try_malloc(sizeof(struct sr_datafeed_packet)))) { |
1367 | sr_err("sigma: %s: packet malloc failed.", __func__); | |
1368 | return SR_ERR_MALLOC; | |
1369 | } | |
1370 | ||
1371 | if (!(header = g_try_malloc(sizeof(struct sr_datafeed_header)))) { | |
1372 | sr_err("sigma: %s: header malloc failed.", __func__); | |
1373 | return SR_ERR_MALLOC; | |
1374 | } | |
28a35d8a | 1375 | |
3c36c403 HE |
1376 | /* Send header packet to the session bus. */ |
1377 | packet->type = SR_DF_HEADER; | |
1378 | packet->payload = header; | |
1379 | header->feed_version = 1; | |
1380 | gettimeofday(&header->starttime, NULL); | |
3c36c403 | 1381 | sr_session_send(ctx->session_dev_id, packet); |
f366e86c BV |
1382 | |
1383 | /* Send metadata about the SR_DF_LOGIC packets to come. */ | |
1384 | packet->type = SR_DF_META_LOGIC; | |
1385 | packet->payload = &meta; | |
1386 | meta.samplerate = ctx->cur_samplerate; | |
1387 | meta.num_probes = ctx->num_probes; | |
1388 | sr_session_send(ctx->session_dev_id, packet); | |
1389 | ||
1390 | /* Add capture source. */ | |
1391 | sr_source_add(0, G_IO_IN, 10, receive_data, sdi); | |
1392 | ||
3c36c403 HE |
1393 | g_free(header); |
1394 | g_free(packet); | |
1395 | ||
ea9cfed7 | 1396 | ctx->state.state = SIGMA_CAPTURE; |
6aac7737 | 1397 | |
e46b8fb1 | 1398 | return SR_OK; |
28a35d8a HE |
1399 | } |
1400 | ||
3cd3a20b | 1401 | static int hw_dev_acquisition_stop(int dev_index, void *cb_data) |
28a35d8a | 1402 | { |
d68e2d1a | 1403 | struct sr_dev_inst *sdi; |
ea9cfed7 | 1404 | struct context *ctx; |
6aac7737 HE |
1405 | uint8_t modestatus; |
1406 | ||
cb93f8a9 | 1407 | /* Avoid compiler warnings. */ |
3cd3a20b | 1408 | (void)cb_data; |
28a35d8a | 1409 | |
ed300b9f | 1410 | if (!(sdi = sr_dev_inst_get(adi->instances, dev_index))) { |
7b48d6e1 | 1411 | sr_err("sigma: %s: sdi was NULL", __func__); |
3010f21c UH |
1412 | return SR_ERR_BUG; |
1413 | } | |
1414 | ||
ea9cfed7 | 1415 | if (!(ctx = sdi->priv)) { |
7b48d6e1 | 1416 | sr_err("sigma: %s: sdi->priv was NULL", __func__); |
3010f21c UH |
1417 | return SR_ERR_BUG; |
1418 | } | |
1419 | ||
fefa1800 | 1420 | /* Stop acquisition. */ |
ea9cfed7 | 1421 | sigma_set_register(WRITE_MODE, 0x11, ctx); |
28a35d8a | 1422 | |
6aac7737 | 1423 | /* Set SDRAM Read Enable. */ |
ea9cfed7 | 1424 | sigma_set_register(WRITE_MODE, 0x02, ctx); |
6aac7737 HE |
1425 | |
1426 | /* Get the current position. */ | |
ea9cfed7 | 1427 | sigma_read_pos(&ctx->state.stoppos, &ctx->state.triggerpos, ctx); |
6aac7737 HE |
1428 | |
1429 | /* Check if trigger has fired. */ | |
ea9cfed7 | 1430 | modestatus = sigma_get_register(READ_MODE, ctx); |
3010f21c | 1431 | if (modestatus & 0x20) |
ea9cfed7 | 1432 | ctx->state.triggerchunk = ctx->state.triggerpos / 512; |
3010f21c | 1433 | else |
ea9cfed7 | 1434 | ctx->state.triggerchunk = -1; |
6aac7737 | 1435 | |
ea9cfed7 | 1436 | ctx->state.chunks_downloaded = 0; |
6aac7737 | 1437 | |
ea9cfed7 | 1438 | ctx->state.state = SIGMA_DOWNLOAD; |
3010f21c UH |
1439 | |
1440 | return SR_OK; | |
28a35d8a HE |
1441 | } |
1442 | ||
c09f0b57 | 1443 | SR_PRIV struct sr_dev_driver asix_sigma_driver_info = { |
e519ba86 | 1444 | .name = "asix-sigma", |
6352d030 | 1445 | .longname = "ASIX SIGMA/SIGMA2", |
e519ba86 UH |
1446 | .api_version = 1, |
1447 | .init = hw_init, | |
1448 | .cleanup = hw_cleanup, | |
61136ea6 | 1449 | .scan = hw_scan, |
e7eb703f UH |
1450 | .dev_open = hw_dev_open, |
1451 | .dev_close = hw_dev_close, | |
5097b0d0 | 1452 | .dev_info_get = hw_dev_info_get, |
e7eb703f | 1453 | .dev_status_get = hw_dev_status_get, |
ffedd0bf | 1454 | .hwcap_get_all = hw_hwcap_get_all, |
a9a245b4 | 1455 | .dev_config_set = hw_dev_config_set, |
6b3dfec8 UH |
1456 | .dev_acquisition_start = hw_dev_acquisition_start, |
1457 | .dev_acquisition_stop = hw_dev_acquisition_stop, | |
ed300b9f | 1458 | .instances = NULL, |
28a35d8a | 1459 | }; |