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Commit | Line | Data |
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28a35d8a HE |
1 | /* |
2 | * This file is part of the sigrok project. | |
3 | * | |
911f1834 UH |
4 | * Copyright (C) 2010 Håvard Espeland <gus@ping.uio.no>, |
5 | * Copyright (C) 2010 Martin Stensgård <mastensg@ping.uio.no> | |
6 | * Copyright (C) 2010 Carl Henrik Lunde <chlunde@ping.uio.no> | |
28a35d8a HE |
7 | * |
8 | * This program is free software: you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation, either version 3 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
20 | */ | |
21 | ||
911f1834 UH |
22 | /* |
23 | * ASIX Sigma Logic Analyzer Driver | |
24 | */ | |
25 | ||
28a35d8a HE |
26 | #include <ftdi.h> |
27 | #include <string.h> | |
28 | #include <zlib.h> | |
fefa1800 | 29 | #include <sigrok.h> |
28a35d8a HE |
30 | #include "asix-sigma.h" |
31 | ||
32 | #define USB_VENDOR 0xa600 | |
33 | #define USB_PRODUCT 0xa000 | |
34 | #define USB_DESCRIPTION "ASIX SIGMA" | |
35 | #define USB_VENDOR_NAME "ASIX" | |
36 | #define USB_MODEL_NAME "SIGMA" | |
37 | #define USB_MODEL_VERSION "" | |
28a35d8a HE |
38 | |
39 | static GSList *device_instances = NULL; | |
40 | ||
41 | // XXX These should be per device | |
42 | static struct ftdi_context ftdic; | |
f78898e9 | 43 | static uint64_t cur_samplerate = 0; |
28a35d8a HE |
44 | static uint32_t limit_msec = 0; |
45 | static struct timeval start_tv; | |
f6564c8d | 46 | static int cur_firmware = -1; |
f78898e9 HE |
47 | static int num_probes = 0; |
48 | static int samples_per_event = 0; | |
28a35d8a HE |
49 | |
50 | static uint64_t supported_samplerates[] = { | |
e8397563 HE |
51 | MHZ(50), |
52 | MHZ(100), | |
28a35d8a HE |
53 | MHZ(200), |
54 | 0, | |
55 | }; | |
56 | ||
57 | static struct samplerates samplerates = { | |
e8397563 | 58 | MHZ(50), |
28a35d8a HE |
59 | MHZ(200), |
60 | 0, | |
61 | supported_samplerates, | |
62 | }; | |
63 | ||
64 | static int capabilities[] = { | |
65 | HWCAP_LOGIC_ANALYZER, | |
66 | HWCAP_SAMPLERATE, | |
67 | ||
68 | /* These are really implemented in the driver, not the hardware. */ | |
69 | HWCAP_LIMIT_MSEC, | |
70 | 0, | |
71 | }; | |
72 | ||
fefa1800 UH |
73 | /* Force the FPGA to reboot. */ |
74 | static uint8_t suicide[] = { | |
75 | 0x84, 0x84, 0x88, 0x84, 0x88, 0x84, 0x88, 0x84, | |
76 | }; | |
77 | ||
78 | /* Prepare to upload firmware (FPGA specific). */ | |
79 | static uint8_t init[] = { | |
80 | 0x03, 0x03, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, | |
81 | }; | |
82 | ||
83 | /* Initialize the logic analyzer mode. */ | |
84 | static uint8_t logic_mode_start[] = { | |
85 | 0x00, 0x40, 0x0f, 0x25, 0x35, 0x40, | |
86 | 0x2a, 0x3a, 0x40, 0x03, 0x20, 0x38, | |
87 | }; | |
88 | ||
f6564c8d HE |
89 | static const char *firmware_files[] = |
90 | { | |
a8116d76 HE |
91 | "asix-sigma-50.fw", /* 50 MHz, supports 8 bit fractions */ |
92 | "asix-sigma-100.fw", /* 100 MHz */ | |
93 | "asix-sigma-200.fw", /* 200 MHz */ | |
94 | "asix-sigma-50sync.fw", /* Asynchronous sampling */ | |
95 | "asix-sigma-phasor.fw", /* Frequency counter */ | |
f6564c8d HE |
96 | }; |
97 | ||
98 | static int sigma_read(void* buf, size_t size) | |
28a35d8a HE |
99 | { |
100 | int ret; | |
fefa1800 UH |
101 | |
102 | ret = ftdi_read_data(&ftdic, (unsigned char *)buf, size); | |
28a35d8a HE |
103 | if (ret < 0) { |
104 | g_warning("ftdi_read_data failed: %s", | |
fefa1800 | 105 | ftdi_get_error_string(&ftdic)); |
28a35d8a HE |
106 | } |
107 | ||
108 | return ret; | |
109 | } | |
110 | ||
fefa1800 | 111 | static int sigma_write(void *buf, size_t size) |
28a35d8a HE |
112 | { |
113 | int ret; | |
fefa1800 UH |
114 | |
115 | ret = ftdi_write_data(&ftdic, (unsigned char *)buf, size); | |
28a35d8a HE |
116 | if (ret < 0) { |
117 | g_warning("ftdi_write_data failed: %s", | |
fefa1800 UH |
118 | ftdi_get_error_string(&ftdic)); |
119 | } else if ((size_t) ret != size) { | |
28a35d8a HE |
120 | g_warning("ftdi_write_data did not complete write\n"); |
121 | } | |
122 | ||
123 | return ret; | |
124 | } | |
125 | ||
126 | static int sigma_write_register(uint8_t reg, uint8_t *data, size_t len) | |
127 | { | |
128 | size_t i; | |
129 | uint8_t buf[len + 2]; | |
130 | int idx = 0; | |
131 | ||
132 | buf[idx++] = REG_ADDR_LOW | (reg & 0xf); | |
133 | buf[idx++] = REG_ADDR_HIGH | (reg >> 4); | |
134 | ||
fefa1800 | 135 | for (i = 0; i < len; ++i) { |
28a35d8a HE |
136 | buf[idx++] = REG_DATA_LOW | (data[i] & 0xf); |
137 | buf[idx++] = REG_DATA_HIGH_WRITE | (data[i] >> 4); | |
138 | } | |
139 | ||
140 | return sigma_write(buf, idx); | |
141 | } | |
142 | ||
143 | static int sigma_set_register(uint8_t reg, uint8_t value) | |
144 | { | |
145 | return sigma_write_register(reg, &value, 1); | |
146 | } | |
147 | ||
148 | static int sigma_read_register(uint8_t reg, uint8_t *data, size_t len) | |
149 | { | |
150 | uint8_t buf[3]; | |
fefa1800 | 151 | |
28a35d8a HE |
152 | buf[0] = REG_ADDR_LOW | (reg & 0xf); |
153 | buf[1] = REG_ADDR_HIGH | (reg >> 4); | |
28a35d8a HE |
154 | buf[2] = REG_READ_ADDR; |
155 | ||
156 | sigma_write(buf, sizeof(buf)); | |
157 | ||
158 | return sigma_read(data, len); | |
159 | } | |
160 | ||
161 | static uint8_t sigma_get_register(uint8_t reg) | |
162 | { | |
163 | uint8_t value; | |
fefa1800 | 164 | |
28a35d8a HE |
165 | if (1 != sigma_read_register(reg, &value, 1)) { |
166 | g_warning("Sigma_get_register: 1 byte expected"); | |
167 | return 0; | |
168 | } | |
169 | ||
170 | return value; | |
171 | } | |
172 | ||
173 | static int sigma_read_pos(uint32_t *stoppos, uint32_t *triggerpos) | |
174 | { | |
175 | uint8_t buf[] = { | |
176 | REG_ADDR_LOW | READ_TRIGGER_POS_LOW, | |
177 | ||
178 | REG_READ_ADDR | NEXT_REG, | |
179 | REG_READ_ADDR | NEXT_REG, | |
180 | REG_READ_ADDR | NEXT_REG, | |
181 | REG_READ_ADDR | NEXT_REG, | |
182 | REG_READ_ADDR | NEXT_REG, | |
183 | REG_READ_ADDR | NEXT_REG, | |
184 | }; | |
28a35d8a HE |
185 | uint8_t result[6]; |
186 | ||
187 | sigma_write(buf, sizeof(buf)); | |
188 | ||
189 | sigma_read(result, sizeof(result)); | |
190 | ||
191 | *triggerpos = result[0] | (result[1] << 8) | (result[2] << 16); | |
192 | *stoppos = result[3] | (result[4] << 8) | (result[5] << 16); | |
193 | ||
194 | return 1; | |
195 | } | |
196 | ||
197 | static int sigma_read_dram(uint16_t startchunk, size_t numchunks, uint8_t *data) | |
198 | { | |
199 | size_t i; | |
200 | uint8_t buf[4096]; | |
201 | int idx = 0; | |
202 | ||
fefa1800 | 203 | /* Send the startchunk. Index start with 1. */ |
28a35d8a HE |
204 | buf[0] = startchunk >> 8; |
205 | buf[1] = startchunk & 0xff; | |
206 | sigma_write_register(WRITE_MEMROW, buf, 2); | |
207 | ||
fefa1800 | 208 | /* Read the DRAM. */ |
28a35d8a HE |
209 | buf[idx++] = REG_DRAM_BLOCK; |
210 | buf[idx++] = REG_DRAM_WAIT_ACK; | |
211 | ||
212 | for (i = 0; i < numchunks; ++i) { | |
fefa1800 UH |
213 | /* Alternate bit to copy from DRAM to cache. */ |
214 | if (i != (numchunks - 1)) | |
215 | buf[idx++] = REG_DRAM_BLOCK | (((i + 1) % 2) << 4); | |
28a35d8a HE |
216 | |
217 | buf[idx++] = REG_DRAM_BLOCK_DATA | ((i % 2) << 4); | |
218 | ||
fefa1800 | 219 | if (i != (numchunks - 1)) |
28a35d8a HE |
220 | buf[idx++] = REG_DRAM_WAIT_ACK; |
221 | } | |
222 | ||
223 | sigma_write(buf, idx); | |
224 | ||
225 | return sigma_read(data, numchunks * CHUNK_SIZE); | |
226 | } | |
227 | ||
fefa1800 | 228 | /* Generate the bitbang stream for programming the FPGA. */ |
28a35d8a | 229 | static int bin2bitbang(const char *filename, |
fefa1800 | 230 | unsigned char **buf, size_t *buf_size) |
28a35d8a | 231 | { |
fefa1800 | 232 | FILE *f; |
28a35d8a HE |
233 | long file_size; |
234 | unsigned long offset = 0; | |
235 | unsigned char *p; | |
236 | uint8_t *compressed_buf, *firmware; | |
237 | uLongf csize, fwsize; | |
238 | const int buffer_size = 65536; | |
239 | size_t i; | |
fefa1800 UH |
240 | int c, ret, bit, v; |
241 | uint32_t imm = 0x3f6df2ab; | |
28a35d8a | 242 | |
fefa1800 | 243 | f = fopen(filename, "r"); |
28a35d8a HE |
244 | if (!f) { |
245 | g_warning("fopen(\"%s\", \"r\")", filename); | |
246 | return -1; | |
247 | } | |
248 | ||
249 | if (-1 == fseek(f, 0, SEEK_END)) { | |
250 | g_warning("fseek on %s failed", filename); | |
251 | fclose(f); | |
252 | return -1; | |
253 | } | |
254 | ||
255 | file_size = ftell(f); | |
256 | ||
257 | fseek(f, 0, SEEK_SET); | |
258 | ||
28a35d8a HE |
259 | compressed_buf = g_malloc(file_size); |
260 | firmware = g_malloc(buffer_size); | |
261 | ||
262 | if (!compressed_buf || !firmware) { | |
263 | g_warning("Error allocating buffers"); | |
264 | return -1; | |
265 | } | |
266 | ||
28a35d8a HE |
267 | csize = 0; |
268 | while ((c = getc(f)) != EOF) { | |
269 | imm = (imm + 0xa853753) % 177 + (imm * 0x8034052); | |
270 | compressed_buf[csize++] = c ^ imm; | |
271 | } | |
272 | fclose(f); | |
273 | ||
274 | fwsize = buffer_size; | |
275 | ret = uncompress(firmware, &fwsize, compressed_buf, csize); | |
276 | if (ret < 0) { | |
277 | g_free(compressed_buf); | |
278 | g_free(firmware); | |
279 | g_warning("Could not unpack Sigma firmware. (Error %d)\n", ret); | |
280 | return -1; | |
281 | } | |
282 | ||
283 | g_free(compressed_buf); | |
284 | ||
285 | *buf_size = fwsize * 2 * 8; | |
286 | ||
fefa1800 | 287 | *buf = p = (unsigned char *)g_malloc(*buf_size); |
28a35d8a HE |
288 | |
289 | if (!p) { | |
290 | g_warning("Error allocating buffers"); | |
291 | return -1; | |
292 | } | |
293 | ||
294 | for (i = 0; i < fwsize; ++i) { | |
28a35d8a | 295 | for (bit = 7; bit >= 0; --bit) { |
fefa1800 | 296 | v = firmware[i] & 1 << bit ? 0x40 : 0x00; |
28a35d8a HE |
297 | p[offset++] = v | 0x01; |
298 | p[offset++] = v; | |
299 | } | |
300 | } | |
301 | ||
302 | g_free(firmware); | |
303 | ||
304 | if (offset != *buf_size) { | |
305 | g_free(*buf); | |
306 | g_warning("Error reading firmware %s " | |
fefa1800 UH |
307 | "offset=%ld, file_size=%ld, buf_size=%zd\n", |
308 | filename, offset, file_size, *buf_size); | |
28a35d8a HE |
309 | |
310 | return -1; | |
311 | } | |
312 | ||
313 | return 0; | |
314 | } | |
315 | ||
316 | static int hw_init(char *deviceinfo) | |
317 | { | |
318 | struct sigrok_device_instance *sdi; | |
319 | ||
320 | deviceinfo = deviceinfo; | |
321 | ||
322 | ftdi_init(&ftdic); | |
323 | ||
fefa1800 UH |
324 | /* Look for SIGMAs. */ |
325 | if (ftdi_usb_open_desc(&ftdic, USB_VENDOR, USB_PRODUCT, | |
326 | USB_DESCRIPTION, NULL) < 0) | |
28a35d8a HE |
327 | return 0; |
328 | ||
fefa1800 | 329 | /* Register SIGMA device. */ |
28a35d8a HE |
330 | sdi = sigrok_device_instance_new(0, ST_INITIALIZING, |
331 | USB_VENDOR_NAME, USB_MODEL_NAME, USB_MODEL_VERSION); | |
332 | if (!sdi) | |
333 | return 0; | |
334 | ||
335 | device_instances = g_slist_append(device_instances, sdi); | |
336 | ||
fefa1800 | 337 | /* We will open the device again when we need it. */ |
28a35d8a HE |
338 | ftdi_usb_close(&ftdic); |
339 | ||
340 | return 1; | |
341 | } | |
342 | ||
f6564c8d | 343 | static int upload_firmware(int firmware_idx) |
28a35d8a HE |
344 | { |
345 | int ret; | |
346 | unsigned char *buf; | |
347 | unsigned char pins; | |
348 | size_t buf_size; | |
28a35d8a | 349 | unsigned char result[32]; |
e8397563 | 350 | char firmware_path[128]; |
28a35d8a | 351 | |
fefa1800 | 352 | /* Make sure it's an ASIX SIGMA. */ |
28a35d8a HE |
353 | if ((ret = ftdi_usb_open_desc(&ftdic, |
354 | USB_VENDOR, USB_PRODUCT, USB_DESCRIPTION, NULL)) < 0) { | |
28a35d8a | 355 | g_warning("ftdi_usb_open failed: %s", |
fefa1800 | 356 | ftdi_get_error_string(&ftdic)); |
28a35d8a HE |
357 | return 0; |
358 | } | |
359 | ||
360 | if ((ret = ftdi_set_bitmode(&ftdic, 0xdf, BITMODE_BITBANG)) < 0) { | |
361 | g_warning("ftdi_set_bitmode failed: %s", | |
fefa1800 | 362 | ftdi_get_error_string(&ftdic)); |
28a35d8a HE |
363 | return 0; |
364 | } | |
365 | ||
fefa1800 | 366 | /* Four times the speed of sigmalogan - Works well. */ |
28a35d8a HE |
367 | if ((ret = ftdi_set_baudrate(&ftdic, 750000)) < 0) { |
368 | g_warning("ftdi_set_baudrate failed: %s", | |
fefa1800 | 369 | ftdi_get_error_string(&ftdic)); |
28a35d8a HE |
370 | return 0; |
371 | } | |
372 | ||
fefa1800 | 373 | /* Force the FPGA to reboot. */ |
28a35d8a HE |
374 | sigma_write(suicide, sizeof(suicide)); |
375 | sigma_write(suicide, sizeof(suicide)); | |
376 | sigma_write(suicide, sizeof(suicide)); | |
377 | sigma_write(suicide, sizeof(suicide)); | |
378 | ||
fefa1800 | 379 | /* Prepare to upload firmware (FPGA specific). */ |
28a35d8a HE |
380 | sigma_write(init, sizeof(init)); |
381 | ||
382 | ftdi_usb_purge_buffers(&ftdic); | |
383 | ||
fefa1800 | 384 | /* Wait until the FPGA asserts INIT_B. */ |
28a35d8a HE |
385 | while (1) { |
386 | ret = sigma_read(result, 1); | |
387 | if (result[0] & 0x20) | |
388 | break; | |
389 | } | |
390 | ||
f6564c8d | 391 | /* Prepare firmware */ |
e8397563 | 392 | snprintf(firmware_path, sizeof(firmware_path), "%s/%s", FIRMWARE_DIR, |
f6564c8d HE |
393 | firmware_files[firmware_idx]); |
394 | ||
e8397563 | 395 | if (-1 == bin2bitbang(firmware_path, &buf, &buf_size)) { |
28a35d8a | 396 | g_warning("An error occured while reading the firmware: %s", |
e8397563 | 397 | firmware_path); |
28a35d8a HE |
398 | return SIGROK_ERR; |
399 | } | |
400 | ||
fefa1800 | 401 | /* Upload firmare. */ |
28a35d8a HE |
402 | sigma_write(buf, buf_size); |
403 | ||
404 | g_free(buf); | |
405 | ||
406 | if ((ret = ftdi_set_bitmode(&ftdic, 0x00, BITMODE_RESET)) < 0) { | |
f6564c8d | 407 | g_warning("ftdi_set_bitmode failed: %s", |
fefa1800 | 408 | ftdi_get_error_string(&ftdic)); |
28a35d8a HE |
409 | return SIGROK_ERR; |
410 | } | |
411 | ||
412 | ftdi_usb_purge_buffers(&ftdic); | |
413 | ||
fefa1800 | 414 | /* Discard garbage. */ |
28a35d8a HE |
415 | while (1 == sigma_read(&pins, 1)) |
416 | ; | |
417 | ||
fefa1800 | 418 | /* Initialize the logic analyzer mode. */ |
28a35d8a HE |
419 | sigma_write(logic_mode_start, sizeof(logic_mode_start)); |
420 | ||
fefa1800 | 421 | /* Expect a 3 byte reply. */ |
28a35d8a HE |
422 | ret = sigma_read(result, 3); |
423 | if (ret != 3 || | |
424 | result[0] != 0xa6 || result[1] != 0x55 || result[2] != 0xaa) { | |
fefa1800 | 425 | g_warning("Configuration failed. Invalid reply received."); |
28a35d8a HE |
426 | return SIGROK_ERR; |
427 | } | |
428 | ||
f6564c8d HE |
429 | cur_firmware = firmware_idx; |
430 | ||
431 | return SIGROK_OK; | |
432 | } | |
433 | ||
434 | static int hw_opendev(int device_index) | |
435 | { | |
436 | struct sigrok_device_instance *sdi; | |
437 | int ret; | |
438 | ||
439 | /* Make sure it's an ASIX SIGMA */ | |
440 | if ((ret = ftdi_usb_open_desc(&ftdic, | |
441 | USB_VENDOR, USB_PRODUCT, USB_DESCRIPTION, NULL)) < 0) { | |
442 | ||
443 | g_warning("ftdi_usb_open failed: %s", | |
444 | ftdi_get_error_string(&ftdic)); | |
445 | ||
446 | return 0; | |
447 | } | |
28a35d8a HE |
448 | |
449 | if (!(sdi = get_sigrok_device_instance(device_instances, device_index))) | |
450 | return SIGROK_ERR; | |
451 | ||
452 | sdi->status = ST_ACTIVE; | |
453 | ||
f6564c8d HE |
454 | return SIGROK_OK; |
455 | } | |
456 | ||
457 | static int set_samplerate(struct sigrok_device_instance *sdi, uint64_t samplerate) | |
458 | { | |
e8397563 | 459 | int i, ret; |
f6564c8d HE |
460 | |
461 | sdi = sdi; | |
462 | ||
463 | for (i = 0; supported_samplerates[i]; i++) { | |
464 | if (supported_samplerates[i] == samplerate) | |
465 | break; | |
466 | } | |
467 | if (supported_samplerates[i] == 0) | |
468 | return SIGROK_ERR_SAMPLERATE; | |
469 | ||
e8397563 HE |
470 | if (samplerate <= MHZ(50)) { |
471 | ret = upload_firmware(0); | |
f78898e9 | 472 | num_probes = 16; |
e8397563 HE |
473 | // XXX: Setup divider |
474 | } | |
f78898e9 | 475 | if (samplerate == MHZ(100)) { |
e8397563 | 476 | ret = upload_firmware(1); |
f78898e9 HE |
477 | num_probes = 8; |
478 | } | |
479 | else if (samplerate == MHZ(200)) { | |
e8397563 | 480 | ret = upload_firmware(2); |
f78898e9 HE |
481 | num_probes = 4; |
482 | } | |
f6564c8d | 483 | |
e8397563 | 484 | cur_samplerate = samplerate; |
f78898e9 | 485 | samples_per_event = 16 / num_probes; |
f6564c8d | 486 | |
28a35d8a HE |
487 | g_message("Firmware uploaded"); |
488 | ||
e8397563 | 489 | return ret; |
28a35d8a HE |
490 | } |
491 | ||
28a35d8a HE |
492 | static void hw_closedev(int device_index) |
493 | { | |
494 | device_index = device_index; | |
495 | ||
496 | ftdi_usb_close(&ftdic); | |
497 | } | |
498 | ||
28a35d8a HE |
499 | static void hw_cleanup(void) |
500 | { | |
501 | } | |
502 | ||
28a35d8a HE |
503 | static void *hw_get_device_info(int device_index, int device_info_id) |
504 | { | |
505 | struct sigrok_device_instance *sdi; | |
506 | void *info = NULL; | |
507 | ||
508 | if (!(sdi = get_sigrok_device_instance(device_instances, device_index))) { | |
509 | fprintf(stderr, "It's NULL.\n"); | |
510 | return NULL; | |
511 | } | |
512 | ||
513 | switch (device_info_id) { | |
514 | case DI_INSTANCE: | |
515 | info = sdi; | |
516 | break; | |
517 | case DI_NUM_PROBES: | |
518 | info = GINT_TO_POINTER(4); | |
519 | break; | |
520 | case DI_SAMPLERATES: | |
521 | info = &samplerates; | |
522 | break; | |
523 | case DI_TRIGGER_TYPES: | |
fefa1800 | 524 | info = 0; //TRIGGER_TYPES; |
28a35d8a HE |
525 | break; |
526 | case DI_CUR_SAMPLERATE: | |
527 | info = &cur_samplerate; | |
528 | break; | |
529 | } | |
530 | ||
531 | return info; | |
532 | } | |
533 | ||
28a35d8a HE |
534 | static int hw_get_status(int device_index) |
535 | { | |
536 | struct sigrok_device_instance *sdi; | |
537 | ||
538 | sdi = get_sigrok_device_instance(device_instances, device_index); | |
539 | if (sdi) | |
540 | return sdi->status; | |
541 | else | |
542 | return ST_NOT_FOUND; | |
543 | } | |
544 | ||
28a35d8a HE |
545 | static int *hw_get_capabilities(void) |
546 | { | |
547 | return capabilities; | |
548 | } | |
549 | ||
550 | static int hw_set_configuration(int device_index, int capability, void *value) | |
551 | { | |
552 | struct sigrok_device_instance *sdi; | |
553 | int ret; | |
f6564c8d | 554 | |
28a35d8a HE |
555 | if (!(sdi = get_sigrok_device_instance(device_instances, device_index))) |
556 | return SIGROK_ERR; | |
557 | ||
558 | if (capability == HWCAP_SAMPLERATE) { | |
f6564c8d | 559 | ret = set_samplerate(sdi, *(uint64_t*) value); |
28a35d8a HE |
560 | } else if (capability == HWCAP_PROBECONFIG) { |
561 | ret = SIGROK_OK; | |
562 | } else if (capability == HWCAP_LIMIT_MSEC) { | |
563 | limit_msec = strtoull(value, NULL, 10); | |
564 | ret = SIGROK_OK; | |
565 | } else { | |
566 | ret = SIGROK_ERR; | |
567 | } | |
568 | ||
569 | return ret; | |
570 | } | |
571 | ||
28a35d8a | 572 | /* |
fefa1800 UH |
573 | * Decode chunk of 1024 bytes, 64 clusters, 7 events per cluster. |
574 | * Each event is 20ns apart, and can contain multiple samples. | |
f78898e9 HE |
575 | * |
576 | * For 200 MHz, events contain 4 samples for each channel, spread 5 ns apart. | |
577 | * For 100 MHz, events contain 2 samples for each channel, spread 10 ns apart. | |
578 | * For 50 MHz and below, events contain one sample for each channel, | |
579 | * spread 20 ns apart. | |
28a35d8a HE |
580 | */ |
581 | static int decode_chunk_ts(uint8_t *buf, uint16_t *lastts, | |
f78898e9 | 582 | uint16_t *lastsample, void *user_data) |
28a35d8a | 583 | { |
fefa1800 | 584 | uint16_t tsdiff, ts; |
f78898e9 | 585 | uint16_t samples[65536 * samples_per_event]; |
28a35d8a | 586 | struct datafeed_packet packet; |
f78898e9 | 587 | int i, j, k, l, numpad, tosend; |
fefa1800 | 588 | size_t n = 0, sent = 0; |
f78898e9 | 589 | int clustersize = EVENTS_PER_CLUSTER * samples_per_event; |
fefa1800 | 590 | uint16_t *event; |
f78898e9 | 591 | uint16_t cur_sample; |
28a35d8a HE |
592 | |
593 | /* For each ts */ | |
594 | for (i = 0; i < 64; ++i) { | |
fefa1800 | 595 | ts = *(uint16_t *) &buf[i * 16]; |
28a35d8a HE |
596 | tsdiff = ts - *lastts; |
597 | *lastts = ts; | |
598 | ||
fefa1800 UH |
599 | /* Pad last sample up to current point. */ |
600 | numpad = tsdiff * samples_per_event - clustersize; | |
28a35d8a | 601 | if (numpad > 0) { |
f78898e9 HE |
602 | for (j = 0; j < numpad; ++j) |
603 | samples[j] = *lastsample; | |
604 | ||
605 | n = numpad; | |
28a35d8a HE |
606 | } |
607 | ||
fefa1800 | 608 | event = (uint16_t *) &buf[i * 16 + 2]; |
28a35d8a | 609 | |
f78898e9 HE |
610 | cur_sample = 0; |
611 | ||
612 | /* For each event in cluster. */ | |
28a35d8a | 613 | for (j = 0; j < 7; ++j) { |
f78898e9 HE |
614 | |
615 | /* For each sample in event. */ | |
28a35d8a | 616 | for (k = 0; k < samples_per_event; ++k) { |
f78898e9 HE |
617 | cur_sample = 0; |
618 | ||
619 | /* For each probe. */ | |
620 | for (l = 0; l < num_probes; ++l) | |
621 | cur_sample |= (!!(event[j] & | |
622 | (1 << (l * 2 + k)))) << l; | |
623 | ||
624 | samples[n++] = cur_sample; | |
28a35d8a HE |
625 | } |
626 | } | |
627 | ||
fefa1800 | 628 | *lastsample = samples[n - 1]; |
28a35d8a | 629 | |
fefa1800 UH |
630 | /* Send to sigrok. */ |
631 | sent = 0; | |
28a35d8a | 632 | while (sent < n) { |
f78898e9 | 633 | tosend = MIN(2048, n - sent); |
28a35d8a | 634 | |
f78898e9 HE |
635 | packet.type = DF_LOGIC16; |
636 | packet.length = tosend * sizeof(uint16_t); | |
fefa1800 | 637 | packet.payload = samples + sent; |
28a35d8a HE |
638 | session_bus(user_data, &packet); |
639 | ||
640 | sent += tosend; | |
641 | } | |
642 | } | |
643 | ||
f78898e9 | 644 | return SIGROK_OK; |
28a35d8a HE |
645 | } |
646 | ||
647 | static int receive_data(int fd, int revents, void *user_data) | |
648 | { | |
649 | struct datafeed_packet packet; | |
28a35d8a HE |
650 | const int chunks_per_read = 32; |
651 | unsigned char buf[chunks_per_read * CHUNK_SIZE]; | |
fefa1800 UH |
652 | int bufsz, numchunks, curchunk, i, newchunks; |
653 | uint32_t triggerpos, stoppos, running_msec; | |
28a35d8a | 654 | struct timeval tv; |
28a35d8a | 655 | uint16_t lastts = 0; |
f78898e9 | 656 | uint16_t lastsample = 0; |
28a35d8a HE |
657 | |
658 | fd = fd; | |
659 | revents = revents; | |
660 | ||
fefa1800 | 661 | /* Get the current position. */ |
28a35d8a HE |
662 | sigma_read_pos(&stoppos, &triggerpos); |
663 | numchunks = stoppos / 512; | |
664 | ||
fefa1800 | 665 | /* Check if the has expired, or memory is full. */ |
28a35d8a HE |
666 | gettimeofday(&tv, 0); |
667 | running_msec = (tv.tv_sec - start_tv.tv_sec) * 1000 + | |
fefa1800 | 668 | (tv.tv_usec - start_tv.tv_usec) / 1000; |
28a35d8a HE |
669 | |
670 | if (running_msec < limit_msec && numchunks < 32767) | |
671 | return FALSE; | |
672 | ||
fefa1800 | 673 | /* Stop acqusition. */ |
28a35d8a HE |
674 | sigma_set_register(WRITE_MODE, 0x11); |
675 | ||
fefa1800 | 676 | /* Set SDRAM Read Enable. */ |
28a35d8a HE |
677 | sigma_set_register(WRITE_MODE, 0x02); |
678 | ||
fefa1800 | 679 | /* Get the current position. */ |
28a35d8a HE |
680 | sigma_read_pos(&stoppos, &triggerpos); |
681 | ||
f78898e9 HE |
682 | /* Read mode status. We will care for this later. */ |
683 | sigma_get_register(READ_MODE); | |
684 | ||
fefa1800 | 685 | /* Download sample data. */ |
28a35d8a | 686 | for (curchunk = 0; curchunk < numchunks;) { |
fefa1800 | 687 | newchunks = MIN(chunks_per_read, numchunks - curchunk); |
28a35d8a HE |
688 | |
689 | g_message("Downloading sample data: %.0f %%", | |
fefa1800 | 690 | 100.0 * curchunk / numchunks); |
28a35d8a HE |
691 | |
692 | bufsz = sigma_read_dram(curchunk, newchunks, buf); | |
693 | ||
fefa1800 UH |
694 | /* Find first ts. */ |
695 | if (curchunk == 0) | |
696 | lastts = *(uint16_t *) buf - 1; | |
28a35d8a | 697 | |
fefa1800 | 698 | /* Decode chunks and send them to sigrok. */ |
28a35d8a HE |
699 | for (i = 0; i < newchunks; ++i) { |
700 | decode_chunk_ts(buf + (i * CHUNK_SIZE), | |
701 | &lastts, &lastsample, user_data); | |
702 | } | |
703 | ||
704 | curchunk += newchunks; | |
705 | } | |
706 | ||
707 | /* End of data */ | |
708 | packet.type = DF_END; | |
709 | packet.length = 0; | |
710 | session_bus(user_data, &packet); | |
711 | ||
712 | return TRUE; | |
713 | } | |
714 | ||
715 | static int hw_start_acquisition(int device_index, gpointer session_device_id) | |
716 | { | |
717 | struct sigrok_device_instance *sdi; | |
718 | struct datafeed_packet packet; | |
719 | struct datafeed_header header; | |
fefa1800 | 720 | uint8_t trigger_option[2] = { 0x38, 0x00 }; |
28a35d8a HE |
721 | |
722 | session_device_id = session_device_id; | |
723 | ||
724 | if (!(sdi = get_sigrok_device_instance(device_instances, device_index))) | |
725 | return SIGROK_ERR; | |
726 | ||
727 | device_index = device_index; | |
728 | ||
e8397563 HE |
729 | if (cur_firmware == -1) { |
730 | /* Samplerate has not been set. Default to 200 MHz */ | |
731 | set_samplerate(sdi, 200); | |
732 | } | |
733 | ||
fefa1800 | 734 | /* Setup trigger (by trigger-in). */ |
28a35d8a HE |
735 | sigma_set_register(WRITE_TRIGGER_SELECT1, 0x20); |
736 | ||
fefa1800 | 737 | /* More trigger setup. */ |
28a35d8a | 738 | sigma_write_register(WRITE_TRIGGER_OPTION, |
fefa1800 | 739 | trigger_option, sizeof(trigger_option)); |
28a35d8a | 740 | |
fefa1800 | 741 | /* Trigger normal (falling edge). */ |
28a35d8a HE |
742 | sigma_set_register(WRITE_TRIGGER_SELECT1, 0x08); |
743 | ||
fefa1800 | 744 | /* Enable pins (200 MHz, 4 pins). */ |
28a35d8a HE |
745 | sigma_set_register(WRITE_CLOCK_SELECT, 0xf0); |
746 | ||
fefa1800 | 747 | /* Setup maximum post trigger time. */ |
28a35d8a HE |
748 | sigma_set_register(WRITE_POST_TRIGGER, 0xff); |
749 | ||
fefa1800 | 750 | /* Start acqusition (software trigger start). */ |
28a35d8a HE |
751 | gettimeofday(&start_tv, 0); |
752 | sigma_set_register(WRITE_MODE, 0x0d); | |
753 | ||
fefa1800 | 754 | /* Add capture source. */ |
28a35d8a HE |
755 | source_add(0, G_IO_IN, 10, receive_data, session_device_id); |
756 | ||
757 | receive_data(0, 1, session_device_id); | |
758 | ||
759 | /* Send header packet to the session bus. */ | |
760 | packet.type = DF_HEADER; | |
761 | packet.length = sizeof(struct datafeed_header); | |
762 | packet.payload = &header; | |
763 | header.feed_version = 1; | |
764 | gettimeofday(&header.starttime, NULL); | |
765 | header.samplerate = cur_samplerate; | |
766 | header.protocol_id = PROTO_RAW; | |
767 | header.num_probes = 4; | |
768 | session_bus(session_device_id, &packet); | |
769 | ||
770 | return SIGROK_OK; | |
771 | } | |
772 | ||
28a35d8a HE |
773 | static void hw_stop_acquisition(int device_index, gpointer session_device_id) |
774 | { | |
775 | device_index = device_index; | |
776 | session_device_id = session_device_id; | |
777 | ||
fefa1800 | 778 | /* Stop acquisition. */ |
28a35d8a HE |
779 | sigma_set_register(WRITE_MODE, 0x11); |
780 | ||
781 | // XXX Set some state to indicate that data should be sent to sigrok | |
782 | // Now, we just wait for timeout | |
783 | } | |
784 | ||
28a35d8a HE |
785 | struct device_plugin asix_sigma_plugin_info = { |
786 | "asix-sigma", | |
787 | 1, | |
788 | hw_init, | |
789 | hw_cleanup, | |
28a35d8a HE |
790 | hw_opendev, |
791 | hw_closedev, | |
792 | hw_get_device_info, | |
793 | hw_get_status, | |
794 | hw_get_capabilities, | |
795 | hw_set_configuration, | |
796 | hw_start_acquisition, | |
797 | hw_stop_acquisition | |
798 | }; |