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Commit | Line | Data |
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28a35d8a HE |
1 | /* |
2 | * This file is part of the sigrok project. | |
3 | * | |
868501fa | 4 | * Copyright (C) 2010-2012 Håvard Espeland <gus@ping.uio.no>, |
911f1834 UH |
5 | * Copyright (C) 2010 Martin Stensgård <mastensg@ping.uio.no> |
6 | * Copyright (C) 2010 Carl Henrik Lunde <chlunde@ping.uio.no> | |
28a35d8a HE |
7 | * |
8 | * This program is free software: you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation, either version 3 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
20 | */ | |
21 | ||
911f1834 | 22 | /* |
6352d030 | 23 | * ASIX SIGMA/SIGMA2 logic analyzer driver |
911f1834 UH |
24 | */ |
25 | ||
3bbd9849 UH |
26 | #include <glib.h> |
27 | #include <glib/gstdio.h> | |
28a35d8a HE |
28 | #include <ftdi.h> |
29 | #include <string.h> | |
b7f09cf8 UH |
30 | #include "sigrok.h" |
31 | #include "sigrok-internal.h" | |
28a35d8a HE |
32 | #include "asix-sigma.h" |
33 | ||
34 | #define USB_VENDOR 0xa600 | |
35 | #define USB_PRODUCT 0xa000 | |
36 | #define USB_DESCRIPTION "ASIX SIGMA" | |
37 | #define USB_VENDOR_NAME "ASIX" | |
38 | #define USB_MODEL_NAME "SIGMA" | |
39 | #define USB_MODEL_VERSION "" | |
ee492173 | 40 | #define TRIGGER_TYPES "rf10" |
464d12c7 | 41 | #define NUM_PROBES 16 |
28a35d8a | 42 | |
d68e2d1a | 43 | static GSList *dev_insts = NULL; |
28a35d8a | 44 | |
28a35d8a | 45 | static uint64_t supported_samplerates[] = { |
59df0c77 UH |
46 | SR_KHZ(200), |
47 | SR_KHZ(250), | |
48 | SR_KHZ(500), | |
49 | SR_MHZ(1), | |
50 | SR_MHZ(5), | |
51 | SR_MHZ(10), | |
52 | SR_MHZ(25), | |
53 | SR_MHZ(50), | |
54 | SR_MHZ(100), | |
55 | SR_MHZ(200), | |
28a35d8a HE |
56 | 0, |
57 | }; | |
58 | ||
d261dbbf UH |
59 | /* |
60 | * Probe numbers seem to go from 1-16, according to this image: | |
61 | * http://tools.asix.net/img/sigma_sigmacab_pins_720.jpg | |
62 | * (the cable has two additional GND pins, and a TI and TO pin) | |
63 | */ | |
c37d2b1b | 64 | static const char *probe_names[NUM_PROBES + 1] = { |
464d12c7 KS |
65 | "1", |
66 | "2", | |
67 | "3", | |
68 | "4", | |
69 | "5", | |
70 | "6", | |
71 | "7", | |
72 | "8", | |
73 | "9", | |
74 | "10", | |
75 | "11", | |
76 | "12", | |
77 | "13", | |
78 | "14", | |
79 | "15", | |
d261dbbf | 80 | "16", |
464d12c7 KS |
81 | NULL, |
82 | }; | |
83 | ||
60679b18 | 84 | static struct sr_samplerates samplerates = { |
590b9f9a UH |
85 | 0, |
86 | 0, | |
87 | 0, | |
28a35d8a HE |
88 | supported_samplerates, |
89 | }; | |
90 | ||
915f7cc8 | 91 | static const int hwcaps[] = { |
5a2326a7 UH |
92 | SR_HWCAP_LOGIC_ANALYZER, |
93 | SR_HWCAP_SAMPLERATE, | |
94 | SR_HWCAP_CAPTURE_RATIO, | |
95 | SR_HWCAP_PROBECONFIG, | |
28a35d8a | 96 | |
5a2326a7 | 97 | SR_HWCAP_LIMIT_MSEC, |
28a35d8a HE |
98 | 0, |
99 | }; | |
100 | ||
fefa1800 UH |
101 | /* Force the FPGA to reboot. */ |
102 | static uint8_t suicide[] = { | |
103 | 0x84, 0x84, 0x88, 0x84, 0x88, 0x84, 0x88, 0x84, | |
104 | }; | |
105 | ||
106 | /* Prepare to upload firmware (FPGA specific). */ | |
107 | static uint8_t init[] = { | |
108 | 0x03, 0x03, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, | |
109 | }; | |
110 | ||
111 | /* Initialize the logic analyzer mode. */ | |
112 | static uint8_t logic_mode_start[] = { | |
113 | 0x00, 0x40, 0x0f, 0x25, 0x35, 0x40, | |
114 | 0x2a, 0x3a, 0x40, 0x03, 0x20, 0x38, | |
115 | }; | |
116 | ||
eec5275e | 117 | static const char *firmware_files[] = { |
a8116d76 HE |
118 | "asix-sigma-50.fw", /* 50 MHz, supports 8 bit fractions */ |
119 | "asix-sigma-100.fw", /* 100 MHz */ | |
120 | "asix-sigma-200.fw", /* 200 MHz */ | |
ed09fd07 | 121 | "asix-sigma-50sync.fw", /* Synchronous clock from pin */ |
a8116d76 | 122 | "asix-sigma-phasor.fw", /* Frequency counter */ |
f6564c8d HE |
123 | }; |
124 | ||
3cd3a20b | 125 | static int hw_dev_acquisition_stop(int dev_index, void *cb_data); |
6aac7737 | 126 | |
ea9cfed7 | 127 | static int sigma_read(void *buf, size_t size, struct context *ctx) |
28a35d8a HE |
128 | { |
129 | int ret; | |
fefa1800 | 130 | |
ea9cfed7 | 131 | ret = ftdi_read_data(&ctx->ftdic, (unsigned char *)buf, size); |
28a35d8a | 132 | if (ret < 0) { |
7b48d6e1 | 133 | sr_err("sigma: ftdi_read_data failed: %s", |
ea9cfed7 | 134 | ftdi_get_error_string(&ctx->ftdic)); |
28a35d8a HE |
135 | } |
136 | ||
137 | return ret; | |
138 | } | |
139 | ||
ea9cfed7 | 140 | static int sigma_write(void *buf, size_t size, struct context *ctx) |
28a35d8a HE |
141 | { |
142 | int ret; | |
fefa1800 | 143 | |
ea9cfed7 | 144 | ret = ftdi_write_data(&ctx->ftdic, (unsigned char *)buf, size); |
28a35d8a | 145 | if (ret < 0) { |
7b48d6e1 | 146 | sr_err("sigma: ftdi_write_data failed: %s", |
ea9cfed7 | 147 | ftdi_get_error_string(&ctx->ftdic)); |
fefa1800 | 148 | } else if ((size_t) ret != size) { |
0aeb0ccd | 149 | sr_err("sigma: ftdi_write_data did not complete write."); |
28a35d8a HE |
150 | } |
151 | ||
152 | return ret; | |
153 | } | |
154 | ||
99965709 | 155 | static int sigma_write_register(uint8_t reg, uint8_t *data, size_t len, |
ea9cfed7 | 156 | struct context *ctx) |
28a35d8a HE |
157 | { |
158 | size_t i; | |
159 | uint8_t buf[len + 2]; | |
160 | int idx = 0; | |
161 | ||
162 | buf[idx++] = REG_ADDR_LOW | (reg & 0xf); | |
163 | buf[idx++] = REG_ADDR_HIGH | (reg >> 4); | |
164 | ||
fefa1800 | 165 | for (i = 0; i < len; ++i) { |
28a35d8a HE |
166 | buf[idx++] = REG_DATA_LOW | (data[i] & 0xf); |
167 | buf[idx++] = REG_DATA_HIGH_WRITE | (data[i] >> 4); | |
168 | } | |
169 | ||
ea9cfed7 | 170 | return sigma_write(buf, idx, ctx); |
28a35d8a HE |
171 | } |
172 | ||
ea9cfed7 | 173 | static int sigma_set_register(uint8_t reg, uint8_t value, struct context *ctx) |
28a35d8a | 174 | { |
ea9cfed7 | 175 | return sigma_write_register(reg, &value, 1, ctx); |
28a35d8a HE |
176 | } |
177 | ||
99965709 | 178 | static int sigma_read_register(uint8_t reg, uint8_t *data, size_t len, |
ea9cfed7 | 179 | struct context *ctx) |
28a35d8a HE |
180 | { |
181 | uint8_t buf[3]; | |
fefa1800 | 182 | |
28a35d8a HE |
183 | buf[0] = REG_ADDR_LOW | (reg & 0xf); |
184 | buf[1] = REG_ADDR_HIGH | (reg >> 4); | |
28a35d8a HE |
185 | buf[2] = REG_READ_ADDR; |
186 | ||
ea9cfed7 | 187 | sigma_write(buf, sizeof(buf), ctx); |
28a35d8a | 188 | |
ea9cfed7 | 189 | return sigma_read(data, len, ctx); |
28a35d8a HE |
190 | } |
191 | ||
ea9cfed7 | 192 | static uint8_t sigma_get_register(uint8_t reg, struct context *ctx) |
28a35d8a HE |
193 | { |
194 | uint8_t value; | |
fefa1800 | 195 | |
ea9cfed7 | 196 | if (1 != sigma_read_register(reg, &value, 1, ctx)) { |
7b48d6e1 | 197 | sr_err("sigma: sigma_get_register: 1 byte expected"); |
28a35d8a HE |
198 | return 0; |
199 | } | |
200 | ||
201 | return value; | |
202 | } | |
203 | ||
99965709 | 204 | static int sigma_read_pos(uint32_t *stoppos, uint32_t *triggerpos, |
ea9cfed7 | 205 | struct context *ctx) |
28a35d8a HE |
206 | { |
207 | uint8_t buf[] = { | |
208 | REG_ADDR_LOW | READ_TRIGGER_POS_LOW, | |
209 | ||
210 | REG_READ_ADDR | NEXT_REG, | |
211 | REG_READ_ADDR | NEXT_REG, | |
212 | REG_READ_ADDR | NEXT_REG, | |
213 | REG_READ_ADDR | NEXT_REG, | |
214 | REG_READ_ADDR | NEXT_REG, | |
215 | REG_READ_ADDR | NEXT_REG, | |
216 | }; | |
28a35d8a HE |
217 | uint8_t result[6]; |
218 | ||
ea9cfed7 | 219 | sigma_write(buf, sizeof(buf), ctx); |
28a35d8a | 220 | |
ea9cfed7 | 221 | sigma_read(result, sizeof(result), ctx); |
28a35d8a HE |
222 | |
223 | *triggerpos = result[0] | (result[1] << 8) | (result[2] << 16); | |
224 | *stoppos = result[3] | (result[4] << 8) | (result[5] << 16); | |
225 | ||
57bbf56b HE |
226 | /* Not really sure why this must be done, but according to spec. */ |
227 | if ((--*stoppos & 0x1ff) == 0x1ff) | |
228 | stoppos -= 64; | |
229 | ||
230 | if ((*--triggerpos & 0x1ff) == 0x1ff) | |
231 | triggerpos -= 64; | |
232 | ||
28a35d8a HE |
233 | return 1; |
234 | } | |
235 | ||
99965709 | 236 | static int sigma_read_dram(uint16_t startchunk, size_t numchunks, |
ea9cfed7 | 237 | uint8_t *data, struct context *ctx) |
28a35d8a HE |
238 | { |
239 | size_t i; | |
240 | uint8_t buf[4096]; | |
241 | int idx = 0; | |
242 | ||
fefa1800 | 243 | /* Send the startchunk. Index start with 1. */ |
28a35d8a HE |
244 | buf[0] = startchunk >> 8; |
245 | buf[1] = startchunk & 0xff; | |
ea9cfed7 | 246 | sigma_write_register(WRITE_MEMROW, buf, 2, ctx); |
28a35d8a | 247 | |
fefa1800 | 248 | /* Read the DRAM. */ |
28a35d8a HE |
249 | buf[idx++] = REG_DRAM_BLOCK; |
250 | buf[idx++] = REG_DRAM_WAIT_ACK; | |
251 | ||
252 | for (i = 0; i < numchunks; ++i) { | |
fefa1800 UH |
253 | /* Alternate bit to copy from DRAM to cache. */ |
254 | if (i != (numchunks - 1)) | |
255 | buf[idx++] = REG_DRAM_BLOCK | (((i + 1) % 2) << 4); | |
28a35d8a HE |
256 | |
257 | buf[idx++] = REG_DRAM_BLOCK_DATA | ((i % 2) << 4); | |
258 | ||
fefa1800 | 259 | if (i != (numchunks - 1)) |
28a35d8a HE |
260 | buf[idx++] = REG_DRAM_WAIT_ACK; |
261 | } | |
262 | ||
ea9cfed7 | 263 | sigma_write(buf, idx, ctx); |
28a35d8a | 264 | |
ea9cfed7 | 265 | return sigma_read(data, numchunks * CHUNK_SIZE, ctx); |
28a35d8a HE |
266 | } |
267 | ||
4ae1f451 | 268 | /* Upload trigger look-up tables to Sigma. */ |
ea9cfed7 | 269 | static int sigma_write_trigger_lut(struct triggerlut *lut, struct context *ctx) |
ee492173 HE |
270 | { |
271 | int i; | |
272 | uint8_t tmp[2]; | |
273 | uint16_t bit; | |
274 | ||
275 | /* Transpose the table and send to Sigma. */ | |
276 | for (i = 0; i < 16; ++i) { | |
277 | bit = 1 << i; | |
278 | ||
279 | tmp[0] = tmp[1] = 0; | |
280 | ||
281 | if (lut->m2d[0] & bit) | |
282 | tmp[0] |= 0x01; | |
283 | if (lut->m2d[1] & bit) | |
284 | tmp[0] |= 0x02; | |
285 | if (lut->m2d[2] & bit) | |
286 | tmp[0] |= 0x04; | |
287 | if (lut->m2d[3] & bit) | |
288 | tmp[0] |= 0x08; | |
289 | ||
290 | if (lut->m3 & bit) | |
291 | tmp[0] |= 0x10; | |
292 | if (lut->m3s & bit) | |
293 | tmp[0] |= 0x20; | |
294 | if (lut->m4 & bit) | |
295 | tmp[0] |= 0x40; | |
296 | ||
297 | if (lut->m0d[0] & bit) | |
298 | tmp[1] |= 0x01; | |
299 | if (lut->m0d[1] & bit) | |
300 | tmp[1] |= 0x02; | |
301 | if (lut->m0d[2] & bit) | |
302 | tmp[1] |= 0x04; | |
303 | if (lut->m0d[3] & bit) | |
304 | tmp[1] |= 0x08; | |
305 | ||
306 | if (lut->m1d[0] & bit) | |
307 | tmp[1] |= 0x10; | |
308 | if (lut->m1d[1] & bit) | |
309 | tmp[1] |= 0x20; | |
310 | if (lut->m1d[2] & bit) | |
311 | tmp[1] |= 0x40; | |
312 | if (lut->m1d[3] & bit) | |
313 | tmp[1] |= 0x80; | |
314 | ||
99965709 | 315 | sigma_write_register(WRITE_TRIGGER_SELECT0, tmp, sizeof(tmp), |
ea9cfed7 UH |
316 | ctx); |
317 | sigma_set_register(WRITE_TRIGGER_SELECT1, 0x30 | i, ctx); | |
ee492173 HE |
318 | } |
319 | ||
320 | /* Send the parameters */ | |
321 | sigma_write_register(WRITE_TRIGGER_SELECT0, (uint8_t *) &lut->params, | |
ea9cfed7 | 322 | sizeof(lut->params), ctx); |
ee492173 | 323 | |
e46b8fb1 | 324 | return SR_OK; |
ee492173 HE |
325 | } |
326 | ||
fefa1800 | 327 | /* Generate the bitbang stream for programming the FPGA. */ |
28a35d8a | 328 | static int bin2bitbang(const char *filename, |
fefa1800 | 329 | unsigned char **buf, size_t *buf_size) |
28a35d8a | 330 | { |
fefa1800 | 331 | FILE *f; |
e3fff420 | 332 | unsigned long file_size; |
28a35d8a HE |
333 | unsigned long offset = 0; |
334 | unsigned char *p; | |
e3fff420 HE |
335 | uint8_t *firmware; |
336 | unsigned long fwsize = 0; | |
28a35d8a HE |
337 | const int buffer_size = 65536; |
338 | size_t i; | |
e3fff420 | 339 | int c, bit, v; |
fefa1800 | 340 | uint32_t imm = 0x3f6df2ab; |
28a35d8a | 341 | |
868d8cef | 342 | f = g_fopen(filename, "rb"); |
28a35d8a | 343 | if (!f) { |
7b48d6e1 | 344 | sr_err("sigma: g_fopen(\"%s\", \"rb\")", filename); |
b53738ba | 345 | return SR_ERR; |
28a35d8a HE |
346 | } |
347 | ||
348 | if (-1 == fseek(f, 0, SEEK_END)) { | |
7b48d6e1 | 349 | sr_err("sigma: fseek on %s failed", filename); |
28a35d8a | 350 | fclose(f); |
b53738ba | 351 | return SR_ERR; |
28a35d8a HE |
352 | } |
353 | ||
354 | file_size = ftell(f); | |
355 | ||
356 | fseek(f, 0, SEEK_SET); | |
357 | ||
b53738ba | 358 | if (!(firmware = g_try_malloc(buffer_size))) { |
340cfac0 | 359 | sr_err("sigma: %s: firmware malloc failed", __func__); |
12ad53f5 | 360 | fclose(f); |
b53738ba | 361 | return SR_ERR_MALLOC; |
28a35d8a HE |
362 | } |
363 | ||
28a35d8a HE |
364 | while ((c = getc(f)) != EOF) { |
365 | imm = (imm + 0xa853753) % 177 + (imm * 0x8034052); | |
e3fff420 | 366 | firmware[fwsize++] = c ^ imm; |
28a35d8a HE |
367 | } |
368 | fclose(f); | |
369 | ||
e3fff420 HE |
370 | if(fwsize != file_size) { |
371 | sr_err("sigma: %s: Error reading firmware", filename); | |
372 | fclose(f); | |
373 | g_free(firmware); | |
374 | return SR_ERR; | |
28a35d8a HE |
375 | } |
376 | ||
28a35d8a HE |
377 | *buf_size = fwsize * 2 * 8; |
378 | ||
b53738ba | 379 | *buf = p = (unsigned char *)g_try_malloc(*buf_size); |
28a35d8a | 380 | if (!p) { |
340cfac0 | 381 | sr_err("sigma: %s: buf/p malloc failed", __func__); |
12ad53f5 | 382 | g_free(firmware); |
b53738ba | 383 | return SR_ERR_MALLOC; |
28a35d8a HE |
384 | } |
385 | ||
386 | for (i = 0; i < fwsize; ++i) { | |
28a35d8a | 387 | for (bit = 7; bit >= 0; --bit) { |
fefa1800 | 388 | v = firmware[i] & 1 << bit ? 0x40 : 0x00; |
28a35d8a HE |
389 | p[offset++] = v | 0x01; |
390 | p[offset++] = v; | |
391 | } | |
392 | } | |
393 | ||
394 | g_free(firmware); | |
395 | ||
396 | if (offset != *buf_size) { | |
397 | g_free(*buf); | |
7b48d6e1 | 398 | sr_err("sigma: Error reading firmware %s " |
0aeb0ccd | 399 | "offset=%ld, file_size=%ld, buf_size=%zd.", |
133a37bf | 400 | filename, offset, file_size, *buf_size); |
28a35d8a | 401 | |
b53738ba | 402 | return SR_ERR; |
28a35d8a HE |
403 | } |
404 | ||
b53738ba | 405 | return SR_OK; |
28a35d8a HE |
406 | } |
407 | ||
bb7ef793 | 408 | static int hw_init(const char *devinfo) |
28a35d8a | 409 | { |
d68e2d1a | 410 | struct sr_dev_inst *sdi; |
ea9cfed7 | 411 | struct context *ctx; |
e3fff420 HE |
412 | struct ftdi_device_list *devlist; |
413 | char serial_txt[10]; | |
414 | uint32_t serial; | |
28a35d8a | 415 | |
b53738ba | 416 | /* Avoid compiler warnings. */ |
bb7ef793 | 417 | (void)devinfo; |
28a35d8a | 418 | |
ea9cfed7 UH |
419 | if (!(ctx = g_try_malloc(sizeof(struct context)))) { |
420 | sr_err("sigma: %s: ctx malloc failed", __func__); | |
e3fff420 | 421 | return SR_ERR_MALLOC; |
b53738ba | 422 | } |
99965709 | 423 | |
ea9cfed7 | 424 | ftdi_init(&ctx->ftdic); |
28a35d8a | 425 | |
fefa1800 | 426 | /* Look for SIGMAs. */ |
e3fff420 HE |
427 | |
428 | if (ftdi_usb_find_all(&ctx->ftdic, &devlist, | |
6352d030 | 429 | USB_VENDOR, USB_PRODUCT) <= 0) |
99965709 HE |
430 | goto free; |
431 | ||
e3fff420 HE |
432 | /* Make sure it's a version 1 or 2 SIGMA. */ |
433 | ftdi_usb_get_strings(&ctx->ftdic, devlist->dev, NULL, 0, NULL, 0, | |
6352d030 | 434 | serial_txt, sizeof(serial_txt)); |
e3fff420 HE |
435 | sscanf(serial_txt, "%x", &serial); |
436 | ||
6352d030 | 437 | if (serial < 0xa6010000 || serial > 0xa602ffff) { |
e3fff420 | 438 | sr_err("sigma: Only SIGMA and SIGMA2 are supported " |
6352d030 | 439 | "in this version of sigrok."); |
e3fff420 HE |
440 | goto free; |
441 | } | |
442 | ||
443 | sr_info("Found ASIX SIGMA - Serial: %s", serial_txt); | |
444 | ||
ea9cfed7 UH |
445 | ctx->cur_samplerate = 0; |
446 | ctx->period_ps = 0; | |
447 | ctx->limit_msec = 0; | |
448 | ctx->cur_firmware = -1; | |
449 | ctx->num_probes = 0; | |
450 | ctx->samples_per_event = 0; | |
451 | ctx->capture_ratio = 50; | |
452 | ctx->use_triggers = 0; | |
28a35d8a | 453 | |
fefa1800 | 454 | /* Register SIGMA device. */ |
d68e2d1a UH |
455 | if (!(sdi = sr_dev_inst_new(0, SR_ST_INITIALIZING, USB_VENDOR_NAME, |
456 | USB_MODEL_NAME, USB_MODEL_VERSION))) { | |
457 | sr_err("sigma: %s: sdi was NULL", __func__); | |
99965709 | 458 | goto free; |
d68e2d1a | 459 | } |
99965709 | 460 | |
ea9cfed7 | 461 | sdi->priv = ctx; |
28a35d8a | 462 | |
d68e2d1a | 463 | dev_insts = g_slist_append(dev_insts, sdi); |
28a35d8a | 464 | |
fefa1800 | 465 | /* We will open the device again when we need it. */ |
e3fff420 | 466 | ftdi_list_free(&devlist); |
28a35d8a HE |
467 | |
468 | return 1; | |
ea9cfed7 | 469 | |
99965709 | 470 | free: |
ea9cfed7 | 471 | g_free(ctx); |
99965709 | 472 | return 0; |
28a35d8a HE |
473 | } |
474 | ||
ea9cfed7 | 475 | static int upload_firmware(int firmware_idx, struct context *ctx) |
28a35d8a HE |
476 | { |
477 | int ret; | |
478 | unsigned char *buf; | |
479 | unsigned char pins; | |
480 | size_t buf_size; | |
28a35d8a | 481 | unsigned char result[32]; |
e8397563 | 482 | char firmware_path[128]; |
28a35d8a | 483 | |
fefa1800 | 484 | /* Make sure it's an ASIX SIGMA. */ |
ea9cfed7 | 485 | if ((ret = ftdi_usb_open_desc(&ctx->ftdic, |
28a35d8a | 486 | USB_VENDOR, USB_PRODUCT, USB_DESCRIPTION, NULL)) < 0) { |
7b48d6e1 | 487 | sr_err("sigma: ftdi_usb_open failed: %s", |
ea9cfed7 | 488 | ftdi_get_error_string(&ctx->ftdic)); |
28a35d8a HE |
489 | return 0; |
490 | } | |
491 | ||
ea9cfed7 | 492 | if ((ret = ftdi_set_bitmode(&ctx->ftdic, 0xdf, BITMODE_BITBANG)) < 0) { |
7b48d6e1 | 493 | sr_err("sigma: ftdi_set_bitmode failed: %s", |
ea9cfed7 | 494 | ftdi_get_error_string(&ctx->ftdic)); |
28a35d8a HE |
495 | return 0; |
496 | } | |
497 | ||
fefa1800 | 498 | /* Four times the speed of sigmalogan - Works well. */ |
ea9cfed7 | 499 | if ((ret = ftdi_set_baudrate(&ctx->ftdic, 750000)) < 0) { |
7b48d6e1 | 500 | sr_err("sigma: ftdi_set_baudrate failed: %s", |
ea9cfed7 | 501 | ftdi_get_error_string(&ctx->ftdic)); |
28a35d8a HE |
502 | return 0; |
503 | } | |
504 | ||
fefa1800 | 505 | /* Force the FPGA to reboot. */ |
ea9cfed7 UH |
506 | sigma_write(suicide, sizeof(suicide), ctx); |
507 | sigma_write(suicide, sizeof(suicide), ctx); | |
508 | sigma_write(suicide, sizeof(suicide), ctx); | |
509 | sigma_write(suicide, sizeof(suicide), ctx); | |
28a35d8a | 510 | |
fefa1800 | 511 | /* Prepare to upload firmware (FPGA specific). */ |
ea9cfed7 | 512 | sigma_write(init, sizeof(init), ctx); |
28a35d8a | 513 | |
ea9cfed7 | 514 | ftdi_usb_purge_buffers(&ctx->ftdic); |
28a35d8a | 515 | |
fefa1800 | 516 | /* Wait until the FPGA asserts INIT_B. */ |
28a35d8a | 517 | while (1) { |
ea9cfed7 | 518 | ret = sigma_read(result, 1, ctx); |
28a35d8a HE |
519 | if (result[0] & 0x20) |
520 | break; | |
521 | } | |
522 | ||
9ddb2a12 | 523 | /* Prepare firmware. */ |
e8397563 | 524 | snprintf(firmware_path, sizeof(firmware_path), "%s/%s", FIRMWARE_DIR, |
f6564c8d HE |
525 | firmware_files[firmware_idx]); |
526 | ||
b53738ba | 527 | if ((ret = bin2bitbang(firmware_path, &buf, &buf_size)) != SR_OK) { |
7b48d6e1 | 528 | sr_err("sigma: An error occured while reading the firmware: %s", |
133a37bf | 529 | firmware_path); |
b53738ba | 530 | return ret; |
28a35d8a HE |
531 | } |
532 | ||
fefa1800 | 533 | /* Upload firmare. */ |
e3fff420 | 534 | sr_info("sigma: Uploading firmware %s", firmware_files[firmware_idx]); |
ea9cfed7 | 535 | sigma_write(buf, buf_size, ctx); |
28a35d8a HE |
536 | |
537 | g_free(buf); | |
538 | ||
ea9cfed7 | 539 | if ((ret = ftdi_set_bitmode(&ctx->ftdic, 0x00, BITMODE_RESET)) < 0) { |
7b48d6e1 | 540 | sr_err("sigma: ftdi_set_bitmode failed: %s", |
ea9cfed7 | 541 | ftdi_get_error_string(&ctx->ftdic)); |
e46b8fb1 | 542 | return SR_ERR; |
28a35d8a HE |
543 | } |
544 | ||
ea9cfed7 | 545 | ftdi_usb_purge_buffers(&ctx->ftdic); |
28a35d8a | 546 | |
fefa1800 | 547 | /* Discard garbage. */ |
ea9cfed7 | 548 | while (1 == sigma_read(&pins, 1, ctx)) |
28a35d8a HE |
549 | ; |
550 | ||
fefa1800 | 551 | /* Initialize the logic analyzer mode. */ |
ea9cfed7 | 552 | sigma_write(logic_mode_start, sizeof(logic_mode_start), ctx); |
28a35d8a | 553 | |
fefa1800 | 554 | /* Expect a 3 byte reply. */ |
ea9cfed7 | 555 | ret = sigma_read(result, 3, ctx); |
28a35d8a HE |
556 | if (ret != 3 || |
557 | result[0] != 0xa6 || result[1] != 0x55 || result[2] != 0xaa) { | |
7b48d6e1 | 558 | sr_err("sigma: Configuration failed. Invalid reply received."); |
e46b8fb1 | 559 | return SR_ERR; |
28a35d8a HE |
560 | } |
561 | ||
ea9cfed7 | 562 | ctx->cur_firmware = firmware_idx; |
f6564c8d | 563 | |
e3fff420 HE |
564 | sr_info("sigma: Firmware uploaded"); |
565 | ||
e46b8fb1 | 566 | return SR_OK; |
f6564c8d HE |
567 | } |
568 | ||
e7eb703f | 569 | static int hw_dev_open(int dev_index) |
f6564c8d | 570 | { |
d68e2d1a | 571 | struct sr_dev_inst *sdi; |
ea9cfed7 | 572 | struct context *ctx; |
f6564c8d HE |
573 | int ret; |
574 | ||
bb7ef793 | 575 | if (!(sdi = sr_dev_inst_get(dev_insts, dev_index))) |
e46b8fb1 | 576 | return SR_ERR; |
99965709 | 577 | |
ea9cfed7 | 578 | ctx = sdi->priv; |
99965709 | 579 | |
9ddb2a12 | 580 | /* Make sure it's an ASIX SIGMA. */ |
ea9cfed7 | 581 | if ((ret = ftdi_usb_open_desc(&ctx->ftdic, |
f6564c8d HE |
582 | USB_VENDOR, USB_PRODUCT, USB_DESCRIPTION, NULL)) < 0) { |
583 | ||
7b48d6e1 | 584 | sr_err("sigma: ftdi_usb_open failed: %s", |
ea9cfed7 | 585 | ftdi_get_error_string(&ctx->ftdic)); |
f6564c8d HE |
586 | |
587 | return 0; | |
588 | } | |
28a35d8a | 589 | |
5a2326a7 | 590 | sdi->status = SR_ST_ACTIVE; |
28a35d8a | 591 | |
e46b8fb1 | 592 | return SR_OK; |
f6564c8d HE |
593 | } |
594 | ||
d68e2d1a | 595 | static int set_samplerate(struct sr_dev_inst *sdi, uint64_t samplerate) |
f6564c8d | 596 | { |
e8397563 | 597 | int i, ret; |
ea9cfed7 | 598 | struct context *ctx = sdi->priv; |
f6564c8d HE |
599 | |
600 | for (i = 0; supported_samplerates[i]; i++) { | |
601 | if (supported_samplerates[i] == samplerate) | |
602 | break; | |
603 | } | |
604 | if (supported_samplerates[i] == 0) | |
e46b8fb1 | 605 | return SR_ERR_SAMPLERATE; |
f6564c8d | 606 | |
59df0c77 | 607 | if (samplerate <= SR_MHZ(50)) { |
ea9cfed7 UH |
608 | ret = upload_firmware(0, ctx); |
609 | ctx->num_probes = 16; | |
e8397563 | 610 | } |
59df0c77 | 611 | if (samplerate == SR_MHZ(100)) { |
ea9cfed7 UH |
612 | ret = upload_firmware(1, ctx); |
613 | ctx->num_probes = 8; | |
f78898e9 | 614 | } |
59df0c77 | 615 | else if (samplerate == SR_MHZ(200)) { |
ea9cfed7 UH |
616 | ret = upload_firmware(2, ctx); |
617 | ctx->num_probes = 4; | |
f78898e9 | 618 | } |
f6564c8d | 619 | |
ea9cfed7 UH |
620 | ctx->cur_samplerate = samplerate; |
621 | ctx->period_ps = 1000000000000 / samplerate; | |
622 | ctx->samples_per_event = 16 / ctx->num_probes; | |
623 | ctx->state.state = SIGMA_IDLE; | |
f6564c8d | 624 | |
e8397563 | 625 | return ret; |
28a35d8a HE |
626 | } |
627 | ||
c53d793f HE |
628 | /* |
629 | * In 100 and 200 MHz mode, only a single pin rising/falling can be | |
630 | * set as trigger. In other modes, two rising/falling triggers can be set, | |
631 | * in addition to value/mask trigger for any number of probes. | |
632 | * | |
633 | * The Sigma supports complex triggers using boolean expressions, but this | |
634 | * has not been implemented yet. | |
635 | */ | |
d68e2d1a | 636 | static int configure_probes(struct sr_dev_inst *sdi, GSList *probes) |
57bbf56b | 637 | { |
ea9cfed7 | 638 | struct context *ctx = sdi->priv; |
1afe8989 | 639 | struct sr_probe *probe; |
57bbf56b HE |
640 | GSList *l; |
641 | int trigger_set = 0; | |
a42aec7f | 642 | int probebit; |
57bbf56b | 643 | |
ea9cfed7 | 644 | memset(&ctx->trigger, 0, sizeof(struct sigma_trigger)); |
eec5275e | 645 | |
57bbf56b | 646 | for (l = probes; l; l = l->next) { |
1afe8989 | 647 | probe = (struct sr_probe *)l->data; |
a42aec7f | 648 | probebit = 1 << (probe->index - 1); |
57bbf56b HE |
649 | |
650 | if (!probe->enabled || !probe->trigger) | |
651 | continue; | |
652 | ||
ea9cfed7 | 653 | if (ctx->cur_samplerate >= SR_MHZ(100)) { |
c53d793f | 654 | /* Fast trigger support. */ |
ee492173 | 655 | if (trigger_set) { |
7b48d6e1 | 656 | sr_err("sigma: ASIX SIGMA only supports a single " |
133a37bf | 657 | "pin trigger in 100 and 200MHz mode."); |
e46b8fb1 | 658 | return SR_ERR; |
ee492173 HE |
659 | } |
660 | if (probe->trigger[0] == 'f') | |
ea9cfed7 | 661 | ctx->trigger.fallingmask |= probebit; |
ee492173 | 662 | else if (probe->trigger[0] == 'r') |
ea9cfed7 | 663 | ctx->trigger.risingmask |= probebit; |
ee492173 | 664 | else { |
7b48d6e1 | 665 | sr_err("sigma: ASIX SIGMA only supports " |
133a37bf UH |
666 | "rising/falling trigger in 100 " |
667 | "and 200MHz mode."); | |
e46b8fb1 | 668 | return SR_ERR; |
ee492173 | 669 | } |
57bbf56b | 670 | |
c53d793f | 671 | ++trigger_set; |
ee492173 | 672 | } else { |
c53d793f HE |
673 | /* Simple trigger support (event). */ |
674 | if (probe->trigger[0] == '1') { | |
ea9cfed7 UH |
675 | ctx->trigger.simplevalue |= probebit; |
676 | ctx->trigger.simplemask |= probebit; | |
c53d793f HE |
677 | } |
678 | else if (probe->trigger[0] == '0') { | |
ea9cfed7 UH |
679 | ctx->trigger.simplevalue &= ~probebit; |
680 | ctx->trigger.simplemask |= probebit; | |
c53d793f HE |
681 | } |
682 | else if (probe->trigger[0] == 'f') { | |
ea9cfed7 | 683 | ctx->trigger.fallingmask |= probebit; |
c53d793f HE |
684 | ++trigger_set; |
685 | } | |
686 | else if (probe->trigger[0] == 'r') { | |
ea9cfed7 | 687 | ctx->trigger.risingmask |= probebit; |
c53d793f HE |
688 | ++trigger_set; |
689 | } | |
ee492173 | 690 | |
ea9cfed7 UH |
691 | /* |
692 | * Actually, Sigma supports 2 rising/falling triggers, | |
693 | * but they are ORed and the current trigger syntax | |
694 | * does not permit ORed triggers. | |
695 | */ | |
98b8cbc1 | 696 | if (trigger_set > 1) { |
7b48d6e1 UH |
697 | sr_err("sigma: ASIX SIGMA only supports 1 " |
698 | "rising/falling triggers."); | |
e46b8fb1 | 699 | return SR_ERR; |
ee492173 | 700 | } |
ee492173 | 701 | } |
5b5ea7c6 HE |
702 | |
703 | if (trigger_set) | |
ea9cfed7 | 704 | ctx->use_triggers = 1; |
57bbf56b HE |
705 | } |
706 | ||
e46b8fb1 | 707 | return SR_OK; |
57bbf56b HE |
708 | } |
709 | ||
e7eb703f | 710 | static int hw_dev_close(int dev_index) |
28a35d8a | 711 | { |
d68e2d1a | 712 | struct sr_dev_inst *sdi; |
ea9cfed7 | 713 | struct context *ctx; |
28a35d8a | 714 | |
bb7ef793 | 715 | if (!(sdi = sr_dev_inst_get(dev_insts, dev_index))) { |
340cfac0 | 716 | sr_err("sigma: %s: sdi was NULL", __func__); |
0abee507 | 717 | return SR_ERR_BUG; |
697785d1 | 718 | } |
9be9893e | 719 | |
ea9cfed7 | 720 | if (!(ctx = sdi->priv)) { |
340cfac0 | 721 | sr_err("sigma: %s: sdi->priv was NULL", __func__); |
0abee507 | 722 | return SR_ERR_BUG; |
9be9893e | 723 | } |
697785d1 UH |
724 | |
725 | /* TODO */ | |
726 | if (sdi->status == SR_ST_ACTIVE) | |
ea9cfed7 | 727 | ftdi_usb_close(&ctx->ftdic); |
697785d1 UH |
728 | |
729 | sdi->status = SR_ST_INACTIVE; | |
730 | ||
731 | return SR_OK; | |
28a35d8a HE |
732 | } |
733 | ||
57ab7d9f | 734 | static int hw_cleanup(void) |
28a35d8a | 735 | { |
99965709 | 736 | GSList *l; |
d68e2d1a | 737 | struct sr_dev_inst *sdi; |
57ab7d9f | 738 | int ret = SR_OK; |
99965709 HE |
739 | |
740 | /* Properly close all devices. */ | |
d68e2d1a | 741 | for (l = dev_insts; l; l = l->next) { |
57ab7d9f UH |
742 | if (!(sdi = l->data)) { |
743 | /* Log error, but continue cleaning up the rest. */ | |
7b48d6e1 | 744 | sr_err("sigma: %s: sdi was NULL, continuing", __func__); |
57ab7d9f UH |
745 | ret = SR_ERR_BUG; |
746 | continue; | |
747 | } | |
d3683c42 | 748 | sr_dev_inst_free(sdi); |
99965709 | 749 | } |
d68e2d1a UH |
750 | g_slist_free(dev_insts); |
751 | dev_insts = NULL; | |
57ab7d9f UH |
752 | |
753 | return ret; | |
28a35d8a HE |
754 | } |
755 | ||
b7f578be | 756 | static const void *hw_dev_info_get(int dev_index, int dev_info_id) |
28a35d8a | 757 | { |
d68e2d1a | 758 | struct sr_dev_inst *sdi; |
ea9cfed7 | 759 | struct context *ctx; |
b7f578be | 760 | const void *info = NULL; |
28a35d8a | 761 | |
bb7ef793 | 762 | if (!(sdi = sr_dev_inst_get(dev_insts, dev_index))) { |
7b48d6e1 | 763 | sr_err("sigma: %s: sdi was NULL", __func__); |
28a35d8a HE |
764 | return NULL; |
765 | } | |
766 | ||
ea9cfed7 | 767 | ctx = sdi->priv; |
99965709 | 768 | |
bb7ef793 | 769 | switch (dev_info_id) { |
1d9a8a5f | 770 | case SR_DI_INST: |
28a35d8a HE |
771 | info = sdi; |
772 | break; | |
5a2326a7 | 773 | case SR_DI_NUM_PROBES: |
464d12c7 KS |
774 | info = GINT_TO_POINTER(NUM_PROBES); |
775 | break; | |
776 | case SR_DI_PROBE_NAMES: | |
777 | info = probe_names; | |
28a35d8a | 778 | break; |
5a2326a7 | 779 | case SR_DI_SAMPLERATES: |
28a35d8a HE |
780 | info = &samplerates; |
781 | break; | |
5a2326a7 | 782 | case SR_DI_TRIGGER_TYPES: |
57bbf56b | 783 | info = (char *)TRIGGER_TYPES; |
28a35d8a | 784 | break; |
5a2326a7 | 785 | case SR_DI_CUR_SAMPLERATE: |
ea9cfed7 | 786 | info = &ctx->cur_samplerate; |
28a35d8a HE |
787 | break; |
788 | } | |
789 | ||
790 | return info; | |
791 | } | |
792 | ||
e7eb703f | 793 | static int hw_dev_status_get(int dev_index) |
28a35d8a | 794 | { |
d68e2d1a | 795 | struct sr_dev_inst *sdi; |
28a35d8a | 796 | |
bb7ef793 | 797 | sdi = sr_dev_inst_get(dev_insts, dev_index); |
28a35d8a HE |
798 | if (sdi) |
799 | return sdi->status; | |
800 | else | |
5a2326a7 | 801 | return SR_ST_NOT_FOUND; |
28a35d8a HE |
802 | } |
803 | ||
915f7cc8 | 804 | static const int *hw_hwcap_get_all(void) |
28a35d8a | 805 | { |
ffedd0bf | 806 | return hwcaps; |
28a35d8a HE |
807 | } |
808 | ||
a9a245b4 | 809 | static int hw_dev_config_set(int dev_index, int hwcap, void *value) |
28a35d8a | 810 | { |
d68e2d1a | 811 | struct sr_dev_inst *sdi; |
ea9cfed7 | 812 | struct context *ctx; |
28a35d8a | 813 | int ret; |
f6564c8d | 814 | |
bb7ef793 | 815 | if (!(sdi = sr_dev_inst_get(dev_insts, dev_index))) |
e46b8fb1 | 816 | return SR_ERR; |
28a35d8a | 817 | |
ea9cfed7 | 818 | ctx = sdi->priv; |
99965709 | 819 | |
ffedd0bf | 820 | if (hwcap == SR_HWCAP_SAMPLERATE) { |
ea9cfed7 | 821 | ret = set_samplerate(sdi, *(uint64_t *)value); |
ffedd0bf | 822 | } else if (hwcap == SR_HWCAP_PROBECONFIG) { |
99965709 | 823 | ret = configure_probes(sdi, value); |
ffedd0bf | 824 | } else if (hwcap == SR_HWCAP_LIMIT_MSEC) { |
ea9cfed7 UH |
825 | ctx->limit_msec = *(uint64_t *)value; |
826 | if (ctx->limit_msec > 0) | |
e46b8fb1 | 827 | ret = SR_OK; |
94ba4bd6 | 828 | else |
e46b8fb1 | 829 | ret = SR_ERR; |
ffedd0bf | 830 | } else if (hwcap == SR_HWCAP_CAPTURE_RATIO) { |
ea9cfed7 UH |
831 | ctx->capture_ratio = *(uint64_t *)value; |
832 | if (ctx->capture_ratio < 0 || ctx->capture_ratio > 100) | |
e46b8fb1 | 833 | ret = SR_ERR; |
94ba4bd6 | 834 | else |
e46b8fb1 | 835 | ret = SR_OK; |
28a35d8a | 836 | } else { |
e46b8fb1 | 837 | ret = SR_ERR; |
28a35d8a HE |
838 | } |
839 | ||
840 | return ret; | |
841 | } | |
842 | ||
36b1c8e6 HE |
843 | /* Software trigger to determine exact trigger position. */ |
844 | static int get_trigger_offset(uint16_t *samples, uint16_t last_sample, | |
845 | struct sigma_trigger *t) | |
846 | { | |
847 | int i; | |
848 | ||
849 | for (i = 0; i < 8; ++i) { | |
850 | if (i > 0) | |
851 | last_sample = samples[i-1]; | |
852 | ||
853 | /* Simple triggers. */ | |
854 | if ((samples[i] & t->simplemask) != t->simplevalue) | |
855 | continue; | |
856 | ||
857 | /* Rising edge. */ | |
858 | if ((last_sample & t->risingmask) != 0 || (samples[i] & | |
859 | t->risingmask) != t->risingmask) | |
860 | continue; | |
861 | ||
862 | /* Falling edge. */ | |
bdfc7a89 HE |
863 | if ((last_sample & t->fallingmask) != t->fallingmask || |
864 | (samples[i] & t->fallingmask) != 0) | |
36b1c8e6 HE |
865 | continue; |
866 | ||
867 | break; | |
868 | } | |
869 | ||
870 | /* If we did not match, return original trigger pos. */ | |
871 | return i & 0x7; | |
872 | } | |
873 | ||
28a35d8a | 874 | /* |
fefa1800 UH |
875 | * Decode chunk of 1024 bytes, 64 clusters, 7 events per cluster. |
876 | * Each event is 20ns apart, and can contain multiple samples. | |
f78898e9 HE |
877 | * |
878 | * For 200 MHz, events contain 4 samples for each channel, spread 5 ns apart. | |
879 | * For 100 MHz, events contain 2 samples for each channel, spread 10 ns apart. | |
880 | * For 50 MHz and below, events contain one sample for each channel, | |
881 | * spread 20 ns apart. | |
28a35d8a HE |
882 | */ |
883 | static int decode_chunk_ts(uint8_t *buf, uint16_t *lastts, | |
88c51afe | 884 | uint16_t *lastsample, int triggerpos, |
3cd3a20b | 885 | uint16_t limit_chunk, void *cb_data) |
28a35d8a | 886 | { |
3cd3a20b | 887 | struct sr_dev_inst *sdi = cb_data; |
ea9cfed7 | 888 | struct context *ctx = sdi->priv; |
fefa1800 | 889 | uint16_t tsdiff, ts; |
ea9cfed7 | 890 | uint16_t samples[65536 * ctx->samples_per_event]; |
b9c735a2 | 891 | struct sr_datafeed_packet packet; |
9c939c51 | 892 | struct sr_datafeed_logic logic; |
f78898e9 | 893 | int i, j, k, l, numpad, tosend; |
fefa1800 | 894 | size_t n = 0, sent = 0; |
ea9cfed7 | 895 | int clustersize = EVENTS_PER_CLUSTER * ctx->samples_per_event; |
fefa1800 | 896 | uint16_t *event; |
f78898e9 | 897 | uint16_t cur_sample; |
57bbf56b | 898 | int triggerts = -1; |
ee492173 | 899 | |
4ae1f451 | 900 | /* Check if trigger is in this chunk. */ |
ee492173 | 901 | if (triggerpos != -1) { |
ea9cfed7 | 902 | if (ctx->cur_samplerate <= SR_MHZ(50)) |
36b1c8e6 | 903 | triggerpos -= EVENTS_PER_CLUSTER - 1; |
ee492173 HE |
904 | |
905 | if (triggerpos < 0) | |
906 | triggerpos = 0; | |
57bbf56b | 907 | |
ee492173 HE |
908 | /* Find in which cluster the trigger occured. */ |
909 | triggerts = triggerpos / 7; | |
910 | } | |
28a35d8a | 911 | |
eec5275e | 912 | /* For each ts. */ |
28a35d8a | 913 | for (i = 0; i < 64; ++i) { |
fefa1800 | 914 | ts = *(uint16_t *) &buf[i * 16]; |
28a35d8a HE |
915 | tsdiff = ts - *lastts; |
916 | *lastts = ts; | |
917 | ||
88c51afe HE |
918 | /* Decode partial chunk. */ |
919 | if (limit_chunk && ts > limit_chunk) | |
e46b8fb1 | 920 | return SR_OK; |
88c51afe | 921 | |
fefa1800 | 922 | /* Pad last sample up to current point. */ |
ea9cfed7 | 923 | numpad = tsdiff * ctx->samples_per_event - clustersize; |
28a35d8a | 924 | if (numpad > 0) { |
f78898e9 HE |
925 | for (j = 0; j < numpad; ++j) |
926 | samples[j] = *lastsample; | |
927 | ||
928 | n = numpad; | |
28a35d8a HE |
929 | } |
930 | ||
57bbf56b HE |
931 | /* Send samples between previous and this timestamp to sigrok. */ |
932 | sent = 0; | |
933 | while (sent < n) { | |
934 | tosend = MIN(2048, n - sent); | |
935 | ||
5a2326a7 | 936 | packet.type = SR_DF_LOGIC; |
9c939c51 BV |
937 | packet.payload = &logic; |
938 | logic.length = tosend * sizeof(uint16_t); | |
939 | logic.unitsize = 2; | |
940 | logic.data = samples + sent; | |
3cd3a20b | 941 | sr_session_send(ctx->session_dev_id, &packet); |
28a35d8a | 942 | |
57bbf56b HE |
943 | sent += tosend; |
944 | } | |
945 | n = 0; | |
946 | ||
947 | event = (uint16_t *) &buf[i * 16 + 2]; | |
f78898e9 HE |
948 | cur_sample = 0; |
949 | ||
950 | /* For each event in cluster. */ | |
28a35d8a | 951 | for (j = 0; j < 7; ++j) { |
f78898e9 HE |
952 | |
953 | /* For each sample in event. */ | |
ea9cfed7 | 954 | for (k = 0; k < ctx->samples_per_event; ++k) { |
f78898e9 HE |
955 | cur_sample = 0; |
956 | ||
957 | /* For each probe. */ | |
ea9cfed7 | 958 | for (l = 0; l < ctx->num_probes; ++l) |
edca2c5c | 959 | cur_sample |= (!!(event[j] & (1 << (l * |
ea9cfed7 | 960 | ctx->samples_per_event + k)))) << l; |
f78898e9 HE |
961 | |
962 | samples[n++] = cur_sample; | |
28a35d8a HE |
963 | } |
964 | } | |
965 | ||
eec5275e | 966 | /* Send data up to trigger point (if triggered). */ |
fefa1800 | 967 | sent = 0; |
57bbf56b HE |
968 | if (i == triggerts) { |
969 | /* | |
36b1c8e6 HE |
970 | * Trigger is not always accurate to sample because of |
971 | * pipeline delay. However, it always triggers before | |
972 | * the actual event. We therefore look at the next | |
973 | * samples to pinpoint the exact position of the trigger. | |
57bbf56b | 974 | */ |
bdfc7a89 | 975 | tosend = get_trigger_offset(samples, *lastsample, |
ea9cfed7 | 976 | &ctx->trigger); |
57bbf56b HE |
977 | |
978 | if (tosend > 0) { | |
5a2326a7 | 979 | packet.type = SR_DF_LOGIC; |
9c939c51 BV |
980 | packet.payload = &logic; |
981 | logic.length = tosend * sizeof(uint16_t); | |
982 | logic.unitsize = 2; | |
983 | logic.data = samples; | |
3cd3a20b | 984 | sr_session_send(ctx->session_dev_id, &packet); |
57bbf56b HE |
985 | |
986 | sent += tosend; | |
987 | } | |
28a35d8a | 988 | |
5b5ea7c6 | 989 | /* Only send trigger if explicitly enabled. */ |
ea9cfed7 | 990 | if (ctx->use_triggers) { |
5a2326a7 | 991 | packet.type = SR_DF_TRIGGER; |
3cd3a20b | 992 | sr_session_send(ctx->session_dev_id, &packet); |
5b5ea7c6 | 993 | } |
28a35d8a | 994 | } |
57bbf56b | 995 | |
eec5275e | 996 | /* Send rest of the chunk to sigrok. */ |
57bbf56b HE |
997 | tosend = n - sent; |
998 | ||
abda62ce | 999 | if (tosend > 0) { |
5a2326a7 | 1000 | packet.type = SR_DF_LOGIC; |
9c939c51 BV |
1001 | packet.payload = &logic; |
1002 | logic.length = tosend * sizeof(uint16_t); | |
1003 | logic.unitsize = 2; | |
1004 | logic.data = samples + sent; | |
3cd3a20b | 1005 | sr_session_send(ctx->session_dev_id, &packet); |
abda62ce | 1006 | } |
ee492173 HE |
1007 | |
1008 | *lastsample = samples[n - 1]; | |
28a35d8a HE |
1009 | } |
1010 | ||
e46b8fb1 | 1011 | return SR_OK; |
28a35d8a HE |
1012 | } |
1013 | ||
1f9813eb | 1014 | static int receive_data(int fd, int revents, void *cb_data) |
28a35d8a | 1015 | { |
1f9813eb | 1016 | struct sr_dev_inst *sdi = cb_data; |
ea9cfed7 | 1017 | struct context *ctx = sdi->priv; |
b9c735a2 | 1018 | struct sr_datafeed_packet packet; |
28a35d8a HE |
1019 | const int chunks_per_read = 32; |
1020 | unsigned char buf[chunks_per_read * CHUNK_SIZE]; | |
6aac7737 | 1021 | int bufsz, numchunks, i, newchunks; |
94ba4bd6 | 1022 | uint64_t running_msec; |
28a35d8a | 1023 | struct timeval tv; |
28a35d8a | 1024 | |
cb93f8a9 UH |
1025 | /* Avoid compiler warnings. */ |
1026 | (void)fd; | |
1027 | (void)revents; | |
28a35d8a | 1028 | |
805919b0 HE |
1029 | /* Get the current position. */ |
1030 | sigma_read_pos(&ctx->state.stoppos, &ctx->state.triggerpos, ctx); | |
1031 | ||
ea9cfed7 | 1032 | numchunks = (ctx->state.stoppos + 511) / 512; |
28a35d8a | 1033 | |
ea9cfed7 | 1034 | if (ctx->state.state == SIGMA_IDLE) |
805919b0 | 1035 | return TRUE; |
28a35d8a | 1036 | |
ea9cfed7 | 1037 | if (ctx->state.state == SIGMA_CAPTURE) { |
6aac7737 HE |
1038 | /* Check if the timer has expired, or memory is full. */ |
1039 | gettimeofday(&tv, 0); | |
ea9cfed7 UH |
1040 | running_msec = (tv.tv_sec - ctx->start_tv.tv_sec) * 1000 + |
1041 | (tv.tv_usec - ctx->start_tv.tv_usec) / 1000; | |
28a35d8a | 1042 | |
ea9cfed7 | 1043 | if (running_msec < ctx->limit_msec && numchunks < 32767) |
805919b0 | 1044 | return TRUE; /* While capturing... */ |
e3fff420 HE |
1045 | else |
1046 | hw_dev_acquisition_stop(sdi->index, sdi); | |
6aac7737 | 1047 | |
ea9cfed7 UH |
1048 | } else if (ctx->state.state == SIGMA_DOWNLOAD) { |
1049 | if (ctx->state.chunks_downloaded >= numchunks) { | |
6aac7737 | 1050 | /* End of samples. */ |
5a2326a7 | 1051 | packet.type = SR_DF_END; |
3cd3a20b | 1052 | sr_session_send(ctx->session_dev_id, &packet); |
6aac7737 | 1053 | |
ea9cfed7 | 1054 | ctx->state.state = SIGMA_IDLE; |
f78898e9 | 1055 | |
6aac7737 HE |
1056 | return TRUE; |
1057 | } | |
1058 | ||
1059 | newchunks = MIN(chunks_per_read, | |
ea9cfed7 | 1060 | numchunks - ctx->state.chunks_downloaded); |
28a35d8a | 1061 | |
7b48d6e1 | 1062 | sr_info("sigma: Downloading sample data: %.0f %%", |
ea9cfed7 | 1063 | 100.0 * ctx->state.chunks_downloaded / numchunks); |
28a35d8a | 1064 | |
ea9cfed7 UH |
1065 | bufsz = sigma_read_dram(ctx->state.chunks_downloaded, |
1066 | newchunks, buf, ctx); | |
719c5a93 UH |
1067 | /* TODO: Check bufsz. For now, just avoid compiler warnings. */ |
1068 | (void)bufsz; | |
28a35d8a | 1069 | |
fefa1800 | 1070 | /* Find first ts. */ |
ea9cfed7 UH |
1071 | if (ctx->state.chunks_downloaded == 0) { |
1072 | ctx->state.lastts = *(uint16_t *) buf - 1; | |
1073 | ctx->state.lastsample = 0; | |
6aac7737 | 1074 | } |
28a35d8a | 1075 | |
fefa1800 | 1076 | /* Decode chunks and send them to sigrok. */ |
28a35d8a | 1077 | for (i = 0; i < newchunks; ++i) { |
88c51afe HE |
1078 | int limit_chunk = 0; |
1079 | ||
1080 | /* The last chunk may potentially be only in part. */ | |
ea9cfed7 | 1081 | if (ctx->state.chunks_downloaded == numchunks - 1) { |
88c51afe | 1082 | /* Find the last valid timestamp */ |
ea9cfed7 | 1083 | limit_chunk = ctx->state.stoppos % 512 + ctx->state.lastts; |
88c51afe HE |
1084 | } |
1085 | ||
ea9cfed7 | 1086 | if (ctx->state.chunks_downloaded + i == ctx->state.triggerchunk) |
57bbf56b | 1087 | decode_chunk_ts(buf + (i * CHUNK_SIZE), |
ea9cfed7 UH |
1088 | &ctx->state.lastts, |
1089 | &ctx->state.lastsample, | |
1090 | ctx->state.triggerpos & 0x1ff, | |
1f9813eb | 1091 | limit_chunk, sdi); |
57bbf56b HE |
1092 | else |
1093 | decode_chunk_ts(buf + (i * CHUNK_SIZE), | |
ea9cfed7 UH |
1094 | &ctx->state.lastts, |
1095 | &ctx->state.lastsample, | |
1f9813eb | 1096 | -1, limit_chunk, sdi); |
28a35d8a | 1097 | |
ea9cfed7 | 1098 | ++ctx->state.chunks_downloaded; |
88c51afe | 1099 | } |
28a35d8a HE |
1100 | } |
1101 | ||
28a35d8a HE |
1102 | return TRUE; |
1103 | } | |
1104 | ||
c53d793f HE |
1105 | /* Build a LUT entry used by the trigger functions. */ |
1106 | static void build_lut_entry(uint16_t value, uint16_t mask, uint16_t *entry) | |
ee492173 HE |
1107 | { |
1108 | int i, j, k, bit; | |
1109 | ||
f758d074 | 1110 | /* For each quad probe. */ |
ee492173 | 1111 | for (i = 0; i < 4; ++i) { |
c53d793f | 1112 | entry[i] = 0xffff; |
ee492173 | 1113 | |
f758d074 | 1114 | /* For each bit in LUT. */ |
ee492173 HE |
1115 | for (j = 0; j < 16; ++j) |
1116 | ||
f758d074 | 1117 | /* For each probe in quad. */ |
ee492173 HE |
1118 | for (k = 0; k < 4; ++k) { |
1119 | bit = 1 << (i * 4 + k); | |
1120 | ||
c53d793f HE |
1121 | /* Set bit in entry */ |
1122 | if ((mask & bit) && | |
1123 | ((!(value & bit)) != | |
4ae1f451 | 1124 | (!(j & (1 << k))))) |
c53d793f | 1125 | entry[i] &= ~(1 << j); |
ee492173 HE |
1126 | } |
1127 | } | |
c53d793f | 1128 | } |
ee492173 | 1129 | |
c53d793f HE |
1130 | /* Add a logical function to LUT mask. */ |
1131 | static void add_trigger_function(enum triggerop oper, enum triggerfunc func, | |
1132 | int index, int neg, uint16_t *mask) | |
1133 | { | |
1134 | int i, j; | |
1135 | int x[2][2], tmp, a, b, aset, bset, rset; | |
1136 | ||
1137 | memset(x, 0, 4 * sizeof(int)); | |
1138 | ||
1139 | /* Trigger detect condition. */ | |
1140 | switch (oper) { | |
1141 | case OP_LEVEL: | |
1142 | x[0][1] = 1; | |
1143 | x[1][1] = 1; | |
1144 | break; | |
1145 | case OP_NOT: | |
1146 | x[0][0] = 1; | |
1147 | x[1][0] = 1; | |
1148 | break; | |
1149 | case OP_RISE: | |
1150 | x[0][1] = 1; | |
1151 | break; | |
1152 | case OP_FALL: | |
1153 | x[1][0] = 1; | |
1154 | break; | |
1155 | case OP_RISEFALL: | |
1156 | x[0][1] = 1; | |
1157 | x[1][0] = 1; | |
1158 | break; | |
1159 | case OP_NOTRISE: | |
1160 | x[1][1] = 1; | |
1161 | x[0][0] = 1; | |
1162 | x[1][0] = 1; | |
1163 | break; | |
1164 | case OP_NOTFALL: | |
1165 | x[1][1] = 1; | |
1166 | x[0][0] = 1; | |
1167 | x[0][1] = 1; | |
1168 | break; | |
1169 | case OP_NOTRISEFALL: | |
1170 | x[1][1] = 1; | |
1171 | x[0][0] = 1; | |
1172 | break; | |
1173 | } | |
1174 | ||
1175 | /* Transpose if neg is set. */ | |
1176 | if (neg) { | |
ea9cfed7 | 1177 | for (i = 0; i < 2; ++i) { |
c53d793f HE |
1178 | for (j = 0; j < 2; ++j) { |
1179 | tmp = x[i][j]; | |
1180 | x[i][j] = x[1-i][1-j]; | |
1181 | x[1-i][1-j] = tmp; | |
1182 | } | |
ea9cfed7 | 1183 | } |
c53d793f HE |
1184 | } |
1185 | ||
1186 | /* Update mask with function. */ | |
1187 | for (i = 0; i < 16; ++i) { | |
1188 | a = (i >> (2 * index + 0)) & 1; | |
1189 | b = (i >> (2 * index + 1)) & 1; | |
1190 | ||
1191 | aset = (*mask >> i) & 1; | |
1192 | bset = x[b][a]; | |
1193 | ||
1194 | if (func == FUNC_AND || func == FUNC_NAND) | |
1195 | rset = aset & bset; | |
1196 | else if (func == FUNC_OR || func == FUNC_NOR) | |
1197 | rset = aset | bset; | |
1198 | else if (func == FUNC_XOR || func == FUNC_NXOR) | |
1199 | rset = aset ^ bset; | |
1200 | ||
1201 | if (func == FUNC_NAND || func == FUNC_NOR || func == FUNC_NXOR) | |
1202 | rset = !rset; | |
1203 | ||
1204 | *mask &= ~(1 << i); | |
1205 | ||
1206 | if (rset) | |
1207 | *mask |= 1 << i; | |
1208 | } | |
1209 | } | |
1210 | ||
1211 | /* | |
1212 | * Build trigger LUTs used by 50 MHz and lower sample rates for supporting | |
1213 | * simple pin change and state triggers. Only two transitions (rise/fall) can be | |
1214 | * set at any time, but a full mask and value can be set (0/1). | |
1215 | */ | |
ea9cfed7 | 1216 | static int build_basic_trigger(struct triggerlut *lut, struct context *ctx) |
c53d793f HE |
1217 | { |
1218 | int i,j; | |
4ae1f451 | 1219 | uint16_t masks[2] = { 0, 0 }; |
c53d793f HE |
1220 | |
1221 | memset(lut, 0, sizeof(struct triggerlut)); | |
1222 | ||
1223 | /* Contant for simple triggers. */ | |
1224 | lut->m4 = 0xa000; | |
1225 | ||
1226 | /* Value/mask trigger support. */ | |
ea9cfed7 | 1227 | build_lut_entry(ctx->trigger.simplevalue, ctx->trigger.simplemask, |
99965709 | 1228 | lut->m2d); |
c53d793f HE |
1229 | |
1230 | /* Rise/fall trigger support. */ | |
1231 | for (i = 0, j = 0; i < 16; ++i) { | |
ea9cfed7 UH |
1232 | if (ctx->trigger.risingmask & (1 << i) || |
1233 | ctx->trigger.fallingmask & (1 << i)) | |
c53d793f HE |
1234 | masks[j++] = 1 << i; |
1235 | } | |
1236 | ||
1237 | build_lut_entry(masks[0], masks[0], lut->m0d); | |
1238 | build_lut_entry(masks[1], masks[1], lut->m1d); | |
1239 | ||
1240 | /* Add glue logic */ | |
1241 | if (masks[0] || masks[1]) { | |
1242 | /* Transition trigger. */ | |
ea9cfed7 | 1243 | if (masks[0] & ctx->trigger.risingmask) |
c53d793f | 1244 | add_trigger_function(OP_RISE, FUNC_OR, 0, 0, &lut->m3); |
ea9cfed7 | 1245 | if (masks[0] & ctx->trigger.fallingmask) |
c53d793f | 1246 | add_trigger_function(OP_FALL, FUNC_OR, 0, 0, &lut->m3); |
ea9cfed7 | 1247 | if (masks[1] & ctx->trigger.risingmask) |
c53d793f | 1248 | add_trigger_function(OP_RISE, FUNC_OR, 1, 0, &lut->m3); |
ea9cfed7 | 1249 | if (masks[1] & ctx->trigger.fallingmask) |
c53d793f HE |
1250 | add_trigger_function(OP_FALL, FUNC_OR, 1, 0, &lut->m3); |
1251 | } else { | |
1252 | /* Only value/mask trigger. */ | |
1253 | lut->m3 = 0xffff; | |
1254 | } | |
ee492173 | 1255 | |
c53d793f | 1256 | /* Triggertype: event. */ |
ee492173 HE |
1257 | lut->params.selres = 3; |
1258 | ||
e46b8fb1 | 1259 | return SR_OK; |
ee492173 HE |
1260 | } |
1261 | ||
3cd3a20b | 1262 | static int hw_dev_acquisition_start(int dev_index, void *cb_data) |
28a35d8a | 1263 | { |
d68e2d1a | 1264 | struct sr_dev_inst *sdi; |
ea9cfed7 | 1265 | struct context *ctx; |
3c36c403 HE |
1266 | struct sr_datafeed_packet *packet; |
1267 | struct sr_datafeed_header *header; | |
f366e86c | 1268 | struct sr_datafeed_meta_logic meta; |
9ddb2a12 | 1269 | struct clockselect_50 clockselect; |
82957b65 | 1270 | int frac, triggerpin, ret; |
57bbf56b HE |
1271 | uint8_t triggerselect; |
1272 | struct triggerinout triggerinout_conf; | |
ee492173 | 1273 | struct triggerlut lut; |
28a35d8a | 1274 | |
bb7ef793 | 1275 | if (!(sdi = sr_dev_inst_get(dev_insts, dev_index))) |
e46b8fb1 | 1276 | return SR_ERR; |
28a35d8a | 1277 | |
ea9cfed7 | 1278 | ctx = sdi->priv; |
28a35d8a | 1279 | |
ea9cfed7 UH |
1280 | /* If the samplerate has not been set, default to 200 kHz. */ |
1281 | if (ctx->cur_firmware == -1) { | |
82957b65 UH |
1282 | if ((ret = set_samplerate(sdi, SR_KHZ(200))) != SR_OK) |
1283 | return ret; | |
1284 | } | |
e8397563 | 1285 | |
eec5275e | 1286 | /* Enter trigger programming mode. */ |
ea9cfed7 | 1287 | sigma_set_register(WRITE_TRIGGER_SELECT1, 0x20, ctx); |
28a35d8a | 1288 | |
eec5275e | 1289 | /* 100 and 200 MHz mode. */ |
ea9cfed7 UH |
1290 | if (ctx->cur_samplerate >= SR_MHZ(100)) { |
1291 | sigma_set_register(WRITE_TRIGGER_SELECT1, 0x81, ctx); | |
57bbf56b | 1292 | |
a42aec7f HE |
1293 | /* Find which pin to trigger on from mask. */ |
1294 | for (triggerpin = 0; triggerpin < 8; ++triggerpin) | |
ea9cfed7 | 1295 | if ((ctx->trigger.risingmask | ctx->trigger.fallingmask) & |
a42aec7f HE |
1296 | (1 << triggerpin)) |
1297 | break; | |
1298 | ||
1299 | /* Set trigger pin and light LED on trigger. */ | |
1300 | triggerselect = (1 << LEDSEL1) | (triggerpin & 0x7); | |
1301 | ||
1302 | /* Default rising edge. */ | |
ea9cfed7 | 1303 | if (ctx->trigger.fallingmask) |
a42aec7f | 1304 | triggerselect |= 1 << 3; |
57bbf56b | 1305 | |
eec5275e | 1306 | /* All other modes. */ |
ea9cfed7 UH |
1307 | } else if (ctx->cur_samplerate <= SR_MHZ(50)) { |
1308 | build_basic_trigger(&lut, ctx); | |
ee492173 | 1309 | |
ea9cfed7 | 1310 | sigma_write_trigger_lut(&lut, ctx); |
57bbf56b HE |
1311 | |
1312 | triggerselect = (1 << LEDSEL1) | (1 << LEDSEL0); | |
1313 | } | |
1314 | ||
eec5275e | 1315 | /* Setup trigger in and out pins to default values. */ |
57bbf56b HE |
1316 | memset(&triggerinout_conf, 0, sizeof(struct triggerinout)); |
1317 | triggerinout_conf.trgout_bytrigger = 1; | |
1318 | triggerinout_conf.trgout_enable = 1; | |
1319 | ||
28a35d8a | 1320 | sigma_write_register(WRITE_TRIGGER_OPTION, |
57bbf56b | 1321 | (uint8_t *) &triggerinout_conf, |
ea9cfed7 | 1322 | sizeof(struct triggerinout), ctx); |
28a35d8a | 1323 | |
eec5275e | 1324 | /* Go back to normal mode. */ |
ea9cfed7 | 1325 | sigma_set_register(WRITE_TRIGGER_SELECT1, triggerselect, ctx); |
28a35d8a | 1326 | |
edca2c5c | 1327 | /* Set clock select register. */ |
ea9cfed7 | 1328 | if (ctx->cur_samplerate == SR_MHZ(200)) |
edca2c5c | 1329 | /* Enable 4 probes. */ |
ea9cfed7 UH |
1330 | sigma_set_register(WRITE_CLOCK_SELECT, 0xf0, ctx); |
1331 | else if (ctx->cur_samplerate == SR_MHZ(100)) | |
edca2c5c | 1332 | /* Enable 8 probes. */ |
ea9cfed7 | 1333 | sigma_set_register(WRITE_CLOCK_SELECT, 0x00, ctx); |
edca2c5c HE |
1334 | else { |
1335 | /* | |
9ddb2a12 | 1336 | * 50 MHz mode (or fraction thereof). Any fraction down to |
eec5275e | 1337 | * 50 MHz / 256 can be used, but is not supported by sigrok API. |
edca2c5c | 1338 | */ |
ea9cfed7 | 1339 | frac = SR_MHZ(50) / ctx->cur_samplerate - 1; |
edca2c5c | 1340 | |
9ddb2a12 UH |
1341 | clockselect.async = 0; |
1342 | clockselect.fraction = frac; | |
1343 | clockselect.disabled_probes = 0; | |
edca2c5c HE |
1344 | |
1345 | sigma_write_register(WRITE_CLOCK_SELECT, | |
9ddb2a12 | 1346 | (uint8_t *) &clockselect, |
ea9cfed7 | 1347 | sizeof(clockselect), ctx); |
edca2c5c HE |
1348 | } |
1349 | ||
fefa1800 | 1350 | /* Setup maximum post trigger time. */ |
99965709 | 1351 | sigma_set_register(WRITE_POST_TRIGGER, |
6352d030 | 1352 | (ctx->capture_ratio * 255) / 100, ctx); |
28a35d8a | 1353 | |
eec5275e | 1354 | /* Start acqusition. */ |
ea9cfed7 UH |
1355 | gettimeofday(&ctx->start_tv, 0); |
1356 | sigma_set_register(WRITE_MODE, 0x0d, ctx); | |
99965709 | 1357 | |
3cd3a20b | 1358 | ctx->session_dev_id = cb_data; |
28a35d8a | 1359 | |
3c36c403 HE |
1360 | if (!(packet = g_try_malloc(sizeof(struct sr_datafeed_packet)))) { |
1361 | sr_err("sigma: %s: packet malloc failed.", __func__); | |
1362 | return SR_ERR_MALLOC; | |
1363 | } | |
1364 | ||
1365 | if (!(header = g_try_malloc(sizeof(struct sr_datafeed_header)))) { | |
1366 | sr_err("sigma: %s: header malloc failed.", __func__); | |
1367 | return SR_ERR_MALLOC; | |
1368 | } | |
28a35d8a | 1369 | |
3c36c403 HE |
1370 | /* Send header packet to the session bus. */ |
1371 | packet->type = SR_DF_HEADER; | |
1372 | packet->payload = header; | |
1373 | header->feed_version = 1; | |
1374 | gettimeofday(&header->starttime, NULL); | |
3c36c403 | 1375 | sr_session_send(ctx->session_dev_id, packet); |
f366e86c BV |
1376 | |
1377 | /* Send metadata about the SR_DF_LOGIC packets to come. */ | |
1378 | packet->type = SR_DF_META_LOGIC; | |
1379 | packet->payload = &meta; | |
1380 | meta.samplerate = ctx->cur_samplerate; | |
1381 | meta.num_probes = ctx->num_probes; | |
1382 | sr_session_send(ctx->session_dev_id, packet); | |
1383 | ||
1384 | /* Add capture source. */ | |
1385 | sr_source_add(0, G_IO_IN, 10, receive_data, sdi); | |
1386 | ||
3c36c403 HE |
1387 | g_free(header); |
1388 | g_free(packet); | |
1389 | ||
ea9cfed7 | 1390 | ctx->state.state = SIGMA_CAPTURE; |
6aac7737 | 1391 | |
e46b8fb1 | 1392 | return SR_OK; |
28a35d8a HE |
1393 | } |
1394 | ||
3cd3a20b | 1395 | static int hw_dev_acquisition_stop(int dev_index, void *cb_data) |
28a35d8a | 1396 | { |
d68e2d1a | 1397 | struct sr_dev_inst *sdi; |
ea9cfed7 | 1398 | struct context *ctx; |
6aac7737 HE |
1399 | uint8_t modestatus; |
1400 | ||
cb93f8a9 | 1401 | /* Avoid compiler warnings. */ |
3cd3a20b | 1402 | (void)cb_data; |
28a35d8a | 1403 | |
bb7ef793 | 1404 | if (!(sdi = sr_dev_inst_get(dev_insts, dev_index))) { |
7b48d6e1 | 1405 | sr_err("sigma: %s: sdi was NULL", __func__); |
3010f21c UH |
1406 | return SR_ERR_BUG; |
1407 | } | |
1408 | ||
ea9cfed7 | 1409 | if (!(ctx = sdi->priv)) { |
7b48d6e1 | 1410 | sr_err("sigma: %s: sdi->priv was NULL", __func__); |
3010f21c UH |
1411 | return SR_ERR_BUG; |
1412 | } | |
1413 | ||
fefa1800 | 1414 | /* Stop acquisition. */ |
ea9cfed7 | 1415 | sigma_set_register(WRITE_MODE, 0x11, ctx); |
28a35d8a | 1416 | |
6aac7737 | 1417 | /* Set SDRAM Read Enable. */ |
ea9cfed7 | 1418 | sigma_set_register(WRITE_MODE, 0x02, ctx); |
6aac7737 HE |
1419 | |
1420 | /* Get the current position. */ | |
ea9cfed7 | 1421 | sigma_read_pos(&ctx->state.stoppos, &ctx->state.triggerpos, ctx); |
6aac7737 HE |
1422 | |
1423 | /* Check if trigger has fired. */ | |
ea9cfed7 | 1424 | modestatus = sigma_get_register(READ_MODE, ctx); |
3010f21c | 1425 | if (modestatus & 0x20) |
ea9cfed7 | 1426 | ctx->state.triggerchunk = ctx->state.triggerpos / 512; |
3010f21c | 1427 | else |
ea9cfed7 | 1428 | ctx->state.triggerchunk = -1; |
6aac7737 | 1429 | |
ea9cfed7 | 1430 | ctx->state.chunks_downloaded = 0; |
6aac7737 | 1431 | |
ea9cfed7 | 1432 | ctx->state.state = SIGMA_DOWNLOAD; |
3010f21c UH |
1433 | |
1434 | return SR_OK; | |
28a35d8a HE |
1435 | } |
1436 | ||
c09f0b57 | 1437 | SR_PRIV struct sr_dev_driver asix_sigma_driver_info = { |
e519ba86 | 1438 | .name = "asix-sigma", |
6352d030 | 1439 | .longname = "ASIX SIGMA/SIGMA2", |
e519ba86 UH |
1440 | .api_version = 1, |
1441 | .init = hw_init, | |
1442 | .cleanup = hw_cleanup, | |
e7eb703f UH |
1443 | .dev_open = hw_dev_open, |
1444 | .dev_close = hw_dev_close, | |
5097b0d0 | 1445 | .dev_info_get = hw_dev_info_get, |
e7eb703f | 1446 | .dev_status_get = hw_dev_status_get, |
ffedd0bf | 1447 | .hwcap_get_all = hw_hwcap_get_all, |
a9a245b4 | 1448 | .dev_config_set = hw_dev_config_set, |
6b3dfec8 UH |
1449 | .dev_acquisition_start = hw_dev_acquisition_start, |
1450 | .dev_acquisition_stop = hw_dev_acquisition_stop, | |
28a35d8a | 1451 | }; |