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Commit | Line | Data |
---|---|---|
28a35d8a | 1 | /* |
50985c20 | 2 | * This file is part of the libsigrok project. |
28a35d8a | 3 | * |
868501fa | 4 | * Copyright (C) 2010-2012 Håvard Espeland <gus@ping.uio.no>, |
911f1834 UH |
5 | * Copyright (C) 2010 Martin Stensgård <mastensg@ping.uio.no> |
6 | * Copyright (C) 2010 Carl Henrik Lunde <chlunde@ping.uio.no> | |
28a35d8a HE |
7 | * |
8 | * This program is free software: you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation, either version 3 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
20 | */ | |
21 | ||
911f1834 | 22 | /* |
6352d030 | 23 | * ASIX SIGMA/SIGMA2 logic analyzer driver |
911f1834 UH |
24 | */ |
25 | ||
3bbd9849 UH |
26 | #include <glib.h> |
27 | #include <glib/gstdio.h> | |
28a35d8a HE |
28 | #include <ftdi.h> |
29 | #include <string.h> | |
45c59c8b BV |
30 | #include "libsigrok.h" |
31 | #include "libsigrok-internal.h" | |
28a35d8a HE |
32 | #include "asix-sigma.h" |
33 | ||
34 | #define USB_VENDOR 0xa600 | |
35 | #define USB_PRODUCT 0xa000 | |
36 | #define USB_DESCRIPTION "ASIX SIGMA" | |
37 | #define USB_VENDOR_NAME "ASIX" | |
38 | #define USB_MODEL_NAME "SIGMA" | |
c50277a6 | 39 | #define TRIGGER_TYPE "rf10" |
28a35d8a | 40 | |
ed300b9f | 41 | SR_PRIV struct sr_dev_driver asix_sigma_driver_info; |
a873c594 | 42 | static struct sr_dev_driver *di = &asix_sigma_driver_info; |
6078d2c9 | 43 | static int dev_acquisition_stop(struct sr_dev_inst *sdi, void *cb_data); |
28a35d8a | 44 | |
b1648dea MV |
45 | /* |
46 | * The ASIX Sigma supports arbitrary integer frequency divider in | |
47 | * the 50MHz mode. The divider is in range 1...256 , allowing for | |
48 | * very precise sampling rate selection. This driver supports only | |
49 | * a subset of the sampling rates. | |
50 | */ | |
2c9c0df8 | 51 | static const uint64_t samplerates[] = { |
b1648dea MV |
52 | SR_KHZ(200), /* div=250 */ |
53 | SR_KHZ(250), /* div=200 */ | |
54 | SR_KHZ(500), /* div=100 */ | |
55 | SR_MHZ(1), /* div=50 */ | |
56 | SR_MHZ(5), /* div=10 */ | |
57 | SR_MHZ(10), /* div=5 */ | |
58 | SR_MHZ(25), /* div=2 */ | |
59 | SR_MHZ(50), /* div=1 */ | |
60 | SR_MHZ(100), /* Special FW needed */ | |
61 | SR_MHZ(200), /* Special FW needed */ | |
28a35d8a HE |
62 | }; |
63 | ||
d261dbbf | 64 | /* |
ba7dd8bb | 65 | * Channel numbers seem to go from 1-16, according to this image: |
d261dbbf UH |
66 | * http://tools.asix.net/img/sigma_sigmacab_pins_720.jpg |
67 | * (the cable has two additional GND pins, and a TI and TO pin) | |
68 | */ | |
790c7ccc | 69 | static const char *channel_names[] = { |
78693401 UH |
70 | "1", "2", "3", "4", "5", "6", "7", "8", |
71 | "9", "10", "11", "12", "13", "14", "15", "16", | |
464d12c7 KS |
72 | }; |
73 | ||
2c9c0df8 | 74 | static const int32_t hwcaps[] = { |
1953564a BV |
75 | SR_CONF_LOGIC_ANALYZER, |
76 | SR_CONF_SAMPLERATE, | |
38d32464 | 77 | SR_CONF_TRIGGER_TYPE, |
1953564a | 78 | SR_CONF_CAPTURE_RATIO, |
1953564a | 79 | SR_CONF_LIMIT_MSEC, |
6868626b | 80 | SR_CONF_LIMIT_SAMPLES, |
28a35d8a HE |
81 | }; |
82 | ||
fefa1800 UH |
83 | /* Initialize the logic analyzer mode. */ |
84 | static uint8_t logic_mode_start[] = { | |
85 | 0x00, 0x40, 0x0f, 0x25, 0x35, 0x40, | |
86 | 0x2a, 0x3a, 0x40, 0x03, 0x20, 0x38, | |
87 | }; | |
88 | ||
499b17e9 MV |
89 | static const char *sigma_firmware_files[] = { |
90 | /* 50 MHz, supports 8 bit fractions */ | |
91 | FIRMWARE_DIR "/asix-sigma-50.fw", | |
92 | /* 100 MHz */ | |
93 | FIRMWARE_DIR "/asix-sigma-100.fw", | |
94 | /* 200 MHz */ | |
95 | FIRMWARE_DIR "/asix-sigma-200.fw", | |
96 | /* Synchronous clock from pin */ | |
97 | FIRMWARE_DIR "/asix-sigma-50sync.fw", | |
98 | /* Frequency counter */ | |
99 | FIRMWARE_DIR "/asix-sigma-phasor.fw", | |
f6564c8d HE |
100 | }; |
101 | ||
0e1357e8 | 102 | static int sigma_read(void *buf, size_t size, struct dev_context *devc) |
28a35d8a HE |
103 | { |
104 | int ret; | |
fefa1800 | 105 | |
0e1357e8 | 106 | ret = ftdi_read_data(&devc->ftdic, (unsigned char *)buf, size); |
28a35d8a | 107 | if (ret < 0) { |
47f4f073 | 108 | sr_err("ftdi_read_data failed: %s", |
0e1357e8 | 109 | ftdi_get_error_string(&devc->ftdic)); |
28a35d8a HE |
110 | } |
111 | ||
112 | return ret; | |
113 | } | |
114 | ||
0e1357e8 | 115 | static int sigma_write(void *buf, size_t size, struct dev_context *devc) |
28a35d8a HE |
116 | { |
117 | int ret; | |
fefa1800 | 118 | |
0e1357e8 | 119 | ret = ftdi_write_data(&devc->ftdic, (unsigned char *)buf, size); |
28a35d8a | 120 | if (ret < 0) { |
47f4f073 | 121 | sr_err("ftdi_write_data failed: %s", |
0e1357e8 | 122 | ftdi_get_error_string(&devc->ftdic)); |
fefa1800 | 123 | } else if ((size_t) ret != size) { |
47f4f073 | 124 | sr_err("ftdi_write_data did not complete write."); |
28a35d8a HE |
125 | } |
126 | ||
127 | return ret; | |
128 | } | |
129 | ||
99965709 | 130 | static int sigma_write_register(uint8_t reg, uint8_t *data, size_t len, |
0e1357e8 | 131 | struct dev_context *devc) |
28a35d8a HE |
132 | { |
133 | size_t i; | |
134 | uint8_t buf[len + 2]; | |
135 | int idx = 0; | |
136 | ||
137 | buf[idx++] = REG_ADDR_LOW | (reg & 0xf); | |
138 | buf[idx++] = REG_ADDR_HIGH | (reg >> 4); | |
139 | ||
fefa1800 | 140 | for (i = 0; i < len; ++i) { |
28a35d8a HE |
141 | buf[idx++] = REG_DATA_LOW | (data[i] & 0xf); |
142 | buf[idx++] = REG_DATA_HIGH_WRITE | (data[i] >> 4); | |
143 | } | |
144 | ||
0e1357e8 | 145 | return sigma_write(buf, idx, devc); |
28a35d8a HE |
146 | } |
147 | ||
0e1357e8 | 148 | static int sigma_set_register(uint8_t reg, uint8_t value, struct dev_context *devc) |
28a35d8a | 149 | { |
0e1357e8 | 150 | return sigma_write_register(reg, &value, 1, devc); |
28a35d8a HE |
151 | } |
152 | ||
99965709 | 153 | static int sigma_read_register(uint8_t reg, uint8_t *data, size_t len, |
0e1357e8 | 154 | struct dev_context *devc) |
28a35d8a HE |
155 | { |
156 | uint8_t buf[3]; | |
fefa1800 | 157 | |
28a35d8a HE |
158 | buf[0] = REG_ADDR_LOW | (reg & 0xf); |
159 | buf[1] = REG_ADDR_HIGH | (reg >> 4); | |
28a35d8a HE |
160 | buf[2] = REG_READ_ADDR; |
161 | ||
0e1357e8 | 162 | sigma_write(buf, sizeof(buf), devc); |
28a35d8a | 163 | |
0e1357e8 | 164 | return sigma_read(data, len, devc); |
28a35d8a HE |
165 | } |
166 | ||
0e1357e8 | 167 | static uint8_t sigma_get_register(uint8_t reg, struct dev_context *devc) |
28a35d8a HE |
168 | { |
169 | uint8_t value; | |
fefa1800 | 170 | |
0e1357e8 | 171 | if (1 != sigma_read_register(reg, &value, 1, devc)) { |
47f4f073 | 172 | sr_err("sigma_get_register: 1 byte expected"); |
28a35d8a HE |
173 | return 0; |
174 | } | |
175 | ||
176 | return value; | |
177 | } | |
178 | ||
99965709 | 179 | static int sigma_read_pos(uint32_t *stoppos, uint32_t *triggerpos, |
0e1357e8 | 180 | struct dev_context *devc) |
28a35d8a HE |
181 | { |
182 | uint8_t buf[] = { | |
183 | REG_ADDR_LOW | READ_TRIGGER_POS_LOW, | |
184 | ||
185 | REG_READ_ADDR | NEXT_REG, | |
186 | REG_READ_ADDR | NEXT_REG, | |
187 | REG_READ_ADDR | NEXT_REG, | |
188 | REG_READ_ADDR | NEXT_REG, | |
189 | REG_READ_ADDR | NEXT_REG, | |
190 | REG_READ_ADDR | NEXT_REG, | |
191 | }; | |
28a35d8a HE |
192 | uint8_t result[6]; |
193 | ||
0e1357e8 | 194 | sigma_write(buf, sizeof(buf), devc); |
28a35d8a | 195 | |
0e1357e8 | 196 | sigma_read(result, sizeof(result), devc); |
28a35d8a HE |
197 | |
198 | *triggerpos = result[0] | (result[1] << 8) | (result[2] << 16); | |
199 | *stoppos = result[3] | (result[4] << 8) | (result[5] << 16); | |
200 | ||
57bbf56b HE |
201 | /* Not really sure why this must be done, but according to spec. */ |
202 | if ((--*stoppos & 0x1ff) == 0x1ff) | |
203 | stoppos -= 64; | |
204 | ||
205 | if ((*--triggerpos & 0x1ff) == 0x1ff) | |
206 | triggerpos -= 64; | |
207 | ||
28a35d8a HE |
208 | return 1; |
209 | } | |
210 | ||
99965709 | 211 | static int sigma_read_dram(uint16_t startchunk, size_t numchunks, |
0e1357e8 | 212 | uint8_t *data, struct dev_context *devc) |
28a35d8a HE |
213 | { |
214 | size_t i; | |
215 | uint8_t buf[4096]; | |
216 | int idx = 0; | |
217 | ||
fefa1800 | 218 | /* Send the startchunk. Index start with 1. */ |
28a35d8a HE |
219 | buf[0] = startchunk >> 8; |
220 | buf[1] = startchunk & 0xff; | |
0e1357e8 | 221 | sigma_write_register(WRITE_MEMROW, buf, 2, devc); |
28a35d8a | 222 | |
fefa1800 | 223 | /* Read the DRAM. */ |
28a35d8a HE |
224 | buf[idx++] = REG_DRAM_BLOCK; |
225 | buf[idx++] = REG_DRAM_WAIT_ACK; | |
226 | ||
227 | for (i = 0; i < numchunks; ++i) { | |
fefa1800 UH |
228 | /* Alternate bit to copy from DRAM to cache. */ |
229 | if (i != (numchunks - 1)) | |
230 | buf[idx++] = REG_DRAM_BLOCK | (((i + 1) % 2) << 4); | |
28a35d8a HE |
231 | |
232 | buf[idx++] = REG_DRAM_BLOCK_DATA | ((i % 2) << 4); | |
233 | ||
fefa1800 | 234 | if (i != (numchunks - 1)) |
28a35d8a HE |
235 | buf[idx++] = REG_DRAM_WAIT_ACK; |
236 | } | |
237 | ||
0e1357e8 | 238 | sigma_write(buf, idx, devc); |
28a35d8a | 239 | |
0e1357e8 | 240 | return sigma_read(data, numchunks * CHUNK_SIZE, devc); |
28a35d8a HE |
241 | } |
242 | ||
4ae1f451 | 243 | /* Upload trigger look-up tables to Sigma. */ |
0e1357e8 | 244 | static int sigma_write_trigger_lut(struct triggerlut *lut, struct dev_context *devc) |
ee492173 HE |
245 | { |
246 | int i; | |
247 | uint8_t tmp[2]; | |
248 | uint16_t bit; | |
249 | ||
250 | /* Transpose the table and send to Sigma. */ | |
251 | for (i = 0; i < 16; ++i) { | |
252 | bit = 1 << i; | |
253 | ||
254 | tmp[0] = tmp[1] = 0; | |
255 | ||
256 | if (lut->m2d[0] & bit) | |
257 | tmp[0] |= 0x01; | |
258 | if (lut->m2d[1] & bit) | |
259 | tmp[0] |= 0x02; | |
260 | if (lut->m2d[2] & bit) | |
261 | tmp[0] |= 0x04; | |
262 | if (lut->m2d[3] & bit) | |
263 | tmp[0] |= 0x08; | |
264 | ||
265 | if (lut->m3 & bit) | |
266 | tmp[0] |= 0x10; | |
267 | if (lut->m3s & bit) | |
268 | tmp[0] |= 0x20; | |
269 | if (lut->m4 & bit) | |
270 | tmp[0] |= 0x40; | |
271 | ||
272 | if (lut->m0d[0] & bit) | |
273 | tmp[1] |= 0x01; | |
274 | if (lut->m0d[1] & bit) | |
275 | tmp[1] |= 0x02; | |
276 | if (lut->m0d[2] & bit) | |
277 | tmp[1] |= 0x04; | |
278 | if (lut->m0d[3] & bit) | |
279 | tmp[1] |= 0x08; | |
280 | ||
281 | if (lut->m1d[0] & bit) | |
282 | tmp[1] |= 0x10; | |
283 | if (lut->m1d[1] & bit) | |
284 | tmp[1] |= 0x20; | |
285 | if (lut->m1d[2] & bit) | |
286 | tmp[1] |= 0x40; | |
287 | if (lut->m1d[3] & bit) | |
288 | tmp[1] |= 0x80; | |
289 | ||
99965709 | 290 | sigma_write_register(WRITE_TRIGGER_SELECT0, tmp, sizeof(tmp), |
0e1357e8 BV |
291 | devc); |
292 | sigma_set_register(WRITE_TRIGGER_SELECT1, 0x30 | i, devc); | |
ee492173 HE |
293 | } |
294 | ||
295 | /* Send the parameters */ | |
296 | sigma_write_register(WRITE_TRIGGER_SELECT0, (uint8_t *) &lut->params, | |
0e1357e8 | 297 | sizeof(lut->params), devc); |
ee492173 | 298 | |
e46b8fb1 | 299 | return SR_OK; |
ee492173 HE |
300 | } |
301 | ||
fefa1800 | 302 | /* Generate the bitbang stream for programming the FPGA. */ |
28a35d8a | 303 | static int bin2bitbang(const char *filename, |
fefa1800 | 304 | unsigned char **buf, size_t *buf_size) |
28a35d8a | 305 | { |
fefa1800 | 306 | FILE *f; |
e3fff420 | 307 | unsigned long file_size; |
28a35d8a HE |
308 | unsigned long offset = 0; |
309 | unsigned char *p; | |
e3fff420 HE |
310 | uint8_t *firmware; |
311 | unsigned long fwsize = 0; | |
28a35d8a HE |
312 | const int buffer_size = 65536; |
313 | size_t i; | |
e3fff420 | 314 | int c, bit, v; |
fefa1800 | 315 | uint32_t imm = 0x3f6df2ab; |
28a35d8a | 316 | |
868d8cef | 317 | f = g_fopen(filename, "rb"); |
28a35d8a | 318 | if (!f) { |
47f4f073 | 319 | sr_err("g_fopen(\"%s\", \"rb\")", filename); |
b53738ba | 320 | return SR_ERR; |
28a35d8a HE |
321 | } |
322 | ||
323 | if (-1 == fseek(f, 0, SEEK_END)) { | |
47f4f073 | 324 | sr_err("fseek on %s failed", filename); |
28a35d8a | 325 | fclose(f); |
b53738ba | 326 | return SR_ERR; |
28a35d8a HE |
327 | } |
328 | ||
329 | file_size = ftell(f); | |
330 | ||
331 | fseek(f, 0, SEEK_SET); | |
332 | ||
b53738ba | 333 | if (!(firmware = g_try_malloc(buffer_size))) { |
47f4f073 | 334 | sr_err("%s: firmware malloc failed", __func__); |
12ad53f5 | 335 | fclose(f); |
b53738ba | 336 | return SR_ERR_MALLOC; |
28a35d8a HE |
337 | } |
338 | ||
28a35d8a HE |
339 | while ((c = getc(f)) != EOF) { |
340 | imm = (imm + 0xa853753) % 177 + (imm * 0x8034052); | |
e3fff420 | 341 | firmware[fwsize++] = c ^ imm; |
28a35d8a HE |
342 | } |
343 | fclose(f); | |
344 | ||
e3fff420 | 345 | if(fwsize != file_size) { |
47f4f073 | 346 | sr_err("%s: Error reading firmware", filename); |
e3fff420 HE |
347 | fclose(f); |
348 | g_free(firmware); | |
349 | return SR_ERR; | |
28a35d8a HE |
350 | } |
351 | ||
28a35d8a HE |
352 | *buf_size = fwsize * 2 * 8; |
353 | ||
b53738ba | 354 | *buf = p = (unsigned char *)g_try_malloc(*buf_size); |
28a35d8a | 355 | if (!p) { |
47f4f073 | 356 | sr_err("%s: buf/p malloc failed", __func__); |
12ad53f5 | 357 | g_free(firmware); |
b53738ba | 358 | return SR_ERR_MALLOC; |
28a35d8a HE |
359 | } |
360 | ||
361 | for (i = 0; i < fwsize; ++i) { | |
28a35d8a | 362 | for (bit = 7; bit >= 0; --bit) { |
fefa1800 | 363 | v = firmware[i] & 1 << bit ? 0x40 : 0x00; |
28a35d8a HE |
364 | p[offset++] = v | 0x01; |
365 | p[offset++] = v; | |
366 | } | |
367 | } | |
368 | ||
369 | g_free(firmware); | |
370 | ||
371 | if (offset != *buf_size) { | |
372 | g_free(*buf); | |
47f4f073 | 373 | sr_err("Error reading firmware %s " |
0aeb0ccd | 374 | "offset=%ld, file_size=%ld, buf_size=%zd.", |
133a37bf | 375 | filename, offset, file_size, *buf_size); |
28a35d8a | 376 | |
b53738ba | 377 | return SR_ERR; |
28a35d8a HE |
378 | } |
379 | ||
b53738ba | 380 | return SR_OK; |
28a35d8a HE |
381 | } |
382 | ||
3678cf73 | 383 | static void clear_helper(void *priv) |
0448d110 | 384 | { |
0e1357e8 | 385 | struct dev_context *devc; |
ce4d26dd | 386 | |
3678cf73 | 387 | devc = priv; |
0e1357e8 | 388 | |
3678cf73 UH |
389 | ftdi_deinit(&devc->ftdic); |
390 | } | |
0448d110 | 391 | |
3b412e3a | 392 | static int dev_clear(void) |
3678cf73 UH |
393 | { |
394 | return std_dev_clear(di, clear_helper); | |
0448d110 BV |
395 | } |
396 | ||
6078d2c9 | 397 | static int init(struct sr_context *sr_ctx) |
61136ea6 | 398 | { |
f6beaac5 | 399 | return std_init(sr_ctx, di, LOG_PREFIX); |
61136ea6 BV |
400 | } |
401 | ||
6078d2c9 | 402 | static GSList *scan(GSList *options) |
28a35d8a | 403 | { |
d68e2d1a | 404 | struct sr_dev_inst *sdi; |
ba7dd8bb | 405 | struct sr_channel *ch; |
0e1357e8 BV |
406 | struct drv_context *drvc; |
407 | struct dev_context *devc; | |
0448d110 | 408 | GSList *devices; |
e3fff420 HE |
409 | struct ftdi_device_list *devlist; |
410 | char serial_txt[10]; | |
411 | uint32_t serial; | |
790c7ccc MV |
412 | int ret; |
413 | unsigned int i; | |
28a35d8a | 414 | |
0448d110 | 415 | (void)options; |
64d33dc2 | 416 | |
a873c594 | 417 | drvc = di->priv; |
4b97c74e | 418 | |
0448d110 | 419 | devices = NULL; |
4b97c74e | 420 | |
0e1357e8 | 421 | if (!(devc = g_try_malloc(sizeof(struct dev_context)))) { |
47f4f073 | 422 | sr_err("%s: devc malloc failed", __func__); |
0448d110 | 423 | return NULL; |
b53738ba | 424 | } |
99965709 | 425 | |
0e1357e8 | 426 | ftdi_init(&devc->ftdic); |
28a35d8a | 427 | |
fefa1800 | 428 | /* Look for SIGMAs. */ |
e3fff420 | 429 | |
0e1357e8 | 430 | if ((ret = ftdi_usb_find_all(&devc->ftdic, &devlist, |
eec944c5 BV |
431 | USB_VENDOR, USB_PRODUCT)) <= 0) { |
432 | if (ret < 0) | |
433 | sr_err("ftdi_usb_find_all(): %d", ret); | |
99965709 | 434 | goto free; |
eec944c5 | 435 | } |
99965709 | 436 | |
e3fff420 | 437 | /* Make sure it's a version 1 or 2 SIGMA. */ |
0e1357e8 | 438 | ftdi_usb_get_strings(&devc->ftdic, devlist->dev, NULL, 0, NULL, 0, |
6352d030 | 439 | serial_txt, sizeof(serial_txt)); |
e3fff420 HE |
440 | sscanf(serial_txt, "%x", &serial); |
441 | ||
6352d030 | 442 | if (serial < 0xa6010000 || serial > 0xa602ffff) { |
47f4f073 UH |
443 | sr_err("Only SIGMA and SIGMA2 are supported " |
444 | "in this version of libsigrok."); | |
e3fff420 HE |
445 | goto free; |
446 | } | |
447 | ||
448 | sr_info("Found ASIX SIGMA - Serial: %s", serial_txt); | |
449 | ||
0e1357e8 BV |
450 | devc->cur_samplerate = 0; |
451 | devc->period_ps = 0; | |
452 | devc->limit_msec = 0; | |
453 | devc->cur_firmware = -1; | |
ba7dd8bb | 454 | devc->num_channels = 0; |
0e1357e8 BV |
455 | devc->samples_per_event = 0; |
456 | devc->capture_ratio = 50; | |
457 | devc->use_triggers = 0; | |
28a35d8a | 458 | |
fefa1800 | 459 | /* Register SIGMA device. */ |
d68e2d1a | 460 | if (!(sdi = sr_dev_inst_new(0, SR_ST_INITIALIZING, USB_VENDOR_NAME, |
55f98c65 | 461 | USB_MODEL_NAME, NULL))) { |
47f4f073 | 462 | sr_err("%s: sdi was NULL", __func__); |
99965709 | 463 | goto free; |
d68e2d1a | 464 | } |
a873c594 | 465 | sdi->driver = di; |
87ca93c5 | 466 | |
790c7ccc MV |
467 | for (i = 0; i < ARRAY_SIZE(channel_names); i++) { |
468 | ch = sr_channel_new(i, SR_CHANNEL_LOGIC, TRUE, | |
469 | channel_names[i]); | |
470 | if (!ch) | |
87ca93c5 | 471 | return NULL; |
ba7dd8bb | 472 | sdi->channels = g_slist_append(sdi->channels, ch); |
87ca93c5 BV |
473 | } |
474 | ||
0448d110 | 475 | devices = g_slist_append(devices, sdi); |
0e1357e8 BV |
476 | drvc->instances = g_slist_append(drvc->instances, sdi); |
477 | sdi->priv = devc; | |
28a35d8a | 478 | |
fefa1800 | 479 | /* We will open the device again when we need it. */ |
e3fff420 | 480 | ftdi_list_free(&devlist); |
28a35d8a | 481 | |
0448d110 | 482 | return devices; |
ea9cfed7 | 483 | |
99965709 | 484 | free: |
0e1357e8 BV |
485 | ftdi_deinit(&devc->ftdic); |
486 | g_free(devc); | |
0448d110 | 487 | return NULL; |
28a35d8a HE |
488 | } |
489 | ||
6078d2c9 | 490 | static GSList *dev_list(void) |
811deee4 | 491 | { |
0e94d524 | 492 | return ((struct drv_context *)(di->priv))->instances; |
811deee4 BV |
493 | } |
494 | ||
d5fa188a MV |
495 | /* |
496 | * Configure the FPGA for bitbang mode. | |
497 | * This sequence is documented in section 2. of the ASIX Sigma programming | |
498 | * manual. This sequence is necessary to configure the FPGA in the Sigma | |
499 | * into Bitbang mode, in which it can be programmed with the firmware. | |
500 | */ | |
501 | static int sigma_fpga_init_bitbang(struct dev_context *devc) | |
502 | { | |
503 | uint8_t suicide[] = { | |
504 | 0x84, 0x84, 0x88, 0x84, 0x88, 0x84, 0x88, 0x84, | |
505 | }; | |
506 | uint8_t init_array[] = { | |
507 | 0x01, 0x03, 0x03, 0x01, 0x01, 0x01, 0x01, 0x01, | |
508 | 0x01, 0x01, | |
509 | }; | |
510 | int i, ret, timeout = 10000; | |
511 | uint8_t data; | |
512 | ||
513 | /* Section 2. part 1), do the FPGA suicide. */ | |
514 | sigma_write(suicide, sizeof(suicide), devc); | |
515 | sigma_write(suicide, sizeof(suicide), devc); | |
516 | sigma_write(suicide, sizeof(suicide), devc); | |
517 | sigma_write(suicide, sizeof(suicide), devc); | |
518 | ||
519 | /* Section 2. part 2), do pulse on D1. */ | |
520 | sigma_write(init_array, sizeof(init_array), devc); | |
521 | ftdi_usb_purge_buffers(&devc->ftdic); | |
522 | ||
523 | /* Wait until the FPGA asserts D6/INIT_B. */ | |
524 | for (i = 0; i < timeout; i++) { | |
525 | ret = sigma_read(&data, 1, devc); | |
526 | if (ret < 0) | |
527 | return ret; | |
528 | /* Test if pin D6 got asserted. */ | |
529 | if (data & (1 << 5)) | |
530 | return 0; | |
531 | /* The D6 was not asserted yet, wait a bit. */ | |
532 | usleep(10000); | |
533 | } | |
534 | ||
535 | return SR_ERR_TIMEOUT; | |
536 | } | |
537 | ||
0e1357e8 | 538 | static int upload_firmware(int firmware_idx, struct dev_context *devc) |
28a35d8a HE |
539 | { |
540 | int ret; | |
541 | unsigned char *buf; | |
542 | unsigned char pins; | |
543 | size_t buf_size; | |
28a35d8a | 544 | unsigned char result[32]; |
499b17e9 | 545 | const char *firmware = sigma_firmware_files[firmware_idx]; |
28a35d8a | 546 | |
fefa1800 | 547 | /* Make sure it's an ASIX SIGMA. */ |
0e1357e8 | 548 | if ((ret = ftdi_usb_open_desc(&devc->ftdic, |
28a35d8a | 549 | USB_VENDOR, USB_PRODUCT, USB_DESCRIPTION, NULL)) < 0) { |
47f4f073 | 550 | sr_err("ftdi_usb_open failed: %s", |
0e1357e8 | 551 | ftdi_get_error_string(&devc->ftdic)); |
28a35d8a HE |
552 | return 0; |
553 | } | |
554 | ||
0e1357e8 | 555 | if ((ret = ftdi_set_bitmode(&devc->ftdic, 0xdf, BITMODE_BITBANG)) < 0) { |
47f4f073 | 556 | sr_err("ftdi_set_bitmode failed: %s", |
0e1357e8 | 557 | ftdi_get_error_string(&devc->ftdic)); |
28a35d8a HE |
558 | return 0; |
559 | } | |
560 | ||
fefa1800 | 561 | /* Four times the speed of sigmalogan - Works well. */ |
0e1357e8 | 562 | if ((ret = ftdi_set_baudrate(&devc->ftdic, 750000)) < 0) { |
47f4f073 | 563 | sr_err("ftdi_set_baudrate failed: %s", |
0e1357e8 | 564 | ftdi_get_error_string(&devc->ftdic)); |
28a35d8a HE |
565 | return 0; |
566 | } | |
567 | ||
d5fa188a MV |
568 | /* Initialize the FPGA for firmware upload. */ |
569 | ret = sigma_fpga_init_bitbang(devc); | |
570 | if (ret) | |
571 | return ret; | |
28a35d8a | 572 | |
9ddb2a12 | 573 | /* Prepare firmware. */ |
499b17e9 | 574 | if ((ret = bin2bitbang(firmware, &buf, &buf_size)) != SR_OK) { |
47f4f073 | 575 | sr_err("An error occured while reading the firmware: %s", |
499b17e9 | 576 | firmware); |
b53738ba | 577 | return ret; |
28a35d8a HE |
578 | } |
579 | ||
fefa1800 | 580 | /* Upload firmare. */ |
499b17e9 | 581 | sr_info("Uploading firmware file '%s'.", firmware); |
0e1357e8 | 582 | sigma_write(buf, buf_size, devc); |
28a35d8a HE |
583 | |
584 | g_free(buf); | |
585 | ||
0e1357e8 | 586 | if ((ret = ftdi_set_bitmode(&devc->ftdic, 0x00, BITMODE_RESET)) < 0) { |
47f4f073 | 587 | sr_err("ftdi_set_bitmode failed: %s", |
0e1357e8 | 588 | ftdi_get_error_string(&devc->ftdic)); |
e46b8fb1 | 589 | return SR_ERR; |
28a35d8a HE |
590 | } |
591 | ||
0e1357e8 | 592 | ftdi_usb_purge_buffers(&devc->ftdic); |
28a35d8a | 593 | |
fefa1800 | 594 | /* Discard garbage. */ |
0e1357e8 | 595 | while (1 == sigma_read(&pins, 1, devc)) |
28a35d8a HE |
596 | ; |
597 | ||
fefa1800 | 598 | /* Initialize the logic analyzer mode. */ |
0e1357e8 | 599 | sigma_write(logic_mode_start, sizeof(logic_mode_start), devc); |
28a35d8a | 600 | |
fefa1800 | 601 | /* Expect a 3 byte reply. */ |
0e1357e8 | 602 | ret = sigma_read(result, 3, devc); |
28a35d8a HE |
603 | if (ret != 3 || |
604 | result[0] != 0xa6 || result[1] != 0x55 || result[2] != 0xaa) { | |
47f4f073 | 605 | sr_err("Configuration failed. Invalid reply received."); |
e46b8fb1 | 606 | return SR_ERR; |
28a35d8a HE |
607 | } |
608 | ||
0e1357e8 | 609 | devc->cur_firmware = firmware_idx; |
f6564c8d | 610 | |
47f4f073 | 611 | sr_info("Firmware uploaded."); |
e3fff420 | 612 | |
e46b8fb1 | 613 | return SR_OK; |
f6564c8d HE |
614 | } |
615 | ||
6078d2c9 | 616 | static int dev_open(struct sr_dev_inst *sdi) |
f6564c8d | 617 | { |
0e1357e8 | 618 | struct dev_context *devc; |
f6564c8d HE |
619 | int ret; |
620 | ||
0e1357e8 | 621 | devc = sdi->priv; |
99965709 | 622 | |
9ddb2a12 | 623 | /* Make sure it's an ASIX SIGMA. */ |
0e1357e8 | 624 | if ((ret = ftdi_usb_open_desc(&devc->ftdic, |
f6564c8d HE |
625 | USB_VENDOR, USB_PRODUCT, USB_DESCRIPTION, NULL)) < 0) { |
626 | ||
47f4f073 | 627 | sr_err("ftdi_usb_open failed: %s", |
0e1357e8 | 628 | ftdi_get_error_string(&devc->ftdic)); |
f6564c8d HE |
629 | |
630 | return 0; | |
631 | } | |
28a35d8a | 632 | |
5a2326a7 | 633 | sdi->status = SR_ST_ACTIVE; |
28a35d8a | 634 | |
e46b8fb1 | 635 | return SR_OK; |
f6564c8d HE |
636 | } |
637 | ||
6f4b1868 | 638 | static int set_samplerate(const struct sr_dev_inst *sdi, uint64_t samplerate) |
f6564c8d | 639 | { |
2c9c0df8 BV |
640 | struct dev_context *devc; |
641 | unsigned int i; | |
642 | int ret; | |
f6564c8d | 643 | |
2c9c0df8 | 644 | devc = sdi->priv; |
f4abaa9f UH |
645 | ret = SR_OK; |
646 | ||
2c9c0df8 BV |
647 | for (i = 0; i < ARRAY_SIZE(samplerates); i++) { |
648 | if (samplerates[i] == samplerate) | |
f6564c8d HE |
649 | break; |
650 | } | |
2c9c0df8 | 651 | if (samplerates[i] == 0) |
e46b8fb1 | 652 | return SR_ERR_SAMPLERATE; |
f6564c8d | 653 | |
59df0c77 | 654 | if (samplerate <= SR_MHZ(50)) { |
0e1357e8 | 655 | ret = upload_firmware(0, devc); |
ba7dd8bb | 656 | devc->num_channels = 16; |
e8397563 | 657 | } |
59df0c77 | 658 | if (samplerate == SR_MHZ(100)) { |
0e1357e8 | 659 | ret = upload_firmware(1, devc); |
ba7dd8bb | 660 | devc->num_channels = 8; |
f78898e9 | 661 | } |
59df0c77 | 662 | else if (samplerate == SR_MHZ(200)) { |
0e1357e8 | 663 | ret = upload_firmware(2, devc); |
ba7dd8bb | 664 | devc->num_channels = 4; |
f78898e9 | 665 | } |
f6564c8d | 666 | |
0e1357e8 | 667 | devc->cur_samplerate = samplerate; |
5edc02c7 | 668 | devc->period_ps = 1000000000000ULL / samplerate; |
ba7dd8bb | 669 | devc->samples_per_event = 16 / devc->num_channels; |
0e1357e8 | 670 | devc->state.state = SIGMA_IDLE; |
f6564c8d | 671 | |
e8397563 | 672 | return ret; |
28a35d8a HE |
673 | } |
674 | ||
c53d793f HE |
675 | /* |
676 | * In 100 and 200 MHz mode, only a single pin rising/falling can be | |
677 | * set as trigger. In other modes, two rising/falling triggers can be set, | |
ba7dd8bb | 678 | * in addition to value/mask trigger for any number of channels. |
c53d793f HE |
679 | * |
680 | * The Sigma supports complex triggers using boolean expressions, but this | |
681 | * has not been implemented yet. | |
682 | */ | |
ba7dd8bb | 683 | static int configure_channels(const struct sr_dev_inst *sdi) |
57bbf56b | 684 | { |
0e1357e8 | 685 | struct dev_context *devc = sdi->priv; |
ba7dd8bb | 686 | const struct sr_channel *ch; |
1b79df2f | 687 | const GSList *l; |
57bbf56b | 688 | int trigger_set = 0; |
ba7dd8bb | 689 | int channelbit; |
57bbf56b | 690 | |
0e1357e8 | 691 | memset(&devc->trigger, 0, sizeof(struct sigma_trigger)); |
eec5275e | 692 | |
ba7dd8bb UH |
693 | for (l = sdi->channels; l; l = l->next) { |
694 | ch = (struct sr_channel *)l->data; | |
695 | channelbit = 1 << (ch->index); | |
57bbf56b | 696 | |
ba7dd8bb | 697 | if (!ch->enabled || !ch->trigger) |
57bbf56b HE |
698 | continue; |
699 | ||
0e1357e8 | 700 | if (devc->cur_samplerate >= SR_MHZ(100)) { |
c53d793f | 701 | /* Fast trigger support. */ |
ee492173 | 702 | if (trigger_set) { |
47f4f073 UH |
703 | sr_err("Only a single pin trigger in 100 and " |
704 | "200MHz mode is supported."); | |
e46b8fb1 | 705 | return SR_ERR; |
ee492173 | 706 | } |
ba7dd8bb UH |
707 | if (ch->trigger[0] == 'f') |
708 | devc->trigger.fallingmask |= channelbit; | |
709 | else if (ch->trigger[0] == 'r') | |
710 | devc->trigger.risingmask |= channelbit; | |
ee492173 | 711 | else { |
47f4f073 UH |
712 | sr_err("Only rising/falling trigger in 100 " |
713 | "and 200MHz mode is supported."); | |
e46b8fb1 | 714 | return SR_ERR; |
ee492173 | 715 | } |
57bbf56b | 716 | |
c53d793f | 717 | ++trigger_set; |
ee492173 | 718 | } else { |
c53d793f | 719 | /* Simple trigger support (event). */ |
ba7dd8bb UH |
720 | if (ch->trigger[0] == '1') { |
721 | devc->trigger.simplevalue |= channelbit; | |
722 | devc->trigger.simplemask |= channelbit; | |
c53d793f | 723 | } |
ba7dd8bb UH |
724 | else if (ch->trigger[0] == '0') { |
725 | devc->trigger.simplevalue &= ~channelbit; | |
726 | devc->trigger.simplemask |= channelbit; | |
c53d793f | 727 | } |
ba7dd8bb UH |
728 | else if (ch->trigger[0] == 'f') { |
729 | devc->trigger.fallingmask |= channelbit; | |
c53d793f HE |
730 | ++trigger_set; |
731 | } | |
ba7dd8bb UH |
732 | else if (ch->trigger[0] == 'r') { |
733 | devc->trigger.risingmask |= channelbit; | |
c53d793f HE |
734 | ++trigger_set; |
735 | } | |
ee492173 | 736 | |
ea9cfed7 UH |
737 | /* |
738 | * Actually, Sigma supports 2 rising/falling triggers, | |
739 | * but they are ORed and the current trigger syntax | |
740 | * does not permit ORed triggers. | |
741 | */ | |
98b8cbc1 | 742 | if (trigger_set > 1) { |
47f4f073 UH |
743 | sr_err("Only 1 rising/falling trigger " |
744 | "is supported."); | |
e46b8fb1 | 745 | return SR_ERR; |
ee492173 | 746 | } |
ee492173 | 747 | } |
5b5ea7c6 HE |
748 | |
749 | if (trigger_set) | |
0e1357e8 | 750 | devc->use_triggers = 1; |
57bbf56b HE |
751 | } |
752 | ||
e46b8fb1 | 753 | return SR_OK; |
57bbf56b HE |
754 | } |
755 | ||
6078d2c9 | 756 | static int dev_close(struct sr_dev_inst *sdi) |
28a35d8a | 757 | { |
0e1357e8 | 758 | struct dev_context *devc; |
28a35d8a | 759 | |
961009b0 | 760 | devc = sdi->priv; |
697785d1 UH |
761 | |
762 | /* TODO */ | |
763 | if (sdi->status == SR_ST_ACTIVE) | |
0e1357e8 | 764 | ftdi_usb_close(&devc->ftdic); |
697785d1 UH |
765 | |
766 | sdi->status = SR_ST_INACTIVE; | |
767 | ||
768 | return SR_OK; | |
28a35d8a HE |
769 | } |
770 | ||
6078d2c9 | 771 | static int cleanup(void) |
28a35d8a | 772 | { |
3b412e3a | 773 | return dev_clear(); |
28a35d8a HE |
774 | } |
775 | ||
8f996b89 | 776 | static int config_get(int id, GVariant **data, const struct sr_dev_inst *sdi, |
53b4680f | 777 | const struct sr_channel_group *cg) |
28a35d8a | 778 | { |
0e1357e8 | 779 | struct dev_context *devc; |
99965709 | 780 | |
53b4680f | 781 | (void)cg; |
8f996b89 | 782 | |
035a1078 | 783 | switch (id) { |
123e1313 | 784 | case SR_CONF_SAMPLERATE: |
41479605 | 785 | if (sdi) { |
0e1357e8 | 786 | devc = sdi->priv; |
2c9c0df8 | 787 | *data = g_variant_new_uint64(devc->cur_samplerate); |
41479605 BV |
788 | } else |
789 | return SR_ERR; | |
28a35d8a | 790 | break; |
d7bbecfd | 791 | default: |
bd6fbf62 | 792 | return SR_ERR_NA; |
28a35d8a HE |
793 | } |
794 | ||
41479605 | 795 | return SR_OK; |
28a35d8a HE |
796 | } |
797 | ||
8f996b89 | 798 | static int config_set(int id, GVariant *data, const struct sr_dev_inst *sdi, |
53b4680f | 799 | const struct sr_channel_group *cg) |
28a35d8a | 800 | { |
0e1357e8 | 801 | struct dev_context *devc; |
6868626b | 802 | uint64_t num_samples; |
28a35d8a | 803 | int ret; |
f6564c8d | 804 | |
53b4680f | 805 | (void)cg; |
8f996b89 | 806 | |
e73ffd42 BV |
807 | if (sdi->status != SR_ST_ACTIVE) |
808 | return SR_ERR_DEV_CLOSED; | |
809 | ||
0e1357e8 | 810 | devc = sdi->priv; |
99965709 | 811 | |
6868626b BV |
812 | switch (id) { |
813 | case SR_CONF_SAMPLERATE: | |
2c9c0df8 | 814 | ret = set_samplerate(sdi, g_variant_get_uint64(data)); |
6868626b BV |
815 | break; |
816 | case SR_CONF_LIMIT_MSEC: | |
2c9c0df8 | 817 | devc->limit_msec = g_variant_get_uint64(data); |
0e1357e8 | 818 | if (devc->limit_msec > 0) |
e46b8fb1 | 819 | ret = SR_OK; |
94ba4bd6 | 820 | else |
e46b8fb1 | 821 | ret = SR_ERR; |
6868626b BV |
822 | break; |
823 | case SR_CONF_LIMIT_SAMPLES: | |
824 | num_samples = g_variant_get_uint64(data); | |
825 | devc->limit_msec = num_samples * 1000 / devc->cur_samplerate; | |
826 | break; | |
827 | case SR_CONF_CAPTURE_RATIO: | |
2c9c0df8 | 828 | devc->capture_ratio = g_variant_get_uint64(data); |
0e1357e8 | 829 | if (devc->capture_ratio < 0 || devc->capture_ratio > 100) |
e46b8fb1 | 830 | ret = SR_ERR; |
94ba4bd6 | 831 | else |
e46b8fb1 | 832 | ret = SR_OK; |
6868626b BV |
833 | break; |
834 | default: | |
bd6fbf62 | 835 | ret = SR_ERR_NA; |
28a35d8a HE |
836 | } |
837 | ||
838 | return ret; | |
839 | } | |
840 | ||
8f996b89 | 841 | static int config_list(int key, GVariant **data, const struct sr_dev_inst *sdi, |
53b4680f | 842 | const struct sr_channel_group *cg) |
a1c743fc | 843 | { |
2c9c0df8 BV |
844 | GVariant *gvar; |
845 | GVariantBuilder gvb; | |
a1c743fc BV |
846 | |
847 | (void)sdi; | |
53b4680f | 848 | (void)cg; |
a1c743fc BV |
849 | |
850 | switch (key) { | |
9a6517d1 | 851 | case SR_CONF_DEVICE_OPTIONS: |
2c9c0df8 BV |
852 | *data = g_variant_new_fixed_array(G_VARIANT_TYPE_INT32, |
853 | hwcaps, ARRAY_SIZE(hwcaps), sizeof(int32_t)); | |
9a6517d1 | 854 | break; |
a1c743fc | 855 | case SR_CONF_SAMPLERATE: |
2c9c0df8 BV |
856 | g_variant_builder_init(&gvb, G_VARIANT_TYPE("a{sv}")); |
857 | gvar = g_variant_new_fixed_array(G_VARIANT_TYPE("t"), samplerates, | |
858 | ARRAY_SIZE(samplerates), sizeof(uint64_t)); | |
859 | g_variant_builder_add(&gvb, "{sv}", "samplerates", gvar); | |
860 | *data = g_variant_builder_end(&gvb); | |
a1c743fc | 861 | break; |
c50277a6 | 862 | case SR_CONF_TRIGGER_TYPE: |
2c9c0df8 | 863 | *data = g_variant_new_string(TRIGGER_TYPE); |
c50277a6 | 864 | break; |
a1c743fc | 865 | default: |
bd6fbf62 | 866 | return SR_ERR_NA; |
a1c743fc BV |
867 | } |
868 | ||
869 | return SR_OK; | |
870 | } | |
871 | ||
36b1c8e6 HE |
872 | /* Software trigger to determine exact trigger position. */ |
873 | static int get_trigger_offset(uint16_t *samples, uint16_t last_sample, | |
874 | struct sigma_trigger *t) | |
875 | { | |
876 | int i; | |
877 | ||
878 | for (i = 0; i < 8; ++i) { | |
879 | if (i > 0) | |
880 | last_sample = samples[i-1]; | |
881 | ||
882 | /* Simple triggers. */ | |
883 | if ((samples[i] & t->simplemask) != t->simplevalue) | |
884 | continue; | |
885 | ||
886 | /* Rising edge. */ | |
887 | if ((last_sample & t->risingmask) != 0 || (samples[i] & | |
888 | t->risingmask) != t->risingmask) | |
889 | continue; | |
890 | ||
891 | /* Falling edge. */ | |
bdfc7a89 HE |
892 | if ((last_sample & t->fallingmask) != t->fallingmask || |
893 | (samples[i] & t->fallingmask) != 0) | |
36b1c8e6 HE |
894 | continue; |
895 | ||
896 | break; | |
897 | } | |
898 | ||
899 | /* If we did not match, return original trigger pos. */ | |
900 | return i & 0x7; | |
901 | } | |
902 | ||
28a35d8a | 903 | /* |
fefa1800 UH |
904 | * Decode chunk of 1024 bytes, 64 clusters, 7 events per cluster. |
905 | * Each event is 20ns apart, and can contain multiple samples. | |
f78898e9 HE |
906 | * |
907 | * For 200 MHz, events contain 4 samples for each channel, spread 5 ns apart. | |
908 | * For 100 MHz, events contain 2 samples for each channel, spread 10 ns apart. | |
909 | * For 50 MHz and below, events contain one sample for each channel, | |
910 | * spread 20 ns apart. | |
28a35d8a HE |
911 | */ |
912 | static int decode_chunk_ts(uint8_t *buf, uint16_t *lastts, | |
88c51afe | 913 | uint16_t *lastsample, int triggerpos, |
3cd3a20b | 914 | uint16_t limit_chunk, void *cb_data) |
28a35d8a | 915 | { |
3cd3a20b | 916 | struct sr_dev_inst *sdi = cb_data; |
0e1357e8 | 917 | struct dev_context *devc = sdi->priv; |
fefa1800 | 918 | uint16_t tsdiff, ts; |
0e1357e8 | 919 | uint16_t samples[65536 * devc->samples_per_event]; |
b9c735a2 | 920 | struct sr_datafeed_packet packet; |
9c939c51 | 921 | struct sr_datafeed_logic logic; |
f78898e9 | 922 | int i, j, k, l, numpad, tosend; |
fefa1800 | 923 | size_t n = 0, sent = 0; |
0e1357e8 | 924 | int clustersize = EVENTS_PER_CLUSTER * devc->samples_per_event; |
fefa1800 | 925 | uint16_t *event; |
f78898e9 | 926 | uint16_t cur_sample; |
57bbf56b | 927 | int triggerts = -1; |
ee492173 | 928 | |
4ae1f451 | 929 | /* Check if trigger is in this chunk. */ |
ee492173 | 930 | if (triggerpos != -1) { |
0e1357e8 | 931 | if (devc->cur_samplerate <= SR_MHZ(50)) |
36b1c8e6 | 932 | triggerpos -= EVENTS_PER_CLUSTER - 1; |
ee492173 HE |
933 | |
934 | if (triggerpos < 0) | |
935 | triggerpos = 0; | |
57bbf56b | 936 | |
ee492173 HE |
937 | /* Find in which cluster the trigger occured. */ |
938 | triggerts = triggerpos / 7; | |
939 | } | |
28a35d8a | 940 | |
eec5275e | 941 | /* For each ts. */ |
28a35d8a | 942 | for (i = 0; i < 64; ++i) { |
fefa1800 | 943 | ts = *(uint16_t *) &buf[i * 16]; |
28a35d8a HE |
944 | tsdiff = ts - *lastts; |
945 | *lastts = ts; | |
946 | ||
88c51afe HE |
947 | /* Decode partial chunk. */ |
948 | if (limit_chunk && ts > limit_chunk) | |
e46b8fb1 | 949 | return SR_OK; |
88c51afe | 950 | |
fefa1800 | 951 | /* Pad last sample up to current point. */ |
0e1357e8 | 952 | numpad = tsdiff * devc->samples_per_event - clustersize; |
28a35d8a | 953 | if (numpad > 0) { |
f78898e9 HE |
954 | for (j = 0; j < numpad; ++j) |
955 | samples[j] = *lastsample; | |
956 | ||
957 | n = numpad; | |
28a35d8a HE |
958 | } |
959 | ||
57bbf56b HE |
960 | /* Send samples between previous and this timestamp to sigrok. */ |
961 | sent = 0; | |
962 | while (sent < n) { | |
963 | tosend = MIN(2048, n - sent); | |
964 | ||
5a2326a7 | 965 | packet.type = SR_DF_LOGIC; |
9c939c51 BV |
966 | packet.payload = &logic; |
967 | logic.length = tosend * sizeof(uint16_t); | |
968 | logic.unitsize = 2; | |
969 | logic.data = samples + sent; | |
3e9b7f9c | 970 | sr_session_send(devc->cb_data, &packet); |
28a35d8a | 971 | |
57bbf56b HE |
972 | sent += tosend; |
973 | } | |
974 | n = 0; | |
975 | ||
976 | event = (uint16_t *) &buf[i * 16 + 2]; | |
f78898e9 HE |
977 | cur_sample = 0; |
978 | ||
979 | /* For each event in cluster. */ | |
28a35d8a | 980 | for (j = 0; j < 7; ++j) { |
f78898e9 HE |
981 | |
982 | /* For each sample in event. */ | |
0e1357e8 | 983 | for (k = 0; k < devc->samples_per_event; ++k) { |
f78898e9 HE |
984 | cur_sample = 0; |
985 | ||
ba7dd8bb UH |
986 | /* For each channel. */ |
987 | for (l = 0; l < devc->num_channels; ++l) | |
edca2c5c | 988 | cur_sample |= (!!(event[j] & (1 << (l * |
0e1357e8 | 989 | devc->samples_per_event + k)))) << l; |
f78898e9 HE |
990 | |
991 | samples[n++] = cur_sample; | |
28a35d8a HE |
992 | } |
993 | } | |
994 | ||
eec5275e | 995 | /* Send data up to trigger point (if triggered). */ |
fefa1800 | 996 | sent = 0; |
57bbf56b HE |
997 | if (i == triggerts) { |
998 | /* | |
36b1c8e6 HE |
999 | * Trigger is not always accurate to sample because of |
1000 | * pipeline delay. However, it always triggers before | |
1001 | * the actual event. We therefore look at the next | |
1002 | * samples to pinpoint the exact position of the trigger. | |
57bbf56b | 1003 | */ |
bdfc7a89 | 1004 | tosend = get_trigger_offset(samples, *lastsample, |
0e1357e8 | 1005 | &devc->trigger); |
57bbf56b HE |
1006 | |
1007 | if (tosend > 0) { | |
5a2326a7 | 1008 | packet.type = SR_DF_LOGIC; |
9c939c51 BV |
1009 | packet.payload = &logic; |
1010 | logic.length = tosend * sizeof(uint16_t); | |
1011 | logic.unitsize = 2; | |
1012 | logic.data = samples; | |
3e9b7f9c | 1013 | sr_session_send(devc->cb_data, &packet); |
57bbf56b HE |
1014 | |
1015 | sent += tosend; | |
1016 | } | |
28a35d8a | 1017 | |
5b5ea7c6 | 1018 | /* Only send trigger if explicitly enabled. */ |
0e1357e8 | 1019 | if (devc->use_triggers) { |
5a2326a7 | 1020 | packet.type = SR_DF_TRIGGER; |
3e9b7f9c | 1021 | sr_session_send(devc->cb_data, &packet); |
5b5ea7c6 | 1022 | } |
28a35d8a | 1023 | } |
57bbf56b | 1024 | |
eec5275e | 1025 | /* Send rest of the chunk to sigrok. */ |
57bbf56b HE |
1026 | tosend = n - sent; |
1027 | ||
abda62ce | 1028 | if (tosend > 0) { |
5a2326a7 | 1029 | packet.type = SR_DF_LOGIC; |
9c939c51 BV |
1030 | packet.payload = &logic; |
1031 | logic.length = tosend * sizeof(uint16_t); | |
1032 | logic.unitsize = 2; | |
1033 | logic.data = samples + sent; | |
3e9b7f9c | 1034 | sr_session_send(devc->cb_data, &packet); |
abda62ce | 1035 | } |
ee492173 HE |
1036 | |
1037 | *lastsample = samples[n - 1]; | |
28a35d8a HE |
1038 | } |
1039 | ||
e46b8fb1 | 1040 | return SR_OK; |
28a35d8a HE |
1041 | } |
1042 | ||
6868626b | 1043 | static void download_capture(struct sr_dev_inst *sdi) |
28a35d8a | 1044 | { |
6868626b | 1045 | struct dev_context *devc; |
28a35d8a HE |
1046 | const int chunks_per_read = 32; |
1047 | unsigned char buf[chunks_per_read * CHUNK_SIZE]; | |
6868626b BV |
1048 | int bufsz, i, numchunks, newchunks; |
1049 | ||
1050 | sr_info("Downloading sample data."); | |
1051 | ||
1052 | devc = sdi->priv; | |
1053 | devc->state.chunks_downloaded = 0; | |
1054 | numchunks = (devc->state.stoppos + 511) / 512; | |
1055 | newchunks = MIN(chunks_per_read, numchunks - devc->state.chunks_downloaded); | |
1056 | ||
1057 | bufsz = sigma_read_dram(devc->state.chunks_downloaded, newchunks, buf, devc); | |
1058 | /* TODO: Check bufsz. For now, just avoid compiler warnings. */ | |
1059 | (void)bufsz; | |
1060 | ||
1061 | /* Find first ts. */ | |
1062 | if (devc->state.chunks_downloaded == 0) { | |
1063 | devc->state.lastts = RL16(buf) - 1; | |
1064 | devc->state.lastsample = 0; | |
1065 | } | |
1066 | ||
1067 | /* Decode chunks and send them to sigrok. */ | |
1068 | for (i = 0; i < newchunks; ++i) { | |
1069 | int limit_chunk = 0; | |
1070 | ||
1071 | /* The last chunk may potentially be only in part. */ | |
1072 | if (devc->state.chunks_downloaded == numchunks - 1) { | |
1073 | /* Find the last valid timestamp */ | |
1074 | limit_chunk = devc->state.stoppos % 512 + devc->state.lastts; | |
1075 | } | |
1076 | ||
1077 | if (devc->state.chunks_downloaded + i == devc->state.triggerchunk) | |
1078 | decode_chunk_ts(buf + (i * CHUNK_SIZE), | |
1079 | &devc->state.lastts, | |
1080 | &devc->state.lastsample, | |
1081 | devc->state.triggerpos & 0x1ff, | |
1082 | limit_chunk, sdi); | |
1083 | else | |
1084 | decode_chunk_ts(buf + (i * CHUNK_SIZE), | |
1085 | &devc->state.lastts, | |
1086 | &devc->state.lastsample, | |
1087 | -1, limit_chunk, sdi); | |
1088 | ||
1089 | ++devc->state.chunks_downloaded; | |
1090 | } | |
1091 | ||
1092 | } | |
1093 | ||
1094 | static int receive_data(int fd, int revents, void *cb_data) | |
1095 | { | |
1096 | struct sr_dev_inst *sdi; | |
1097 | struct dev_context *devc; | |
1098 | struct sr_datafeed_packet packet; | |
94ba4bd6 | 1099 | uint64_t running_msec; |
28a35d8a | 1100 | struct timeval tv; |
6868626b BV |
1101 | int numchunks; |
1102 | uint8_t modestatus; | |
28a35d8a | 1103 | |
cb93f8a9 UH |
1104 | (void)fd; |
1105 | (void)revents; | |
28a35d8a | 1106 | |
6868626b BV |
1107 | sdi = cb_data; |
1108 | devc = sdi->priv; | |
1109 | ||
805919b0 | 1110 | /* Get the current position. */ |
0e1357e8 | 1111 | sigma_read_pos(&devc->state.stoppos, &devc->state.triggerpos, devc); |
805919b0 | 1112 | |
0e1357e8 | 1113 | if (devc->state.state == SIGMA_IDLE) |
805919b0 | 1114 | return TRUE; |
28a35d8a | 1115 | |
0e1357e8 | 1116 | if (devc->state.state == SIGMA_CAPTURE) { |
6868626b BV |
1117 | numchunks = (devc->state.stoppos + 511) / 512; |
1118 | ||
6aac7737 HE |
1119 | /* Check if the timer has expired, or memory is full. */ |
1120 | gettimeofday(&tv, 0); | |
0e1357e8 BV |
1121 | running_msec = (tv.tv_sec - devc->start_tv.tv_sec) * 1000 + |
1122 | (tv.tv_usec - devc->start_tv.tv_usec) / 1000; | |
28a35d8a | 1123 | |
0e1357e8 | 1124 | if (running_msec < devc->limit_msec && numchunks < 32767) |
6868626b | 1125 | /* Still capturing. */ |
6aac7737 | 1126 | return TRUE; |
6aac7737 | 1127 | |
6868626b BV |
1128 | /* Stop acquisition. */ |
1129 | sigma_set_register(WRITE_MODE, 0x11, devc); | |
28a35d8a | 1130 | |
6868626b BV |
1131 | /* Set SDRAM Read Enable. */ |
1132 | sigma_set_register(WRITE_MODE, 0x02, devc); | |
28a35d8a | 1133 | |
6868626b BV |
1134 | /* Get the current position. */ |
1135 | sigma_read_pos(&devc->state.stoppos, &devc->state.triggerpos, devc); | |
28a35d8a | 1136 | |
6868626b BV |
1137 | /* Check if trigger has fired. */ |
1138 | modestatus = sigma_get_register(READ_MODE, devc); | |
1139 | if (modestatus & 0x20) | |
1140 | devc->state.triggerchunk = devc->state.triggerpos / 512; | |
1141 | else | |
1142 | devc->state.triggerchunk = -1; | |
28a35d8a | 1143 | |
6868626b BV |
1144 | /* Transfer captured data from device. */ |
1145 | download_capture(sdi); | |
88c51afe | 1146 | |
6868626b BV |
1147 | /* All done. */ |
1148 | packet.type = SR_DF_END; | |
1149 | sr_session_send(sdi, &packet); | |
88c51afe | 1150 | |
6868626b | 1151 | dev_acquisition_stop(sdi, sdi); |
28a35d8a HE |
1152 | } |
1153 | ||
28a35d8a HE |
1154 | return TRUE; |
1155 | } | |
1156 | ||
c53d793f HE |
1157 | /* Build a LUT entry used by the trigger functions. */ |
1158 | static void build_lut_entry(uint16_t value, uint16_t mask, uint16_t *entry) | |
ee492173 HE |
1159 | { |
1160 | int i, j, k, bit; | |
1161 | ||
ba7dd8bb | 1162 | /* For each quad channel. */ |
ee492173 | 1163 | for (i = 0; i < 4; ++i) { |
c53d793f | 1164 | entry[i] = 0xffff; |
ee492173 | 1165 | |
f758d074 | 1166 | /* For each bit in LUT. */ |
ee492173 HE |
1167 | for (j = 0; j < 16; ++j) |
1168 | ||
ba7dd8bb | 1169 | /* For each channel in quad. */ |
ee492173 HE |
1170 | for (k = 0; k < 4; ++k) { |
1171 | bit = 1 << (i * 4 + k); | |
1172 | ||
c53d793f HE |
1173 | /* Set bit in entry */ |
1174 | if ((mask & bit) && | |
1175 | ((!(value & bit)) != | |
4ae1f451 | 1176 | (!(j & (1 << k))))) |
c53d793f | 1177 | entry[i] &= ~(1 << j); |
ee492173 HE |
1178 | } |
1179 | } | |
c53d793f | 1180 | } |
ee492173 | 1181 | |
c53d793f HE |
1182 | /* Add a logical function to LUT mask. */ |
1183 | static void add_trigger_function(enum triggerop oper, enum triggerfunc func, | |
1184 | int index, int neg, uint16_t *mask) | |
1185 | { | |
1186 | int i, j; | |
1187 | int x[2][2], tmp, a, b, aset, bset, rset; | |
1188 | ||
1189 | memset(x, 0, 4 * sizeof(int)); | |
1190 | ||
1191 | /* Trigger detect condition. */ | |
1192 | switch (oper) { | |
1193 | case OP_LEVEL: | |
1194 | x[0][1] = 1; | |
1195 | x[1][1] = 1; | |
1196 | break; | |
1197 | case OP_NOT: | |
1198 | x[0][0] = 1; | |
1199 | x[1][0] = 1; | |
1200 | break; | |
1201 | case OP_RISE: | |
1202 | x[0][1] = 1; | |
1203 | break; | |
1204 | case OP_FALL: | |
1205 | x[1][0] = 1; | |
1206 | break; | |
1207 | case OP_RISEFALL: | |
1208 | x[0][1] = 1; | |
1209 | x[1][0] = 1; | |
1210 | break; | |
1211 | case OP_NOTRISE: | |
1212 | x[1][1] = 1; | |
1213 | x[0][0] = 1; | |
1214 | x[1][0] = 1; | |
1215 | break; | |
1216 | case OP_NOTFALL: | |
1217 | x[1][1] = 1; | |
1218 | x[0][0] = 1; | |
1219 | x[0][1] = 1; | |
1220 | break; | |
1221 | case OP_NOTRISEFALL: | |
1222 | x[1][1] = 1; | |
1223 | x[0][0] = 1; | |
1224 | break; | |
1225 | } | |
1226 | ||
1227 | /* Transpose if neg is set. */ | |
1228 | if (neg) { | |
ea9cfed7 | 1229 | for (i = 0; i < 2; ++i) { |
c53d793f HE |
1230 | for (j = 0; j < 2; ++j) { |
1231 | tmp = x[i][j]; | |
1232 | x[i][j] = x[1-i][1-j]; | |
1233 | x[1-i][1-j] = tmp; | |
1234 | } | |
ea9cfed7 | 1235 | } |
c53d793f HE |
1236 | } |
1237 | ||
1238 | /* Update mask with function. */ | |
1239 | for (i = 0; i < 16; ++i) { | |
1240 | a = (i >> (2 * index + 0)) & 1; | |
1241 | b = (i >> (2 * index + 1)) & 1; | |
1242 | ||
1243 | aset = (*mask >> i) & 1; | |
1244 | bset = x[b][a]; | |
1245 | ||
1246 | if (func == FUNC_AND || func == FUNC_NAND) | |
1247 | rset = aset & bset; | |
1248 | else if (func == FUNC_OR || func == FUNC_NOR) | |
1249 | rset = aset | bset; | |
1250 | else if (func == FUNC_XOR || func == FUNC_NXOR) | |
1251 | rset = aset ^ bset; | |
1252 | ||
1253 | if (func == FUNC_NAND || func == FUNC_NOR || func == FUNC_NXOR) | |
1254 | rset = !rset; | |
1255 | ||
1256 | *mask &= ~(1 << i); | |
1257 | ||
1258 | if (rset) | |
1259 | *mask |= 1 << i; | |
1260 | } | |
1261 | } | |
1262 | ||
1263 | /* | |
1264 | * Build trigger LUTs used by 50 MHz and lower sample rates for supporting | |
1265 | * simple pin change and state triggers. Only two transitions (rise/fall) can be | |
1266 | * set at any time, but a full mask and value can be set (0/1). | |
1267 | */ | |
0e1357e8 | 1268 | static int build_basic_trigger(struct triggerlut *lut, struct dev_context *devc) |
c53d793f HE |
1269 | { |
1270 | int i,j; | |
4ae1f451 | 1271 | uint16_t masks[2] = { 0, 0 }; |
c53d793f HE |
1272 | |
1273 | memset(lut, 0, sizeof(struct triggerlut)); | |
1274 | ||
1275 | /* Contant for simple triggers. */ | |
1276 | lut->m4 = 0xa000; | |
1277 | ||
1278 | /* Value/mask trigger support. */ | |
0e1357e8 | 1279 | build_lut_entry(devc->trigger.simplevalue, devc->trigger.simplemask, |
99965709 | 1280 | lut->m2d); |
c53d793f HE |
1281 | |
1282 | /* Rise/fall trigger support. */ | |
1283 | for (i = 0, j = 0; i < 16; ++i) { | |
0e1357e8 BV |
1284 | if (devc->trigger.risingmask & (1 << i) || |
1285 | devc->trigger.fallingmask & (1 << i)) | |
c53d793f HE |
1286 | masks[j++] = 1 << i; |
1287 | } | |
1288 | ||
1289 | build_lut_entry(masks[0], masks[0], lut->m0d); | |
1290 | build_lut_entry(masks[1], masks[1], lut->m1d); | |
1291 | ||
1292 | /* Add glue logic */ | |
1293 | if (masks[0] || masks[1]) { | |
1294 | /* Transition trigger. */ | |
0e1357e8 | 1295 | if (masks[0] & devc->trigger.risingmask) |
c53d793f | 1296 | add_trigger_function(OP_RISE, FUNC_OR, 0, 0, &lut->m3); |
0e1357e8 | 1297 | if (masks[0] & devc->trigger.fallingmask) |
c53d793f | 1298 | add_trigger_function(OP_FALL, FUNC_OR, 0, 0, &lut->m3); |
0e1357e8 | 1299 | if (masks[1] & devc->trigger.risingmask) |
c53d793f | 1300 | add_trigger_function(OP_RISE, FUNC_OR, 1, 0, &lut->m3); |
0e1357e8 | 1301 | if (masks[1] & devc->trigger.fallingmask) |
c53d793f HE |
1302 | add_trigger_function(OP_FALL, FUNC_OR, 1, 0, &lut->m3); |
1303 | } else { | |
1304 | /* Only value/mask trigger. */ | |
1305 | lut->m3 = 0xffff; | |
1306 | } | |
ee492173 | 1307 | |
c53d793f | 1308 | /* Triggertype: event. */ |
ee492173 HE |
1309 | lut->params.selres = 3; |
1310 | ||
e46b8fb1 | 1311 | return SR_OK; |
ee492173 HE |
1312 | } |
1313 | ||
6078d2c9 | 1314 | static int dev_acquisition_start(const struct sr_dev_inst *sdi, void *cb_data) |
28a35d8a | 1315 | { |
0e1357e8 | 1316 | struct dev_context *devc; |
9ddb2a12 | 1317 | struct clockselect_50 clockselect; |
82957b65 | 1318 | int frac, triggerpin, ret; |
f4abaa9f | 1319 | uint8_t triggerselect = 0; |
57bbf56b | 1320 | struct triggerinout triggerinout_conf; |
ee492173 | 1321 | struct triggerlut lut; |
28a35d8a | 1322 | |
e73ffd42 BV |
1323 | if (sdi->status != SR_ST_ACTIVE) |
1324 | return SR_ERR_DEV_CLOSED; | |
1325 | ||
0e1357e8 | 1326 | devc = sdi->priv; |
28a35d8a | 1327 | |
ba7dd8bb UH |
1328 | if (configure_channels(sdi) != SR_OK) { |
1329 | sr_err("Failed to configure channels."); | |
014359e3 BV |
1330 | return SR_ERR; |
1331 | } | |
1332 | ||
ea9cfed7 | 1333 | /* If the samplerate has not been set, default to 200 kHz. */ |
0e1357e8 | 1334 | if (devc->cur_firmware == -1) { |
82957b65 UH |
1335 | if ((ret = set_samplerate(sdi, SR_KHZ(200))) != SR_OK) |
1336 | return ret; | |
1337 | } | |
e8397563 | 1338 | |
eec5275e | 1339 | /* Enter trigger programming mode. */ |
0e1357e8 | 1340 | sigma_set_register(WRITE_TRIGGER_SELECT1, 0x20, devc); |
28a35d8a | 1341 | |
eec5275e | 1342 | /* 100 and 200 MHz mode. */ |
0e1357e8 BV |
1343 | if (devc->cur_samplerate >= SR_MHZ(100)) { |
1344 | sigma_set_register(WRITE_TRIGGER_SELECT1, 0x81, devc); | |
57bbf56b | 1345 | |
a42aec7f HE |
1346 | /* Find which pin to trigger on from mask. */ |
1347 | for (triggerpin = 0; triggerpin < 8; ++triggerpin) | |
0e1357e8 | 1348 | if ((devc->trigger.risingmask | devc->trigger.fallingmask) & |
a42aec7f HE |
1349 | (1 << triggerpin)) |
1350 | break; | |
1351 | ||
1352 | /* Set trigger pin and light LED on trigger. */ | |
1353 | triggerselect = (1 << LEDSEL1) | (triggerpin & 0x7); | |
1354 | ||
1355 | /* Default rising edge. */ | |
0e1357e8 | 1356 | if (devc->trigger.fallingmask) |
a42aec7f | 1357 | triggerselect |= 1 << 3; |
57bbf56b | 1358 | |
eec5275e | 1359 | /* All other modes. */ |
0e1357e8 BV |
1360 | } else if (devc->cur_samplerate <= SR_MHZ(50)) { |
1361 | build_basic_trigger(&lut, devc); | |
ee492173 | 1362 | |
0e1357e8 | 1363 | sigma_write_trigger_lut(&lut, devc); |
57bbf56b HE |
1364 | |
1365 | triggerselect = (1 << LEDSEL1) | (1 << LEDSEL0); | |
1366 | } | |
1367 | ||
eec5275e | 1368 | /* Setup trigger in and out pins to default values. */ |
57bbf56b HE |
1369 | memset(&triggerinout_conf, 0, sizeof(struct triggerinout)); |
1370 | triggerinout_conf.trgout_bytrigger = 1; | |
1371 | triggerinout_conf.trgout_enable = 1; | |
1372 | ||
28a35d8a | 1373 | sigma_write_register(WRITE_TRIGGER_OPTION, |
57bbf56b | 1374 | (uint8_t *) &triggerinout_conf, |
0e1357e8 | 1375 | sizeof(struct triggerinout), devc); |
28a35d8a | 1376 | |
eec5275e | 1377 | /* Go back to normal mode. */ |
0e1357e8 | 1378 | sigma_set_register(WRITE_TRIGGER_SELECT1, triggerselect, devc); |
28a35d8a | 1379 | |
edca2c5c | 1380 | /* Set clock select register. */ |
0e1357e8 | 1381 | if (devc->cur_samplerate == SR_MHZ(200)) |
ba7dd8bb | 1382 | /* Enable 4 channels. */ |
0e1357e8 BV |
1383 | sigma_set_register(WRITE_CLOCK_SELECT, 0xf0, devc); |
1384 | else if (devc->cur_samplerate == SR_MHZ(100)) | |
ba7dd8bb | 1385 | /* Enable 8 channels. */ |
0e1357e8 | 1386 | sigma_set_register(WRITE_CLOCK_SELECT, 0x00, devc); |
edca2c5c HE |
1387 | else { |
1388 | /* | |
9ddb2a12 | 1389 | * 50 MHz mode (or fraction thereof). Any fraction down to |
eec5275e | 1390 | * 50 MHz / 256 can be used, but is not supported by sigrok API. |
edca2c5c | 1391 | */ |
0e1357e8 | 1392 | frac = SR_MHZ(50) / devc->cur_samplerate - 1; |
edca2c5c | 1393 | |
9ddb2a12 UH |
1394 | clockselect.async = 0; |
1395 | clockselect.fraction = frac; | |
ba7dd8bb | 1396 | clockselect.disabled_channels = 0; |
edca2c5c HE |
1397 | |
1398 | sigma_write_register(WRITE_CLOCK_SELECT, | |
9ddb2a12 | 1399 | (uint8_t *) &clockselect, |
0e1357e8 | 1400 | sizeof(clockselect), devc); |
edca2c5c HE |
1401 | } |
1402 | ||
fefa1800 | 1403 | /* Setup maximum post trigger time. */ |
99965709 | 1404 | sigma_set_register(WRITE_POST_TRIGGER, |
0e1357e8 | 1405 | (devc->capture_ratio * 255) / 100, devc); |
28a35d8a | 1406 | |
eec5275e | 1407 | /* Start acqusition. */ |
0e1357e8 BV |
1408 | gettimeofday(&devc->start_tv, 0); |
1409 | sigma_set_register(WRITE_MODE, 0x0d, devc); | |
99965709 | 1410 | |
3e9b7f9c | 1411 | devc->cb_data = cb_data; |
28a35d8a | 1412 | |
3c36c403 | 1413 | /* Send header packet to the session bus. */ |
29a27196 | 1414 | std_session_send_df_header(cb_data, LOG_PREFIX); |
f366e86c | 1415 | |
f366e86c | 1416 | /* Add capture source. */ |
3ffb6964 | 1417 | sr_source_add(0, G_IO_IN, 10, receive_data, (void *)sdi); |
f366e86c | 1418 | |
0e1357e8 | 1419 | devc->state.state = SIGMA_CAPTURE; |
6aac7737 | 1420 | |
e46b8fb1 | 1421 | return SR_OK; |
28a35d8a HE |
1422 | } |
1423 | ||
6078d2c9 | 1424 | static int dev_acquisition_stop(struct sr_dev_inst *sdi, void *cb_data) |
28a35d8a | 1425 | { |
0e1357e8 | 1426 | struct dev_context *devc; |
6aac7737 | 1427 | |
3cd3a20b | 1428 | (void)cb_data; |
28a35d8a | 1429 | |
6868626b BV |
1430 | devc = sdi->priv; |
1431 | devc->state.state = SIGMA_IDLE; | |
6aac7737 | 1432 | |
6868626b | 1433 | sr_source_remove(0); |
3010f21c UH |
1434 | |
1435 | return SR_OK; | |
28a35d8a HE |
1436 | } |
1437 | ||
c09f0b57 | 1438 | SR_PRIV struct sr_dev_driver asix_sigma_driver_info = { |
e519ba86 | 1439 | .name = "asix-sigma", |
6352d030 | 1440 | .longname = "ASIX SIGMA/SIGMA2", |
e519ba86 | 1441 | .api_version = 1, |
6078d2c9 UH |
1442 | .init = init, |
1443 | .cleanup = cleanup, | |
1444 | .scan = scan, | |
1445 | .dev_list = dev_list, | |
3b412e3a | 1446 | .dev_clear = dev_clear, |
035a1078 BV |
1447 | .config_get = config_get, |
1448 | .config_set = config_set, | |
a1c743fc | 1449 | .config_list = config_list, |
6078d2c9 UH |
1450 | .dev_open = dev_open, |
1451 | .dev_close = dev_close, | |
1452 | .dev_acquisition_start = dev_acquisition_start, | |
1453 | .dev_acquisition_stop = dev_acquisition_stop, | |
0e1357e8 | 1454 | .priv = NULL, |
28a35d8a | 1455 | }; |