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Commit | Line | Data |
---|---|---|
28a35d8a | 1 | /* |
50985c20 | 2 | * This file is part of the libsigrok project. |
28a35d8a | 3 | * |
868501fa | 4 | * Copyright (C) 2010-2012 Håvard Espeland <gus@ping.uio.no>, |
911f1834 UH |
5 | * Copyright (C) 2010 Martin Stensgård <mastensg@ping.uio.no> |
6 | * Copyright (C) 2010 Carl Henrik Lunde <chlunde@ping.uio.no> | |
28a35d8a HE |
7 | * |
8 | * This program is free software: you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation, either version 3 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
20 | */ | |
21 | ||
911f1834 | 22 | /* |
6352d030 | 23 | * ASIX SIGMA/SIGMA2 logic analyzer driver |
911f1834 UH |
24 | */ |
25 | ||
3bbd9849 UH |
26 | #include <glib.h> |
27 | #include <glib/gstdio.h> | |
28a35d8a HE |
28 | #include <ftdi.h> |
29 | #include <string.h> | |
45c59c8b BV |
30 | #include "libsigrok.h" |
31 | #include "libsigrok-internal.h" | |
28a35d8a HE |
32 | #include "asix-sigma.h" |
33 | ||
34 | #define USB_VENDOR 0xa600 | |
35 | #define USB_PRODUCT 0xa000 | |
36 | #define USB_DESCRIPTION "ASIX SIGMA" | |
37 | #define USB_VENDOR_NAME "ASIX" | |
38 | #define USB_MODEL_NAME "SIGMA" | |
c50277a6 | 39 | #define TRIGGER_TYPE "rf10" |
3f239f08 | 40 | #define NUM_CHANNELS 16 |
28a35d8a | 41 | |
ed300b9f | 42 | SR_PRIV struct sr_dev_driver asix_sigma_driver_info; |
a873c594 | 43 | static struct sr_dev_driver *di = &asix_sigma_driver_info; |
6078d2c9 | 44 | static int dev_acquisition_stop(struct sr_dev_inst *sdi, void *cb_data); |
28a35d8a | 45 | |
2c9c0df8 | 46 | static const uint64_t samplerates[] = { |
59df0c77 UH |
47 | SR_KHZ(200), |
48 | SR_KHZ(250), | |
49 | SR_KHZ(500), | |
50 | SR_MHZ(1), | |
51 | SR_MHZ(5), | |
52 | SR_MHZ(10), | |
53 | SR_MHZ(25), | |
54 | SR_MHZ(50), | |
55 | SR_MHZ(100), | |
56 | SR_MHZ(200), | |
28a35d8a HE |
57 | }; |
58 | ||
d261dbbf | 59 | /* |
ba7dd8bb | 60 | * Channel numbers seem to go from 1-16, according to this image: |
d261dbbf UH |
61 | * http://tools.asix.net/img/sigma_sigmacab_pins_720.jpg |
62 | * (the cable has two additional GND pins, and a TI and TO pin) | |
63 | */ | |
3f239f08 | 64 | static const char *channel_names[NUM_CHANNELS + 1] = { |
78693401 UH |
65 | "1", "2", "3", "4", "5", "6", "7", "8", |
66 | "9", "10", "11", "12", "13", "14", "15", "16", | |
464d12c7 KS |
67 | NULL, |
68 | }; | |
69 | ||
2c9c0df8 | 70 | static const int32_t hwcaps[] = { |
1953564a BV |
71 | SR_CONF_LOGIC_ANALYZER, |
72 | SR_CONF_SAMPLERATE, | |
38d32464 | 73 | SR_CONF_TRIGGER_TYPE, |
1953564a | 74 | SR_CONF_CAPTURE_RATIO, |
1953564a | 75 | SR_CONF_LIMIT_MSEC, |
6868626b | 76 | SR_CONF_LIMIT_SAMPLES, |
28a35d8a HE |
77 | }; |
78 | ||
fefa1800 UH |
79 | /* Force the FPGA to reboot. */ |
80 | static uint8_t suicide[] = { | |
81 | 0x84, 0x84, 0x88, 0x84, 0x88, 0x84, 0x88, 0x84, | |
82 | }; | |
83 | ||
84 | /* Prepare to upload firmware (FPGA specific). */ | |
6078d2c9 | 85 | static uint8_t init_array[] = { |
fefa1800 UH |
86 | 0x03, 0x03, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, |
87 | }; | |
88 | ||
89 | /* Initialize the logic analyzer mode. */ | |
90 | static uint8_t logic_mode_start[] = { | |
91 | 0x00, 0x40, 0x0f, 0x25, 0x35, 0x40, | |
92 | 0x2a, 0x3a, 0x40, 0x03, 0x20, 0x38, | |
93 | }; | |
94 | ||
eec5275e | 95 | static const char *firmware_files[] = { |
a8116d76 HE |
96 | "asix-sigma-50.fw", /* 50 MHz, supports 8 bit fractions */ |
97 | "asix-sigma-100.fw", /* 100 MHz */ | |
98 | "asix-sigma-200.fw", /* 200 MHz */ | |
ed09fd07 | 99 | "asix-sigma-50sync.fw", /* Synchronous clock from pin */ |
a8116d76 | 100 | "asix-sigma-phasor.fw", /* Frequency counter */ |
f6564c8d HE |
101 | }; |
102 | ||
0e1357e8 | 103 | static int sigma_read(void *buf, size_t size, struct dev_context *devc) |
28a35d8a HE |
104 | { |
105 | int ret; | |
fefa1800 | 106 | |
0e1357e8 | 107 | ret = ftdi_read_data(&devc->ftdic, (unsigned char *)buf, size); |
28a35d8a | 108 | if (ret < 0) { |
47f4f073 | 109 | sr_err("ftdi_read_data failed: %s", |
0e1357e8 | 110 | ftdi_get_error_string(&devc->ftdic)); |
28a35d8a HE |
111 | } |
112 | ||
113 | return ret; | |
114 | } | |
115 | ||
0e1357e8 | 116 | static int sigma_write(void *buf, size_t size, struct dev_context *devc) |
28a35d8a HE |
117 | { |
118 | int ret; | |
fefa1800 | 119 | |
0e1357e8 | 120 | ret = ftdi_write_data(&devc->ftdic, (unsigned char *)buf, size); |
28a35d8a | 121 | if (ret < 0) { |
47f4f073 | 122 | sr_err("ftdi_write_data failed: %s", |
0e1357e8 | 123 | ftdi_get_error_string(&devc->ftdic)); |
fefa1800 | 124 | } else if ((size_t) ret != size) { |
47f4f073 | 125 | sr_err("ftdi_write_data did not complete write."); |
28a35d8a HE |
126 | } |
127 | ||
128 | return ret; | |
129 | } | |
130 | ||
99965709 | 131 | static int sigma_write_register(uint8_t reg, uint8_t *data, size_t len, |
0e1357e8 | 132 | struct dev_context *devc) |
28a35d8a HE |
133 | { |
134 | size_t i; | |
135 | uint8_t buf[len + 2]; | |
136 | int idx = 0; | |
137 | ||
138 | buf[idx++] = REG_ADDR_LOW | (reg & 0xf); | |
139 | buf[idx++] = REG_ADDR_HIGH | (reg >> 4); | |
140 | ||
fefa1800 | 141 | for (i = 0; i < len; ++i) { |
28a35d8a HE |
142 | buf[idx++] = REG_DATA_LOW | (data[i] & 0xf); |
143 | buf[idx++] = REG_DATA_HIGH_WRITE | (data[i] >> 4); | |
144 | } | |
145 | ||
0e1357e8 | 146 | return sigma_write(buf, idx, devc); |
28a35d8a HE |
147 | } |
148 | ||
0e1357e8 | 149 | static int sigma_set_register(uint8_t reg, uint8_t value, struct dev_context *devc) |
28a35d8a | 150 | { |
0e1357e8 | 151 | return sigma_write_register(reg, &value, 1, devc); |
28a35d8a HE |
152 | } |
153 | ||
99965709 | 154 | static int sigma_read_register(uint8_t reg, uint8_t *data, size_t len, |
0e1357e8 | 155 | struct dev_context *devc) |
28a35d8a HE |
156 | { |
157 | uint8_t buf[3]; | |
fefa1800 | 158 | |
28a35d8a HE |
159 | buf[0] = REG_ADDR_LOW | (reg & 0xf); |
160 | buf[1] = REG_ADDR_HIGH | (reg >> 4); | |
28a35d8a HE |
161 | buf[2] = REG_READ_ADDR; |
162 | ||
0e1357e8 | 163 | sigma_write(buf, sizeof(buf), devc); |
28a35d8a | 164 | |
0e1357e8 | 165 | return sigma_read(data, len, devc); |
28a35d8a HE |
166 | } |
167 | ||
0e1357e8 | 168 | static uint8_t sigma_get_register(uint8_t reg, struct dev_context *devc) |
28a35d8a HE |
169 | { |
170 | uint8_t value; | |
fefa1800 | 171 | |
0e1357e8 | 172 | if (1 != sigma_read_register(reg, &value, 1, devc)) { |
47f4f073 | 173 | sr_err("sigma_get_register: 1 byte expected"); |
28a35d8a HE |
174 | return 0; |
175 | } | |
176 | ||
177 | return value; | |
178 | } | |
179 | ||
99965709 | 180 | static int sigma_read_pos(uint32_t *stoppos, uint32_t *triggerpos, |
0e1357e8 | 181 | struct dev_context *devc) |
28a35d8a HE |
182 | { |
183 | uint8_t buf[] = { | |
184 | REG_ADDR_LOW | READ_TRIGGER_POS_LOW, | |
185 | ||
186 | REG_READ_ADDR | NEXT_REG, | |
187 | REG_READ_ADDR | NEXT_REG, | |
188 | REG_READ_ADDR | NEXT_REG, | |
189 | REG_READ_ADDR | NEXT_REG, | |
190 | REG_READ_ADDR | NEXT_REG, | |
191 | REG_READ_ADDR | NEXT_REG, | |
192 | }; | |
28a35d8a HE |
193 | uint8_t result[6]; |
194 | ||
0e1357e8 | 195 | sigma_write(buf, sizeof(buf), devc); |
28a35d8a | 196 | |
0e1357e8 | 197 | sigma_read(result, sizeof(result), devc); |
28a35d8a HE |
198 | |
199 | *triggerpos = result[0] | (result[1] << 8) | (result[2] << 16); | |
200 | *stoppos = result[3] | (result[4] << 8) | (result[5] << 16); | |
201 | ||
57bbf56b HE |
202 | /* Not really sure why this must be done, but according to spec. */ |
203 | if ((--*stoppos & 0x1ff) == 0x1ff) | |
204 | stoppos -= 64; | |
205 | ||
206 | if ((*--triggerpos & 0x1ff) == 0x1ff) | |
207 | triggerpos -= 64; | |
208 | ||
28a35d8a HE |
209 | return 1; |
210 | } | |
211 | ||
99965709 | 212 | static int sigma_read_dram(uint16_t startchunk, size_t numchunks, |
0e1357e8 | 213 | uint8_t *data, struct dev_context *devc) |
28a35d8a HE |
214 | { |
215 | size_t i; | |
216 | uint8_t buf[4096]; | |
217 | int idx = 0; | |
218 | ||
fefa1800 | 219 | /* Send the startchunk. Index start with 1. */ |
28a35d8a HE |
220 | buf[0] = startchunk >> 8; |
221 | buf[1] = startchunk & 0xff; | |
0e1357e8 | 222 | sigma_write_register(WRITE_MEMROW, buf, 2, devc); |
28a35d8a | 223 | |
fefa1800 | 224 | /* Read the DRAM. */ |
28a35d8a HE |
225 | buf[idx++] = REG_DRAM_BLOCK; |
226 | buf[idx++] = REG_DRAM_WAIT_ACK; | |
227 | ||
228 | for (i = 0; i < numchunks; ++i) { | |
fefa1800 UH |
229 | /* Alternate bit to copy from DRAM to cache. */ |
230 | if (i != (numchunks - 1)) | |
231 | buf[idx++] = REG_DRAM_BLOCK | (((i + 1) % 2) << 4); | |
28a35d8a HE |
232 | |
233 | buf[idx++] = REG_DRAM_BLOCK_DATA | ((i % 2) << 4); | |
234 | ||
fefa1800 | 235 | if (i != (numchunks - 1)) |
28a35d8a HE |
236 | buf[idx++] = REG_DRAM_WAIT_ACK; |
237 | } | |
238 | ||
0e1357e8 | 239 | sigma_write(buf, idx, devc); |
28a35d8a | 240 | |
0e1357e8 | 241 | return sigma_read(data, numchunks * CHUNK_SIZE, devc); |
28a35d8a HE |
242 | } |
243 | ||
4ae1f451 | 244 | /* Upload trigger look-up tables to Sigma. */ |
0e1357e8 | 245 | static int sigma_write_trigger_lut(struct triggerlut *lut, struct dev_context *devc) |
ee492173 HE |
246 | { |
247 | int i; | |
248 | uint8_t tmp[2]; | |
249 | uint16_t bit; | |
250 | ||
251 | /* Transpose the table and send to Sigma. */ | |
252 | for (i = 0; i < 16; ++i) { | |
253 | bit = 1 << i; | |
254 | ||
255 | tmp[0] = tmp[1] = 0; | |
256 | ||
257 | if (lut->m2d[0] & bit) | |
258 | tmp[0] |= 0x01; | |
259 | if (lut->m2d[1] & bit) | |
260 | tmp[0] |= 0x02; | |
261 | if (lut->m2d[2] & bit) | |
262 | tmp[0] |= 0x04; | |
263 | if (lut->m2d[3] & bit) | |
264 | tmp[0] |= 0x08; | |
265 | ||
266 | if (lut->m3 & bit) | |
267 | tmp[0] |= 0x10; | |
268 | if (lut->m3s & bit) | |
269 | tmp[0] |= 0x20; | |
270 | if (lut->m4 & bit) | |
271 | tmp[0] |= 0x40; | |
272 | ||
273 | if (lut->m0d[0] & bit) | |
274 | tmp[1] |= 0x01; | |
275 | if (lut->m0d[1] & bit) | |
276 | tmp[1] |= 0x02; | |
277 | if (lut->m0d[2] & bit) | |
278 | tmp[1] |= 0x04; | |
279 | if (lut->m0d[3] & bit) | |
280 | tmp[1] |= 0x08; | |
281 | ||
282 | if (lut->m1d[0] & bit) | |
283 | tmp[1] |= 0x10; | |
284 | if (lut->m1d[1] & bit) | |
285 | tmp[1] |= 0x20; | |
286 | if (lut->m1d[2] & bit) | |
287 | tmp[1] |= 0x40; | |
288 | if (lut->m1d[3] & bit) | |
289 | tmp[1] |= 0x80; | |
290 | ||
99965709 | 291 | sigma_write_register(WRITE_TRIGGER_SELECT0, tmp, sizeof(tmp), |
0e1357e8 BV |
292 | devc); |
293 | sigma_set_register(WRITE_TRIGGER_SELECT1, 0x30 | i, devc); | |
ee492173 HE |
294 | } |
295 | ||
296 | /* Send the parameters */ | |
297 | sigma_write_register(WRITE_TRIGGER_SELECT0, (uint8_t *) &lut->params, | |
0e1357e8 | 298 | sizeof(lut->params), devc); |
ee492173 | 299 | |
e46b8fb1 | 300 | return SR_OK; |
ee492173 HE |
301 | } |
302 | ||
fefa1800 | 303 | /* Generate the bitbang stream for programming the FPGA. */ |
28a35d8a | 304 | static int bin2bitbang(const char *filename, |
fefa1800 | 305 | unsigned char **buf, size_t *buf_size) |
28a35d8a | 306 | { |
fefa1800 | 307 | FILE *f; |
e3fff420 | 308 | unsigned long file_size; |
28a35d8a HE |
309 | unsigned long offset = 0; |
310 | unsigned char *p; | |
e3fff420 HE |
311 | uint8_t *firmware; |
312 | unsigned long fwsize = 0; | |
28a35d8a HE |
313 | const int buffer_size = 65536; |
314 | size_t i; | |
e3fff420 | 315 | int c, bit, v; |
fefa1800 | 316 | uint32_t imm = 0x3f6df2ab; |
28a35d8a | 317 | |
868d8cef | 318 | f = g_fopen(filename, "rb"); |
28a35d8a | 319 | if (!f) { |
47f4f073 | 320 | sr_err("g_fopen(\"%s\", \"rb\")", filename); |
b53738ba | 321 | return SR_ERR; |
28a35d8a HE |
322 | } |
323 | ||
324 | if (-1 == fseek(f, 0, SEEK_END)) { | |
47f4f073 | 325 | sr_err("fseek on %s failed", filename); |
28a35d8a | 326 | fclose(f); |
b53738ba | 327 | return SR_ERR; |
28a35d8a HE |
328 | } |
329 | ||
330 | file_size = ftell(f); | |
331 | ||
332 | fseek(f, 0, SEEK_SET); | |
333 | ||
b53738ba | 334 | if (!(firmware = g_try_malloc(buffer_size))) { |
47f4f073 | 335 | sr_err("%s: firmware malloc failed", __func__); |
12ad53f5 | 336 | fclose(f); |
b53738ba | 337 | return SR_ERR_MALLOC; |
28a35d8a HE |
338 | } |
339 | ||
28a35d8a HE |
340 | while ((c = getc(f)) != EOF) { |
341 | imm = (imm + 0xa853753) % 177 + (imm * 0x8034052); | |
e3fff420 | 342 | firmware[fwsize++] = c ^ imm; |
28a35d8a HE |
343 | } |
344 | fclose(f); | |
345 | ||
e3fff420 | 346 | if(fwsize != file_size) { |
47f4f073 | 347 | sr_err("%s: Error reading firmware", filename); |
e3fff420 HE |
348 | fclose(f); |
349 | g_free(firmware); | |
350 | return SR_ERR; | |
28a35d8a HE |
351 | } |
352 | ||
28a35d8a HE |
353 | *buf_size = fwsize * 2 * 8; |
354 | ||
b53738ba | 355 | *buf = p = (unsigned char *)g_try_malloc(*buf_size); |
28a35d8a | 356 | if (!p) { |
47f4f073 | 357 | sr_err("%s: buf/p malloc failed", __func__); |
12ad53f5 | 358 | g_free(firmware); |
b53738ba | 359 | return SR_ERR_MALLOC; |
28a35d8a HE |
360 | } |
361 | ||
362 | for (i = 0; i < fwsize; ++i) { | |
28a35d8a | 363 | for (bit = 7; bit >= 0; --bit) { |
fefa1800 | 364 | v = firmware[i] & 1 << bit ? 0x40 : 0x00; |
28a35d8a HE |
365 | p[offset++] = v | 0x01; |
366 | p[offset++] = v; | |
367 | } | |
368 | } | |
369 | ||
370 | g_free(firmware); | |
371 | ||
372 | if (offset != *buf_size) { | |
373 | g_free(*buf); | |
47f4f073 | 374 | sr_err("Error reading firmware %s " |
0aeb0ccd | 375 | "offset=%ld, file_size=%ld, buf_size=%zd.", |
133a37bf | 376 | filename, offset, file_size, *buf_size); |
28a35d8a | 377 | |
b53738ba | 378 | return SR_ERR; |
28a35d8a HE |
379 | } |
380 | ||
b53738ba | 381 | return SR_OK; |
28a35d8a HE |
382 | } |
383 | ||
3678cf73 | 384 | static void clear_helper(void *priv) |
0448d110 | 385 | { |
0e1357e8 | 386 | struct dev_context *devc; |
ce4d26dd | 387 | |
3678cf73 | 388 | devc = priv; |
0e1357e8 | 389 | |
3678cf73 UH |
390 | ftdi_deinit(&devc->ftdic); |
391 | } | |
0448d110 | 392 | |
3b412e3a | 393 | static int dev_clear(void) |
3678cf73 UH |
394 | { |
395 | return std_dev_clear(di, clear_helper); | |
0448d110 BV |
396 | } |
397 | ||
6078d2c9 | 398 | static int init(struct sr_context *sr_ctx) |
61136ea6 | 399 | { |
f6beaac5 | 400 | return std_init(sr_ctx, di, LOG_PREFIX); |
61136ea6 BV |
401 | } |
402 | ||
6078d2c9 | 403 | static GSList *scan(GSList *options) |
28a35d8a | 404 | { |
d68e2d1a | 405 | struct sr_dev_inst *sdi; |
ba7dd8bb | 406 | struct sr_channel *ch; |
0e1357e8 BV |
407 | struct drv_context *drvc; |
408 | struct dev_context *devc; | |
0448d110 | 409 | GSList *devices; |
e3fff420 HE |
410 | struct ftdi_device_list *devlist; |
411 | char serial_txt[10]; | |
412 | uint32_t serial; | |
87ca93c5 | 413 | int ret, i; |
28a35d8a | 414 | |
0448d110 | 415 | (void)options; |
64d33dc2 | 416 | |
a873c594 | 417 | drvc = di->priv; |
4b97c74e | 418 | |
0448d110 | 419 | devices = NULL; |
4b97c74e | 420 | |
0e1357e8 | 421 | if (!(devc = g_try_malloc(sizeof(struct dev_context)))) { |
47f4f073 | 422 | sr_err("%s: devc malloc failed", __func__); |
0448d110 | 423 | return NULL; |
b53738ba | 424 | } |
99965709 | 425 | |
0e1357e8 | 426 | ftdi_init(&devc->ftdic); |
28a35d8a | 427 | |
fefa1800 | 428 | /* Look for SIGMAs. */ |
e3fff420 | 429 | |
0e1357e8 | 430 | if ((ret = ftdi_usb_find_all(&devc->ftdic, &devlist, |
eec944c5 BV |
431 | USB_VENDOR, USB_PRODUCT)) <= 0) { |
432 | if (ret < 0) | |
433 | sr_err("ftdi_usb_find_all(): %d", ret); | |
99965709 | 434 | goto free; |
eec944c5 | 435 | } |
99965709 | 436 | |
e3fff420 | 437 | /* Make sure it's a version 1 or 2 SIGMA. */ |
0e1357e8 | 438 | ftdi_usb_get_strings(&devc->ftdic, devlist->dev, NULL, 0, NULL, 0, |
6352d030 | 439 | serial_txt, sizeof(serial_txt)); |
e3fff420 HE |
440 | sscanf(serial_txt, "%x", &serial); |
441 | ||
6352d030 | 442 | if (serial < 0xa6010000 || serial > 0xa602ffff) { |
47f4f073 UH |
443 | sr_err("Only SIGMA and SIGMA2 are supported " |
444 | "in this version of libsigrok."); | |
e3fff420 HE |
445 | goto free; |
446 | } | |
447 | ||
448 | sr_info("Found ASIX SIGMA - Serial: %s", serial_txt); | |
449 | ||
0e1357e8 BV |
450 | devc->cur_samplerate = 0; |
451 | devc->period_ps = 0; | |
452 | devc->limit_msec = 0; | |
453 | devc->cur_firmware = -1; | |
ba7dd8bb | 454 | devc->num_channels = 0; |
0e1357e8 BV |
455 | devc->samples_per_event = 0; |
456 | devc->capture_ratio = 50; | |
457 | devc->use_triggers = 0; | |
28a35d8a | 458 | |
fefa1800 | 459 | /* Register SIGMA device. */ |
d68e2d1a | 460 | if (!(sdi = sr_dev_inst_new(0, SR_ST_INITIALIZING, USB_VENDOR_NAME, |
55f98c65 | 461 | USB_MODEL_NAME, NULL))) { |
47f4f073 | 462 | sr_err("%s: sdi was NULL", __func__); |
99965709 | 463 | goto free; |
d68e2d1a | 464 | } |
a873c594 | 465 | sdi->driver = di; |
87ca93c5 | 466 | |
ba7dd8bb | 467 | for (i = 0; channel_names[i]; i++) { |
3f239f08 | 468 | if (!(ch = sr_channel_new(i, SR_CHANNEL_LOGIC, TRUE, |
ba7dd8bb | 469 | channel_names[i]))) |
87ca93c5 | 470 | return NULL; |
ba7dd8bb | 471 | sdi->channels = g_slist_append(sdi->channels, ch); |
87ca93c5 BV |
472 | } |
473 | ||
0448d110 | 474 | devices = g_slist_append(devices, sdi); |
0e1357e8 BV |
475 | drvc->instances = g_slist_append(drvc->instances, sdi); |
476 | sdi->priv = devc; | |
28a35d8a | 477 | |
fefa1800 | 478 | /* We will open the device again when we need it. */ |
e3fff420 | 479 | ftdi_list_free(&devlist); |
28a35d8a | 480 | |
0448d110 | 481 | return devices; |
ea9cfed7 | 482 | |
99965709 | 483 | free: |
0e1357e8 BV |
484 | ftdi_deinit(&devc->ftdic); |
485 | g_free(devc); | |
0448d110 | 486 | return NULL; |
28a35d8a HE |
487 | } |
488 | ||
6078d2c9 | 489 | static GSList *dev_list(void) |
811deee4 | 490 | { |
0e94d524 | 491 | return ((struct drv_context *)(di->priv))->instances; |
811deee4 BV |
492 | } |
493 | ||
0e1357e8 | 494 | static int upload_firmware(int firmware_idx, struct dev_context *devc) |
28a35d8a HE |
495 | { |
496 | int ret; | |
497 | unsigned char *buf; | |
498 | unsigned char pins; | |
499 | size_t buf_size; | |
28a35d8a | 500 | unsigned char result[32]; |
e8397563 | 501 | char firmware_path[128]; |
28a35d8a | 502 | |
fefa1800 | 503 | /* Make sure it's an ASIX SIGMA. */ |
0e1357e8 | 504 | if ((ret = ftdi_usb_open_desc(&devc->ftdic, |
28a35d8a | 505 | USB_VENDOR, USB_PRODUCT, USB_DESCRIPTION, NULL)) < 0) { |
47f4f073 | 506 | sr_err("ftdi_usb_open failed: %s", |
0e1357e8 | 507 | ftdi_get_error_string(&devc->ftdic)); |
28a35d8a HE |
508 | return 0; |
509 | } | |
510 | ||
0e1357e8 | 511 | if ((ret = ftdi_set_bitmode(&devc->ftdic, 0xdf, BITMODE_BITBANG)) < 0) { |
47f4f073 | 512 | sr_err("ftdi_set_bitmode failed: %s", |
0e1357e8 | 513 | ftdi_get_error_string(&devc->ftdic)); |
28a35d8a HE |
514 | return 0; |
515 | } | |
516 | ||
fefa1800 | 517 | /* Four times the speed of sigmalogan - Works well. */ |
0e1357e8 | 518 | if ((ret = ftdi_set_baudrate(&devc->ftdic, 750000)) < 0) { |
47f4f073 | 519 | sr_err("ftdi_set_baudrate failed: %s", |
0e1357e8 | 520 | ftdi_get_error_string(&devc->ftdic)); |
28a35d8a HE |
521 | return 0; |
522 | } | |
523 | ||
fefa1800 | 524 | /* Force the FPGA to reboot. */ |
0e1357e8 BV |
525 | sigma_write(suicide, sizeof(suicide), devc); |
526 | sigma_write(suicide, sizeof(suicide), devc); | |
527 | sigma_write(suicide, sizeof(suicide), devc); | |
528 | sigma_write(suicide, sizeof(suicide), devc); | |
28a35d8a | 529 | |
fefa1800 | 530 | /* Prepare to upload firmware (FPGA specific). */ |
6078d2c9 | 531 | sigma_write(init_array, sizeof(init_array), devc); |
28a35d8a | 532 | |
0e1357e8 | 533 | ftdi_usb_purge_buffers(&devc->ftdic); |
28a35d8a | 534 | |
fefa1800 | 535 | /* Wait until the FPGA asserts INIT_B. */ |
28a35d8a | 536 | while (1) { |
0e1357e8 | 537 | ret = sigma_read(result, 1, devc); |
28a35d8a HE |
538 | if (result[0] & 0x20) |
539 | break; | |
540 | } | |
541 | ||
9ddb2a12 | 542 | /* Prepare firmware. */ |
e8397563 | 543 | snprintf(firmware_path, sizeof(firmware_path), "%s/%s", FIRMWARE_DIR, |
f6564c8d HE |
544 | firmware_files[firmware_idx]); |
545 | ||
b53738ba | 546 | if ((ret = bin2bitbang(firmware_path, &buf, &buf_size)) != SR_OK) { |
47f4f073 | 547 | sr_err("An error occured while reading the firmware: %s", |
133a37bf | 548 | firmware_path); |
b53738ba | 549 | return ret; |
28a35d8a HE |
550 | } |
551 | ||
fefa1800 | 552 | /* Upload firmare. */ |
47f4f073 | 553 | sr_info("Uploading firmware file '%s'.", firmware_files[firmware_idx]); |
0e1357e8 | 554 | sigma_write(buf, buf_size, devc); |
28a35d8a HE |
555 | |
556 | g_free(buf); | |
557 | ||
0e1357e8 | 558 | if ((ret = ftdi_set_bitmode(&devc->ftdic, 0x00, BITMODE_RESET)) < 0) { |
47f4f073 | 559 | sr_err("ftdi_set_bitmode failed: %s", |
0e1357e8 | 560 | ftdi_get_error_string(&devc->ftdic)); |
e46b8fb1 | 561 | return SR_ERR; |
28a35d8a HE |
562 | } |
563 | ||
0e1357e8 | 564 | ftdi_usb_purge_buffers(&devc->ftdic); |
28a35d8a | 565 | |
fefa1800 | 566 | /* Discard garbage. */ |
0e1357e8 | 567 | while (1 == sigma_read(&pins, 1, devc)) |
28a35d8a HE |
568 | ; |
569 | ||
fefa1800 | 570 | /* Initialize the logic analyzer mode. */ |
0e1357e8 | 571 | sigma_write(logic_mode_start, sizeof(logic_mode_start), devc); |
28a35d8a | 572 | |
fefa1800 | 573 | /* Expect a 3 byte reply. */ |
0e1357e8 | 574 | ret = sigma_read(result, 3, devc); |
28a35d8a HE |
575 | if (ret != 3 || |
576 | result[0] != 0xa6 || result[1] != 0x55 || result[2] != 0xaa) { | |
47f4f073 | 577 | sr_err("Configuration failed. Invalid reply received."); |
e46b8fb1 | 578 | return SR_ERR; |
28a35d8a HE |
579 | } |
580 | ||
0e1357e8 | 581 | devc->cur_firmware = firmware_idx; |
f6564c8d | 582 | |
47f4f073 | 583 | sr_info("Firmware uploaded."); |
e3fff420 | 584 | |
e46b8fb1 | 585 | return SR_OK; |
f6564c8d HE |
586 | } |
587 | ||
6078d2c9 | 588 | static int dev_open(struct sr_dev_inst *sdi) |
f6564c8d | 589 | { |
0e1357e8 | 590 | struct dev_context *devc; |
f6564c8d HE |
591 | int ret; |
592 | ||
0e1357e8 | 593 | devc = sdi->priv; |
99965709 | 594 | |
9ddb2a12 | 595 | /* Make sure it's an ASIX SIGMA. */ |
0e1357e8 | 596 | if ((ret = ftdi_usb_open_desc(&devc->ftdic, |
f6564c8d HE |
597 | USB_VENDOR, USB_PRODUCT, USB_DESCRIPTION, NULL)) < 0) { |
598 | ||
47f4f073 | 599 | sr_err("ftdi_usb_open failed: %s", |
0e1357e8 | 600 | ftdi_get_error_string(&devc->ftdic)); |
f6564c8d HE |
601 | |
602 | return 0; | |
603 | } | |
28a35d8a | 604 | |
5a2326a7 | 605 | sdi->status = SR_ST_ACTIVE; |
28a35d8a | 606 | |
e46b8fb1 | 607 | return SR_OK; |
f6564c8d HE |
608 | } |
609 | ||
6f4b1868 | 610 | static int set_samplerate(const struct sr_dev_inst *sdi, uint64_t samplerate) |
f6564c8d | 611 | { |
2c9c0df8 BV |
612 | struct dev_context *devc; |
613 | unsigned int i; | |
614 | int ret; | |
f6564c8d | 615 | |
2c9c0df8 | 616 | devc = sdi->priv; |
f4abaa9f UH |
617 | ret = SR_OK; |
618 | ||
2c9c0df8 BV |
619 | for (i = 0; i < ARRAY_SIZE(samplerates); i++) { |
620 | if (samplerates[i] == samplerate) | |
f6564c8d HE |
621 | break; |
622 | } | |
2c9c0df8 | 623 | if (samplerates[i] == 0) |
e46b8fb1 | 624 | return SR_ERR_SAMPLERATE; |
f6564c8d | 625 | |
59df0c77 | 626 | if (samplerate <= SR_MHZ(50)) { |
0e1357e8 | 627 | ret = upload_firmware(0, devc); |
ba7dd8bb | 628 | devc->num_channels = 16; |
e8397563 | 629 | } |
59df0c77 | 630 | if (samplerate == SR_MHZ(100)) { |
0e1357e8 | 631 | ret = upload_firmware(1, devc); |
ba7dd8bb | 632 | devc->num_channels = 8; |
f78898e9 | 633 | } |
59df0c77 | 634 | else if (samplerate == SR_MHZ(200)) { |
0e1357e8 | 635 | ret = upload_firmware(2, devc); |
ba7dd8bb | 636 | devc->num_channels = 4; |
f78898e9 | 637 | } |
f6564c8d | 638 | |
0e1357e8 | 639 | devc->cur_samplerate = samplerate; |
5edc02c7 | 640 | devc->period_ps = 1000000000000ULL / samplerate; |
ba7dd8bb | 641 | devc->samples_per_event = 16 / devc->num_channels; |
0e1357e8 | 642 | devc->state.state = SIGMA_IDLE; |
f6564c8d | 643 | |
e8397563 | 644 | return ret; |
28a35d8a HE |
645 | } |
646 | ||
c53d793f HE |
647 | /* |
648 | * In 100 and 200 MHz mode, only a single pin rising/falling can be | |
649 | * set as trigger. In other modes, two rising/falling triggers can be set, | |
ba7dd8bb | 650 | * in addition to value/mask trigger for any number of channels. |
c53d793f HE |
651 | * |
652 | * The Sigma supports complex triggers using boolean expressions, but this | |
653 | * has not been implemented yet. | |
654 | */ | |
ba7dd8bb | 655 | static int configure_channels(const struct sr_dev_inst *sdi) |
57bbf56b | 656 | { |
0e1357e8 | 657 | struct dev_context *devc = sdi->priv; |
ba7dd8bb | 658 | const struct sr_channel *ch; |
1b79df2f | 659 | const GSList *l; |
57bbf56b | 660 | int trigger_set = 0; |
ba7dd8bb | 661 | int channelbit; |
57bbf56b | 662 | |
0e1357e8 | 663 | memset(&devc->trigger, 0, sizeof(struct sigma_trigger)); |
eec5275e | 664 | |
ba7dd8bb UH |
665 | for (l = sdi->channels; l; l = l->next) { |
666 | ch = (struct sr_channel *)l->data; | |
667 | channelbit = 1 << (ch->index); | |
57bbf56b | 668 | |
ba7dd8bb | 669 | if (!ch->enabled || !ch->trigger) |
57bbf56b HE |
670 | continue; |
671 | ||
0e1357e8 | 672 | if (devc->cur_samplerate >= SR_MHZ(100)) { |
c53d793f | 673 | /* Fast trigger support. */ |
ee492173 | 674 | if (trigger_set) { |
47f4f073 UH |
675 | sr_err("Only a single pin trigger in 100 and " |
676 | "200MHz mode is supported."); | |
e46b8fb1 | 677 | return SR_ERR; |
ee492173 | 678 | } |
ba7dd8bb UH |
679 | if (ch->trigger[0] == 'f') |
680 | devc->trigger.fallingmask |= channelbit; | |
681 | else if (ch->trigger[0] == 'r') | |
682 | devc->trigger.risingmask |= channelbit; | |
ee492173 | 683 | else { |
47f4f073 UH |
684 | sr_err("Only rising/falling trigger in 100 " |
685 | "and 200MHz mode is supported."); | |
e46b8fb1 | 686 | return SR_ERR; |
ee492173 | 687 | } |
57bbf56b | 688 | |
c53d793f | 689 | ++trigger_set; |
ee492173 | 690 | } else { |
c53d793f | 691 | /* Simple trigger support (event). */ |
ba7dd8bb UH |
692 | if (ch->trigger[0] == '1') { |
693 | devc->trigger.simplevalue |= channelbit; | |
694 | devc->trigger.simplemask |= channelbit; | |
c53d793f | 695 | } |
ba7dd8bb UH |
696 | else if (ch->trigger[0] == '0') { |
697 | devc->trigger.simplevalue &= ~channelbit; | |
698 | devc->trigger.simplemask |= channelbit; | |
c53d793f | 699 | } |
ba7dd8bb UH |
700 | else if (ch->trigger[0] == 'f') { |
701 | devc->trigger.fallingmask |= channelbit; | |
c53d793f HE |
702 | ++trigger_set; |
703 | } | |
ba7dd8bb UH |
704 | else if (ch->trigger[0] == 'r') { |
705 | devc->trigger.risingmask |= channelbit; | |
c53d793f HE |
706 | ++trigger_set; |
707 | } | |
ee492173 | 708 | |
ea9cfed7 UH |
709 | /* |
710 | * Actually, Sigma supports 2 rising/falling triggers, | |
711 | * but they are ORed and the current trigger syntax | |
712 | * does not permit ORed triggers. | |
713 | */ | |
98b8cbc1 | 714 | if (trigger_set > 1) { |
47f4f073 UH |
715 | sr_err("Only 1 rising/falling trigger " |
716 | "is supported."); | |
e46b8fb1 | 717 | return SR_ERR; |
ee492173 | 718 | } |
ee492173 | 719 | } |
5b5ea7c6 HE |
720 | |
721 | if (trigger_set) | |
0e1357e8 | 722 | devc->use_triggers = 1; |
57bbf56b HE |
723 | } |
724 | ||
e46b8fb1 | 725 | return SR_OK; |
57bbf56b HE |
726 | } |
727 | ||
6078d2c9 | 728 | static int dev_close(struct sr_dev_inst *sdi) |
28a35d8a | 729 | { |
0e1357e8 | 730 | struct dev_context *devc; |
28a35d8a | 731 | |
961009b0 | 732 | devc = sdi->priv; |
697785d1 UH |
733 | |
734 | /* TODO */ | |
735 | if (sdi->status == SR_ST_ACTIVE) | |
0e1357e8 | 736 | ftdi_usb_close(&devc->ftdic); |
697785d1 UH |
737 | |
738 | sdi->status = SR_ST_INACTIVE; | |
739 | ||
740 | return SR_OK; | |
28a35d8a HE |
741 | } |
742 | ||
6078d2c9 | 743 | static int cleanup(void) |
28a35d8a | 744 | { |
3b412e3a | 745 | return dev_clear(); |
28a35d8a HE |
746 | } |
747 | ||
8f996b89 | 748 | static int config_get(int id, GVariant **data, const struct sr_dev_inst *sdi, |
53b4680f | 749 | const struct sr_channel_group *cg) |
28a35d8a | 750 | { |
0e1357e8 | 751 | struct dev_context *devc; |
99965709 | 752 | |
53b4680f | 753 | (void)cg; |
8f996b89 | 754 | |
035a1078 | 755 | switch (id) { |
123e1313 | 756 | case SR_CONF_SAMPLERATE: |
41479605 | 757 | if (sdi) { |
0e1357e8 | 758 | devc = sdi->priv; |
2c9c0df8 | 759 | *data = g_variant_new_uint64(devc->cur_samplerate); |
41479605 BV |
760 | } else |
761 | return SR_ERR; | |
28a35d8a | 762 | break; |
d7bbecfd | 763 | default: |
bd6fbf62 | 764 | return SR_ERR_NA; |
28a35d8a HE |
765 | } |
766 | ||
41479605 | 767 | return SR_OK; |
28a35d8a HE |
768 | } |
769 | ||
8f996b89 | 770 | static int config_set(int id, GVariant *data, const struct sr_dev_inst *sdi, |
53b4680f | 771 | const struct sr_channel_group *cg) |
28a35d8a | 772 | { |
0e1357e8 | 773 | struct dev_context *devc; |
6868626b | 774 | uint64_t num_samples; |
28a35d8a | 775 | int ret; |
f6564c8d | 776 | |
53b4680f | 777 | (void)cg; |
8f996b89 | 778 | |
e73ffd42 BV |
779 | if (sdi->status != SR_ST_ACTIVE) |
780 | return SR_ERR_DEV_CLOSED; | |
781 | ||
0e1357e8 | 782 | devc = sdi->priv; |
99965709 | 783 | |
6868626b BV |
784 | switch (id) { |
785 | case SR_CONF_SAMPLERATE: | |
2c9c0df8 | 786 | ret = set_samplerate(sdi, g_variant_get_uint64(data)); |
6868626b BV |
787 | break; |
788 | case SR_CONF_LIMIT_MSEC: | |
2c9c0df8 | 789 | devc->limit_msec = g_variant_get_uint64(data); |
0e1357e8 | 790 | if (devc->limit_msec > 0) |
e46b8fb1 | 791 | ret = SR_OK; |
94ba4bd6 | 792 | else |
e46b8fb1 | 793 | ret = SR_ERR; |
6868626b BV |
794 | break; |
795 | case SR_CONF_LIMIT_SAMPLES: | |
796 | num_samples = g_variant_get_uint64(data); | |
797 | devc->limit_msec = num_samples * 1000 / devc->cur_samplerate; | |
798 | break; | |
799 | case SR_CONF_CAPTURE_RATIO: | |
2c9c0df8 | 800 | devc->capture_ratio = g_variant_get_uint64(data); |
0e1357e8 | 801 | if (devc->capture_ratio < 0 || devc->capture_ratio > 100) |
e46b8fb1 | 802 | ret = SR_ERR; |
94ba4bd6 | 803 | else |
e46b8fb1 | 804 | ret = SR_OK; |
6868626b BV |
805 | break; |
806 | default: | |
bd6fbf62 | 807 | ret = SR_ERR_NA; |
28a35d8a HE |
808 | } |
809 | ||
810 | return ret; | |
811 | } | |
812 | ||
8f996b89 | 813 | static int config_list(int key, GVariant **data, const struct sr_dev_inst *sdi, |
53b4680f | 814 | const struct sr_channel_group *cg) |
a1c743fc | 815 | { |
2c9c0df8 BV |
816 | GVariant *gvar; |
817 | GVariantBuilder gvb; | |
a1c743fc BV |
818 | |
819 | (void)sdi; | |
53b4680f | 820 | (void)cg; |
a1c743fc BV |
821 | |
822 | switch (key) { | |
9a6517d1 | 823 | case SR_CONF_DEVICE_OPTIONS: |
2c9c0df8 BV |
824 | *data = g_variant_new_fixed_array(G_VARIANT_TYPE_INT32, |
825 | hwcaps, ARRAY_SIZE(hwcaps), sizeof(int32_t)); | |
9a6517d1 | 826 | break; |
a1c743fc | 827 | case SR_CONF_SAMPLERATE: |
2c9c0df8 BV |
828 | g_variant_builder_init(&gvb, G_VARIANT_TYPE("a{sv}")); |
829 | gvar = g_variant_new_fixed_array(G_VARIANT_TYPE("t"), samplerates, | |
830 | ARRAY_SIZE(samplerates), sizeof(uint64_t)); | |
831 | g_variant_builder_add(&gvb, "{sv}", "samplerates", gvar); | |
832 | *data = g_variant_builder_end(&gvb); | |
a1c743fc | 833 | break; |
c50277a6 | 834 | case SR_CONF_TRIGGER_TYPE: |
2c9c0df8 | 835 | *data = g_variant_new_string(TRIGGER_TYPE); |
c50277a6 | 836 | break; |
a1c743fc | 837 | default: |
bd6fbf62 | 838 | return SR_ERR_NA; |
a1c743fc BV |
839 | } |
840 | ||
841 | return SR_OK; | |
842 | } | |
843 | ||
36b1c8e6 HE |
844 | /* Software trigger to determine exact trigger position. */ |
845 | static int get_trigger_offset(uint16_t *samples, uint16_t last_sample, | |
846 | struct sigma_trigger *t) | |
847 | { | |
848 | int i; | |
849 | ||
850 | for (i = 0; i < 8; ++i) { | |
851 | if (i > 0) | |
852 | last_sample = samples[i-1]; | |
853 | ||
854 | /* Simple triggers. */ | |
855 | if ((samples[i] & t->simplemask) != t->simplevalue) | |
856 | continue; | |
857 | ||
858 | /* Rising edge. */ | |
859 | if ((last_sample & t->risingmask) != 0 || (samples[i] & | |
860 | t->risingmask) != t->risingmask) | |
861 | continue; | |
862 | ||
863 | /* Falling edge. */ | |
bdfc7a89 HE |
864 | if ((last_sample & t->fallingmask) != t->fallingmask || |
865 | (samples[i] & t->fallingmask) != 0) | |
36b1c8e6 HE |
866 | continue; |
867 | ||
868 | break; | |
869 | } | |
870 | ||
871 | /* If we did not match, return original trigger pos. */ | |
872 | return i & 0x7; | |
873 | } | |
874 | ||
28a35d8a | 875 | /* |
fefa1800 UH |
876 | * Decode chunk of 1024 bytes, 64 clusters, 7 events per cluster. |
877 | * Each event is 20ns apart, and can contain multiple samples. | |
f78898e9 HE |
878 | * |
879 | * For 200 MHz, events contain 4 samples for each channel, spread 5 ns apart. | |
880 | * For 100 MHz, events contain 2 samples for each channel, spread 10 ns apart. | |
881 | * For 50 MHz and below, events contain one sample for each channel, | |
882 | * spread 20 ns apart. | |
28a35d8a HE |
883 | */ |
884 | static int decode_chunk_ts(uint8_t *buf, uint16_t *lastts, | |
88c51afe | 885 | uint16_t *lastsample, int triggerpos, |
3cd3a20b | 886 | uint16_t limit_chunk, void *cb_data) |
28a35d8a | 887 | { |
3cd3a20b | 888 | struct sr_dev_inst *sdi = cb_data; |
0e1357e8 | 889 | struct dev_context *devc = sdi->priv; |
fefa1800 | 890 | uint16_t tsdiff, ts; |
0e1357e8 | 891 | uint16_t samples[65536 * devc->samples_per_event]; |
b9c735a2 | 892 | struct sr_datafeed_packet packet; |
9c939c51 | 893 | struct sr_datafeed_logic logic; |
f78898e9 | 894 | int i, j, k, l, numpad, tosend; |
fefa1800 | 895 | size_t n = 0, sent = 0; |
0e1357e8 | 896 | int clustersize = EVENTS_PER_CLUSTER * devc->samples_per_event; |
fefa1800 | 897 | uint16_t *event; |
f78898e9 | 898 | uint16_t cur_sample; |
57bbf56b | 899 | int triggerts = -1; |
ee492173 | 900 | |
4ae1f451 | 901 | /* Check if trigger is in this chunk. */ |
ee492173 | 902 | if (triggerpos != -1) { |
0e1357e8 | 903 | if (devc->cur_samplerate <= SR_MHZ(50)) |
36b1c8e6 | 904 | triggerpos -= EVENTS_PER_CLUSTER - 1; |
ee492173 HE |
905 | |
906 | if (triggerpos < 0) | |
907 | triggerpos = 0; | |
57bbf56b | 908 | |
ee492173 HE |
909 | /* Find in which cluster the trigger occured. */ |
910 | triggerts = triggerpos / 7; | |
911 | } | |
28a35d8a | 912 | |
eec5275e | 913 | /* For each ts. */ |
28a35d8a | 914 | for (i = 0; i < 64; ++i) { |
fefa1800 | 915 | ts = *(uint16_t *) &buf[i * 16]; |
28a35d8a HE |
916 | tsdiff = ts - *lastts; |
917 | *lastts = ts; | |
918 | ||
88c51afe HE |
919 | /* Decode partial chunk. */ |
920 | if (limit_chunk && ts > limit_chunk) | |
e46b8fb1 | 921 | return SR_OK; |
88c51afe | 922 | |
fefa1800 | 923 | /* Pad last sample up to current point. */ |
0e1357e8 | 924 | numpad = tsdiff * devc->samples_per_event - clustersize; |
28a35d8a | 925 | if (numpad > 0) { |
f78898e9 HE |
926 | for (j = 0; j < numpad; ++j) |
927 | samples[j] = *lastsample; | |
928 | ||
929 | n = numpad; | |
28a35d8a HE |
930 | } |
931 | ||
57bbf56b HE |
932 | /* Send samples between previous and this timestamp to sigrok. */ |
933 | sent = 0; | |
934 | while (sent < n) { | |
935 | tosend = MIN(2048, n - sent); | |
936 | ||
5a2326a7 | 937 | packet.type = SR_DF_LOGIC; |
9c939c51 BV |
938 | packet.payload = &logic; |
939 | logic.length = tosend * sizeof(uint16_t); | |
940 | logic.unitsize = 2; | |
941 | logic.data = samples + sent; | |
3e9b7f9c | 942 | sr_session_send(devc->cb_data, &packet); |
28a35d8a | 943 | |
57bbf56b HE |
944 | sent += tosend; |
945 | } | |
946 | n = 0; | |
947 | ||
948 | event = (uint16_t *) &buf[i * 16 + 2]; | |
f78898e9 HE |
949 | cur_sample = 0; |
950 | ||
951 | /* For each event in cluster. */ | |
28a35d8a | 952 | for (j = 0; j < 7; ++j) { |
f78898e9 HE |
953 | |
954 | /* For each sample in event. */ | |
0e1357e8 | 955 | for (k = 0; k < devc->samples_per_event; ++k) { |
f78898e9 HE |
956 | cur_sample = 0; |
957 | ||
ba7dd8bb UH |
958 | /* For each channel. */ |
959 | for (l = 0; l < devc->num_channels; ++l) | |
edca2c5c | 960 | cur_sample |= (!!(event[j] & (1 << (l * |
0e1357e8 | 961 | devc->samples_per_event + k)))) << l; |
f78898e9 HE |
962 | |
963 | samples[n++] = cur_sample; | |
28a35d8a HE |
964 | } |
965 | } | |
966 | ||
eec5275e | 967 | /* Send data up to trigger point (if triggered). */ |
fefa1800 | 968 | sent = 0; |
57bbf56b HE |
969 | if (i == triggerts) { |
970 | /* | |
36b1c8e6 HE |
971 | * Trigger is not always accurate to sample because of |
972 | * pipeline delay. However, it always triggers before | |
973 | * the actual event. We therefore look at the next | |
974 | * samples to pinpoint the exact position of the trigger. | |
57bbf56b | 975 | */ |
bdfc7a89 | 976 | tosend = get_trigger_offset(samples, *lastsample, |
0e1357e8 | 977 | &devc->trigger); |
57bbf56b HE |
978 | |
979 | if (tosend > 0) { | |
5a2326a7 | 980 | packet.type = SR_DF_LOGIC; |
9c939c51 BV |
981 | packet.payload = &logic; |
982 | logic.length = tosend * sizeof(uint16_t); | |
983 | logic.unitsize = 2; | |
984 | logic.data = samples; | |
3e9b7f9c | 985 | sr_session_send(devc->cb_data, &packet); |
57bbf56b HE |
986 | |
987 | sent += tosend; | |
988 | } | |
28a35d8a | 989 | |
5b5ea7c6 | 990 | /* Only send trigger if explicitly enabled. */ |
0e1357e8 | 991 | if (devc->use_triggers) { |
5a2326a7 | 992 | packet.type = SR_DF_TRIGGER; |
3e9b7f9c | 993 | sr_session_send(devc->cb_data, &packet); |
5b5ea7c6 | 994 | } |
28a35d8a | 995 | } |
57bbf56b | 996 | |
eec5275e | 997 | /* Send rest of the chunk to sigrok. */ |
57bbf56b HE |
998 | tosend = n - sent; |
999 | ||
abda62ce | 1000 | if (tosend > 0) { |
5a2326a7 | 1001 | packet.type = SR_DF_LOGIC; |
9c939c51 BV |
1002 | packet.payload = &logic; |
1003 | logic.length = tosend * sizeof(uint16_t); | |
1004 | logic.unitsize = 2; | |
1005 | logic.data = samples + sent; | |
3e9b7f9c | 1006 | sr_session_send(devc->cb_data, &packet); |
abda62ce | 1007 | } |
ee492173 HE |
1008 | |
1009 | *lastsample = samples[n - 1]; | |
28a35d8a HE |
1010 | } |
1011 | ||
e46b8fb1 | 1012 | return SR_OK; |
28a35d8a HE |
1013 | } |
1014 | ||
6868626b | 1015 | static void download_capture(struct sr_dev_inst *sdi) |
28a35d8a | 1016 | { |
6868626b | 1017 | struct dev_context *devc; |
28a35d8a HE |
1018 | const int chunks_per_read = 32; |
1019 | unsigned char buf[chunks_per_read * CHUNK_SIZE]; | |
6868626b BV |
1020 | int bufsz, i, numchunks, newchunks; |
1021 | ||
1022 | sr_info("Downloading sample data."); | |
1023 | ||
1024 | devc = sdi->priv; | |
1025 | devc->state.chunks_downloaded = 0; | |
1026 | numchunks = (devc->state.stoppos + 511) / 512; | |
1027 | newchunks = MIN(chunks_per_read, numchunks - devc->state.chunks_downloaded); | |
1028 | ||
1029 | bufsz = sigma_read_dram(devc->state.chunks_downloaded, newchunks, buf, devc); | |
1030 | /* TODO: Check bufsz. For now, just avoid compiler warnings. */ | |
1031 | (void)bufsz; | |
1032 | ||
1033 | /* Find first ts. */ | |
1034 | if (devc->state.chunks_downloaded == 0) { | |
1035 | devc->state.lastts = RL16(buf) - 1; | |
1036 | devc->state.lastsample = 0; | |
1037 | } | |
1038 | ||
1039 | /* Decode chunks and send them to sigrok. */ | |
1040 | for (i = 0; i < newchunks; ++i) { | |
1041 | int limit_chunk = 0; | |
1042 | ||
1043 | /* The last chunk may potentially be only in part. */ | |
1044 | if (devc->state.chunks_downloaded == numchunks - 1) { | |
1045 | /* Find the last valid timestamp */ | |
1046 | limit_chunk = devc->state.stoppos % 512 + devc->state.lastts; | |
1047 | } | |
1048 | ||
1049 | if (devc->state.chunks_downloaded + i == devc->state.triggerchunk) | |
1050 | decode_chunk_ts(buf + (i * CHUNK_SIZE), | |
1051 | &devc->state.lastts, | |
1052 | &devc->state.lastsample, | |
1053 | devc->state.triggerpos & 0x1ff, | |
1054 | limit_chunk, sdi); | |
1055 | else | |
1056 | decode_chunk_ts(buf + (i * CHUNK_SIZE), | |
1057 | &devc->state.lastts, | |
1058 | &devc->state.lastsample, | |
1059 | -1, limit_chunk, sdi); | |
1060 | ||
1061 | ++devc->state.chunks_downloaded; | |
1062 | } | |
1063 | ||
1064 | } | |
1065 | ||
1066 | static int receive_data(int fd, int revents, void *cb_data) | |
1067 | { | |
1068 | struct sr_dev_inst *sdi; | |
1069 | struct dev_context *devc; | |
1070 | struct sr_datafeed_packet packet; | |
94ba4bd6 | 1071 | uint64_t running_msec; |
28a35d8a | 1072 | struct timeval tv; |
6868626b BV |
1073 | int numchunks; |
1074 | uint8_t modestatus; | |
28a35d8a | 1075 | |
cb93f8a9 UH |
1076 | (void)fd; |
1077 | (void)revents; | |
28a35d8a | 1078 | |
6868626b BV |
1079 | sdi = cb_data; |
1080 | devc = sdi->priv; | |
1081 | ||
805919b0 | 1082 | /* Get the current position. */ |
0e1357e8 | 1083 | sigma_read_pos(&devc->state.stoppos, &devc->state.triggerpos, devc); |
805919b0 | 1084 | |
0e1357e8 | 1085 | if (devc->state.state == SIGMA_IDLE) |
805919b0 | 1086 | return TRUE; |
28a35d8a | 1087 | |
0e1357e8 | 1088 | if (devc->state.state == SIGMA_CAPTURE) { |
6868626b BV |
1089 | numchunks = (devc->state.stoppos + 511) / 512; |
1090 | ||
6aac7737 HE |
1091 | /* Check if the timer has expired, or memory is full. */ |
1092 | gettimeofday(&tv, 0); | |
0e1357e8 BV |
1093 | running_msec = (tv.tv_sec - devc->start_tv.tv_sec) * 1000 + |
1094 | (tv.tv_usec - devc->start_tv.tv_usec) / 1000; | |
28a35d8a | 1095 | |
0e1357e8 | 1096 | if (running_msec < devc->limit_msec && numchunks < 32767) |
6868626b | 1097 | /* Still capturing. */ |
6aac7737 | 1098 | return TRUE; |
6aac7737 | 1099 | |
6868626b BV |
1100 | /* Stop acquisition. */ |
1101 | sigma_set_register(WRITE_MODE, 0x11, devc); | |
28a35d8a | 1102 | |
6868626b BV |
1103 | /* Set SDRAM Read Enable. */ |
1104 | sigma_set_register(WRITE_MODE, 0x02, devc); | |
28a35d8a | 1105 | |
6868626b BV |
1106 | /* Get the current position. */ |
1107 | sigma_read_pos(&devc->state.stoppos, &devc->state.triggerpos, devc); | |
28a35d8a | 1108 | |
6868626b BV |
1109 | /* Check if trigger has fired. */ |
1110 | modestatus = sigma_get_register(READ_MODE, devc); | |
1111 | if (modestatus & 0x20) | |
1112 | devc->state.triggerchunk = devc->state.triggerpos / 512; | |
1113 | else | |
1114 | devc->state.triggerchunk = -1; | |
28a35d8a | 1115 | |
6868626b BV |
1116 | /* Transfer captured data from device. */ |
1117 | download_capture(sdi); | |
88c51afe | 1118 | |
6868626b BV |
1119 | /* All done. */ |
1120 | packet.type = SR_DF_END; | |
1121 | sr_session_send(sdi, &packet); | |
88c51afe | 1122 | |
6868626b | 1123 | dev_acquisition_stop(sdi, sdi); |
28a35d8a HE |
1124 | } |
1125 | ||
28a35d8a HE |
1126 | return TRUE; |
1127 | } | |
1128 | ||
c53d793f HE |
1129 | /* Build a LUT entry used by the trigger functions. */ |
1130 | static void build_lut_entry(uint16_t value, uint16_t mask, uint16_t *entry) | |
ee492173 HE |
1131 | { |
1132 | int i, j, k, bit; | |
1133 | ||
ba7dd8bb | 1134 | /* For each quad channel. */ |
ee492173 | 1135 | for (i = 0; i < 4; ++i) { |
c53d793f | 1136 | entry[i] = 0xffff; |
ee492173 | 1137 | |
f758d074 | 1138 | /* For each bit in LUT. */ |
ee492173 HE |
1139 | for (j = 0; j < 16; ++j) |
1140 | ||
ba7dd8bb | 1141 | /* For each channel in quad. */ |
ee492173 HE |
1142 | for (k = 0; k < 4; ++k) { |
1143 | bit = 1 << (i * 4 + k); | |
1144 | ||
c53d793f HE |
1145 | /* Set bit in entry */ |
1146 | if ((mask & bit) && | |
1147 | ((!(value & bit)) != | |
4ae1f451 | 1148 | (!(j & (1 << k))))) |
c53d793f | 1149 | entry[i] &= ~(1 << j); |
ee492173 HE |
1150 | } |
1151 | } | |
c53d793f | 1152 | } |
ee492173 | 1153 | |
c53d793f HE |
1154 | /* Add a logical function to LUT mask. */ |
1155 | static void add_trigger_function(enum triggerop oper, enum triggerfunc func, | |
1156 | int index, int neg, uint16_t *mask) | |
1157 | { | |
1158 | int i, j; | |
1159 | int x[2][2], tmp, a, b, aset, bset, rset; | |
1160 | ||
1161 | memset(x, 0, 4 * sizeof(int)); | |
1162 | ||
1163 | /* Trigger detect condition. */ | |
1164 | switch (oper) { | |
1165 | case OP_LEVEL: | |
1166 | x[0][1] = 1; | |
1167 | x[1][1] = 1; | |
1168 | break; | |
1169 | case OP_NOT: | |
1170 | x[0][0] = 1; | |
1171 | x[1][0] = 1; | |
1172 | break; | |
1173 | case OP_RISE: | |
1174 | x[0][1] = 1; | |
1175 | break; | |
1176 | case OP_FALL: | |
1177 | x[1][0] = 1; | |
1178 | break; | |
1179 | case OP_RISEFALL: | |
1180 | x[0][1] = 1; | |
1181 | x[1][0] = 1; | |
1182 | break; | |
1183 | case OP_NOTRISE: | |
1184 | x[1][1] = 1; | |
1185 | x[0][0] = 1; | |
1186 | x[1][0] = 1; | |
1187 | break; | |
1188 | case OP_NOTFALL: | |
1189 | x[1][1] = 1; | |
1190 | x[0][0] = 1; | |
1191 | x[0][1] = 1; | |
1192 | break; | |
1193 | case OP_NOTRISEFALL: | |
1194 | x[1][1] = 1; | |
1195 | x[0][0] = 1; | |
1196 | break; | |
1197 | } | |
1198 | ||
1199 | /* Transpose if neg is set. */ | |
1200 | if (neg) { | |
ea9cfed7 | 1201 | for (i = 0; i < 2; ++i) { |
c53d793f HE |
1202 | for (j = 0; j < 2; ++j) { |
1203 | tmp = x[i][j]; | |
1204 | x[i][j] = x[1-i][1-j]; | |
1205 | x[1-i][1-j] = tmp; | |
1206 | } | |
ea9cfed7 | 1207 | } |
c53d793f HE |
1208 | } |
1209 | ||
1210 | /* Update mask with function. */ | |
1211 | for (i = 0; i < 16; ++i) { | |
1212 | a = (i >> (2 * index + 0)) & 1; | |
1213 | b = (i >> (2 * index + 1)) & 1; | |
1214 | ||
1215 | aset = (*mask >> i) & 1; | |
1216 | bset = x[b][a]; | |
1217 | ||
1218 | if (func == FUNC_AND || func == FUNC_NAND) | |
1219 | rset = aset & bset; | |
1220 | else if (func == FUNC_OR || func == FUNC_NOR) | |
1221 | rset = aset | bset; | |
1222 | else if (func == FUNC_XOR || func == FUNC_NXOR) | |
1223 | rset = aset ^ bset; | |
1224 | ||
1225 | if (func == FUNC_NAND || func == FUNC_NOR || func == FUNC_NXOR) | |
1226 | rset = !rset; | |
1227 | ||
1228 | *mask &= ~(1 << i); | |
1229 | ||
1230 | if (rset) | |
1231 | *mask |= 1 << i; | |
1232 | } | |
1233 | } | |
1234 | ||
1235 | /* | |
1236 | * Build trigger LUTs used by 50 MHz and lower sample rates for supporting | |
1237 | * simple pin change and state triggers. Only two transitions (rise/fall) can be | |
1238 | * set at any time, but a full mask and value can be set (0/1). | |
1239 | */ | |
0e1357e8 | 1240 | static int build_basic_trigger(struct triggerlut *lut, struct dev_context *devc) |
c53d793f HE |
1241 | { |
1242 | int i,j; | |
4ae1f451 | 1243 | uint16_t masks[2] = { 0, 0 }; |
c53d793f HE |
1244 | |
1245 | memset(lut, 0, sizeof(struct triggerlut)); | |
1246 | ||
1247 | /* Contant for simple triggers. */ | |
1248 | lut->m4 = 0xa000; | |
1249 | ||
1250 | /* Value/mask trigger support. */ | |
0e1357e8 | 1251 | build_lut_entry(devc->trigger.simplevalue, devc->trigger.simplemask, |
99965709 | 1252 | lut->m2d); |
c53d793f HE |
1253 | |
1254 | /* Rise/fall trigger support. */ | |
1255 | for (i = 0, j = 0; i < 16; ++i) { | |
0e1357e8 BV |
1256 | if (devc->trigger.risingmask & (1 << i) || |
1257 | devc->trigger.fallingmask & (1 << i)) | |
c53d793f HE |
1258 | masks[j++] = 1 << i; |
1259 | } | |
1260 | ||
1261 | build_lut_entry(masks[0], masks[0], lut->m0d); | |
1262 | build_lut_entry(masks[1], masks[1], lut->m1d); | |
1263 | ||
1264 | /* Add glue logic */ | |
1265 | if (masks[0] || masks[1]) { | |
1266 | /* Transition trigger. */ | |
0e1357e8 | 1267 | if (masks[0] & devc->trigger.risingmask) |
c53d793f | 1268 | add_trigger_function(OP_RISE, FUNC_OR, 0, 0, &lut->m3); |
0e1357e8 | 1269 | if (masks[0] & devc->trigger.fallingmask) |
c53d793f | 1270 | add_trigger_function(OP_FALL, FUNC_OR, 0, 0, &lut->m3); |
0e1357e8 | 1271 | if (masks[1] & devc->trigger.risingmask) |
c53d793f | 1272 | add_trigger_function(OP_RISE, FUNC_OR, 1, 0, &lut->m3); |
0e1357e8 | 1273 | if (masks[1] & devc->trigger.fallingmask) |
c53d793f HE |
1274 | add_trigger_function(OP_FALL, FUNC_OR, 1, 0, &lut->m3); |
1275 | } else { | |
1276 | /* Only value/mask trigger. */ | |
1277 | lut->m3 = 0xffff; | |
1278 | } | |
ee492173 | 1279 | |
c53d793f | 1280 | /* Triggertype: event. */ |
ee492173 HE |
1281 | lut->params.selres = 3; |
1282 | ||
e46b8fb1 | 1283 | return SR_OK; |
ee492173 HE |
1284 | } |
1285 | ||
6078d2c9 | 1286 | static int dev_acquisition_start(const struct sr_dev_inst *sdi, void *cb_data) |
28a35d8a | 1287 | { |
0e1357e8 | 1288 | struct dev_context *devc; |
9ddb2a12 | 1289 | struct clockselect_50 clockselect; |
82957b65 | 1290 | int frac, triggerpin, ret; |
f4abaa9f | 1291 | uint8_t triggerselect = 0; |
57bbf56b | 1292 | struct triggerinout triggerinout_conf; |
ee492173 | 1293 | struct triggerlut lut; |
28a35d8a | 1294 | |
e73ffd42 BV |
1295 | if (sdi->status != SR_ST_ACTIVE) |
1296 | return SR_ERR_DEV_CLOSED; | |
1297 | ||
0e1357e8 | 1298 | devc = sdi->priv; |
28a35d8a | 1299 | |
ba7dd8bb UH |
1300 | if (configure_channels(sdi) != SR_OK) { |
1301 | sr_err("Failed to configure channels."); | |
014359e3 BV |
1302 | return SR_ERR; |
1303 | } | |
1304 | ||
ea9cfed7 | 1305 | /* If the samplerate has not been set, default to 200 kHz. */ |
0e1357e8 | 1306 | if (devc->cur_firmware == -1) { |
82957b65 UH |
1307 | if ((ret = set_samplerate(sdi, SR_KHZ(200))) != SR_OK) |
1308 | return ret; | |
1309 | } | |
e8397563 | 1310 | |
eec5275e | 1311 | /* Enter trigger programming mode. */ |
0e1357e8 | 1312 | sigma_set_register(WRITE_TRIGGER_SELECT1, 0x20, devc); |
28a35d8a | 1313 | |
eec5275e | 1314 | /* 100 and 200 MHz mode. */ |
0e1357e8 BV |
1315 | if (devc->cur_samplerate >= SR_MHZ(100)) { |
1316 | sigma_set_register(WRITE_TRIGGER_SELECT1, 0x81, devc); | |
57bbf56b | 1317 | |
a42aec7f HE |
1318 | /* Find which pin to trigger on from mask. */ |
1319 | for (triggerpin = 0; triggerpin < 8; ++triggerpin) | |
0e1357e8 | 1320 | if ((devc->trigger.risingmask | devc->trigger.fallingmask) & |
a42aec7f HE |
1321 | (1 << triggerpin)) |
1322 | break; | |
1323 | ||
1324 | /* Set trigger pin and light LED on trigger. */ | |
1325 | triggerselect = (1 << LEDSEL1) | (triggerpin & 0x7); | |
1326 | ||
1327 | /* Default rising edge. */ | |
0e1357e8 | 1328 | if (devc->trigger.fallingmask) |
a42aec7f | 1329 | triggerselect |= 1 << 3; |
57bbf56b | 1330 | |
eec5275e | 1331 | /* All other modes. */ |
0e1357e8 BV |
1332 | } else if (devc->cur_samplerate <= SR_MHZ(50)) { |
1333 | build_basic_trigger(&lut, devc); | |
ee492173 | 1334 | |
0e1357e8 | 1335 | sigma_write_trigger_lut(&lut, devc); |
57bbf56b HE |
1336 | |
1337 | triggerselect = (1 << LEDSEL1) | (1 << LEDSEL0); | |
1338 | } | |
1339 | ||
eec5275e | 1340 | /* Setup trigger in and out pins to default values. */ |
57bbf56b HE |
1341 | memset(&triggerinout_conf, 0, sizeof(struct triggerinout)); |
1342 | triggerinout_conf.trgout_bytrigger = 1; | |
1343 | triggerinout_conf.trgout_enable = 1; | |
1344 | ||
28a35d8a | 1345 | sigma_write_register(WRITE_TRIGGER_OPTION, |
57bbf56b | 1346 | (uint8_t *) &triggerinout_conf, |
0e1357e8 | 1347 | sizeof(struct triggerinout), devc); |
28a35d8a | 1348 | |
eec5275e | 1349 | /* Go back to normal mode. */ |
0e1357e8 | 1350 | sigma_set_register(WRITE_TRIGGER_SELECT1, triggerselect, devc); |
28a35d8a | 1351 | |
edca2c5c | 1352 | /* Set clock select register. */ |
0e1357e8 | 1353 | if (devc->cur_samplerate == SR_MHZ(200)) |
ba7dd8bb | 1354 | /* Enable 4 channels. */ |
0e1357e8 BV |
1355 | sigma_set_register(WRITE_CLOCK_SELECT, 0xf0, devc); |
1356 | else if (devc->cur_samplerate == SR_MHZ(100)) | |
ba7dd8bb | 1357 | /* Enable 8 channels. */ |
0e1357e8 | 1358 | sigma_set_register(WRITE_CLOCK_SELECT, 0x00, devc); |
edca2c5c HE |
1359 | else { |
1360 | /* | |
9ddb2a12 | 1361 | * 50 MHz mode (or fraction thereof). Any fraction down to |
eec5275e | 1362 | * 50 MHz / 256 can be used, but is not supported by sigrok API. |
edca2c5c | 1363 | */ |
0e1357e8 | 1364 | frac = SR_MHZ(50) / devc->cur_samplerate - 1; |
edca2c5c | 1365 | |
9ddb2a12 UH |
1366 | clockselect.async = 0; |
1367 | clockselect.fraction = frac; | |
ba7dd8bb | 1368 | clockselect.disabled_channels = 0; |
edca2c5c HE |
1369 | |
1370 | sigma_write_register(WRITE_CLOCK_SELECT, | |
9ddb2a12 | 1371 | (uint8_t *) &clockselect, |
0e1357e8 | 1372 | sizeof(clockselect), devc); |
edca2c5c HE |
1373 | } |
1374 | ||
fefa1800 | 1375 | /* Setup maximum post trigger time. */ |
99965709 | 1376 | sigma_set_register(WRITE_POST_TRIGGER, |
0e1357e8 | 1377 | (devc->capture_ratio * 255) / 100, devc); |
28a35d8a | 1378 | |
eec5275e | 1379 | /* Start acqusition. */ |
0e1357e8 BV |
1380 | gettimeofday(&devc->start_tv, 0); |
1381 | sigma_set_register(WRITE_MODE, 0x0d, devc); | |
99965709 | 1382 | |
3e9b7f9c | 1383 | devc->cb_data = cb_data; |
28a35d8a | 1384 | |
3c36c403 | 1385 | /* Send header packet to the session bus. */ |
29a27196 | 1386 | std_session_send_df_header(cb_data, LOG_PREFIX); |
f366e86c | 1387 | |
f366e86c | 1388 | /* Add capture source. */ |
3ffb6964 | 1389 | sr_source_add(0, G_IO_IN, 10, receive_data, (void *)sdi); |
f366e86c | 1390 | |
0e1357e8 | 1391 | devc->state.state = SIGMA_CAPTURE; |
6aac7737 | 1392 | |
e46b8fb1 | 1393 | return SR_OK; |
28a35d8a HE |
1394 | } |
1395 | ||
6078d2c9 | 1396 | static int dev_acquisition_stop(struct sr_dev_inst *sdi, void *cb_data) |
28a35d8a | 1397 | { |
0e1357e8 | 1398 | struct dev_context *devc; |
6aac7737 | 1399 | |
3cd3a20b | 1400 | (void)cb_data; |
28a35d8a | 1401 | |
6868626b BV |
1402 | devc = sdi->priv; |
1403 | devc->state.state = SIGMA_IDLE; | |
6aac7737 | 1404 | |
6868626b | 1405 | sr_source_remove(0); |
3010f21c UH |
1406 | |
1407 | return SR_OK; | |
28a35d8a HE |
1408 | } |
1409 | ||
c09f0b57 | 1410 | SR_PRIV struct sr_dev_driver asix_sigma_driver_info = { |
e519ba86 | 1411 | .name = "asix-sigma", |
6352d030 | 1412 | .longname = "ASIX SIGMA/SIGMA2", |
e519ba86 | 1413 | .api_version = 1, |
6078d2c9 UH |
1414 | .init = init, |
1415 | .cleanup = cleanup, | |
1416 | .scan = scan, | |
1417 | .dev_list = dev_list, | |
3b412e3a | 1418 | .dev_clear = dev_clear, |
035a1078 BV |
1419 | .config_get = config_get, |
1420 | .config_set = config_set, | |
a1c743fc | 1421 | .config_list = config_list, |
6078d2c9 UH |
1422 | .dev_open = dev_open, |
1423 | .dev_close = dev_close, | |
1424 | .dev_acquisition_start = dev_acquisition_start, | |
1425 | .dev_acquisition_stop = dev_acquisition_stop, | |
0e1357e8 | 1426 | .priv = NULL, |
28a35d8a | 1427 | }; |