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Commit | Line | Data |
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28a35d8a HE |
1 | /* |
2 | * This file is part of the sigrok project. | |
3 | * | |
868501fa | 4 | * Copyright (C) 2010-2012 Håvard Espeland <gus@ping.uio.no>, |
911f1834 UH |
5 | * Copyright (C) 2010 Martin Stensgård <mastensg@ping.uio.no> |
6 | * Copyright (C) 2010 Carl Henrik Lunde <chlunde@ping.uio.no> | |
28a35d8a HE |
7 | * |
8 | * This program is free software: you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation, either version 3 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
20 | */ | |
21 | ||
911f1834 | 22 | /* |
6352d030 | 23 | * ASIX SIGMA/SIGMA2 logic analyzer driver |
911f1834 UH |
24 | */ |
25 | ||
3bbd9849 UH |
26 | #include <glib.h> |
27 | #include <glib/gstdio.h> | |
28a35d8a HE |
28 | #include <ftdi.h> |
29 | #include <string.h> | |
45c59c8b BV |
30 | #include "libsigrok.h" |
31 | #include "libsigrok-internal.h" | |
28a35d8a HE |
32 | #include "asix-sigma.h" |
33 | ||
34 | #define USB_VENDOR 0xa600 | |
35 | #define USB_PRODUCT 0xa000 | |
36 | #define USB_DESCRIPTION "ASIX SIGMA" | |
37 | #define USB_VENDOR_NAME "ASIX" | |
38 | #define USB_MODEL_NAME "SIGMA" | |
39 | #define USB_MODEL_VERSION "" | |
ee492173 | 40 | #define TRIGGER_TYPES "rf10" |
464d12c7 | 41 | #define NUM_PROBES 16 |
28a35d8a | 42 | |
ed300b9f | 43 | SR_PRIV struct sr_dev_driver asix_sigma_driver_info; |
a873c594 | 44 | static struct sr_dev_driver *di = &asix_sigma_driver_info; |
69b07d14 | 45 | static int hw_dev_acquisition_stop(struct sr_dev_inst *sdi, void *cb_data); |
28a35d8a | 46 | |
a533743d | 47 | static const uint64_t supported_samplerates[] = { |
59df0c77 UH |
48 | SR_KHZ(200), |
49 | SR_KHZ(250), | |
50 | SR_KHZ(500), | |
51 | SR_MHZ(1), | |
52 | SR_MHZ(5), | |
53 | SR_MHZ(10), | |
54 | SR_MHZ(25), | |
55 | SR_MHZ(50), | |
56 | SR_MHZ(100), | |
57 | SR_MHZ(200), | |
28a35d8a HE |
58 | 0, |
59 | }; | |
60 | ||
d261dbbf UH |
61 | /* |
62 | * Probe numbers seem to go from 1-16, according to this image: | |
63 | * http://tools.asix.net/img/sigma_sigmacab_pins_720.jpg | |
64 | * (the cable has two additional GND pins, and a TI and TO pin) | |
65 | */ | |
c37d2b1b | 66 | static const char *probe_names[NUM_PROBES + 1] = { |
464d12c7 KS |
67 | "1", |
68 | "2", | |
69 | "3", | |
70 | "4", | |
71 | "5", | |
72 | "6", | |
73 | "7", | |
74 | "8", | |
75 | "9", | |
76 | "10", | |
77 | "11", | |
78 | "12", | |
79 | "13", | |
80 | "14", | |
81 | "15", | |
d261dbbf | 82 | "16", |
464d12c7 KS |
83 | NULL, |
84 | }; | |
85 | ||
a533743d | 86 | static const struct sr_samplerates samplerates = { |
590b9f9a UH |
87 | 0, |
88 | 0, | |
89 | 0, | |
28a35d8a HE |
90 | supported_samplerates, |
91 | }; | |
92 | ||
915f7cc8 | 93 | static const int hwcaps[] = { |
5a2326a7 UH |
94 | SR_HWCAP_LOGIC_ANALYZER, |
95 | SR_HWCAP_SAMPLERATE, | |
96 | SR_HWCAP_CAPTURE_RATIO, | |
28a35d8a | 97 | |
5a2326a7 | 98 | SR_HWCAP_LIMIT_MSEC, |
28a35d8a HE |
99 | 0, |
100 | }; | |
101 | ||
fefa1800 UH |
102 | /* Force the FPGA to reboot. */ |
103 | static uint8_t suicide[] = { | |
104 | 0x84, 0x84, 0x88, 0x84, 0x88, 0x84, 0x88, 0x84, | |
105 | }; | |
106 | ||
107 | /* Prepare to upload firmware (FPGA specific). */ | |
108 | static uint8_t init[] = { | |
109 | 0x03, 0x03, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, | |
110 | }; | |
111 | ||
112 | /* Initialize the logic analyzer mode. */ | |
113 | static uint8_t logic_mode_start[] = { | |
114 | 0x00, 0x40, 0x0f, 0x25, 0x35, 0x40, | |
115 | 0x2a, 0x3a, 0x40, 0x03, 0x20, 0x38, | |
116 | }; | |
117 | ||
eec5275e | 118 | static const char *firmware_files[] = { |
a8116d76 HE |
119 | "asix-sigma-50.fw", /* 50 MHz, supports 8 bit fractions */ |
120 | "asix-sigma-100.fw", /* 100 MHz */ | |
121 | "asix-sigma-200.fw", /* 200 MHz */ | |
ed09fd07 | 122 | "asix-sigma-50sync.fw", /* Synchronous clock from pin */ |
a8116d76 | 123 | "asix-sigma-phasor.fw", /* Frequency counter */ |
f6564c8d HE |
124 | }; |
125 | ||
0e1357e8 | 126 | static int sigma_read(void *buf, size_t size, struct dev_context *devc) |
28a35d8a HE |
127 | { |
128 | int ret; | |
fefa1800 | 129 | |
0e1357e8 | 130 | ret = ftdi_read_data(&devc->ftdic, (unsigned char *)buf, size); |
28a35d8a | 131 | if (ret < 0) { |
47f4f073 | 132 | sr_err("ftdi_read_data failed: %s", |
0e1357e8 | 133 | ftdi_get_error_string(&devc->ftdic)); |
28a35d8a HE |
134 | } |
135 | ||
136 | return ret; | |
137 | } | |
138 | ||
0e1357e8 | 139 | static int sigma_write(void *buf, size_t size, struct dev_context *devc) |
28a35d8a HE |
140 | { |
141 | int ret; | |
fefa1800 | 142 | |
0e1357e8 | 143 | ret = ftdi_write_data(&devc->ftdic, (unsigned char *)buf, size); |
28a35d8a | 144 | if (ret < 0) { |
47f4f073 | 145 | sr_err("ftdi_write_data failed: %s", |
0e1357e8 | 146 | ftdi_get_error_string(&devc->ftdic)); |
fefa1800 | 147 | } else if ((size_t) ret != size) { |
47f4f073 | 148 | sr_err("ftdi_write_data did not complete write."); |
28a35d8a HE |
149 | } |
150 | ||
151 | return ret; | |
152 | } | |
153 | ||
99965709 | 154 | static int sigma_write_register(uint8_t reg, uint8_t *data, size_t len, |
0e1357e8 | 155 | struct dev_context *devc) |
28a35d8a HE |
156 | { |
157 | size_t i; | |
158 | uint8_t buf[len + 2]; | |
159 | int idx = 0; | |
160 | ||
161 | buf[idx++] = REG_ADDR_LOW | (reg & 0xf); | |
162 | buf[idx++] = REG_ADDR_HIGH | (reg >> 4); | |
163 | ||
fefa1800 | 164 | for (i = 0; i < len; ++i) { |
28a35d8a HE |
165 | buf[idx++] = REG_DATA_LOW | (data[i] & 0xf); |
166 | buf[idx++] = REG_DATA_HIGH_WRITE | (data[i] >> 4); | |
167 | } | |
168 | ||
0e1357e8 | 169 | return sigma_write(buf, idx, devc); |
28a35d8a HE |
170 | } |
171 | ||
0e1357e8 | 172 | static int sigma_set_register(uint8_t reg, uint8_t value, struct dev_context *devc) |
28a35d8a | 173 | { |
0e1357e8 | 174 | return sigma_write_register(reg, &value, 1, devc); |
28a35d8a HE |
175 | } |
176 | ||
99965709 | 177 | static int sigma_read_register(uint8_t reg, uint8_t *data, size_t len, |
0e1357e8 | 178 | struct dev_context *devc) |
28a35d8a HE |
179 | { |
180 | uint8_t buf[3]; | |
fefa1800 | 181 | |
28a35d8a HE |
182 | buf[0] = REG_ADDR_LOW | (reg & 0xf); |
183 | buf[1] = REG_ADDR_HIGH | (reg >> 4); | |
28a35d8a HE |
184 | buf[2] = REG_READ_ADDR; |
185 | ||
0e1357e8 | 186 | sigma_write(buf, sizeof(buf), devc); |
28a35d8a | 187 | |
0e1357e8 | 188 | return sigma_read(data, len, devc); |
28a35d8a HE |
189 | } |
190 | ||
0e1357e8 | 191 | static uint8_t sigma_get_register(uint8_t reg, struct dev_context *devc) |
28a35d8a HE |
192 | { |
193 | uint8_t value; | |
fefa1800 | 194 | |
0e1357e8 | 195 | if (1 != sigma_read_register(reg, &value, 1, devc)) { |
47f4f073 | 196 | sr_err("sigma_get_register: 1 byte expected"); |
28a35d8a HE |
197 | return 0; |
198 | } | |
199 | ||
200 | return value; | |
201 | } | |
202 | ||
99965709 | 203 | static int sigma_read_pos(uint32_t *stoppos, uint32_t *triggerpos, |
0e1357e8 | 204 | struct dev_context *devc) |
28a35d8a HE |
205 | { |
206 | uint8_t buf[] = { | |
207 | REG_ADDR_LOW | READ_TRIGGER_POS_LOW, | |
208 | ||
209 | REG_READ_ADDR | NEXT_REG, | |
210 | REG_READ_ADDR | NEXT_REG, | |
211 | REG_READ_ADDR | NEXT_REG, | |
212 | REG_READ_ADDR | NEXT_REG, | |
213 | REG_READ_ADDR | NEXT_REG, | |
214 | REG_READ_ADDR | NEXT_REG, | |
215 | }; | |
28a35d8a HE |
216 | uint8_t result[6]; |
217 | ||
0e1357e8 | 218 | sigma_write(buf, sizeof(buf), devc); |
28a35d8a | 219 | |
0e1357e8 | 220 | sigma_read(result, sizeof(result), devc); |
28a35d8a HE |
221 | |
222 | *triggerpos = result[0] | (result[1] << 8) | (result[2] << 16); | |
223 | *stoppos = result[3] | (result[4] << 8) | (result[5] << 16); | |
224 | ||
57bbf56b HE |
225 | /* Not really sure why this must be done, but according to spec. */ |
226 | if ((--*stoppos & 0x1ff) == 0x1ff) | |
227 | stoppos -= 64; | |
228 | ||
229 | if ((*--triggerpos & 0x1ff) == 0x1ff) | |
230 | triggerpos -= 64; | |
231 | ||
28a35d8a HE |
232 | return 1; |
233 | } | |
234 | ||
99965709 | 235 | static int sigma_read_dram(uint16_t startchunk, size_t numchunks, |
0e1357e8 | 236 | uint8_t *data, struct dev_context *devc) |
28a35d8a HE |
237 | { |
238 | size_t i; | |
239 | uint8_t buf[4096]; | |
240 | int idx = 0; | |
241 | ||
fefa1800 | 242 | /* Send the startchunk. Index start with 1. */ |
28a35d8a HE |
243 | buf[0] = startchunk >> 8; |
244 | buf[1] = startchunk & 0xff; | |
0e1357e8 | 245 | sigma_write_register(WRITE_MEMROW, buf, 2, devc); |
28a35d8a | 246 | |
fefa1800 | 247 | /* Read the DRAM. */ |
28a35d8a HE |
248 | buf[idx++] = REG_DRAM_BLOCK; |
249 | buf[idx++] = REG_DRAM_WAIT_ACK; | |
250 | ||
251 | for (i = 0; i < numchunks; ++i) { | |
fefa1800 UH |
252 | /* Alternate bit to copy from DRAM to cache. */ |
253 | if (i != (numchunks - 1)) | |
254 | buf[idx++] = REG_DRAM_BLOCK | (((i + 1) % 2) << 4); | |
28a35d8a HE |
255 | |
256 | buf[idx++] = REG_DRAM_BLOCK_DATA | ((i % 2) << 4); | |
257 | ||
fefa1800 | 258 | if (i != (numchunks - 1)) |
28a35d8a HE |
259 | buf[idx++] = REG_DRAM_WAIT_ACK; |
260 | } | |
261 | ||
0e1357e8 | 262 | sigma_write(buf, idx, devc); |
28a35d8a | 263 | |
0e1357e8 | 264 | return sigma_read(data, numchunks * CHUNK_SIZE, devc); |
28a35d8a HE |
265 | } |
266 | ||
4ae1f451 | 267 | /* Upload trigger look-up tables to Sigma. */ |
0e1357e8 | 268 | static int sigma_write_trigger_lut(struct triggerlut *lut, struct dev_context *devc) |
ee492173 HE |
269 | { |
270 | int i; | |
271 | uint8_t tmp[2]; | |
272 | uint16_t bit; | |
273 | ||
274 | /* Transpose the table and send to Sigma. */ | |
275 | for (i = 0; i < 16; ++i) { | |
276 | bit = 1 << i; | |
277 | ||
278 | tmp[0] = tmp[1] = 0; | |
279 | ||
280 | if (lut->m2d[0] & bit) | |
281 | tmp[0] |= 0x01; | |
282 | if (lut->m2d[1] & bit) | |
283 | tmp[0] |= 0x02; | |
284 | if (lut->m2d[2] & bit) | |
285 | tmp[0] |= 0x04; | |
286 | if (lut->m2d[3] & bit) | |
287 | tmp[0] |= 0x08; | |
288 | ||
289 | if (lut->m3 & bit) | |
290 | tmp[0] |= 0x10; | |
291 | if (lut->m3s & bit) | |
292 | tmp[0] |= 0x20; | |
293 | if (lut->m4 & bit) | |
294 | tmp[0] |= 0x40; | |
295 | ||
296 | if (lut->m0d[0] & bit) | |
297 | tmp[1] |= 0x01; | |
298 | if (lut->m0d[1] & bit) | |
299 | tmp[1] |= 0x02; | |
300 | if (lut->m0d[2] & bit) | |
301 | tmp[1] |= 0x04; | |
302 | if (lut->m0d[3] & bit) | |
303 | tmp[1] |= 0x08; | |
304 | ||
305 | if (lut->m1d[0] & bit) | |
306 | tmp[1] |= 0x10; | |
307 | if (lut->m1d[1] & bit) | |
308 | tmp[1] |= 0x20; | |
309 | if (lut->m1d[2] & bit) | |
310 | tmp[1] |= 0x40; | |
311 | if (lut->m1d[3] & bit) | |
312 | tmp[1] |= 0x80; | |
313 | ||
99965709 | 314 | sigma_write_register(WRITE_TRIGGER_SELECT0, tmp, sizeof(tmp), |
0e1357e8 BV |
315 | devc); |
316 | sigma_set_register(WRITE_TRIGGER_SELECT1, 0x30 | i, devc); | |
ee492173 HE |
317 | } |
318 | ||
319 | /* Send the parameters */ | |
320 | sigma_write_register(WRITE_TRIGGER_SELECT0, (uint8_t *) &lut->params, | |
0e1357e8 | 321 | sizeof(lut->params), devc); |
ee492173 | 322 | |
e46b8fb1 | 323 | return SR_OK; |
ee492173 HE |
324 | } |
325 | ||
fefa1800 | 326 | /* Generate the bitbang stream for programming the FPGA. */ |
28a35d8a | 327 | static int bin2bitbang(const char *filename, |
fefa1800 | 328 | unsigned char **buf, size_t *buf_size) |
28a35d8a | 329 | { |
fefa1800 | 330 | FILE *f; |
e3fff420 | 331 | unsigned long file_size; |
28a35d8a HE |
332 | unsigned long offset = 0; |
333 | unsigned char *p; | |
e3fff420 HE |
334 | uint8_t *firmware; |
335 | unsigned long fwsize = 0; | |
28a35d8a HE |
336 | const int buffer_size = 65536; |
337 | size_t i; | |
e3fff420 | 338 | int c, bit, v; |
fefa1800 | 339 | uint32_t imm = 0x3f6df2ab; |
28a35d8a | 340 | |
868d8cef | 341 | f = g_fopen(filename, "rb"); |
28a35d8a | 342 | if (!f) { |
47f4f073 | 343 | sr_err("g_fopen(\"%s\", \"rb\")", filename); |
b53738ba | 344 | return SR_ERR; |
28a35d8a HE |
345 | } |
346 | ||
347 | if (-1 == fseek(f, 0, SEEK_END)) { | |
47f4f073 | 348 | sr_err("fseek on %s failed", filename); |
28a35d8a | 349 | fclose(f); |
b53738ba | 350 | return SR_ERR; |
28a35d8a HE |
351 | } |
352 | ||
353 | file_size = ftell(f); | |
354 | ||
355 | fseek(f, 0, SEEK_SET); | |
356 | ||
b53738ba | 357 | if (!(firmware = g_try_malloc(buffer_size))) { |
47f4f073 | 358 | sr_err("%s: firmware malloc failed", __func__); |
12ad53f5 | 359 | fclose(f); |
b53738ba | 360 | return SR_ERR_MALLOC; |
28a35d8a HE |
361 | } |
362 | ||
28a35d8a HE |
363 | while ((c = getc(f)) != EOF) { |
364 | imm = (imm + 0xa853753) % 177 + (imm * 0x8034052); | |
e3fff420 | 365 | firmware[fwsize++] = c ^ imm; |
28a35d8a HE |
366 | } |
367 | fclose(f); | |
368 | ||
e3fff420 | 369 | if(fwsize != file_size) { |
47f4f073 | 370 | sr_err("%s: Error reading firmware", filename); |
e3fff420 HE |
371 | fclose(f); |
372 | g_free(firmware); | |
373 | return SR_ERR; | |
28a35d8a HE |
374 | } |
375 | ||
28a35d8a HE |
376 | *buf_size = fwsize * 2 * 8; |
377 | ||
b53738ba | 378 | *buf = p = (unsigned char *)g_try_malloc(*buf_size); |
28a35d8a | 379 | if (!p) { |
47f4f073 | 380 | sr_err("%s: buf/p malloc failed", __func__); |
12ad53f5 | 381 | g_free(firmware); |
b53738ba | 382 | return SR_ERR_MALLOC; |
28a35d8a HE |
383 | } |
384 | ||
385 | for (i = 0; i < fwsize; ++i) { | |
28a35d8a | 386 | for (bit = 7; bit >= 0; --bit) { |
fefa1800 | 387 | v = firmware[i] & 1 << bit ? 0x40 : 0x00; |
28a35d8a HE |
388 | p[offset++] = v | 0x01; |
389 | p[offset++] = v; | |
390 | } | |
391 | } | |
392 | ||
393 | g_free(firmware); | |
394 | ||
395 | if (offset != *buf_size) { | |
396 | g_free(*buf); | |
47f4f073 | 397 | sr_err("Error reading firmware %s " |
0aeb0ccd | 398 | "offset=%ld, file_size=%ld, buf_size=%zd.", |
133a37bf | 399 | filename, offset, file_size, *buf_size); |
28a35d8a | 400 | |
b53738ba | 401 | return SR_ERR; |
28a35d8a HE |
402 | } |
403 | ||
b53738ba | 404 | return SR_OK; |
28a35d8a HE |
405 | } |
406 | ||
811deee4 | 407 | static int clear_instances(void) |
0448d110 BV |
408 | { |
409 | GSList *l; | |
410 | struct sr_dev_inst *sdi; | |
0e1357e8 BV |
411 | struct drv_context *drvc; |
412 | struct dev_context *devc; | |
413 | ||
a873c594 | 414 | drvc = di->priv; |
0448d110 BV |
415 | |
416 | /* Properly close all devices. */ | |
0e1357e8 | 417 | for (l = drvc->instances; l; l = l->next) { |
0448d110 BV |
418 | if (!(sdi = l->data)) { |
419 | /* Log error, but continue cleaning up the rest. */ | |
47f4f073 | 420 | sr_err("%s: sdi was NULL, continuing", __func__); |
0448d110 BV |
421 | continue; |
422 | } | |
423 | if (sdi->priv) { | |
0e1357e8 BV |
424 | devc = sdi->priv; |
425 | ftdi_free(&devc->ftdic); | |
0448d110 BV |
426 | } |
427 | sr_dev_inst_free(sdi); | |
428 | } | |
0e1357e8 BV |
429 | g_slist_free(drvc->instances); |
430 | drvc->instances = NULL; | |
0448d110 | 431 | |
811deee4 | 432 | return SR_OK; |
0448d110 BV |
433 | } |
434 | ||
34f06b90 | 435 | static int hw_init(struct sr_context *sr_ctx) |
61136ea6 | 436 | { |
b32503cc | 437 | struct drv_context *drvc; |
61136ea6 | 438 | |
b32503cc | 439 | if (!(drvc = g_try_malloc0(sizeof(struct drv_context)))) { |
47f4f073 | 440 | sr_err("Driver context malloc failed."); |
886a52b6 | 441 | return SR_ERR_MALLOC; |
b32503cc | 442 | } |
1ebe4b4e | 443 | drvc->sr_ctx = sr_ctx; |
a873c594 | 444 | di->priv = drvc; |
61136ea6 BV |
445 | |
446 | return SR_OK; | |
447 | } | |
448 | ||
0448d110 | 449 | static GSList *hw_scan(GSList *options) |
28a35d8a | 450 | { |
d68e2d1a | 451 | struct sr_dev_inst *sdi; |
87ca93c5 | 452 | struct sr_probe *probe; |
0e1357e8 BV |
453 | struct drv_context *drvc; |
454 | struct dev_context *devc; | |
0448d110 | 455 | GSList *devices; |
e3fff420 HE |
456 | struct ftdi_device_list *devlist; |
457 | char serial_txt[10]; | |
458 | uint32_t serial; | |
87ca93c5 | 459 | int ret, i; |
28a35d8a | 460 | |
0448d110 | 461 | (void)options; |
64d33dc2 | 462 | |
a873c594 | 463 | drvc = di->priv; |
0448d110 BV |
464 | devices = NULL; |
465 | clear_instances(); | |
466 | ||
0e1357e8 | 467 | if (!(devc = g_try_malloc(sizeof(struct dev_context)))) { |
47f4f073 | 468 | sr_err("%s: devc malloc failed", __func__); |
0448d110 | 469 | return NULL; |
b53738ba | 470 | } |
99965709 | 471 | |
0e1357e8 | 472 | ftdi_init(&devc->ftdic); |
28a35d8a | 473 | |
fefa1800 | 474 | /* Look for SIGMAs. */ |
e3fff420 | 475 | |
0e1357e8 | 476 | if ((ret = ftdi_usb_find_all(&devc->ftdic, &devlist, |
eec944c5 BV |
477 | USB_VENDOR, USB_PRODUCT)) <= 0) { |
478 | if (ret < 0) | |
479 | sr_err("ftdi_usb_find_all(): %d", ret); | |
99965709 | 480 | goto free; |
eec944c5 | 481 | } |
99965709 | 482 | |
e3fff420 | 483 | /* Make sure it's a version 1 or 2 SIGMA. */ |
0e1357e8 | 484 | ftdi_usb_get_strings(&devc->ftdic, devlist->dev, NULL, 0, NULL, 0, |
6352d030 | 485 | serial_txt, sizeof(serial_txt)); |
e3fff420 HE |
486 | sscanf(serial_txt, "%x", &serial); |
487 | ||
6352d030 | 488 | if (serial < 0xa6010000 || serial > 0xa602ffff) { |
47f4f073 UH |
489 | sr_err("Only SIGMA and SIGMA2 are supported " |
490 | "in this version of libsigrok."); | |
e3fff420 HE |
491 | goto free; |
492 | } | |
493 | ||
494 | sr_info("Found ASIX SIGMA - Serial: %s", serial_txt); | |
495 | ||
0e1357e8 BV |
496 | devc->cur_samplerate = 0; |
497 | devc->period_ps = 0; | |
498 | devc->limit_msec = 0; | |
499 | devc->cur_firmware = -1; | |
500 | devc->num_probes = 0; | |
501 | devc->samples_per_event = 0; | |
502 | devc->capture_ratio = 50; | |
503 | devc->use_triggers = 0; | |
28a35d8a | 504 | |
fefa1800 | 505 | /* Register SIGMA device. */ |
d68e2d1a UH |
506 | if (!(sdi = sr_dev_inst_new(0, SR_ST_INITIALIZING, USB_VENDOR_NAME, |
507 | USB_MODEL_NAME, USB_MODEL_VERSION))) { | |
47f4f073 | 508 | sr_err("%s: sdi was NULL", __func__); |
99965709 | 509 | goto free; |
d68e2d1a | 510 | } |
a873c594 | 511 | sdi->driver = di; |
87ca93c5 BV |
512 | |
513 | for (i = 0; probe_names[i]; i++) { | |
de6e0eca | 514 | if (!(probe = sr_probe_new(i, SR_PROBE_LOGIC, TRUE, |
87ca93c5 BV |
515 | probe_names[i]))) |
516 | return NULL; | |
517 | sdi->probes = g_slist_append(sdi->probes, probe); | |
518 | } | |
519 | ||
0448d110 | 520 | devices = g_slist_append(devices, sdi); |
0e1357e8 BV |
521 | drvc->instances = g_slist_append(drvc->instances, sdi); |
522 | sdi->priv = devc; | |
28a35d8a | 523 | |
fefa1800 | 524 | /* We will open the device again when we need it. */ |
e3fff420 | 525 | ftdi_list_free(&devlist); |
28a35d8a | 526 | |
0448d110 | 527 | return devices; |
ea9cfed7 | 528 | |
99965709 | 529 | free: |
0e1357e8 BV |
530 | ftdi_deinit(&devc->ftdic); |
531 | g_free(devc); | |
0448d110 | 532 | return NULL; |
28a35d8a HE |
533 | } |
534 | ||
811deee4 BV |
535 | static GSList *hw_dev_list(void) |
536 | { | |
537 | struct drv_context *drvc; | |
538 | ||
a873c594 | 539 | drvc = di->priv; |
811deee4 BV |
540 | |
541 | return drvc->instances; | |
542 | } | |
543 | ||
0e1357e8 | 544 | static int upload_firmware(int firmware_idx, struct dev_context *devc) |
28a35d8a HE |
545 | { |
546 | int ret; | |
547 | unsigned char *buf; | |
548 | unsigned char pins; | |
549 | size_t buf_size; | |
28a35d8a | 550 | unsigned char result[32]; |
e8397563 | 551 | char firmware_path[128]; |
28a35d8a | 552 | |
fefa1800 | 553 | /* Make sure it's an ASIX SIGMA. */ |
0e1357e8 | 554 | if ((ret = ftdi_usb_open_desc(&devc->ftdic, |
28a35d8a | 555 | USB_VENDOR, USB_PRODUCT, USB_DESCRIPTION, NULL)) < 0) { |
47f4f073 | 556 | sr_err("ftdi_usb_open failed: %s", |
0e1357e8 | 557 | ftdi_get_error_string(&devc->ftdic)); |
28a35d8a HE |
558 | return 0; |
559 | } | |
560 | ||
0e1357e8 | 561 | if ((ret = ftdi_set_bitmode(&devc->ftdic, 0xdf, BITMODE_BITBANG)) < 0) { |
47f4f073 | 562 | sr_err("ftdi_set_bitmode failed: %s", |
0e1357e8 | 563 | ftdi_get_error_string(&devc->ftdic)); |
28a35d8a HE |
564 | return 0; |
565 | } | |
566 | ||
fefa1800 | 567 | /* Four times the speed of sigmalogan - Works well. */ |
0e1357e8 | 568 | if ((ret = ftdi_set_baudrate(&devc->ftdic, 750000)) < 0) { |
47f4f073 | 569 | sr_err("ftdi_set_baudrate failed: %s", |
0e1357e8 | 570 | ftdi_get_error_string(&devc->ftdic)); |
28a35d8a HE |
571 | return 0; |
572 | } | |
573 | ||
fefa1800 | 574 | /* Force the FPGA to reboot. */ |
0e1357e8 BV |
575 | sigma_write(suicide, sizeof(suicide), devc); |
576 | sigma_write(suicide, sizeof(suicide), devc); | |
577 | sigma_write(suicide, sizeof(suicide), devc); | |
578 | sigma_write(suicide, sizeof(suicide), devc); | |
28a35d8a | 579 | |
fefa1800 | 580 | /* Prepare to upload firmware (FPGA specific). */ |
0e1357e8 | 581 | sigma_write(init, sizeof(init), devc); |
28a35d8a | 582 | |
0e1357e8 | 583 | ftdi_usb_purge_buffers(&devc->ftdic); |
28a35d8a | 584 | |
fefa1800 | 585 | /* Wait until the FPGA asserts INIT_B. */ |
28a35d8a | 586 | while (1) { |
0e1357e8 | 587 | ret = sigma_read(result, 1, devc); |
28a35d8a HE |
588 | if (result[0] & 0x20) |
589 | break; | |
590 | } | |
591 | ||
9ddb2a12 | 592 | /* Prepare firmware. */ |
e8397563 | 593 | snprintf(firmware_path, sizeof(firmware_path), "%s/%s", FIRMWARE_DIR, |
f6564c8d HE |
594 | firmware_files[firmware_idx]); |
595 | ||
b53738ba | 596 | if ((ret = bin2bitbang(firmware_path, &buf, &buf_size)) != SR_OK) { |
47f4f073 | 597 | sr_err("An error occured while reading the firmware: %s", |
133a37bf | 598 | firmware_path); |
b53738ba | 599 | return ret; |
28a35d8a HE |
600 | } |
601 | ||
fefa1800 | 602 | /* Upload firmare. */ |
47f4f073 | 603 | sr_info("Uploading firmware file '%s'.", firmware_files[firmware_idx]); |
0e1357e8 | 604 | sigma_write(buf, buf_size, devc); |
28a35d8a HE |
605 | |
606 | g_free(buf); | |
607 | ||
0e1357e8 | 608 | if ((ret = ftdi_set_bitmode(&devc->ftdic, 0x00, BITMODE_RESET)) < 0) { |
47f4f073 | 609 | sr_err("ftdi_set_bitmode failed: %s", |
0e1357e8 | 610 | ftdi_get_error_string(&devc->ftdic)); |
e46b8fb1 | 611 | return SR_ERR; |
28a35d8a HE |
612 | } |
613 | ||
0e1357e8 | 614 | ftdi_usb_purge_buffers(&devc->ftdic); |
28a35d8a | 615 | |
fefa1800 | 616 | /* Discard garbage. */ |
0e1357e8 | 617 | while (1 == sigma_read(&pins, 1, devc)) |
28a35d8a HE |
618 | ; |
619 | ||
fefa1800 | 620 | /* Initialize the logic analyzer mode. */ |
0e1357e8 | 621 | sigma_write(logic_mode_start, sizeof(logic_mode_start), devc); |
28a35d8a | 622 | |
fefa1800 | 623 | /* Expect a 3 byte reply. */ |
0e1357e8 | 624 | ret = sigma_read(result, 3, devc); |
28a35d8a HE |
625 | if (ret != 3 || |
626 | result[0] != 0xa6 || result[1] != 0x55 || result[2] != 0xaa) { | |
47f4f073 | 627 | sr_err("Configuration failed. Invalid reply received."); |
e46b8fb1 | 628 | return SR_ERR; |
28a35d8a HE |
629 | } |
630 | ||
0e1357e8 | 631 | devc->cur_firmware = firmware_idx; |
f6564c8d | 632 | |
47f4f073 | 633 | sr_info("Firmware uploaded."); |
e3fff420 | 634 | |
e46b8fb1 | 635 | return SR_OK; |
f6564c8d HE |
636 | } |
637 | ||
25a0f108 | 638 | static int hw_dev_open(struct sr_dev_inst *sdi) |
f6564c8d | 639 | { |
0e1357e8 | 640 | struct dev_context *devc; |
f6564c8d HE |
641 | int ret; |
642 | ||
0e1357e8 | 643 | devc = sdi->priv; |
99965709 | 644 | |
9ddb2a12 | 645 | /* Make sure it's an ASIX SIGMA. */ |
0e1357e8 | 646 | if ((ret = ftdi_usb_open_desc(&devc->ftdic, |
f6564c8d HE |
647 | USB_VENDOR, USB_PRODUCT, USB_DESCRIPTION, NULL)) < 0) { |
648 | ||
47f4f073 | 649 | sr_err("ftdi_usb_open failed: %s", |
0e1357e8 | 650 | ftdi_get_error_string(&devc->ftdic)); |
f6564c8d HE |
651 | |
652 | return 0; | |
653 | } | |
28a35d8a | 654 | |
5a2326a7 | 655 | sdi->status = SR_ST_ACTIVE; |
28a35d8a | 656 | |
e46b8fb1 | 657 | return SR_OK; |
f6564c8d HE |
658 | } |
659 | ||
6f4b1868 | 660 | static int set_samplerate(const struct sr_dev_inst *sdi, uint64_t samplerate) |
f6564c8d | 661 | { |
e8397563 | 662 | int i, ret; |
0e1357e8 | 663 | struct dev_context *devc = sdi->priv; |
f6564c8d HE |
664 | |
665 | for (i = 0; supported_samplerates[i]; i++) { | |
666 | if (supported_samplerates[i] == samplerate) | |
667 | break; | |
668 | } | |
669 | if (supported_samplerates[i] == 0) | |
e46b8fb1 | 670 | return SR_ERR_SAMPLERATE; |
f6564c8d | 671 | |
59df0c77 | 672 | if (samplerate <= SR_MHZ(50)) { |
0e1357e8 BV |
673 | ret = upload_firmware(0, devc); |
674 | devc->num_probes = 16; | |
e8397563 | 675 | } |
59df0c77 | 676 | if (samplerate == SR_MHZ(100)) { |
0e1357e8 BV |
677 | ret = upload_firmware(1, devc); |
678 | devc->num_probes = 8; | |
f78898e9 | 679 | } |
59df0c77 | 680 | else if (samplerate == SR_MHZ(200)) { |
0e1357e8 BV |
681 | ret = upload_firmware(2, devc); |
682 | devc->num_probes = 4; | |
f78898e9 | 683 | } |
f6564c8d | 684 | |
0e1357e8 BV |
685 | devc->cur_samplerate = samplerate; |
686 | devc->period_ps = 1000000000000 / samplerate; | |
687 | devc->samples_per_event = 16 / devc->num_probes; | |
688 | devc->state.state = SIGMA_IDLE; | |
f6564c8d | 689 | |
e8397563 | 690 | return ret; |
28a35d8a HE |
691 | } |
692 | ||
c53d793f HE |
693 | /* |
694 | * In 100 and 200 MHz mode, only a single pin rising/falling can be | |
695 | * set as trigger. In other modes, two rising/falling triggers can be set, | |
696 | * in addition to value/mask trigger for any number of probes. | |
697 | * | |
698 | * The Sigma supports complex triggers using boolean expressions, but this | |
699 | * has not been implemented yet. | |
700 | */ | |
014359e3 | 701 | static int configure_probes(const struct sr_dev_inst *sdi) |
57bbf56b | 702 | { |
0e1357e8 | 703 | struct dev_context *devc = sdi->priv; |
1b79df2f JH |
704 | const struct sr_probe *probe; |
705 | const GSList *l; | |
57bbf56b | 706 | int trigger_set = 0; |
a42aec7f | 707 | int probebit; |
57bbf56b | 708 | |
0e1357e8 | 709 | memset(&devc->trigger, 0, sizeof(struct sigma_trigger)); |
eec5275e | 710 | |
014359e3 | 711 | for (l = sdi->probes; l; l = l->next) { |
1afe8989 | 712 | probe = (struct sr_probe *)l->data; |
b35c8293 | 713 | probebit = 1 << (probe->index); |
57bbf56b HE |
714 | |
715 | if (!probe->enabled || !probe->trigger) | |
716 | continue; | |
717 | ||
0e1357e8 | 718 | if (devc->cur_samplerate >= SR_MHZ(100)) { |
c53d793f | 719 | /* Fast trigger support. */ |
ee492173 | 720 | if (trigger_set) { |
47f4f073 UH |
721 | sr_err("Only a single pin trigger in 100 and " |
722 | "200MHz mode is supported."); | |
e46b8fb1 | 723 | return SR_ERR; |
ee492173 HE |
724 | } |
725 | if (probe->trigger[0] == 'f') | |
0e1357e8 | 726 | devc->trigger.fallingmask |= probebit; |
ee492173 | 727 | else if (probe->trigger[0] == 'r') |
0e1357e8 | 728 | devc->trigger.risingmask |= probebit; |
ee492173 | 729 | else { |
47f4f073 UH |
730 | sr_err("Only rising/falling trigger in 100 " |
731 | "and 200MHz mode is supported."); | |
e46b8fb1 | 732 | return SR_ERR; |
ee492173 | 733 | } |
57bbf56b | 734 | |
c53d793f | 735 | ++trigger_set; |
ee492173 | 736 | } else { |
c53d793f HE |
737 | /* Simple trigger support (event). */ |
738 | if (probe->trigger[0] == '1') { | |
0e1357e8 BV |
739 | devc->trigger.simplevalue |= probebit; |
740 | devc->trigger.simplemask |= probebit; | |
c53d793f HE |
741 | } |
742 | else if (probe->trigger[0] == '0') { | |
0e1357e8 BV |
743 | devc->trigger.simplevalue &= ~probebit; |
744 | devc->trigger.simplemask |= probebit; | |
c53d793f HE |
745 | } |
746 | else if (probe->trigger[0] == 'f') { | |
0e1357e8 | 747 | devc->trigger.fallingmask |= probebit; |
c53d793f HE |
748 | ++trigger_set; |
749 | } | |
750 | else if (probe->trigger[0] == 'r') { | |
0e1357e8 | 751 | devc->trigger.risingmask |= probebit; |
c53d793f HE |
752 | ++trigger_set; |
753 | } | |
ee492173 | 754 | |
ea9cfed7 UH |
755 | /* |
756 | * Actually, Sigma supports 2 rising/falling triggers, | |
757 | * but they are ORed and the current trigger syntax | |
758 | * does not permit ORed triggers. | |
759 | */ | |
98b8cbc1 | 760 | if (trigger_set > 1) { |
47f4f073 UH |
761 | sr_err("Only 1 rising/falling trigger " |
762 | "is supported."); | |
e46b8fb1 | 763 | return SR_ERR; |
ee492173 | 764 | } |
ee492173 | 765 | } |
5b5ea7c6 HE |
766 | |
767 | if (trigger_set) | |
0e1357e8 | 768 | devc->use_triggers = 1; |
57bbf56b HE |
769 | } |
770 | ||
e46b8fb1 | 771 | return SR_OK; |
57bbf56b HE |
772 | } |
773 | ||
25a0f108 | 774 | static int hw_dev_close(struct sr_dev_inst *sdi) |
28a35d8a | 775 | { |
0e1357e8 | 776 | struct dev_context *devc; |
28a35d8a | 777 | |
0e1357e8 | 778 | if (!(devc = sdi->priv)) { |
47f4f073 | 779 | sr_err("%s: sdi->priv was NULL", __func__); |
0abee507 | 780 | return SR_ERR_BUG; |
9be9893e | 781 | } |
697785d1 UH |
782 | |
783 | /* TODO */ | |
784 | if (sdi->status == SR_ST_ACTIVE) | |
0e1357e8 | 785 | ftdi_usb_close(&devc->ftdic); |
697785d1 UH |
786 | |
787 | sdi->status = SR_ST_INACTIVE; | |
788 | ||
789 | return SR_OK; | |
28a35d8a HE |
790 | } |
791 | ||
57ab7d9f | 792 | static int hw_cleanup(void) |
28a35d8a | 793 | { |
a873c594 | 794 | if (!di->priv) |
b32503cc BV |
795 | return SR_OK; |
796 | ||
0448d110 | 797 | clear_instances(); |
57ab7d9f | 798 | |
0448d110 | 799 | return SR_OK; |
28a35d8a HE |
800 | } |
801 | ||
41479605 | 802 | static int hw_info_get(int info_id, const void **data, |
47f4f073 | 803 | const struct sr_dev_inst *sdi) |
28a35d8a | 804 | { |
0e1357e8 | 805 | struct dev_context *devc; |
99965709 | 806 | |
41479605 | 807 | switch (info_id) { |
b2b5445c BV |
808 | case SR_DI_HWCAPS: |
809 | *data = hwcaps; | |
810 | break; | |
5a2326a7 | 811 | case SR_DI_NUM_PROBES: |
41479605 | 812 | *data = GINT_TO_POINTER(NUM_PROBES); |
464d12c7 KS |
813 | break; |
814 | case SR_DI_PROBE_NAMES: | |
41479605 | 815 | *data = probe_names; |
28a35d8a | 816 | break; |
5a2326a7 | 817 | case SR_DI_SAMPLERATES: |
41479605 | 818 | *data = &samplerates; |
28a35d8a | 819 | break; |
5a2326a7 | 820 | case SR_DI_TRIGGER_TYPES: |
41479605 | 821 | *data = (char *)TRIGGER_TYPES; |
28a35d8a | 822 | break; |
5a2326a7 | 823 | case SR_DI_CUR_SAMPLERATE: |
41479605 | 824 | if (sdi) { |
0e1357e8 BV |
825 | devc = sdi->priv; |
826 | *data = &devc->cur_samplerate; | |
41479605 BV |
827 | } else |
828 | return SR_ERR; | |
28a35d8a | 829 | break; |
d7bbecfd BV |
830 | default: |
831 | return SR_ERR_ARG; | |
28a35d8a HE |
832 | } |
833 | ||
41479605 | 834 | return SR_OK; |
28a35d8a HE |
835 | } |
836 | ||
6f4b1868 | 837 | static int hw_dev_config_set(const struct sr_dev_inst *sdi, int hwcap, |
47f4f073 | 838 | const void *value) |
28a35d8a | 839 | { |
0e1357e8 | 840 | struct dev_context *devc; |
28a35d8a | 841 | int ret; |
f6564c8d | 842 | |
0e1357e8 | 843 | devc = sdi->priv; |
99965709 | 844 | |
ffedd0bf | 845 | if (hwcap == SR_HWCAP_SAMPLERATE) { |
1b79df2f | 846 | ret = set_samplerate(sdi, *(const uint64_t *)value); |
ffedd0bf | 847 | } else if (hwcap == SR_HWCAP_LIMIT_MSEC) { |
0e1357e8 BV |
848 | devc->limit_msec = *(const uint64_t *)value; |
849 | if (devc->limit_msec > 0) | |
e46b8fb1 | 850 | ret = SR_OK; |
94ba4bd6 | 851 | else |
e46b8fb1 | 852 | ret = SR_ERR; |
ffedd0bf | 853 | } else if (hwcap == SR_HWCAP_CAPTURE_RATIO) { |
0e1357e8 BV |
854 | devc->capture_ratio = *(const uint64_t *)value; |
855 | if (devc->capture_ratio < 0 || devc->capture_ratio > 100) | |
e46b8fb1 | 856 | ret = SR_ERR; |
94ba4bd6 | 857 | else |
e46b8fb1 | 858 | ret = SR_OK; |
28a35d8a | 859 | } else { |
e46b8fb1 | 860 | ret = SR_ERR; |
28a35d8a HE |
861 | } |
862 | ||
863 | return ret; | |
864 | } | |
865 | ||
36b1c8e6 HE |
866 | /* Software trigger to determine exact trigger position. */ |
867 | static int get_trigger_offset(uint16_t *samples, uint16_t last_sample, | |
868 | struct sigma_trigger *t) | |
869 | { | |
870 | int i; | |
871 | ||
872 | for (i = 0; i < 8; ++i) { | |
873 | if (i > 0) | |
874 | last_sample = samples[i-1]; | |
875 | ||
876 | /* Simple triggers. */ | |
877 | if ((samples[i] & t->simplemask) != t->simplevalue) | |
878 | continue; | |
879 | ||
880 | /* Rising edge. */ | |
881 | if ((last_sample & t->risingmask) != 0 || (samples[i] & | |
882 | t->risingmask) != t->risingmask) | |
883 | continue; | |
884 | ||
885 | /* Falling edge. */ | |
bdfc7a89 HE |
886 | if ((last_sample & t->fallingmask) != t->fallingmask || |
887 | (samples[i] & t->fallingmask) != 0) | |
36b1c8e6 HE |
888 | continue; |
889 | ||
890 | break; | |
891 | } | |
892 | ||
893 | /* If we did not match, return original trigger pos. */ | |
894 | return i & 0x7; | |
895 | } | |
896 | ||
28a35d8a | 897 | /* |
fefa1800 UH |
898 | * Decode chunk of 1024 bytes, 64 clusters, 7 events per cluster. |
899 | * Each event is 20ns apart, and can contain multiple samples. | |
f78898e9 HE |
900 | * |
901 | * For 200 MHz, events contain 4 samples for each channel, spread 5 ns apart. | |
902 | * For 100 MHz, events contain 2 samples for each channel, spread 10 ns apart. | |
903 | * For 50 MHz and below, events contain one sample for each channel, | |
904 | * spread 20 ns apart. | |
28a35d8a HE |
905 | */ |
906 | static int decode_chunk_ts(uint8_t *buf, uint16_t *lastts, | |
88c51afe | 907 | uint16_t *lastsample, int triggerpos, |
3cd3a20b | 908 | uint16_t limit_chunk, void *cb_data) |
28a35d8a | 909 | { |
3cd3a20b | 910 | struct sr_dev_inst *sdi = cb_data; |
0e1357e8 | 911 | struct dev_context *devc = sdi->priv; |
fefa1800 | 912 | uint16_t tsdiff, ts; |
0e1357e8 | 913 | uint16_t samples[65536 * devc->samples_per_event]; |
b9c735a2 | 914 | struct sr_datafeed_packet packet; |
9c939c51 | 915 | struct sr_datafeed_logic logic; |
f78898e9 | 916 | int i, j, k, l, numpad, tosend; |
fefa1800 | 917 | size_t n = 0, sent = 0; |
0e1357e8 | 918 | int clustersize = EVENTS_PER_CLUSTER * devc->samples_per_event; |
fefa1800 | 919 | uint16_t *event; |
f78898e9 | 920 | uint16_t cur_sample; |
57bbf56b | 921 | int triggerts = -1; |
ee492173 | 922 | |
4ae1f451 | 923 | /* Check if trigger is in this chunk. */ |
ee492173 | 924 | if (triggerpos != -1) { |
0e1357e8 | 925 | if (devc->cur_samplerate <= SR_MHZ(50)) |
36b1c8e6 | 926 | triggerpos -= EVENTS_PER_CLUSTER - 1; |
ee492173 HE |
927 | |
928 | if (triggerpos < 0) | |
929 | triggerpos = 0; | |
57bbf56b | 930 | |
ee492173 HE |
931 | /* Find in which cluster the trigger occured. */ |
932 | triggerts = triggerpos / 7; | |
933 | } | |
28a35d8a | 934 | |
eec5275e | 935 | /* For each ts. */ |
28a35d8a | 936 | for (i = 0; i < 64; ++i) { |
fefa1800 | 937 | ts = *(uint16_t *) &buf[i * 16]; |
28a35d8a HE |
938 | tsdiff = ts - *lastts; |
939 | *lastts = ts; | |
940 | ||
88c51afe HE |
941 | /* Decode partial chunk. */ |
942 | if (limit_chunk && ts > limit_chunk) | |
e46b8fb1 | 943 | return SR_OK; |
88c51afe | 944 | |
fefa1800 | 945 | /* Pad last sample up to current point. */ |
0e1357e8 | 946 | numpad = tsdiff * devc->samples_per_event - clustersize; |
28a35d8a | 947 | if (numpad > 0) { |
f78898e9 HE |
948 | for (j = 0; j < numpad; ++j) |
949 | samples[j] = *lastsample; | |
950 | ||
951 | n = numpad; | |
28a35d8a HE |
952 | } |
953 | ||
57bbf56b HE |
954 | /* Send samples between previous and this timestamp to sigrok. */ |
955 | sent = 0; | |
956 | while (sent < n) { | |
957 | tosend = MIN(2048, n - sent); | |
958 | ||
5a2326a7 | 959 | packet.type = SR_DF_LOGIC; |
9c939c51 BV |
960 | packet.payload = &logic; |
961 | logic.length = tosend * sizeof(uint16_t); | |
962 | logic.unitsize = 2; | |
963 | logic.data = samples + sent; | |
0e1357e8 | 964 | sr_session_send(devc->session_dev_id, &packet); |
28a35d8a | 965 | |
57bbf56b HE |
966 | sent += tosend; |
967 | } | |
968 | n = 0; | |
969 | ||
970 | event = (uint16_t *) &buf[i * 16 + 2]; | |
f78898e9 HE |
971 | cur_sample = 0; |
972 | ||
973 | /* For each event in cluster. */ | |
28a35d8a | 974 | for (j = 0; j < 7; ++j) { |
f78898e9 HE |
975 | |
976 | /* For each sample in event. */ | |
0e1357e8 | 977 | for (k = 0; k < devc->samples_per_event; ++k) { |
f78898e9 HE |
978 | cur_sample = 0; |
979 | ||
980 | /* For each probe. */ | |
0e1357e8 | 981 | for (l = 0; l < devc->num_probes; ++l) |
edca2c5c | 982 | cur_sample |= (!!(event[j] & (1 << (l * |
0e1357e8 | 983 | devc->samples_per_event + k)))) << l; |
f78898e9 HE |
984 | |
985 | samples[n++] = cur_sample; | |
28a35d8a HE |
986 | } |
987 | } | |
988 | ||
eec5275e | 989 | /* Send data up to trigger point (if triggered). */ |
fefa1800 | 990 | sent = 0; |
57bbf56b HE |
991 | if (i == triggerts) { |
992 | /* | |
36b1c8e6 HE |
993 | * Trigger is not always accurate to sample because of |
994 | * pipeline delay. However, it always triggers before | |
995 | * the actual event. We therefore look at the next | |
996 | * samples to pinpoint the exact position of the trigger. | |
57bbf56b | 997 | */ |
bdfc7a89 | 998 | tosend = get_trigger_offset(samples, *lastsample, |
0e1357e8 | 999 | &devc->trigger); |
57bbf56b HE |
1000 | |
1001 | if (tosend > 0) { | |
5a2326a7 | 1002 | packet.type = SR_DF_LOGIC; |
9c939c51 BV |
1003 | packet.payload = &logic; |
1004 | logic.length = tosend * sizeof(uint16_t); | |
1005 | logic.unitsize = 2; | |
1006 | logic.data = samples; | |
0e1357e8 | 1007 | sr_session_send(devc->session_dev_id, &packet); |
57bbf56b HE |
1008 | |
1009 | sent += tosend; | |
1010 | } | |
28a35d8a | 1011 | |
5b5ea7c6 | 1012 | /* Only send trigger if explicitly enabled. */ |
0e1357e8 | 1013 | if (devc->use_triggers) { |
5a2326a7 | 1014 | packet.type = SR_DF_TRIGGER; |
0e1357e8 | 1015 | sr_session_send(devc->session_dev_id, &packet); |
5b5ea7c6 | 1016 | } |
28a35d8a | 1017 | } |
57bbf56b | 1018 | |
eec5275e | 1019 | /* Send rest of the chunk to sigrok. */ |
57bbf56b HE |
1020 | tosend = n - sent; |
1021 | ||
abda62ce | 1022 | if (tosend > 0) { |
5a2326a7 | 1023 | packet.type = SR_DF_LOGIC; |
9c939c51 BV |
1024 | packet.payload = &logic; |
1025 | logic.length = tosend * sizeof(uint16_t); | |
1026 | logic.unitsize = 2; | |
1027 | logic.data = samples + sent; | |
0e1357e8 | 1028 | sr_session_send(devc->session_dev_id, &packet); |
abda62ce | 1029 | } |
ee492173 HE |
1030 | |
1031 | *lastsample = samples[n - 1]; | |
28a35d8a HE |
1032 | } |
1033 | ||
e46b8fb1 | 1034 | return SR_OK; |
28a35d8a HE |
1035 | } |
1036 | ||
1f9813eb | 1037 | static int receive_data(int fd, int revents, void *cb_data) |
28a35d8a | 1038 | { |
1f9813eb | 1039 | struct sr_dev_inst *sdi = cb_data; |
0e1357e8 | 1040 | struct dev_context *devc = sdi->priv; |
b9c735a2 | 1041 | struct sr_datafeed_packet packet; |
28a35d8a HE |
1042 | const int chunks_per_read = 32; |
1043 | unsigned char buf[chunks_per_read * CHUNK_SIZE]; | |
6aac7737 | 1044 | int bufsz, numchunks, i, newchunks; |
94ba4bd6 | 1045 | uint64_t running_msec; |
28a35d8a | 1046 | struct timeval tv; |
28a35d8a | 1047 | |
cb93f8a9 UH |
1048 | (void)fd; |
1049 | (void)revents; | |
28a35d8a | 1050 | |
805919b0 | 1051 | /* Get the current position. */ |
0e1357e8 | 1052 | sigma_read_pos(&devc->state.stoppos, &devc->state.triggerpos, devc); |
805919b0 | 1053 | |
0e1357e8 | 1054 | numchunks = (devc->state.stoppos + 511) / 512; |
28a35d8a | 1055 | |
0e1357e8 | 1056 | if (devc->state.state == SIGMA_IDLE) |
805919b0 | 1057 | return TRUE; |
28a35d8a | 1058 | |
0e1357e8 | 1059 | if (devc->state.state == SIGMA_CAPTURE) { |
6aac7737 HE |
1060 | /* Check if the timer has expired, or memory is full. */ |
1061 | gettimeofday(&tv, 0); | |
0e1357e8 BV |
1062 | running_msec = (tv.tv_sec - devc->start_tv.tv_sec) * 1000 + |
1063 | (tv.tv_usec - devc->start_tv.tv_usec) / 1000; | |
28a35d8a | 1064 | |
0e1357e8 | 1065 | if (running_msec < devc->limit_msec && numchunks < 32767) |
805919b0 | 1066 | return TRUE; /* While capturing... */ |
e3fff420 | 1067 | else |
3ffb6964 | 1068 | hw_dev_acquisition_stop(sdi, sdi); |
6aac7737 | 1069 | |
dc890b8f UH |
1070 | } |
1071 | ||
1072 | if (devc->state.state == SIGMA_DOWNLOAD) { | |
0e1357e8 | 1073 | if (devc->state.chunks_downloaded >= numchunks) { |
6aac7737 | 1074 | /* End of samples. */ |
5a2326a7 | 1075 | packet.type = SR_DF_END; |
0e1357e8 | 1076 | sr_session_send(devc->session_dev_id, &packet); |
6aac7737 | 1077 | |
0e1357e8 | 1078 | devc->state.state = SIGMA_IDLE; |
f78898e9 | 1079 | |
6aac7737 HE |
1080 | return TRUE; |
1081 | } | |
1082 | ||
1083 | newchunks = MIN(chunks_per_read, | |
0e1357e8 | 1084 | numchunks - devc->state.chunks_downloaded); |
28a35d8a | 1085 | |
47f4f073 | 1086 | sr_info("Downloading sample data: %.0f %%.", |
0e1357e8 | 1087 | 100.0 * devc->state.chunks_downloaded / numchunks); |
28a35d8a | 1088 | |
0e1357e8 BV |
1089 | bufsz = sigma_read_dram(devc->state.chunks_downloaded, |
1090 | newchunks, buf, devc); | |
719c5a93 UH |
1091 | /* TODO: Check bufsz. For now, just avoid compiler warnings. */ |
1092 | (void)bufsz; | |
28a35d8a | 1093 | |
fefa1800 | 1094 | /* Find first ts. */ |
0e1357e8 BV |
1095 | if (devc->state.chunks_downloaded == 0) { |
1096 | devc->state.lastts = *(uint16_t *) buf - 1; | |
1097 | devc->state.lastsample = 0; | |
6aac7737 | 1098 | } |
28a35d8a | 1099 | |
fefa1800 | 1100 | /* Decode chunks and send them to sigrok. */ |
28a35d8a | 1101 | for (i = 0; i < newchunks; ++i) { |
88c51afe HE |
1102 | int limit_chunk = 0; |
1103 | ||
1104 | /* The last chunk may potentially be only in part. */ | |
0e1357e8 | 1105 | if (devc->state.chunks_downloaded == numchunks - 1) { |
88c51afe | 1106 | /* Find the last valid timestamp */ |
0e1357e8 | 1107 | limit_chunk = devc->state.stoppos % 512 + devc->state.lastts; |
88c51afe HE |
1108 | } |
1109 | ||
0e1357e8 | 1110 | if (devc->state.chunks_downloaded + i == devc->state.triggerchunk) |
57bbf56b | 1111 | decode_chunk_ts(buf + (i * CHUNK_SIZE), |
0e1357e8 BV |
1112 | &devc->state.lastts, |
1113 | &devc->state.lastsample, | |
1114 | devc->state.triggerpos & 0x1ff, | |
1f9813eb | 1115 | limit_chunk, sdi); |
57bbf56b HE |
1116 | else |
1117 | decode_chunk_ts(buf + (i * CHUNK_SIZE), | |
0e1357e8 BV |
1118 | &devc->state.lastts, |
1119 | &devc->state.lastsample, | |
1f9813eb | 1120 | -1, limit_chunk, sdi); |
28a35d8a | 1121 | |
0e1357e8 | 1122 | ++devc->state.chunks_downloaded; |
88c51afe | 1123 | } |
28a35d8a HE |
1124 | } |
1125 | ||
28a35d8a HE |
1126 | return TRUE; |
1127 | } | |
1128 | ||
c53d793f HE |
1129 | /* Build a LUT entry used by the trigger functions. */ |
1130 | static void build_lut_entry(uint16_t value, uint16_t mask, uint16_t *entry) | |
ee492173 HE |
1131 | { |
1132 | int i, j, k, bit; | |
1133 | ||
f758d074 | 1134 | /* For each quad probe. */ |
ee492173 | 1135 | for (i = 0; i < 4; ++i) { |
c53d793f | 1136 | entry[i] = 0xffff; |
ee492173 | 1137 | |
f758d074 | 1138 | /* For each bit in LUT. */ |
ee492173 HE |
1139 | for (j = 0; j < 16; ++j) |
1140 | ||
f758d074 | 1141 | /* For each probe in quad. */ |
ee492173 HE |
1142 | for (k = 0; k < 4; ++k) { |
1143 | bit = 1 << (i * 4 + k); | |
1144 | ||
c53d793f HE |
1145 | /* Set bit in entry */ |
1146 | if ((mask & bit) && | |
1147 | ((!(value & bit)) != | |
4ae1f451 | 1148 | (!(j & (1 << k))))) |
c53d793f | 1149 | entry[i] &= ~(1 << j); |
ee492173 HE |
1150 | } |
1151 | } | |
c53d793f | 1152 | } |
ee492173 | 1153 | |
c53d793f HE |
1154 | /* Add a logical function to LUT mask. */ |
1155 | static void add_trigger_function(enum triggerop oper, enum triggerfunc func, | |
1156 | int index, int neg, uint16_t *mask) | |
1157 | { | |
1158 | int i, j; | |
1159 | int x[2][2], tmp, a, b, aset, bset, rset; | |
1160 | ||
1161 | memset(x, 0, 4 * sizeof(int)); | |
1162 | ||
1163 | /* Trigger detect condition. */ | |
1164 | switch (oper) { | |
1165 | case OP_LEVEL: | |
1166 | x[0][1] = 1; | |
1167 | x[1][1] = 1; | |
1168 | break; | |
1169 | case OP_NOT: | |
1170 | x[0][0] = 1; | |
1171 | x[1][0] = 1; | |
1172 | break; | |
1173 | case OP_RISE: | |
1174 | x[0][1] = 1; | |
1175 | break; | |
1176 | case OP_FALL: | |
1177 | x[1][0] = 1; | |
1178 | break; | |
1179 | case OP_RISEFALL: | |
1180 | x[0][1] = 1; | |
1181 | x[1][0] = 1; | |
1182 | break; | |
1183 | case OP_NOTRISE: | |
1184 | x[1][1] = 1; | |
1185 | x[0][0] = 1; | |
1186 | x[1][0] = 1; | |
1187 | break; | |
1188 | case OP_NOTFALL: | |
1189 | x[1][1] = 1; | |
1190 | x[0][0] = 1; | |
1191 | x[0][1] = 1; | |
1192 | break; | |
1193 | case OP_NOTRISEFALL: | |
1194 | x[1][1] = 1; | |
1195 | x[0][0] = 1; | |
1196 | break; | |
1197 | } | |
1198 | ||
1199 | /* Transpose if neg is set. */ | |
1200 | if (neg) { | |
ea9cfed7 | 1201 | for (i = 0; i < 2; ++i) { |
c53d793f HE |
1202 | for (j = 0; j < 2; ++j) { |
1203 | tmp = x[i][j]; | |
1204 | x[i][j] = x[1-i][1-j]; | |
1205 | x[1-i][1-j] = tmp; | |
1206 | } | |
ea9cfed7 | 1207 | } |
c53d793f HE |
1208 | } |
1209 | ||
1210 | /* Update mask with function. */ | |
1211 | for (i = 0; i < 16; ++i) { | |
1212 | a = (i >> (2 * index + 0)) & 1; | |
1213 | b = (i >> (2 * index + 1)) & 1; | |
1214 | ||
1215 | aset = (*mask >> i) & 1; | |
1216 | bset = x[b][a]; | |
1217 | ||
1218 | if (func == FUNC_AND || func == FUNC_NAND) | |
1219 | rset = aset & bset; | |
1220 | else if (func == FUNC_OR || func == FUNC_NOR) | |
1221 | rset = aset | bset; | |
1222 | else if (func == FUNC_XOR || func == FUNC_NXOR) | |
1223 | rset = aset ^ bset; | |
1224 | ||
1225 | if (func == FUNC_NAND || func == FUNC_NOR || func == FUNC_NXOR) | |
1226 | rset = !rset; | |
1227 | ||
1228 | *mask &= ~(1 << i); | |
1229 | ||
1230 | if (rset) | |
1231 | *mask |= 1 << i; | |
1232 | } | |
1233 | } | |
1234 | ||
1235 | /* | |
1236 | * Build trigger LUTs used by 50 MHz and lower sample rates for supporting | |
1237 | * simple pin change and state triggers. Only two transitions (rise/fall) can be | |
1238 | * set at any time, but a full mask and value can be set (0/1). | |
1239 | */ | |
0e1357e8 | 1240 | static int build_basic_trigger(struct triggerlut *lut, struct dev_context *devc) |
c53d793f HE |
1241 | { |
1242 | int i,j; | |
4ae1f451 | 1243 | uint16_t masks[2] = { 0, 0 }; |
c53d793f HE |
1244 | |
1245 | memset(lut, 0, sizeof(struct triggerlut)); | |
1246 | ||
1247 | /* Contant for simple triggers. */ | |
1248 | lut->m4 = 0xa000; | |
1249 | ||
1250 | /* Value/mask trigger support. */ | |
0e1357e8 | 1251 | build_lut_entry(devc->trigger.simplevalue, devc->trigger.simplemask, |
99965709 | 1252 | lut->m2d); |
c53d793f HE |
1253 | |
1254 | /* Rise/fall trigger support. */ | |
1255 | for (i = 0, j = 0; i < 16; ++i) { | |
0e1357e8 BV |
1256 | if (devc->trigger.risingmask & (1 << i) || |
1257 | devc->trigger.fallingmask & (1 << i)) | |
c53d793f HE |
1258 | masks[j++] = 1 << i; |
1259 | } | |
1260 | ||
1261 | build_lut_entry(masks[0], masks[0], lut->m0d); | |
1262 | build_lut_entry(masks[1], masks[1], lut->m1d); | |
1263 | ||
1264 | /* Add glue logic */ | |
1265 | if (masks[0] || masks[1]) { | |
1266 | /* Transition trigger. */ | |
0e1357e8 | 1267 | if (masks[0] & devc->trigger.risingmask) |
c53d793f | 1268 | add_trigger_function(OP_RISE, FUNC_OR, 0, 0, &lut->m3); |
0e1357e8 | 1269 | if (masks[0] & devc->trigger.fallingmask) |
c53d793f | 1270 | add_trigger_function(OP_FALL, FUNC_OR, 0, 0, &lut->m3); |
0e1357e8 | 1271 | if (masks[1] & devc->trigger.risingmask) |
c53d793f | 1272 | add_trigger_function(OP_RISE, FUNC_OR, 1, 0, &lut->m3); |
0e1357e8 | 1273 | if (masks[1] & devc->trigger.fallingmask) |
c53d793f HE |
1274 | add_trigger_function(OP_FALL, FUNC_OR, 1, 0, &lut->m3); |
1275 | } else { | |
1276 | /* Only value/mask trigger. */ | |
1277 | lut->m3 = 0xffff; | |
1278 | } | |
ee492173 | 1279 | |
c53d793f | 1280 | /* Triggertype: event. */ |
ee492173 HE |
1281 | lut->params.selres = 3; |
1282 | ||
e46b8fb1 | 1283 | return SR_OK; |
ee492173 HE |
1284 | } |
1285 | ||
3ffb6964 BV |
1286 | static int hw_dev_acquisition_start(const struct sr_dev_inst *sdi, |
1287 | void *cb_data) | |
28a35d8a | 1288 | { |
0e1357e8 | 1289 | struct dev_context *devc; |
3c36c403 HE |
1290 | struct sr_datafeed_packet *packet; |
1291 | struct sr_datafeed_header *header; | |
f366e86c | 1292 | struct sr_datafeed_meta_logic meta; |
9ddb2a12 | 1293 | struct clockselect_50 clockselect; |
82957b65 | 1294 | int frac, triggerpin, ret; |
57bbf56b HE |
1295 | uint8_t triggerselect; |
1296 | struct triggerinout triggerinout_conf; | |
ee492173 | 1297 | struct triggerlut lut; |
28a35d8a | 1298 | |
0e1357e8 | 1299 | devc = sdi->priv; |
28a35d8a | 1300 | |
014359e3 | 1301 | if (configure_probes(sdi) != SR_OK) { |
47f4f073 | 1302 | sr_err("Failed to configure probes."); |
014359e3 BV |
1303 | return SR_ERR; |
1304 | } | |
1305 | ||
ea9cfed7 | 1306 | /* If the samplerate has not been set, default to 200 kHz. */ |
0e1357e8 | 1307 | if (devc->cur_firmware == -1) { |
82957b65 UH |
1308 | if ((ret = set_samplerate(sdi, SR_KHZ(200))) != SR_OK) |
1309 | return ret; | |
1310 | } | |
e8397563 | 1311 | |
eec5275e | 1312 | /* Enter trigger programming mode. */ |
0e1357e8 | 1313 | sigma_set_register(WRITE_TRIGGER_SELECT1, 0x20, devc); |
28a35d8a | 1314 | |
eec5275e | 1315 | /* 100 and 200 MHz mode. */ |
0e1357e8 BV |
1316 | if (devc->cur_samplerate >= SR_MHZ(100)) { |
1317 | sigma_set_register(WRITE_TRIGGER_SELECT1, 0x81, devc); | |
57bbf56b | 1318 | |
a42aec7f HE |
1319 | /* Find which pin to trigger on from mask. */ |
1320 | for (triggerpin = 0; triggerpin < 8; ++triggerpin) | |
0e1357e8 | 1321 | if ((devc->trigger.risingmask | devc->trigger.fallingmask) & |
a42aec7f HE |
1322 | (1 << triggerpin)) |
1323 | break; | |
1324 | ||
1325 | /* Set trigger pin and light LED on trigger. */ | |
1326 | triggerselect = (1 << LEDSEL1) | (triggerpin & 0x7); | |
1327 | ||
1328 | /* Default rising edge. */ | |
0e1357e8 | 1329 | if (devc->trigger.fallingmask) |
a42aec7f | 1330 | triggerselect |= 1 << 3; |
57bbf56b | 1331 | |
eec5275e | 1332 | /* All other modes. */ |
0e1357e8 BV |
1333 | } else if (devc->cur_samplerate <= SR_MHZ(50)) { |
1334 | build_basic_trigger(&lut, devc); | |
ee492173 | 1335 | |
0e1357e8 | 1336 | sigma_write_trigger_lut(&lut, devc); |
57bbf56b HE |
1337 | |
1338 | triggerselect = (1 << LEDSEL1) | (1 << LEDSEL0); | |
1339 | } | |
1340 | ||
eec5275e | 1341 | /* Setup trigger in and out pins to default values. */ |
57bbf56b HE |
1342 | memset(&triggerinout_conf, 0, sizeof(struct triggerinout)); |
1343 | triggerinout_conf.trgout_bytrigger = 1; | |
1344 | triggerinout_conf.trgout_enable = 1; | |
1345 | ||
28a35d8a | 1346 | sigma_write_register(WRITE_TRIGGER_OPTION, |
57bbf56b | 1347 | (uint8_t *) &triggerinout_conf, |
0e1357e8 | 1348 | sizeof(struct triggerinout), devc); |
28a35d8a | 1349 | |
eec5275e | 1350 | /* Go back to normal mode. */ |
0e1357e8 | 1351 | sigma_set_register(WRITE_TRIGGER_SELECT1, triggerselect, devc); |
28a35d8a | 1352 | |
edca2c5c | 1353 | /* Set clock select register. */ |
0e1357e8 | 1354 | if (devc->cur_samplerate == SR_MHZ(200)) |
edca2c5c | 1355 | /* Enable 4 probes. */ |
0e1357e8 BV |
1356 | sigma_set_register(WRITE_CLOCK_SELECT, 0xf0, devc); |
1357 | else if (devc->cur_samplerate == SR_MHZ(100)) | |
edca2c5c | 1358 | /* Enable 8 probes. */ |
0e1357e8 | 1359 | sigma_set_register(WRITE_CLOCK_SELECT, 0x00, devc); |
edca2c5c HE |
1360 | else { |
1361 | /* | |
9ddb2a12 | 1362 | * 50 MHz mode (or fraction thereof). Any fraction down to |
eec5275e | 1363 | * 50 MHz / 256 can be used, but is not supported by sigrok API. |
edca2c5c | 1364 | */ |
0e1357e8 | 1365 | frac = SR_MHZ(50) / devc->cur_samplerate - 1; |
edca2c5c | 1366 | |
9ddb2a12 UH |
1367 | clockselect.async = 0; |
1368 | clockselect.fraction = frac; | |
1369 | clockselect.disabled_probes = 0; | |
edca2c5c HE |
1370 | |
1371 | sigma_write_register(WRITE_CLOCK_SELECT, | |
9ddb2a12 | 1372 | (uint8_t *) &clockselect, |
0e1357e8 | 1373 | sizeof(clockselect), devc); |
edca2c5c HE |
1374 | } |
1375 | ||
fefa1800 | 1376 | /* Setup maximum post trigger time. */ |
99965709 | 1377 | sigma_set_register(WRITE_POST_TRIGGER, |
0e1357e8 | 1378 | (devc->capture_ratio * 255) / 100, devc); |
28a35d8a | 1379 | |
eec5275e | 1380 | /* Start acqusition. */ |
0e1357e8 BV |
1381 | gettimeofday(&devc->start_tv, 0); |
1382 | sigma_set_register(WRITE_MODE, 0x0d, devc); | |
99965709 | 1383 | |
0e1357e8 | 1384 | devc->session_dev_id = cb_data; |
28a35d8a | 1385 | |
3c36c403 | 1386 | if (!(packet = g_try_malloc(sizeof(struct sr_datafeed_packet)))) { |
47f4f073 | 1387 | sr_err("%s: packet malloc failed.", __func__); |
3c36c403 HE |
1388 | return SR_ERR_MALLOC; |
1389 | } | |
1390 | ||
1391 | if (!(header = g_try_malloc(sizeof(struct sr_datafeed_header)))) { | |
47f4f073 | 1392 | sr_err("%s: header malloc failed.", __func__); |
3c36c403 HE |
1393 | return SR_ERR_MALLOC; |
1394 | } | |
28a35d8a | 1395 | |
3c36c403 HE |
1396 | /* Send header packet to the session bus. */ |
1397 | packet->type = SR_DF_HEADER; | |
1398 | packet->payload = header; | |
1399 | header->feed_version = 1; | |
1400 | gettimeofday(&header->starttime, NULL); | |
0e1357e8 | 1401 | sr_session_send(devc->session_dev_id, packet); |
f366e86c BV |
1402 | |
1403 | /* Send metadata about the SR_DF_LOGIC packets to come. */ | |
1404 | packet->type = SR_DF_META_LOGIC; | |
1405 | packet->payload = &meta; | |
0e1357e8 BV |
1406 | meta.samplerate = devc->cur_samplerate; |
1407 | meta.num_probes = devc->num_probes; | |
1408 | sr_session_send(devc->session_dev_id, packet); | |
f366e86c BV |
1409 | |
1410 | /* Add capture source. */ | |
3ffb6964 | 1411 | sr_source_add(0, G_IO_IN, 10, receive_data, (void *)sdi); |
f366e86c | 1412 | |
3c36c403 HE |
1413 | g_free(header); |
1414 | g_free(packet); | |
1415 | ||
0e1357e8 | 1416 | devc->state.state = SIGMA_CAPTURE; |
6aac7737 | 1417 | |
e46b8fb1 | 1418 | return SR_OK; |
28a35d8a HE |
1419 | } |
1420 | ||
69b07d14 | 1421 | static int hw_dev_acquisition_stop(struct sr_dev_inst *sdi, void *cb_data) |
28a35d8a | 1422 | { |
0e1357e8 | 1423 | struct dev_context *devc; |
6aac7737 HE |
1424 | uint8_t modestatus; |
1425 | ||
3cd3a20b | 1426 | (void)cb_data; |
28a35d8a | 1427 | |
503c4afb BV |
1428 | sr_source_remove(0); |
1429 | ||
0e1357e8 | 1430 | if (!(devc = sdi->priv)) { |
47f4f073 | 1431 | sr_err("%s: sdi->priv was NULL", __func__); |
3010f21c UH |
1432 | return SR_ERR_BUG; |
1433 | } | |
1434 | ||
fefa1800 | 1435 | /* Stop acquisition. */ |
0e1357e8 | 1436 | sigma_set_register(WRITE_MODE, 0x11, devc); |
28a35d8a | 1437 | |
6aac7737 | 1438 | /* Set SDRAM Read Enable. */ |
0e1357e8 | 1439 | sigma_set_register(WRITE_MODE, 0x02, devc); |
6aac7737 HE |
1440 | |
1441 | /* Get the current position. */ | |
0e1357e8 | 1442 | sigma_read_pos(&devc->state.stoppos, &devc->state.triggerpos, devc); |
6aac7737 HE |
1443 | |
1444 | /* Check if trigger has fired. */ | |
0e1357e8 | 1445 | modestatus = sigma_get_register(READ_MODE, devc); |
3010f21c | 1446 | if (modestatus & 0x20) |
0e1357e8 | 1447 | devc->state.triggerchunk = devc->state.triggerpos / 512; |
3010f21c | 1448 | else |
0e1357e8 | 1449 | devc->state.triggerchunk = -1; |
6aac7737 | 1450 | |
0e1357e8 | 1451 | devc->state.chunks_downloaded = 0; |
6aac7737 | 1452 | |
0e1357e8 | 1453 | devc->state.state = SIGMA_DOWNLOAD; |
3010f21c UH |
1454 | |
1455 | return SR_OK; | |
28a35d8a HE |
1456 | } |
1457 | ||
c09f0b57 | 1458 | SR_PRIV struct sr_dev_driver asix_sigma_driver_info = { |
e519ba86 | 1459 | .name = "asix-sigma", |
6352d030 | 1460 | .longname = "ASIX SIGMA/SIGMA2", |
e519ba86 UH |
1461 | .api_version = 1, |
1462 | .init = hw_init, | |
1463 | .cleanup = hw_cleanup, | |
61136ea6 | 1464 | .scan = hw_scan, |
811deee4 BV |
1465 | .dev_list = hw_dev_list, |
1466 | .dev_clear = clear_instances, | |
e7eb703f UH |
1467 | .dev_open = hw_dev_open, |
1468 | .dev_close = hw_dev_close, | |
41479605 | 1469 | .info_get = hw_info_get, |
a9a245b4 | 1470 | .dev_config_set = hw_dev_config_set, |
6b3dfec8 UH |
1471 | .dev_acquisition_start = hw_dev_acquisition_start, |
1472 | .dev_acquisition_stop = hw_dev_acquisition_stop, | |
0e1357e8 | 1473 | .priv = NULL, |
28a35d8a | 1474 | }; |