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Commit | Line | Data |
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28a35d8a HE |
1 | /* |
2 | * This file is part of the sigrok project. | |
3 | * | |
911f1834 UH |
4 | * Copyright (C) 2010 Håvard Espeland <gus@ping.uio.no>, |
5 | * Copyright (C) 2010 Martin Stensgård <mastensg@ping.uio.no> | |
6 | * Copyright (C) 2010 Carl Henrik Lunde <chlunde@ping.uio.no> | |
28a35d8a HE |
7 | * |
8 | * This program is free software: you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation, either version 3 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
20 | */ | |
21 | ||
911f1834 UH |
22 | /* |
23 | * ASIX Sigma Logic Analyzer Driver | |
24 | */ | |
25 | ||
28a35d8a HE |
26 | #include <ftdi.h> |
27 | #include <string.h> | |
28 | #include <zlib.h> | |
fefa1800 | 29 | #include <sigrok.h> |
28a35d8a HE |
30 | #include "asix-sigma.h" |
31 | ||
32 | #define USB_VENDOR 0xa600 | |
33 | #define USB_PRODUCT 0xa000 | |
34 | #define USB_DESCRIPTION "ASIX SIGMA" | |
35 | #define USB_VENDOR_NAME "ASIX" | |
36 | #define USB_MODEL_NAME "SIGMA" | |
37 | #define USB_MODEL_VERSION "" | |
38 | #define FIRMWARE FIRMWARE_DIR "/asix-sigma-200.firmware" | |
39 | ||
40 | static GSList *device_instances = NULL; | |
41 | ||
42 | // XXX These should be per device | |
43 | static struct ftdi_context ftdic; | |
44 | static uint64_t cur_samplerate = MHZ(200); | |
45 | static uint32_t limit_msec = 0; | |
46 | static struct timeval start_tv; | |
f6564c8d | 47 | static int cur_firmware = -1; |
28a35d8a HE |
48 | |
49 | static uint64_t supported_samplerates[] = { | |
50 | MHZ(200), | |
51 | 0, | |
52 | }; | |
53 | ||
54 | static struct samplerates samplerates = { | |
55 | MHZ(200), | |
56 | MHZ(200), | |
57 | 0, | |
58 | supported_samplerates, | |
59 | }; | |
60 | ||
61 | static int capabilities[] = { | |
62 | HWCAP_LOGIC_ANALYZER, | |
63 | HWCAP_SAMPLERATE, | |
64 | ||
65 | /* These are really implemented in the driver, not the hardware. */ | |
66 | HWCAP_LIMIT_MSEC, | |
67 | 0, | |
68 | }; | |
69 | ||
fefa1800 UH |
70 | /* Force the FPGA to reboot. */ |
71 | static uint8_t suicide[] = { | |
72 | 0x84, 0x84, 0x88, 0x84, 0x88, 0x84, 0x88, 0x84, | |
73 | }; | |
74 | ||
75 | /* Prepare to upload firmware (FPGA specific). */ | |
76 | static uint8_t init[] = { | |
77 | 0x03, 0x03, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, | |
78 | }; | |
79 | ||
80 | /* Initialize the logic analyzer mode. */ | |
81 | static uint8_t logic_mode_start[] = { | |
82 | 0x00, 0x40, 0x0f, 0x25, 0x35, 0x40, | |
83 | 0x2a, 0x3a, 0x40, 0x03, 0x20, 0x38, | |
84 | }; | |
85 | ||
f6564c8d HE |
86 | static const char *firmware_files[] = |
87 | { | |
88 | "asix-sigma-50.firmware", /* Supports fractions (8 bits) */ | |
89 | "asix-sigma-50sync.firmware", /* Asynchronous sampling */ | |
90 | "asix-sigma-100.firmware", /* 100 MHz */ | |
91 | "asix-sigma-200.firmware", /* 200 MHz */ | |
92 | "asix-sigma-phasor.firmware", /* Frequency counter */ | |
93 | }; | |
94 | ||
95 | static int sigma_read(void* buf, size_t size) | |
28a35d8a HE |
96 | { |
97 | int ret; | |
fefa1800 UH |
98 | |
99 | ret = ftdi_read_data(&ftdic, (unsigned char *)buf, size); | |
28a35d8a HE |
100 | if (ret < 0) { |
101 | g_warning("ftdi_read_data failed: %s", | |
fefa1800 | 102 | ftdi_get_error_string(&ftdic)); |
28a35d8a HE |
103 | } |
104 | ||
105 | return ret; | |
106 | } | |
107 | ||
fefa1800 | 108 | static int sigma_write(void *buf, size_t size) |
28a35d8a HE |
109 | { |
110 | int ret; | |
fefa1800 UH |
111 | |
112 | ret = ftdi_write_data(&ftdic, (unsigned char *)buf, size); | |
28a35d8a HE |
113 | if (ret < 0) { |
114 | g_warning("ftdi_write_data failed: %s", | |
fefa1800 UH |
115 | ftdi_get_error_string(&ftdic)); |
116 | } else if ((size_t) ret != size) { | |
28a35d8a HE |
117 | g_warning("ftdi_write_data did not complete write\n"); |
118 | } | |
119 | ||
120 | return ret; | |
121 | } | |
122 | ||
123 | static int sigma_write_register(uint8_t reg, uint8_t *data, size_t len) | |
124 | { | |
125 | size_t i; | |
126 | uint8_t buf[len + 2]; | |
127 | int idx = 0; | |
128 | ||
129 | buf[idx++] = REG_ADDR_LOW | (reg & 0xf); | |
130 | buf[idx++] = REG_ADDR_HIGH | (reg >> 4); | |
131 | ||
fefa1800 | 132 | for (i = 0; i < len; ++i) { |
28a35d8a HE |
133 | buf[idx++] = REG_DATA_LOW | (data[i] & 0xf); |
134 | buf[idx++] = REG_DATA_HIGH_WRITE | (data[i] >> 4); | |
135 | } | |
136 | ||
137 | return sigma_write(buf, idx); | |
138 | } | |
139 | ||
140 | static int sigma_set_register(uint8_t reg, uint8_t value) | |
141 | { | |
142 | return sigma_write_register(reg, &value, 1); | |
143 | } | |
144 | ||
145 | static int sigma_read_register(uint8_t reg, uint8_t *data, size_t len) | |
146 | { | |
147 | uint8_t buf[3]; | |
fefa1800 | 148 | |
28a35d8a HE |
149 | buf[0] = REG_ADDR_LOW | (reg & 0xf); |
150 | buf[1] = REG_ADDR_HIGH | (reg >> 4); | |
28a35d8a HE |
151 | buf[2] = REG_READ_ADDR; |
152 | ||
153 | sigma_write(buf, sizeof(buf)); | |
154 | ||
155 | return sigma_read(data, len); | |
156 | } | |
157 | ||
158 | static uint8_t sigma_get_register(uint8_t reg) | |
159 | { | |
160 | uint8_t value; | |
fefa1800 | 161 | |
28a35d8a HE |
162 | if (1 != sigma_read_register(reg, &value, 1)) { |
163 | g_warning("Sigma_get_register: 1 byte expected"); | |
164 | return 0; | |
165 | } | |
166 | ||
167 | return value; | |
168 | } | |
169 | ||
170 | static int sigma_read_pos(uint32_t *stoppos, uint32_t *triggerpos) | |
171 | { | |
172 | uint8_t buf[] = { | |
173 | REG_ADDR_LOW | READ_TRIGGER_POS_LOW, | |
174 | ||
175 | REG_READ_ADDR | NEXT_REG, | |
176 | REG_READ_ADDR | NEXT_REG, | |
177 | REG_READ_ADDR | NEXT_REG, | |
178 | REG_READ_ADDR | NEXT_REG, | |
179 | REG_READ_ADDR | NEXT_REG, | |
180 | REG_READ_ADDR | NEXT_REG, | |
181 | }; | |
28a35d8a HE |
182 | uint8_t result[6]; |
183 | ||
184 | sigma_write(buf, sizeof(buf)); | |
185 | ||
186 | sigma_read(result, sizeof(result)); | |
187 | ||
188 | *triggerpos = result[0] | (result[1] << 8) | (result[2] << 16); | |
189 | *stoppos = result[3] | (result[4] << 8) | (result[5] << 16); | |
190 | ||
191 | return 1; | |
192 | } | |
193 | ||
194 | static int sigma_read_dram(uint16_t startchunk, size_t numchunks, uint8_t *data) | |
195 | { | |
196 | size_t i; | |
197 | uint8_t buf[4096]; | |
198 | int idx = 0; | |
199 | ||
fefa1800 | 200 | /* Send the startchunk. Index start with 1. */ |
28a35d8a HE |
201 | buf[0] = startchunk >> 8; |
202 | buf[1] = startchunk & 0xff; | |
203 | sigma_write_register(WRITE_MEMROW, buf, 2); | |
204 | ||
fefa1800 | 205 | /* Read the DRAM. */ |
28a35d8a HE |
206 | buf[idx++] = REG_DRAM_BLOCK; |
207 | buf[idx++] = REG_DRAM_WAIT_ACK; | |
208 | ||
209 | for (i = 0; i < numchunks; ++i) { | |
fefa1800 UH |
210 | /* Alternate bit to copy from DRAM to cache. */ |
211 | if (i != (numchunks - 1)) | |
212 | buf[idx++] = REG_DRAM_BLOCK | (((i + 1) % 2) << 4); | |
28a35d8a HE |
213 | |
214 | buf[idx++] = REG_DRAM_BLOCK_DATA | ((i % 2) << 4); | |
215 | ||
fefa1800 | 216 | if (i != (numchunks - 1)) |
28a35d8a HE |
217 | buf[idx++] = REG_DRAM_WAIT_ACK; |
218 | } | |
219 | ||
220 | sigma_write(buf, idx); | |
221 | ||
222 | return sigma_read(data, numchunks * CHUNK_SIZE); | |
223 | } | |
224 | ||
fefa1800 | 225 | /* Generate the bitbang stream for programming the FPGA. */ |
28a35d8a | 226 | static int bin2bitbang(const char *filename, |
fefa1800 | 227 | unsigned char **buf, size_t *buf_size) |
28a35d8a | 228 | { |
fefa1800 | 229 | FILE *f; |
28a35d8a HE |
230 | long file_size; |
231 | unsigned long offset = 0; | |
232 | unsigned char *p; | |
233 | uint8_t *compressed_buf, *firmware; | |
234 | uLongf csize, fwsize; | |
235 | const int buffer_size = 65536; | |
236 | size_t i; | |
fefa1800 UH |
237 | int c, ret, bit, v; |
238 | uint32_t imm = 0x3f6df2ab; | |
28a35d8a | 239 | |
fefa1800 | 240 | f = fopen(filename, "r"); |
28a35d8a HE |
241 | if (!f) { |
242 | g_warning("fopen(\"%s\", \"r\")", filename); | |
243 | return -1; | |
244 | } | |
245 | ||
246 | if (-1 == fseek(f, 0, SEEK_END)) { | |
247 | g_warning("fseek on %s failed", filename); | |
248 | fclose(f); | |
249 | return -1; | |
250 | } | |
251 | ||
252 | file_size = ftell(f); | |
253 | ||
254 | fseek(f, 0, SEEK_SET); | |
255 | ||
28a35d8a HE |
256 | compressed_buf = g_malloc(file_size); |
257 | firmware = g_malloc(buffer_size); | |
258 | ||
259 | if (!compressed_buf || !firmware) { | |
260 | g_warning("Error allocating buffers"); | |
261 | return -1; | |
262 | } | |
263 | ||
28a35d8a HE |
264 | csize = 0; |
265 | while ((c = getc(f)) != EOF) { | |
266 | imm = (imm + 0xa853753) % 177 + (imm * 0x8034052); | |
267 | compressed_buf[csize++] = c ^ imm; | |
268 | } | |
269 | fclose(f); | |
270 | ||
271 | fwsize = buffer_size; | |
272 | ret = uncompress(firmware, &fwsize, compressed_buf, csize); | |
273 | if (ret < 0) { | |
274 | g_free(compressed_buf); | |
275 | g_free(firmware); | |
276 | g_warning("Could not unpack Sigma firmware. (Error %d)\n", ret); | |
277 | return -1; | |
278 | } | |
279 | ||
280 | g_free(compressed_buf); | |
281 | ||
282 | *buf_size = fwsize * 2 * 8; | |
283 | ||
fefa1800 | 284 | *buf = p = (unsigned char *)g_malloc(*buf_size); |
28a35d8a HE |
285 | |
286 | if (!p) { | |
287 | g_warning("Error allocating buffers"); | |
288 | return -1; | |
289 | } | |
290 | ||
291 | for (i = 0; i < fwsize; ++i) { | |
28a35d8a | 292 | for (bit = 7; bit >= 0; --bit) { |
fefa1800 | 293 | v = firmware[i] & 1 << bit ? 0x40 : 0x00; |
28a35d8a HE |
294 | p[offset++] = v | 0x01; |
295 | p[offset++] = v; | |
296 | } | |
297 | } | |
298 | ||
299 | g_free(firmware); | |
300 | ||
301 | if (offset != *buf_size) { | |
302 | g_free(*buf); | |
303 | g_warning("Error reading firmware %s " | |
fefa1800 UH |
304 | "offset=%ld, file_size=%ld, buf_size=%zd\n", |
305 | filename, offset, file_size, *buf_size); | |
28a35d8a HE |
306 | |
307 | return -1; | |
308 | } | |
309 | ||
310 | return 0; | |
311 | } | |
312 | ||
313 | static int hw_init(char *deviceinfo) | |
314 | { | |
315 | struct sigrok_device_instance *sdi; | |
316 | ||
317 | deviceinfo = deviceinfo; | |
318 | ||
319 | ftdi_init(&ftdic); | |
320 | ||
fefa1800 UH |
321 | /* Look for SIGMAs. */ |
322 | if (ftdi_usb_open_desc(&ftdic, USB_VENDOR, USB_PRODUCT, | |
323 | USB_DESCRIPTION, NULL) < 0) | |
28a35d8a HE |
324 | return 0; |
325 | ||
fefa1800 | 326 | /* Register SIGMA device. */ |
28a35d8a HE |
327 | sdi = sigrok_device_instance_new(0, ST_INITIALIZING, |
328 | USB_VENDOR_NAME, USB_MODEL_NAME, USB_MODEL_VERSION); | |
329 | if (!sdi) | |
330 | return 0; | |
331 | ||
332 | device_instances = g_slist_append(device_instances, sdi); | |
333 | ||
fefa1800 | 334 | /* We will open the device again when we need it. */ |
28a35d8a HE |
335 | ftdi_usb_close(&ftdic); |
336 | ||
337 | return 1; | |
338 | } | |
339 | ||
f6564c8d | 340 | static int upload_firmware(int firmware_idx) |
28a35d8a HE |
341 | { |
342 | int ret; | |
343 | unsigned char *buf; | |
344 | unsigned char pins; | |
345 | size_t buf_size; | |
28a35d8a | 346 | unsigned char result[32]; |
f6564c8d | 347 | char firmware_file[64]; |
28a35d8a | 348 | |
fefa1800 | 349 | /* Make sure it's an ASIX SIGMA. */ |
28a35d8a HE |
350 | if ((ret = ftdi_usb_open_desc(&ftdic, |
351 | USB_VENDOR, USB_PRODUCT, USB_DESCRIPTION, NULL)) < 0) { | |
28a35d8a | 352 | g_warning("ftdi_usb_open failed: %s", |
fefa1800 | 353 | ftdi_get_error_string(&ftdic)); |
28a35d8a HE |
354 | return 0; |
355 | } | |
356 | ||
357 | if ((ret = ftdi_set_bitmode(&ftdic, 0xdf, BITMODE_BITBANG)) < 0) { | |
358 | g_warning("ftdi_set_bitmode failed: %s", | |
fefa1800 | 359 | ftdi_get_error_string(&ftdic)); |
28a35d8a HE |
360 | return 0; |
361 | } | |
362 | ||
fefa1800 | 363 | /* Four times the speed of sigmalogan - Works well. */ |
28a35d8a HE |
364 | if ((ret = ftdi_set_baudrate(&ftdic, 750000)) < 0) { |
365 | g_warning("ftdi_set_baudrate failed: %s", | |
fefa1800 | 366 | ftdi_get_error_string(&ftdic)); |
28a35d8a HE |
367 | return 0; |
368 | } | |
369 | ||
fefa1800 | 370 | /* Force the FPGA to reboot. */ |
28a35d8a HE |
371 | sigma_write(suicide, sizeof(suicide)); |
372 | sigma_write(suicide, sizeof(suicide)); | |
373 | sigma_write(suicide, sizeof(suicide)); | |
374 | sigma_write(suicide, sizeof(suicide)); | |
375 | ||
fefa1800 | 376 | /* Prepare to upload firmware (FPGA specific). */ |
28a35d8a HE |
377 | sigma_write(init, sizeof(init)); |
378 | ||
379 | ftdi_usb_purge_buffers(&ftdic); | |
380 | ||
fefa1800 | 381 | /* Wait until the FPGA asserts INIT_B. */ |
28a35d8a HE |
382 | while (1) { |
383 | ret = sigma_read(result, 1); | |
384 | if (result[0] & 0x20) | |
385 | break; | |
386 | } | |
387 | ||
f6564c8d HE |
388 | /* Prepare firmware */ |
389 | snprintf(firmware_file, sizeof(firmware_file), "%s/%s", FIRMWARE_DIR, | |
390 | firmware_files[firmware_idx]); | |
391 | ||
392 | if (-1 == bin2bitbang(firmware_file, &buf, &buf_size)) { | |
28a35d8a | 393 | g_warning("An error occured while reading the firmware: %s", |
fefa1800 | 394 | FIRMWARE); |
28a35d8a HE |
395 | return SIGROK_ERR; |
396 | } | |
397 | ||
fefa1800 | 398 | /* Upload firmare. */ |
28a35d8a HE |
399 | sigma_write(buf, buf_size); |
400 | ||
401 | g_free(buf); | |
402 | ||
403 | if ((ret = ftdi_set_bitmode(&ftdic, 0x00, BITMODE_RESET)) < 0) { | |
f6564c8d | 404 | g_warning("ftdi_set_bitmode failed: %s", |
fefa1800 | 405 | ftdi_get_error_string(&ftdic)); |
28a35d8a HE |
406 | return SIGROK_ERR; |
407 | } | |
408 | ||
409 | ftdi_usb_purge_buffers(&ftdic); | |
410 | ||
fefa1800 | 411 | /* Discard garbage. */ |
28a35d8a HE |
412 | while (1 == sigma_read(&pins, 1)) |
413 | ; | |
414 | ||
fefa1800 | 415 | /* Initialize the logic analyzer mode. */ |
28a35d8a HE |
416 | sigma_write(logic_mode_start, sizeof(logic_mode_start)); |
417 | ||
fefa1800 | 418 | /* Expect a 3 byte reply. */ |
28a35d8a HE |
419 | ret = sigma_read(result, 3); |
420 | if (ret != 3 || | |
421 | result[0] != 0xa6 || result[1] != 0x55 || result[2] != 0xaa) { | |
fefa1800 | 422 | g_warning("Configuration failed. Invalid reply received."); |
28a35d8a HE |
423 | return SIGROK_ERR; |
424 | } | |
425 | ||
f6564c8d HE |
426 | cur_firmware = firmware_idx; |
427 | ||
428 | return SIGROK_OK; | |
429 | } | |
430 | ||
431 | static int hw_opendev(int device_index) | |
432 | { | |
433 | struct sigrok_device_instance *sdi; | |
434 | int ret; | |
435 | ||
436 | /* Make sure it's an ASIX SIGMA */ | |
437 | if ((ret = ftdi_usb_open_desc(&ftdic, | |
438 | USB_VENDOR, USB_PRODUCT, USB_DESCRIPTION, NULL)) < 0) { | |
439 | ||
440 | g_warning("ftdi_usb_open failed: %s", | |
441 | ftdi_get_error_string(&ftdic)); | |
442 | ||
443 | return 0; | |
444 | } | |
28a35d8a HE |
445 | |
446 | if (!(sdi = get_sigrok_device_instance(device_instances, device_index))) | |
447 | return SIGROK_ERR; | |
448 | ||
449 | sdi->status = ST_ACTIVE; | |
450 | ||
f6564c8d HE |
451 | return SIGROK_OK; |
452 | } | |
453 | ||
454 | static int set_samplerate(struct sigrok_device_instance *sdi, uint64_t samplerate) | |
455 | { | |
456 | int i; | |
457 | ||
458 | sdi = sdi; | |
459 | ||
460 | for (i = 0; supported_samplerates[i]; i++) { | |
461 | if (supported_samplerates[i] == samplerate) | |
462 | break; | |
463 | } | |
464 | if (supported_samplerates[i] == 0) | |
465 | return SIGROK_ERR_SAMPLERATE; | |
466 | ||
467 | cur_samplerate = samplerate; | |
468 | ||
469 | upload_firmware(3); | |
470 | ||
28a35d8a HE |
471 | g_message("Firmware uploaded"); |
472 | ||
473 | return SIGROK_OK; | |
474 | } | |
475 | ||
28a35d8a HE |
476 | static void hw_closedev(int device_index) |
477 | { | |
478 | device_index = device_index; | |
479 | ||
480 | ftdi_usb_close(&ftdic); | |
481 | } | |
482 | ||
28a35d8a HE |
483 | static void hw_cleanup(void) |
484 | { | |
485 | } | |
486 | ||
28a35d8a HE |
487 | static void *hw_get_device_info(int device_index, int device_info_id) |
488 | { | |
489 | struct sigrok_device_instance *sdi; | |
490 | void *info = NULL; | |
491 | ||
492 | if (!(sdi = get_sigrok_device_instance(device_instances, device_index))) { | |
493 | fprintf(stderr, "It's NULL.\n"); | |
494 | return NULL; | |
495 | } | |
496 | ||
497 | switch (device_info_id) { | |
498 | case DI_INSTANCE: | |
499 | info = sdi; | |
500 | break; | |
501 | case DI_NUM_PROBES: | |
502 | info = GINT_TO_POINTER(4); | |
503 | break; | |
504 | case DI_SAMPLERATES: | |
505 | info = &samplerates; | |
506 | break; | |
507 | case DI_TRIGGER_TYPES: | |
fefa1800 | 508 | info = 0; //TRIGGER_TYPES; |
28a35d8a HE |
509 | break; |
510 | case DI_CUR_SAMPLERATE: | |
511 | info = &cur_samplerate; | |
512 | break; | |
513 | } | |
514 | ||
515 | return info; | |
516 | } | |
517 | ||
28a35d8a HE |
518 | static int hw_get_status(int device_index) |
519 | { | |
520 | struct sigrok_device_instance *sdi; | |
521 | ||
522 | sdi = get_sigrok_device_instance(device_instances, device_index); | |
523 | if (sdi) | |
524 | return sdi->status; | |
525 | else | |
526 | return ST_NOT_FOUND; | |
527 | } | |
528 | ||
28a35d8a HE |
529 | static int *hw_get_capabilities(void) |
530 | { | |
531 | return capabilities; | |
532 | } | |
533 | ||
534 | static int hw_set_configuration(int device_index, int capability, void *value) | |
535 | { | |
536 | struct sigrok_device_instance *sdi; | |
537 | int ret; | |
f6564c8d HE |
538 | |
539 | fprintf(stderr, "Set config: %d\n", capability); | |
28a35d8a HE |
540 | |
541 | if (!(sdi = get_sigrok_device_instance(device_instances, device_index))) | |
542 | return SIGROK_ERR; | |
543 | ||
544 | if (capability == HWCAP_SAMPLERATE) { | |
f6564c8d | 545 | ret = set_samplerate(sdi, *(uint64_t*) value); |
28a35d8a HE |
546 | } else if (capability == HWCAP_PROBECONFIG) { |
547 | ret = SIGROK_OK; | |
548 | } else if (capability == HWCAP_LIMIT_MSEC) { | |
549 | limit_msec = strtoull(value, NULL, 10); | |
550 | ret = SIGROK_OK; | |
551 | } else { | |
552 | ret = SIGROK_ERR; | |
553 | } | |
554 | ||
555 | return ret; | |
556 | } | |
557 | ||
28a35d8a | 558 | /* |
fefa1800 UH |
559 | * Decode chunk of 1024 bytes, 64 clusters, 7 events per cluster. |
560 | * Each event is 20ns apart, and can contain multiple samples. | |
561 | * For 200 MHz, an event contains 4 samples for each channel, | |
562 | * spread 5 ns apart. | |
28a35d8a HE |
563 | */ |
564 | static int decode_chunk_ts(uint8_t *buf, uint16_t *lastts, | |
565 | uint8_t *lastsample, void *user_data) | |
566 | { | |
567 | const int samples_per_event = 4; | |
fefa1800 | 568 | uint16_t tsdiff, ts; |
28a35d8a | 569 | uint8_t samples[65536 * samples_per_event]; |
28a35d8a | 570 | struct datafeed_packet packet; |
fefa1800 UH |
571 | int i, j, k, numpad, tosend; |
572 | size_t n = 0, sent = 0; | |
28a35d8a | 573 | int clustersize = EVENTS_PER_CLUSTER * samples_per_event; /* 4 for 200 MHz */ |
fefa1800 | 574 | uint16_t *event; |
28a35d8a HE |
575 | |
576 | /* For each ts */ | |
577 | for (i = 0; i < 64; ++i) { | |
fefa1800 | 578 | ts = *(uint16_t *) &buf[i * 16]; |
28a35d8a HE |
579 | tsdiff = ts - *lastts; |
580 | *lastts = ts; | |
581 | ||
fefa1800 UH |
582 | /* Pad last sample up to current point. */ |
583 | numpad = tsdiff * samples_per_event - clustersize; | |
28a35d8a HE |
584 | if (numpad > 0) { |
585 | memset(samples, *lastsample, | |
fefa1800 UH |
586 | tsdiff * samples_per_event - clustersize); |
587 | n = tsdiff * samples_per_event - clustersize; | |
28a35d8a HE |
588 | } |
589 | ||
fefa1800 | 590 | event = (uint16_t *) &buf[i * 16 + 2]; |
28a35d8a | 591 | |
fefa1800 | 592 | /* For each sample in cluster. */ |
28a35d8a HE |
593 | for (j = 0; j < 7; ++j) { |
594 | for (k = 0; k < samples_per_event; ++k) { | |
fefa1800 UH |
595 | /* |
596 | * Extract samples from bytestream. | |
597 | * Samples are packed together in a short. | |
598 | */ | |
28a35d8a | 599 | samples[n++] = |
fefa1800 UH |
600 | ((!!(event[j] & (1 << (k + 0x0)))) << 0) | |
601 | ((!!(event[j] & (1 << (k + 0x4)))) << 1) | | |
602 | ((!!(event[j] & (1 << (k + 0x8)))) << 2) | | |
603 | ((!!(event[j] & (1 << (k + 0xc)))) << 3); | |
28a35d8a HE |
604 | } |
605 | } | |
606 | ||
fefa1800 | 607 | *lastsample = samples[n - 1]; |
28a35d8a | 608 | |
fefa1800 UH |
609 | /* Send to sigrok. */ |
610 | sent = 0; | |
28a35d8a | 611 | while (sent < n) { |
fefa1800 | 612 | tosend = MIN(4096, n - sent); |
28a35d8a HE |
613 | |
614 | packet.type = DF_LOGIC8; | |
615 | packet.length = tosend; | |
fefa1800 | 616 | packet.payload = samples + sent; |
28a35d8a HE |
617 | session_bus(user_data, &packet); |
618 | ||
619 | sent += tosend; | |
620 | } | |
621 | } | |
622 | ||
623 | return 0; | |
624 | } | |
625 | ||
626 | static int receive_data(int fd, int revents, void *user_data) | |
627 | { | |
628 | struct datafeed_packet packet; | |
28a35d8a HE |
629 | const int chunks_per_read = 32; |
630 | unsigned char buf[chunks_per_read * CHUNK_SIZE]; | |
fefa1800 UH |
631 | int bufsz, numchunks, curchunk, i, newchunks; |
632 | uint32_t triggerpos, stoppos, running_msec; | |
28a35d8a | 633 | struct timeval tv; |
28a35d8a HE |
634 | uint16_t lastts = 0; |
635 | uint8_t lastsample = 0; | |
28a35d8a HE |
636 | |
637 | fd = fd; | |
638 | revents = revents; | |
639 | ||
fefa1800 | 640 | /* Get the current position. */ |
28a35d8a HE |
641 | sigma_read_pos(&stoppos, &triggerpos); |
642 | numchunks = stoppos / 512; | |
643 | ||
fefa1800 | 644 | /* Check if the has expired, or memory is full. */ |
28a35d8a HE |
645 | gettimeofday(&tv, 0); |
646 | running_msec = (tv.tv_sec - start_tv.tv_sec) * 1000 + | |
fefa1800 | 647 | (tv.tv_usec - start_tv.tv_usec) / 1000; |
28a35d8a HE |
648 | |
649 | if (running_msec < limit_msec && numchunks < 32767) | |
650 | return FALSE; | |
651 | ||
fefa1800 | 652 | /* Stop acqusition. */ |
28a35d8a HE |
653 | sigma_set_register(WRITE_MODE, 0x11); |
654 | ||
fefa1800 | 655 | /* Set SDRAM Read Enable. */ |
28a35d8a HE |
656 | sigma_set_register(WRITE_MODE, 0x02); |
657 | ||
fefa1800 | 658 | /* Get the current position. */ |
28a35d8a HE |
659 | sigma_read_pos(&stoppos, &triggerpos); |
660 | ||
fefa1800 | 661 | /* Download sample data. */ |
28a35d8a | 662 | for (curchunk = 0; curchunk < numchunks;) { |
fefa1800 | 663 | newchunks = MIN(chunks_per_read, numchunks - curchunk); |
28a35d8a HE |
664 | |
665 | g_message("Downloading sample data: %.0f %%", | |
fefa1800 | 666 | 100.0 * curchunk / numchunks); |
28a35d8a HE |
667 | |
668 | bufsz = sigma_read_dram(curchunk, newchunks, buf); | |
669 | ||
fefa1800 UH |
670 | /* Find first ts. */ |
671 | if (curchunk == 0) | |
672 | lastts = *(uint16_t *) buf - 1; | |
28a35d8a | 673 | |
fefa1800 | 674 | /* Decode chunks and send them to sigrok. */ |
28a35d8a HE |
675 | for (i = 0; i < newchunks; ++i) { |
676 | decode_chunk_ts(buf + (i * CHUNK_SIZE), | |
677 | &lastts, &lastsample, user_data); | |
678 | } | |
679 | ||
680 | curchunk += newchunks; | |
681 | } | |
682 | ||
683 | /* End of data */ | |
684 | packet.type = DF_END; | |
685 | packet.length = 0; | |
686 | session_bus(user_data, &packet); | |
687 | ||
688 | return TRUE; | |
689 | } | |
690 | ||
691 | static int hw_start_acquisition(int device_index, gpointer session_device_id) | |
692 | { | |
693 | struct sigrok_device_instance *sdi; | |
694 | struct datafeed_packet packet; | |
695 | struct datafeed_header header; | |
fefa1800 | 696 | uint8_t trigger_option[2] = { 0x38, 0x00 }; |
28a35d8a HE |
697 | |
698 | session_device_id = session_device_id; | |
699 | ||
700 | if (!(sdi = get_sigrok_device_instance(device_instances, device_index))) | |
701 | return SIGROK_ERR; | |
702 | ||
703 | device_index = device_index; | |
704 | ||
fefa1800 | 705 | /* Setup trigger (by trigger-in). */ |
28a35d8a HE |
706 | sigma_set_register(WRITE_TRIGGER_SELECT1, 0x20); |
707 | ||
fefa1800 | 708 | /* More trigger setup. */ |
28a35d8a | 709 | sigma_write_register(WRITE_TRIGGER_OPTION, |
fefa1800 | 710 | trigger_option, sizeof(trigger_option)); |
28a35d8a | 711 | |
fefa1800 | 712 | /* Trigger normal (falling edge). */ |
28a35d8a HE |
713 | sigma_set_register(WRITE_TRIGGER_SELECT1, 0x08); |
714 | ||
fefa1800 | 715 | /* Enable pins (200 MHz, 4 pins). */ |
28a35d8a HE |
716 | sigma_set_register(WRITE_CLOCK_SELECT, 0xf0); |
717 | ||
fefa1800 | 718 | /* Setup maximum post trigger time. */ |
28a35d8a HE |
719 | sigma_set_register(WRITE_POST_TRIGGER, 0xff); |
720 | ||
fefa1800 | 721 | /* Start acqusition (software trigger start). */ |
28a35d8a HE |
722 | gettimeofday(&start_tv, 0); |
723 | sigma_set_register(WRITE_MODE, 0x0d); | |
724 | ||
fefa1800 | 725 | /* Add capture source. */ |
28a35d8a HE |
726 | source_add(0, G_IO_IN, 10, receive_data, session_device_id); |
727 | ||
728 | receive_data(0, 1, session_device_id); | |
729 | ||
730 | /* Send header packet to the session bus. */ | |
731 | packet.type = DF_HEADER; | |
732 | packet.length = sizeof(struct datafeed_header); | |
733 | packet.payload = &header; | |
734 | header.feed_version = 1; | |
735 | gettimeofday(&header.starttime, NULL); | |
736 | header.samplerate = cur_samplerate; | |
737 | header.protocol_id = PROTO_RAW; | |
738 | header.num_probes = 4; | |
739 | session_bus(session_device_id, &packet); | |
740 | ||
741 | return SIGROK_OK; | |
742 | } | |
743 | ||
28a35d8a HE |
744 | static void hw_stop_acquisition(int device_index, gpointer session_device_id) |
745 | { | |
746 | device_index = device_index; | |
747 | session_device_id = session_device_id; | |
748 | ||
fefa1800 | 749 | /* Stop acquisition. */ |
28a35d8a HE |
750 | sigma_set_register(WRITE_MODE, 0x11); |
751 | ||
752 | // XXX Set some state to indicate that data should be sent to sigrok | |
753 | // Now, we just wait for timeout | |
754 | } | |
755 | ||
28a35d8a HE |
756 | struct device_plugin asix_sigma_plugin_info = { |
757 | "asix-sigma", | |
758 | 1, | |
759 | hw_init, | |
760 | hw_cleanup, | |
28a35d8a HE |
761 | hw_opendev, |
762 | hw_closedev, | |
763 | hw_get_device_info, | |
764 | hw_get_status, | |
765 | hw_get_capabilities, | |
766 | hw_set_configuration, | |
767 | hw_start_acquisition, | |
768 | hw_stop_acquisition | |
769 | }; |