]>
Commit | Line | Data |
---|---|---|
1 | /* | |
2 | * This file is part of the libsigrok project. | |
3 | * | |
4 | * Copyright (C) 2010-2012 Håvard Espeland <gus@ping.uio.no>, | |
5 | * Copyright (C) 2010 Martin Stensgård <mastensg@ping.uio.no> | |
6 | * Copyright (C) 2010 Carl Henrik Lunde <chlunde@ping.uio.no> | |
7 | * | |
8 | * This program is free software: you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation, either version 3 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
20 | */ | |
21 | ||
22 | /* | |
23 | * ASIX SIGMA/SIGMA2 logic analyzer driver | |
24 | */ | |
25 | ||
26 | #include <glib.h> | |
27 | #include <glib/gstdio.h> | |
28 | #include <ftdi.h> | |
29 | #include <string.h> | |
30 | #include "libsigrok.h" | |
31 | #include "libsigrok-internal.h" | |
32 | #include "asix-sigma.h" | |
33 | ||
34 | #define USB_VENDOR 0xa600 | |
35 | #define USB_PRODUCT 0xa000 | |
36 | #define USB_DESCRIPTION "ASIX SIGMA" | |
37 | #define USB_VENDOR_NAME "ASIX" | |
38 | #define USB_MODEL_NAME "SIGMA" | |
39 | #define TRIGGER_TYPE "rf10" | |
40 | ||
41 | SR_PRIV struct sr_dev_driver asix_sigma_driver_info; | |
42 | static struct sr_dev_driver *di = &asix_sigma_driver_info; | |
43 | static int dev_acquisition_stop(struct sr_dev_inst *sdi, void *cb_data); | |
44 | ||
45 | /* | |
46 | * The ASIX Sigma supports arbitrary integer frequency divider in | |
47 | * the 50MHz mode. The divider is in range 1...256 , allowing for | |
48 | * very precise sampling rate selection. This driver supports only | |
49 | * a subset of the sampling rates. | |
50 | */ | |
51 | static const uint64_t samplerates[] = { | |
52 | SR_KHZ(200), /* div=250 */ | |
53 | SR_KHZ(250), /* div=200 */ | |
54 | SR_KHZ(500), /* div=100 */ | |
55 | SR_MHZ(1), /* div=50 */ | |
56 | SR_MHZ(5), /* div=10 */ | |
57 | SR_MHZ(10), /* div=5 */ | |
58 | SR_MHZ(25), /* div=2 */ | |
59 | SR_MHZ(50), /* div=1 */ | |
60 | SR_MHZ(100), /* Special FW needed */ | |
61 | SR_MHZ(200), /* Special FW needed */ | |
62 | }; | |
63 | ||
64 | /* | |
65 | * Channel numbers seem to go from 1-16, according to this image: | |
66 | * http://tools.asix.net/img/sigma_sigmacab_pins_720.jpg | |
67 | * (the cable has two additional GND pins, and a TI and TO pin) | |
68 | */ | |
69 | static const char *channel_names[] = { | |
70 | "1", "2", "3", "4", "5", "6", "7", "8", | |
71 | "9", "10", "11", "12", "13", "14", "15", "16", | |
72 | }; | |
73 | ||
74 | static const int32_t hwcaps[] = { | |
75 | SR_CONF_LOGIC_ANALYZER, | |
76 | SR_CONF_SAMPLERATE, | |
77 | SR_CONF_TRIGGER_TYPE, | |
78 | SR_CONF_CAPTURE_RATIO, | |
79 | SR_CONF_LIMIT_MSEC, | |
80 | SR_CONF_LIMIT_SAMPLES, | |
81 | }; | |
82 | ||
83 | /* Initialize the logic analyzer mode. */ | |
84 | static uint8_t logic_mode_start[] = { | |
85 | 0x00, 0x40, 0x0f, 0x25, 0x35, 0x40, | |
86 | 0x2a, 0x3a, 0x40, 0x03, 0x20, 0x38, | |
87 | }; | |
88 | ||
89 | static const char *sigma_firmware_files[] = { | |
90 | /* 50 MHz, supports 8 bit fractions */ | |
91 | FIRMWARE_DIR "/asix-sigma-50.fw", | |
92 | /* 100 MHz */ | |
93 | FIRMWARE_DIR "/asix-sigma-100.fw", | |
94 | /* 200 MHz */ | |
95 | FIRMWARE_DIR "/asix-sigma-200.fw", | |
96 | /* Synchronous clock from pin */ | |
97 | FIRMWARE_DIR "/asix-sigma-50sync.fw", | |
98 | /* Frequency counter */ | |
99 | FIRMWARE_DIR "/asix-sigma-phasor.fw", | |
100 | }; | |
101 | ||
102 | static int sigma_read(void *buf, size_t size, struct dev_context *devc) | |
103 | { | |
104 | int ret; | |
105 | ||
106 | ret = ftdi_read_data(&devc->ftdic, (unsigned char *)buf, size); | |
107 | if (ret < 0) { | |
108 | sr_err("ftdi_read_data failed: %s", | |
109 | ftdi_get_error_string(&devc->ftdic)); | |
110 | } | |
111 | ||
112 | return ret; | |
113 | } | |
114 | ||
115 | static int sigma_write(void *buf, size_t size, struct dev_context *devc) | |
116 | { | |
117 | int ret; | |
118 | ||
119 | ret = ftdi_write_data(&devc->ftdic, (unsigned char *)buf, size); | |
120 | if (ret < 0) { | |
121 | sr_err("ftdi_write_data failed: %s", | |
122 | ftdi_get_error_string(&devc->ftdic)); | |
123 | } else if ((size_t) ret != size) { | |
124 | sr_err("ftdi_write_data did not complete write."); | |
125 | } | |
126 | ||
127 | return ret; | |
128 | } | |
129 | ||
130 | static int sigma_write_register(uint8_t reg, uint8_t *data, size_t len, | |
131 | struct dev_context *devc) | |
132 | { | |
133 | size_t i; | |
134 | uint8_t buf[len + 2]; | |
135 | int idx = 0; | |
136 | ||
137 | buf[idx++] = REG_ADDR_LOW | (reg & 0xf); | |
138 | buf[idx++] = REG_ADDR_HIGH | (reg >> 4); | |
139 | ||
140 | for (i = 0; i < len; ++i) { | |
141 | buf[idx++] = REG_DATA_LOW | (data[i] & 0xf); | |
142 | buf[idx++] = REG_DATA_HIGH_WRITE | (data[i] >> 4); | |
143 | } | |
144 | ||
145 | return sigma_write(buf, idx, devc); | |
146 | } | |
147 | ||
148 | static int sigma_set_register(uint8_t reg, uint8_t value, struct dev_context *devc) | |
149 | { | |
150 | return sigma_write_register(reg, &value, 1, devc); | |
151 | } | |
152 | ||
153 | static int sigma_read_register(uint8_t reg, uint8_t *data, size_t len, | |
154 | struct dev_context *devc) | |
155 | { | |
156 | uint8_t buf[3]; | |
157 | ||
158 | buf[0] = REG_ADDR_LOW | (reg & 0xf); | |
159 | buf[1] = REG_ADDR_HIGH | (reg >> 4); | |
160 | buf[2] = REG_READ_ADDR; | |
161 | ||
162 | sigma_write(buf, sizeof(buf), devc); | |
163 | ||
164 | return sigma_read(data, len, devc); | |
165 | } | |
166 | ||
167 | static uint8_t sigma_get_register(uint8_t reg, struct dev_context *devc) | |
168 | { | |
169 | uint8_t value; | |
170 | ||
171 | if (1 != sigma_read_register(reg, &value, 1, devc)) { | |
172 | sr_err("sigma_get_register: 1 byte expected"); | |
173 | return 0; | |
174 | } | |
175 | ||
176 | return value; | |
177 | } | |
178 | ||
179 | static int sigma_read_pos(uint32_t *stoppos, uint32_t *triggerpos, | |
180 | struct dev_context *devc) | |
181 | { | |
182 | uint8_t buf[] = { | |
183 | REG_ADDR_LOW | READ_TRIGGER_POS_LOW, | |
184 | ||
185 | REG_READ_ADDR | NEXT_REG, | |
186 | REG_READ_ADDR | NEXT_REG, | |
187 | REG_READ_ADDR | NEXT_REG, | |
188 | REG_READ_ADDR | NEXT_REG, | |
189 | REG_READ_ADDR | NEXT_REG, | |
190 | REG_READ_ADDR | NEXT_REG, | |
191 | }; | |
192 | uint8_t result[6]; | |
193 | ||
194 | sigma_write(buf, sizeof(buf), devc); | |
195 | ||
196 | sigma_read(result, sizeof(result), devc); | |
197 | ||
198 | *triggerpos = result[0] | (result[1] << 8) | (result[2] << 16); | |
199 | *stoppos = result[3] | (result[4] << 8) | (result[5] << 16); | |
200 | ||
201 | /* Not really sure why this must be done, but according to spec. */ | |
202 | if ((--*stoppos & 0x1ff) == 0x1ff) | |
203 | stoppos -= 64; | |
204 | ||
205 | if ((*--triggerpos & 0x1ff) == 0x1ff) | |
206 | triggerpos -= 64; | |
207 | ||
208 | return 1; | |
209 | } | |
210 | ||
211 | static int sigma_read_dram(uint16_t startchunk, size_t numchunks, | |
212 | uint8_t *data, struct dev_context *devc) | |
213 | { | |
214 | size_t i; | |
215 | uint8_t buf[4096]; | |
216 | int idx = 0; | |
217 | ||
218 | /* Send the startchunk. Index start with 1. */ | |
219 | buf[0] = startchunk >> 8; | |
220 | buf[1] = startchunk & 0xff; | |
221 | sigma_write_register(WRITE_MEMROW, buf, 2, devc); | |
222 | ||
223 | /* Read the DRAM. */ | |
224 | buf[idx++] = REG_DRAM_BLOCK; | |
225 | buf[idx++] = REG_DRAM_WAIT_ACK; | |
226 | ||
227 | for (i = 0; i < numchunks; ++i) { | |
228 | /* Alternate bit to copy from DRAM to cache. */ | |
229 | if (i != (numchunks - 1)) | |
230 | buf[idx++] = REG_DRAM_BLOCK | (((i + 1) % 2) << 4); | |
231 | ||
232 | buf[idx++] = REG_DRAM_BLOCK_DATA | ((i % 2) << 4); | |
233 | ||
234 | if (i != (numchunks - 1)) | |
235 | buf[idx++] = REG_DRAM_WAIT_ACK; | |
236 | } | |
237 | ||
238 | sigma_write(buf, idx, devc); | |
239 | ||
240 | return sigma_read(data, numchunks * CHUNK_SIZE, devc); | |
241 | } | |
242 | ||
243 | /* Upload trigger look-up tables to Sigma. */ | |
244 | static int sigma_write_trigger_lut(struct triggerlut *lut, struct dev_context *devc) | |
245 | { | |
246 | int i; | |
247 | uint8_t tmp[2]; | |
248 | uint16_t bit; | |
249 | ||
250 | /* Transpose the table and send to Sigma. */ | |
251 | for (i = 0; i < 16; ++i) { | |
252 | bit = 1 << i; | |
253 | ||
254 | tmp[0] = tmp[1] = 0; | |
255 | ||
256 | if (lut->m2d[0] & bit) | |
257 | tmp[0] |= 0x01; | |
258 | if (lut->m2d[1] & bit) | |
259 | tmp[0] |= 0x02; | |
260 | if (lut->m2d[2] & bit) | |
261 | tmp[0] |= 0x04; | |
262 | if (lut->m2d[3] & bit) | |
263 | tmp[0] |= 0x08; | |
264 | ||
265 | if (lut->m3 & bit) | |
266 | tmp[0] |= 0x10; | |
267 | if (lut->m3s & bit) | |
268 | tmp[0] |= 0x20; | |
269 | if (lut->m4 & bit) | |
270 | tmp[0] |= 0x40; | |
271 | ||
272 | if (lut->m0d[0] & bit) | |
273 | tmp[1] |= 0x01; | |
274 | if (lut->m0d[1] & bit) | |
275 | tmp[1] |= 0x02; | |
276 | if (lut->m0d[2] & bit) | |
277 | tmp[1] |= 0x04; | |
278 | if (lut->m0d[3] & bit) | |
279 | tmp[1] |= 0x08; | |
280 | ||
281 | if (lut->m1d[0] & bit) | |
282 | tmp[1] |= 0x10; | |
283 | if (lut->m1d[1] & bit) | |
284 | tmp[1] |= 0x20; | |
285 | if (lut->m1d[2] & bit) | |
286 | tmp[1] |= 0x40; | |
287 | if (lut->m1d[3] & bit) | |
288 | tmp[1] |= 0x80; | |
289 | ||
290 | sigma_write_register(WRITE_TRIGGER_SELECT0, tmp, sizeof(tmp), | |
291 | devc); | |
292 | sigma_set_register(WRITE_TRIGGER_SELECT1, 0x30 | i, devc); | |
293 | } | |
294 | ||
295 | /* Send the parameters */ | |
296 | sigma_write_register(WRITE_TRIGGER_SELECT0, (uint8_t *) &lut->params, | |
297 | sizeof(lut->params), devc); | |
298 | ||
299 | return SR_OK; | |
300 | } | |
301 | ||
302 | static void clear_helper(void *priv) | |
303 | { | |
304 | struct dev_context *devc; | |
305 | ||
306 | devc = priv; | |
307 | ||
308 | ftdi_deinit(&devc->ftdic); | |
309 | } | |
310 | ||
311 | static int dev_clear(void) | |
312 | { | |
313 | return std_dev_clear(di, clear_helper); | |
314 | } | |
315 | ||
316 | static int init(struct sr_context *sr_ctx) | |
317 | { | |
318 | return std_init(sr_ctx, di, LOG_PREFIX); | |
319 | } | |
320 | ||
321 | static GSList *scan(GSList *options) | |
322 | { | |
323 | struct sr_dev_inst *sdi; | |
324 | struct sr_channel *ch; | |
325 | struct drv_context *drvc; | |
326 | struct dev_context *devc; | |
327 | GSList *devices; | |
328 | struct ftdi_device_list *devlist; | |
329 | char serial_txt[10]; | |
330 | uint32_t serial; | |
331 | int ret; | |
332 | unsigned int i; | |
333 | ||
334 | (void)options; | |
335 | ||
336 | drvc = di->priv; | |
337 | ||
338 | devices = NULL; | |
339 | ||
340 | if (!(devc = g_try_malloc(sizeof(struct dev_context)))) { | |
341 | sr_err("%s: devc malloc failed", __func__); | |
342 | return NULL; | |
343 | } | |
344 | ||
345 | ftdi_init(&devc->ftdic); | |
346 | ||
347 | /* Look for SIGMAs. */ | |
348 | ||
349 | if ((ret = ftdi_usb_find_all(&devc->ftdic, &devlist, | |
350 | USB_VENDOR, USB_PRODUCT)) <= 0) { | |
351 | if (ret < 0) | |
352 | sr_err("ftdi_usb_find_all(): %d", ret); | |
353 | goto free; | |
354 | } | |
355 | ||
356 | /* Make sure it's a version 1 or 2 SIGMA. */ | |
357 | ftdi_usb_get_strings(&devc->ftdic, devlist->dev, NULL, 0, NULL, 0, | |
358 | serial_txt, sizeof(serial_txt)); | |
359 | sscanf(serial_txt, "%x", &serial); | |
360 | ||
361 | if (serial < 0xa6010000 || serial > 0xa602ffff) { | |
362 | sr_err("Only SIGMA and SIGMA2 are supported " | |
363 | "in this version of libsigrok."); | |
364 | goto free; | |
365 | } | |
366 | ||
367 | sr_info("Found ASIX SIGMA - Serial: %s", serial_txt); | |
368 | ||
369 | devc->cur_samplerate = 0; | |
370 | devc->period_ps = 0; | |
371 | devc->limit_msec = 0; | |
372 | devc->cur_firmware = -1; | |
373 | devc->num_channels = 0; | |
374 | devc->samples_per_event = 0; | |
375 | devc->capture_ratio = 50; | |
376 | devc->use_triggers = 0; | |
377 | ||
378 | /* Register SIGMA device. */ | |
379 | if (!(sdi = sr_dev_inst_new(0, SR_ST_INITIALIZING, USB_VENDOR_NAME, | |
380 | USB_MODEL_NAME, NULL))) { | |
381 | sr_err("%s: sdi was NULL", __func__); | |
382 | goto free; | |
383 | } | |
384 | sdi->driver = di; | |
385 | ||
386 | for (i = 0; i < ARRAY_SIZE(channel_names); i++) { | |
387 | ch = sr_channel_new(i, SR_CHANNEL_LOGIC, TRUE, | |
388 | channel_names[i]); | |
389 | if (!ch) | |
390 | return NULL; | |
391 | sdi->channels = g_slist_append(sdi->channels, ch); | |
392 | } | |
393 | ||
394 | devices = g_slist_append(devices, sdi); | |
395 | drvc->instances = g_slist_append(drvc->instances, sdi); | |
396 | sdi->priv = devc; | |
397 | ||
398 | /* We will open the device again when we need it. */ | |
399 | ftdi_list_free(&devlist); | |
400 | ||
401 | return devices; | |
402 | ||
403 | free: | |
404 | ftdi_deinit(&devc->ftdic); | |
405 | g_free(devc); | |
406 | return NULL; | |
407 | } | |
408 | ||
409 | static GSList *dev_list(void) | |
410 | { | |
411 | return ((struct drv_context *)(di->priv))->instances; | |
412 | } | |
413 | ||
414 | /* | |
415 | * Configure the FPGA for bitbang mode. | |
416 | * This sequence is documented in section 2. of the ASIX Sigma programming | |
417 | * manual. This sequence is necessary to configure the FPGA in the Sigma | |
418 | * into Bitbang mode, in which it can be programmed with the firmware. | |
419 | */ | |
420 | static int sigma_fpga_init_bitbang(struct dev_context *devc) | |
421 | { | |
422 | uint8_t suicide[] = { | |
423 | 0x84, 0x84, 0x88, 0x84, 0x88, 0x84, 0x88, 0x84, | |
424 | }; | |
425 | uint8_t init_array[] = { | |
426 | 0x01, 0x03, 0x03, 0x01, 0x01, 0x01, 0x01, 0x01, | |
427 | 0x01, 0x01, | |
428 | }; | |
429 | int i, ret, timeout = 10000; | |
430 | uint8_t data; | |
431 | ||
432 | /* Section 2. part 1), do the FPGA suicide. */ | |
433 | sigma_write(suicide, sizeof(suicide), devc); | |
434 | sigma_write(suicide, sizeof(suicide), devc); | |
435 | sigma_write(suicide, sizeof(suicide), devc); | |
436 | sigma_write(suicide, sizeof(suicide), devc); | |
437 | ||
438 | /* Section 2. part 2), do pulse on D1. */ | |
439 | sigma_write(init_array, sizeof(init_array), devc); | |
440 | ftdi_usb_purge_buffers(&devc->ftdic); | |
441 | ||
442 | /* Wait until the FPGA asserts D6/INIT_B. */ | |
443 | for (i = 0; i < timeout; i++) { | |
444 | ret = sigma_read(&data, 1, devc); | |
445 | if (ret < 0) | |
446 | return ret; | |
447 | /* Test if pin D6 got asserted. */ | |
448 | if (data & (1 << 5)) | |
449 | return 0; | |
450 | /* The D6 was not asserted yet, wait a bit. */ | |
451 | usleep(10000); | |
452 | } | |
453 | ||
454 | return SR_ERR_TIMEOUT; | |
455 | } | |
456 | ||
457 | /* | |
458 | * Read the firmware from a file and transform it into a series of bitbang | |
459 | * pulses used to program the FPGA. Note that the *bb_cmd must be free()'d | |
460 | * by the caller of this function. | |
461 | */ | |
462 | static int sigma_fw_2_bitbang(const char *filename, | |
463 | uint8_t **bb_cmd, gsize *bb_cmd_size) | |
464 | { | |
465 | GMappedFile *file; | |
466 | GError *error; | |
467 | gsize i, file_size, bb_size; | |
468 | gchar *firmware; | |
469 | uint8_t *bb_stream, *bbs; | |
470 | uint32_t imm; | |
471 | int bit, v; | |
472 | int ret = SR_OK; | |
473 | ||
474 | /* | |
475 | * Map the file and make the mapped buffer writable. | |
476 | * NOTE: Using writable=TRUE does _NOT_ mean that file that is mapped | |
477 | * will be modified. It will not be modified until someone uses | |
478 | * g_file_set_contents() on it. | |
479 | */ | |
480 | error = NULL; | |
481 | file = g_mapped_file_new(filename, TRUE, &error); | |
482 | g_assert_no_error(error); | |
483 | ||
484 | file_size = g_mapped_file_get_length(file); | |
485 | firmware = g_mapped_file_get_contents(file); | |
486 | g_assert(firmware); | |
487 | ||
488 | /* Weird magic transformation below, I have no idea what it does. */ | |
489 | imm = 0x3f6df2ab; | |
490 | for (i = 0; i < file_size; i++) { | |
491 | imm = (imm + 0xa853753) % 177 + (imm * 0x8034052); | |
492 | firmware[i] ^= imm & 0xff; | |
493 | } | |
494 | ||
495 | /* | |
496 | * Now that the firmware is "transformed", we will transcribe the | |
497 | * firmware blob into a sequence of toggles of the Dx wires. This | |
498 | * sequence will be fed directly into the Sigma, which must be in | |
499 | * the FPGA bitbang programming mode. | |
500 | */ | |
501 | ||
502 | /* Each bit of firmware is transcribed as two toggles of Dx wires. */ | |
503 | bb_size = file_size * 8 * 2; | |
504 | bb_stream = (uint8_t *)g_try_malloc(bb_size); | |
505 | if (!bb_stream) { | |
506 | sr_err("%s: Failed to allocate bitbang stream", __func__); | |
507 | ret = SR_ERR_MALLOC; | |
508 | goto exit; | |
509 | } | |
510 | ||
511 | bbs = bb_stream; | |
512 | for (i = 0; i < file_size; i++) { | |
513 | for (bit = 7; bit >= 0; bit--) { | |
514 | v = (firmware[i] & (1 << bit)) ? 0x40 : 0x00; | |
515 | *bbs++ = v | 0x01; | |
516 | *bbs++ = v; | |
517 | } | |
518 | } | |
519 | ||
520 | /* The transformation completed successfully, return the result. */ | |
521 | *bb_cmd = bb_stream; | |
522 | *bb_cmd_size = bb_size; | |
523 | ||
524 | exit: | |
525 | g_mapped_file_unref(file); | |
526 | return ret; | |
527 | } | |
528 | ||
529 | static int upload_firmware(int firmware_idx, struct dev_context *devc) | |
530 | { | |
531 | int ret; | |
532 | unsigned char *buf; | |
533 | unsigned char pins; | |
534 | size_t buf_size; | |
535 | unsigned char result[32]; | |
536 | const char *firmware = sigma_firmware_files[firmware_idx]; | |
537 | struct ftdi_context *ftdic = &devc->ftdic; | |
538 | ||
539 | /* Make sure it's an ASIX SIGMA. */ | |
540 | ret = ftdi_usb_open_desc(ftdic, USB_VENDOR, USB_PRODUCT, | |
541 | USB_DESCRIPTION, NULL); | |
542 | if (ret < 0) { | |
543 | sr_err("ftdi_usb_open failed: %s", | |
544 | ftdi_get_error_string(ftdic)); | |
545 | return 0; | |
546 | } | |
547 | ||
548 | ret = ftdi_set_bitmode(ftdic, 0xdf, BITMODE_BITBANG); | |
549 | if (ret < 0) { | |
550 | sr_err("ftdi_set_bitmode failed: %s", | |
551 | ftdi_get_error_string(ftdic)); | |
552 | return 0; | |
553 | } | |
554 | ||
555 | /* Four times the speed of sigmalogan - Works well. */ | |
556 | ret = ftdi_set_baudrate(ftdic, 750000); | |
557 | if (ret < 0) { | |
558 | sr_err("ftdi_set_baudrate failed: %s", | |
559 | ftdi_get_error_string(ftdic)); | |
560 | return 0; | |
561 | } | |
562 | ||
563 | /* Initialize the FPGA for firmware upload. */ | |
564 | ret = sigma_fpga_init_bitbang(devc); | |
565 | if (ret) | |
566 | return ret; | |
567 | ||
568 | /* Prepare firmware. */ | |
569 | ret = sigma_fw_2_bitbang(firmware, &buf, &buf_size); | |
570 | if (ret != SR_OK) { | |
571 | sr_err("An error occured while reading the firmware: %s", | |
572 | firmware); | |
573 | return ret; | |
574 | } | |
575 | ||
576 | /* Upload firmare. */ | |
577 | sr_info("Uploading firmware file '%s'.", firmware); | |
578 | sigma_write(buf, buf_size, devc); | |
579 | ||
580 | g_free(buf); | |
581 | ||
582 | ret = ftdi_set_bitmode(ftdic, 0x00, BITMODE_RESET); | |
583 | if (ret < 0) { | |
584 | sr_err("ftdi_set_bitmode failed: %s", | |
585 | ftdi_get_error_string(ftdic)); | |
586 | return SR_ERR; | |
587 | } | |
588 | ||
589 | ftdi_usb_purge_buffers(ftdic); | |
590 | ||
591 | /* Discard garbage. */ | |
592 | while (sigma_read(&pins, 1, devc) == 1) | |
593 | ; | |
594 | ||
595 | /* Initialize the logic analyzer mode. */ | |
596 | sigma_write(logic_mode_start, sizeof(logic_mode_start), devc); | |
597 | ||
598 | /* Expect a 3 byte reply. */ | |
599 | ret = sigma_read(result, 3, devc); | |
600 | if (ret != 3 || | |
601 | result[0] != 0xa6 || result[1] != 0x55 || result[2] != 0xaa) { | |
602 | sr_err("Configuration failed. Invalid reply received."); | |
603 | return SR_ERR; | |
604 | } | |
605 | ||
606 | devc->cur_firmware = firmware_idx; | |
607 | ||
608 | sr_info("Firmware uploaded."); | |
609 | ||
610 | return SR_OK; | |
611 | } | |
612 | ||
613 | static int dev_open(struct sr_dev_inst *sdi) | |
614 | { | |
615 | struct dev_context *devc; | |
616 | int ret; | |
617 | ||
618 | devc = sdi->priv; | |
619 | ||
620 | /* Make sure it's an ASIX SIGMA. */ | |
621 | if ((ret = ftdi_usb_open_desc(&devc->ftdic, | |
622 | USB_VENDOR, USB_PRODUCT, USB_DESCRIPTION, NULL)) < 0) { | |
623 | ||
624 | sr_err("ftdi_usb_open failed: %s", | |
625 | ftdi_get_error_string(&devc->ftdic)); | |
626 | ||
627 | return 0; | |
628 | } | |
629 | ||
630 | sdi->status = SR_ST_ACTIVE; | |
631 | ||
632 | return SR_OK; | |
633 | } | |
634 | ||
635 | static int set_samplerate(const struct sr_dev_inst *sdi, uint64_t samplerate) | |
636 | { | |
637 | struct dev_context *devc; | |
638 | unsigned int i; | |
639 | int ret; | |
640 | ||
641 | devc = sdi->priv; | |
642 | ret = SR_OK; | |
643 | ||
644 | for (i = 0; i < ARRAY_SIZE(samplerates); i++) { | |
645 | if (samplerates[i] == samplerate) | |
646 | break; | |
647 | } | |
648 | if (samplerates[i] == 0) | |
649 | return SR_ERR_SAMPLERATE; | |
650 | ||
651 | if (samplerate <= SR_MHZ(50)) { | |
652 | ret = upload_firmware(0, devc); | |
653 | devc->num_channels = 16; | |
654 | } | |
655 | if (samplerate == SR_MHZ(100)) { | |
656 | ret = upload_firmware(1, devc); | |
657 | devc->num_channels = 8; | |
658 | } | |
659 | else if (samplerate == SR_MHZ(200)) { | |
660 | ret = upload_firmware(2, devc); | |
661 | devc->num_channels = 4; | |
662 | } | |
663 | ||
664 | devc->cur_samplerate = samplerate; | |
665 | devc->period_ps = 1000000000000ULL / samplerate; | |
666 | devc->samples_per_event = 16 / devc->num_channels; | |
667 | devc->state.state = SIGMA_IDLE; | |
668 | ||
669 | return ret; | |
670 | } | |
671 | ||
672 | /* | |
673 | * In 100 and 200 MHz mode, only a single pin rising/falling can be | |
674 | * set as trigger. In other modes, two rising/falling triggers can be set, | |
675 | * in addition to value/mask trigger for any number of channels. | |
676 | * | |
677 | * The Sigma supports complex triggers using boolean expressions, but this | |
678 | * has not been implemented yet. | |
679 | */ | |
680 | static int configure_channels(const struct sr_dev_inst *sdi) | |
681 | { | |
682 | struct dev_context *devc = sdi->priv; | |
683 | const struct sr_channel *ch; | |
684 | const GSList *l; | |
685 | int trigger_set = 0; | |
686 | int channelbit; | |
687 | ||
688 | memset(&devc->trigger, 0, sizeof(struct sigma_trigger)); | |
689 | ||
690 | for (l = sdi->channels; l; l = l->next) { | |
691 | ch = (struct sr_channel *)l->data; | |
692 | channelbit = 1 << (ch->index); | |
693 | ||
694 | if (!ch->enabled || !ch->trigger) | |
695 | continue; | |
696 | ||
697 | if (devc->cur_samplerate >= SR_MHZ(100)) { | |
698 | /* Fast trigger support. */ | |
699 | if (trigger_set) { | |
700 | sr_err("Only a single pin trigger in 100 and " | |
701 | "200MHz mode is supported."); | |
702 | return SR_ERR; | |
703 | } | |
704 | if (ch->trigger[0] == 'f') | |
705 | devc->trigger.fallingmask |= channelbit; | |
706 | else if (ch->trigger[0] == 'r') | |
707 | devc->trigger.risingmask |= channelbit; | |
708 | else { | |
709 | sr_err("Only rising/falling trigger in 100 " | |
710 | "and 200MHz mode is supported."); | |
711 | return SR_ERR; | |
712 | } | |
713 | ||
714 | ++trigger_set; | |
715 | } else { | |
716 | /* Simple trigger support (event). */ | |
717 | if (ch->trigger[0] == '1') { | |
718 | devc->trigger.simplevalue |= channelbit; | |
719 | devc->trigger.simplemask |= channelbit; | |
720 | } | |
721 | else if (ch->trigger[0] == '0') { | |
722 | devc->trigger.simplevalue &= ~channelbit; | |
723 | devc->trigger.simplemask |= channelbit; | |
724 | } | |
725 | else if (ch->trigger[0] == 'f') { | |
726 | devc->trigger.fallingmask |= channelbit; | |
727 | ++trigger_set; | |
728 | } | |
729 | else if (ch->trigger[0] == 'r') { | |
730 | devc->trigger.risingmask |= channelbit; | |
731 | ++trigger_set; | |
732 | } | |
733 | ||
734 | /* | |
735 | * Actually, Sigma supports 2 rising/falling triggers, | |
736 | * but they are ORed and the current trigger syntax | |
737 | * does not permit ORed triggers. | |
738 | */ | |
739 | if (trigger_set > 1) { | |
740 | sr_err("Only 1 rising/falling trigger " | |
741 | "is supported."); | |
742 | return SR_ERR; | |
743 | } | |
744 | } | |
745 | ||
746 | if (trigger_set) | |
747 | devc->use_triggers = 1; | |
748 | } | |
749 | ||
750 | return SR_OK; | |
751 | } | |
752 | ||
753 | static int dev_close(struct sr_dev_inst *sdi) | |
754 | { | |
755 | struct dev_context *devc; | |
756 | ||
757 | devc = sdi->priv; | |
758 | ||
759 | /* TODO */ | |
760 | if (sdi->status == SR_ST_ACTIVE) | |
761 | ftdi_usb_close(&devc->ftdic); | |
762 | ||
763 | sdi->status = SR_ST_INACTIVE; | |
764 | ||
765 | return SR_OK; | |
766 | } | |
767 | ||
768 | static int cleanup(void) | |
769 | { | |
770 | return dev_clear(); | |
771 | } | |
772 | ||
773 | static int config_get(int id, GVariant **data, const struct sr_dev_inst *sdi, | |
774 | const struct sr_channel_group *cg) | |
775 | { | |
776 | struct dev_context *devc; | |
777 | ||
778 | (void)cg; | |
779 | ||
780 | switch (id) { | |
781 | case SR_CONF_SAMPLERATE: | |
782 | if (sdi) { | |
783 | devc = sdi->priv; | |
784 | *data = g_variant_new_uint64(devc->cur_samplerate); | |
785 | } else | |
786 | return SR_ERR; | |
787 | break; | |
788 | default: | |
789 | return SR_ERR_NA; | |
790 | } | |
791 | ||
792 | return SR_OK; | |
793 | } | |
794 | ||
795 | static int config_set(int id, GVariant *data, const struct sr_dev_inst *sdi, | |
796 | const struct sr_channel_group *cg) | |
797 | { | |
798 | struct dev_context *devc; | |
799 | uint64_t num_samples; | |
800 | int ret; | |
801 | ||
802 | (void)cg; | |
803 | ||
804 | if (sdi->status != SR_ST_ACTIVE) | |
805 | return SR_ERR_DEV_CLOSED; | |
806 | ||
807 | devc = sdi->priv; | |
808 | ||
809 | switch (id) { | |
810 | case SR_CONF_SAMPLERATE: | |
811 | ret = set_samplerate(sdi, g_variant_get_uint64(data)); | |
812 | break; | |
813 | case SR_CONF_LIMIT_MSEC: | |
814 | devc->limit_msec = g_variant_get_uint64(data); | |
815 | if (devc->limit_msec > 0) | |
816 | ret = SR_OK; | |
817 | else | |
818 | ret = SR_ERR; | |
819 | break; | |
820 | case SR_CONF_LIMIT_SAMPLES: | |
821 | num_samples = g_variant_get_uint64(data); | |
822 | devc->limit_msec = num_samples * 1000 / devc->cur_samplerate; | |
823 | break; | |
824 | case SR_CONF_CAPTURE_RATIO: | |
825 | devc->capture_ratio = g_variant_get_uint64(data); | |
826 | if (devc->capture_ratio < 0 || devc->capture_ratio > 100) | |
827 | ret = SR_ERR; | |
828 | else | |
829 | ret = SR_OK; | |
830 | break; | |
831 | default: | |
832 | ret = SR_ERR_NA; | |
833 | } | |
834 | ||
835 | return ret; | |
836 | } | |
837 | ||
838 | static int config_list(int key, GVariant **data, const struct sr_dev_inst *sdi, | |
839 | const struct sr_channel_group *cg) | |
840 | { | |
841 | GVariant *gvar; | |
842 | GVariantBuilder gvb; | |
843 | ||
844 | (void)sdi; | |
845 | (void)cg; | |
846 | ||
847 | switch (key) { | |
848 | case SR_CONF_DEVICE_OPTIONS: | |
849 | *data = g_variant_new_fixed_array(G_VARIANT_TYPE_INT32, | |
850 | hwcaps, ARRAY_SIZE(hwcaps), sizeof(int32_t)); | |
851 | break; | |
852 | case SR_CONF_SAMPLERATE: | |
853 | g_variant_builder_init(&gvb, G_VARIANT_TYPE("a{sv}")); | |
854 | gvar = g_variant_new_fixed_array(G_VARIANT_TYPE("t"), samplerates, | |
855 | ARRAY_SIZE(samplerates), sizeof(uint64_t)); | |
856 | g_variant_builder_add(&gvb, "{sv}", "samplerates", gvar); | |
857 | *data = g_variant_builder_end(&gvb); | |
858 | break; | |
859 | case SR_CONF_TRIGGER_TYPE: | |
860 | *data = g_variant_new_string(TRIGGER_TYPE); | |
861 | break; | |
862 | default: | |
863 | return SR_ERR_NA; | |
864 | } | |
865 | ||
866 | return SR_OK; | |
867 | } | |
868 | ||
869 | /* Software trigger to determine exact trigger position. */ | |
870 | static int get_trigger_offset(uint16_t *samples, uint16_t last_sample, | |
871 | struct sigma_trigger *t) | |
872 | { | |
873 | int i; | |
874 | ||
875 | for (i = 0; i < 8; ++i) { | |
876 | if (i > 0) | |
877 | last_sample = samples[i-1]; | |
878 | ||
879 | /* Simple triggers. */ | |
880 | if ((samples[i] & t->simplemask) != t->simplevalue) | |
881 | continue; | |
882 | ||
883 | /* Rising edge. */ | |
884 | if ((last_sample & t->risingmask) != 0 || (samples[i] & | |
885 | t->risingmask) != t->risingmask) | |
886 | continue; | |
887 | ||
888 | /* Falling edge. */ | |
889 | if ((last_sample & t->fallingmask) != t->fallingmask || | |
890 | (samples[i] & t->fallingmask) != 0) | |
891 | continue; | |
892 | ||
893 | break; | |
894 | } | |
895 | ||
896 | /* If we did not match, return original trigger pos. */ | |
897 | return i & 0x7; | |
898 | } | |
899 | ||
900 | /* | |
901 | * Decode chunk of 1024 bytes, 64 clusters, 7 events per cluster. | |
902 | * Each event is 20ns apart, and can contain multiple samples. | |
903 | * | |
904 | * For 200 MHz, events contain 4 samples for each channel, spread 5 ns apart. | |
905 | * For 100 MHz, events contain 2 samples for each channel, spread 10 ns apart. | |
906 | * For 50 MHz and below, events contain one sample for each channel, | |
907 | * spread 20 ns apart. | |
908 | */ | |
909 | static int decode_chunk_ts(uint8_t *buf, uint16_t *lastts, | |
910 | uint16_t *lastsample, int triggerpos, | |
911 | uint16_t limit_chunk, void *cb_data) | |
912 | { | |
913 | struct sr_dev_inst *sdi = cb_data; | |
914 | struct dev_context *devc = sdi->priv; | |
915 | uint16_t tsdiff, ts; | |
916 | uint16_t samples[65536 * devc->samples_per_event]; | |
917 | struct sr_datafeed_packet packet; | |
918 | struct sr_datafeed_logic logic; | |
919 | int i, j, k, l, numpad, tosend; | |
920 | size_t n = 0, sent = 0; | |
921 | int clustersize = EVENTS_PER_CLUSTER * devc->samples_per_event; | |
922 | uint16_t *event; | |
923 | uint16_t cur_sample; | |
924 | int triggerts = -1; | |
925 | ||
926 | /* Check if trigger is in this chunk. */ | |
927 | if (triggerpos != -1) { | |
928 | if (devc->cur_samplerate <= SR_MHZ(50)) | |
929 | triggerpos -= EVENTS_PER_CLUSTER - 1; | |
930 | ||
931 | if (triggerpos < 0) | |
932 | triggerpos = 0; | |
933 | ||
934 | /* Find in which cluster the trigger occured. */ | |
935 | triggerts = triggerpos / 7; | |
936 | } | |
937 | ||
938 | /* For each ts. */ | |
939 | for (i = 0; i < 64; ++i) { | |
940 | ts = *(uint16_t *) &buf[i * 16]; | |
941 | tsdiff = ts - *lastts; | |
942 | *lastts = ts; | |
943 | ||
944 | /* Decode partial chunk. */ | |
945 | if (limit_chunk && ts > limit_chunk) | |
946 | return SR_OK; | |
947 | ||
948 | /* Pad last sample up to current point. */ | |
949 | numpad = tsdiff * devc->samples_per_event - clustersize; | |
950 | if (numpad > 0) { | |
951 | for (j = 0; j < numpad; ++j) | |
952 | samples[j] = *lastsample; | |
953 | ||
954 | n = numpad; | |
955 | } | |
956 | ||
957 | /* Send samples between previous and this timestamp to sigrok. */ | |
958 | sent = 0; | |
959 | while (sent < n) { | |
960 | tosend = MIN(2048, n - sent); | |
961 | ||
962 | packet.type = SR_DF_LOGIC; | |
963 | packet.payload = &logic; | |
964 | logic.length = tosend * sizeof(uint16_t); | |
965 | logic.unitsize = 2; | |
966 | logic.data = samples + sent; | |
967 | sr_session_send(devc->cb_data, &packet); | |
968 | ||
969 | sent += tosend; | |
970 | } | |
971 | n = 0; | |
972 | ||
973 | event = (uint16_t *) &buf[i * 16 + 2]; | |
974 | cur_sample = 0; | |
975 | ||
976 | /* For each event in cluster. */ | |
977 | for (j = 0; j < 7; ++j) { | |
978 | ||
979 | /* For each sample in event. */ | |
980 | for (k = 0; k < devc->samples_per_event; ++k) { | |
981 | cur_sample = 0; | |
982 | ||
983 | /* For each channel. */ | |
984 | for (l = 0; l < devc->num_channels; ++l) | |
985 | cur_sample |= (!!(event[j] & (1 << (l * | |
986 | devc->samples_per_event + k)))) << l; | |
987 | ||
988 | samples[n++] = cur_sample; | |
989 | } | |
990 | } | |
991 | ||
992 | /* Send data up to trigger point (if triggered). */ | |
993 | sent = 0; | |
994 | if (i == triggerts) { | |
995 | /* | |
996 | * Trigger is not always accurate to sample because of | |
997 | * pipeline delay. However, it always triggers before | |
998 | * the actual event. We therefore look at the next | |
999 | * samples to pinpoint the exact position of the trigger. | |
1000 | */ | |
1001 | tosend = get_trigger_offset(samples, *lastsample, | |
1002 | &devc->trigger); | |
1003 | ||
1004 | if (tosend > 0) { | |
1005 | packet.type = SR_DF_LOGIC; | |
1006 | packet.payload = &logic; | |
1007 | logic.length = tosend * sizeof(uint16_t); | |
1008 | logic.unitsize = 2; | |
1009 | logic.data = samples; | |
1010 | sr_session_send(devc->cb_data, &packet); | |
1011 | ||
1012 | sent += tosend; | |
1013 | } | |
1014 | ||
1015 | /* Only send trigger if explicitly enabled. */ | |
1016 | if (devc->use_triggers) { | |
1017 | packet.type = SR_DF_TRIGGER; | |
1018 | sr_session_send(devc->cb_data, &packet); | |
1019 | } | |
1020 | } | |
1021 | ||
1022 | /* Send rest of the chunk to sigrok. */ | |
1023 | tosend = n - sent; | |
1024 | ||
1025 | if (tosend > 0) { | |
1026 | packet.type = SR_DF_LOGIC; | |
1027 | packet.payload = &logic; | |
1028 | logic.length = tosend * sizeof(uint16_t); | |
1029 | logic.unitsize = 2; | |
1030 | logic.data = samples + sent; | |
1031 | sr_session_send(devc->cb_data, &packet); | |
1032 | } | |
1033 | ||
1034 | *lastsample = samples[n - 1]; | |
1035 | } | |
1036 | ||
1037 | return SR_OK; | |
1038 | } | |
1039 | ||
1040 | static void download_capture(struct sr_dev_inst *sdi) | |
1041 | { | |
1042 | struct dev_context *devc; | |
1043 | const int chunks_per_read = 32; | |
1044 | unsigned char buf[chunks_per_read * CHUNK_SIZE]; | |
1045 | int bufsz, i, numchunks, newchunks; | |
1046 | ||
1047 | sr_info("Downloading sample data."); | |
1048 | ||
1049 | devc = sdi->priv; | |
1050 | devc->state.chunks_downloaded = 0; | |
1051 | numchunks = (devc->state.stoppos + 511) / 512; | |
1052 | newchunks = MIN(chunks_per_read, numchunks - devc->state.chunks_downloaded); | |
1053 | ||
1054 | bufsz = sigma_read_dram(devc->state.chunks_downloaded, newchunks, buf, devc); | |
1055 | /* TODO: Check bufsz. For now, just avoid compiler warnings. */ | |
1056 | (void)bufsz; | |
1057 | ||
1058 | /* Find first ts. */ | |
1059 | if (devc->state.chunks_downloaded == 0) { | |
1060 | devc->state.lastts = RL16(buf) - 1; | |
1061 | devc->state.lastsample = 0; | |
1062 | } | |
1063 | ||
1064 | /* Decode chunks and send them to sigrok. */ | |
1065 | for (i = 0; i < newchunks; ++i) { | |
1066 | int limit_chunk = 0; | |
1067 | ||
1068 | /* The last chunk may potentially be only in part. */ | |
1069 | if (devc->state.chunks_downloaded == numchunks - 1) { | |
1070 | /* Find the last valid timestamp */ | |
1071 | limit_chunk = devc->state.stoppos % 512 + devc->state.lastts; | |
1072 | } | |
1073 | ||
1074 | if (devc->state.chunks_downloaded + i == devc->state.triggerchunk) | |
1075 | decode_chunk_ts(buf + (i * CHUNK_SIZE), | |
1076 | &devc->state.lastts, | |
1077 | &devc->state.lastsample, | |
1078 | devc->state.triggerpos & 0x1ff, | |
1079 | limit_chunk, sdi); | |
1080 | else | |
1081 | decode_chunk_ts(buf + (i * CHUNK_SIZE), | |
1082 | &devc->state.lastts, | |
1083 | &devc->state.lastsample, | |
1084 | -1, limit_chunk, sdi); | |
1085 | ||
1086 | ++devc->state.chunks_downloaded; | |
1087 | } | |
1088 | ||
1089 | } | |
1090 | ||
1091 | static int receive_data(int fd, int revents, void *cb_data) | |
1092 | { | |
1093 | struct sr_dev_inst *sdi; | |
1094 | struct dev_context *devc; | |
1095 | struct sr_datafeed_packet packet; | |
1096 | uint64_t running_msec; | |
1097 | struct timeval tv; | |
1098 | int numchunks; | |
1099 | uint8_t modestatus; | |
1100 | ||
1101 | (void)fd; | |
1102 | (void)revents; | |
1103 | ||
1104 | sdi = cb_data; | |
1105 | devc = sdi->priv; | |
1106 | ||
1107 | /* Get the current position. */ | |
1108 | sigma_read_pos(&devc->state.stoppos, &devc->state.triggerpos, devc); | |
1109 | ||
1110 | if (devc->state.state == SIGMA_IDLE) | |
1111 | return TRUE; | |
1112 | ||
1113 | if (devc->state.state == SIGMA_CAPTURE) { | |
1114 | numchunks = (devc->state.stoppos + 511) / 512; | |
1115 | ||
1116 | /* Check if the timer has expired, or memory is full. */ | |
1117 | gettimeofday(&tv, 0); | |
1118 | running_msec = (tv.tv_sec - devc->start_tv.tv_sec) * 1000 + | |
1119 | (tv.tv_usec - devc->start_tv.tv_usec) / 1000; | |
1120 | ||
1121 | if (running_msec < devc->limit_msec && numchunks < 32767) | |
1122 | /* Still capturing. */ | |
1123 | return TRUE; | |
1124 | ||
1125 | /* Stop acquisition. */ | |
1126 | sigma_set_register(WRITE_MODE, 0x11, devc); | |
1127 | ||
1128 | /* Set SDRAM Read Enable. */ | |
1129 | sigma_set_register(WRITE_MODE, 0x02, devc); | |
1130 | ||
1131 | /* Get the current position. */ | |
1132 | sigma_read_pos(&devc->state.stoppos, &devc->state.triggerpos, devc); | |
1133 | ||
1134 | /* Check if trigger has fired. */ | |
1135 | modestatus = sigma_get_register(READ_MODE, devc); | |
1136 | if (modestatus & 0x20) | |
1137 | devc->state.triggerchunk = devc->state.triggerpos / 512; | |
1138 | else | |
1139 | devc->state.triggerchunk = -1; | |
1140 | ||
1141 | /* Transfer captured data from device. */ | |
1142 | download_capture(sdi); | |
1143 | ||
1144 | /* All done. */ | |
1145 | packet.type = SR_DF_END; | |
1146 | sr_session_send(sdi, &packet); | |
1147 | ||
1148 | dev_acquisition_stop(sdi, sdi); | |
1149 | } | |
1150 | ||
1151 | return TRUE; | |
1152 | } | |
1153 | ||
1154 | /* Build a LUT entry used by the trigger functions. */ | |
1155 | static void build_lut_entry(uint16_t value, uint16_t mask, uint16_t *entry) | |
1156 | { | |
1157 | int i, j, k, bit; | |
1158 | ||
1159 | /* For each quad channel. */ | |
1160 | for (i = 0; i < 4; ++i) { | |
1161 | entry[i] = 0xffff; | |
1162 | ||
1163 | /* For each bit in LUT. */ | |
1164 | for (j = 0; j < 16; ++j) | |
1165 | ||
1166 | /* For each channel in quad. */ | |
1167 | for (k = 0; k < 4; ++k) { | |
1168 | bit = 1 << (i * 4 + k); | |
1169 | ||
1170 | /* Set bit in entry */ | |
1171 | if ((mask & bit) && | |
1172 | ((!(value & bit)) != | |
1173 | (!(j & (1 << k))))) | |
1174 | entry[i] &= ~(1 << j); | |
1175 | } | |
1176 | } | |
1177 | } | |
1178 | ||
1179 | /* Add a logical function to LUT mask. */ | |
1180 | static void add_trigger_function(enum triggerop oper, enum triggerfunc func, | |
1181 | int index, int neg, uint16_t *mask) | |
1182 | { | |
1183 | int i, j; | |
1184 | int x[2][2], tmp, a, b, aset, bset, rset; | |
1185 | ||
1186 | memset(x, 0, 4 * sizeof(int)); | |
1187 | ||
1188 | /* Trigger detect condition. */ | |
1189 | switch (oper) { | |
1190 | case OP_LEVEL: | |
1191 | x[0][1] = 1; | |
1192 | x[1][1] = 1; | |
1193 | break; | |
1194 | case OP_NOT: | |
1195 | x[0][0] = 1; | |
1196 | x[1][0] = 1; | |
1197 | break; | |
1198 | case OP_RISE: | |
1199 | x[0][1] = 1; | |
1200 | break; | |
1201 | case OP_FALL: | |
1202 | x[1][0] = 1; | |
1203 | break; | |
1204 | case OP_RISEFALL: | |
1205 | x[0][1] = 1; | |
1206 | x[1][0] = 1; | |
1207 | break; | |
1208 | case OP_NOTRISE: | |
1209 | x[1][1] = 1; | |
1210 | x[0][0] = 1; | |
1211 | x[1][0] = 1; | |
1212 | break; | |
1213 | case OP_NOTFALL: | |
1214 | x[1][1] = 1; | |
1215 | x[0][0] = 1; | |
1216 | x[0][1] = 1; | |
1217 | break; | |
1218 | case OP_NOTRISEFALL: | |
1219 | x[1][1] = 1; | |
1220 | x[0][0] = 1; | |
1221 | break; | |
1222 | } | |
1223 | ||
1224 | /* Transpose if neg is set. */ | |
1225 | if (neg) { | |
1226 | for (i = 0; i < 2; ++i) { | |
1227 | for (j = 0; j < 2; ++j) { | |
1228 | tmp = x[i][j]; | |
1229 | x[i][j] = x[1-i][1-j]; | |
1230 | x[1-i][1-j] = tmp; | |
1231 | } | |
1232 | } | |
1233 | } | |
1234 | ||
1235 | /* Update mask with function. */ | |
1236 | for (i = 0; i < 16; ++i) { | |
1237 | a = (i >> (2 * index + 0)) & 1; | |
1238 | b = (i >> (2 * index + 1)) & 1; | |
1239 | ||
1240 | aset = (*mask >> i) & 1; | |
1241 | bset = x[b][a]; | |
1242 | ||
1243 | if (func == FUNC_AND || func == FUNC_NAND) | |
1244 | rset = aset & bset; | |
1245 | else if (func == FUNC_OR || func == FUNC_NOR) | |
1246 | rset = aset | bset; | |
1247 | else if (func == FUNC_XOR || func == FUNC_NXOR) | |
1248 | rset = aset ^ bset; | |
1249 | ||
1250 | if (func == FUNC_NAND || func == FUNC_NOR || func == FUNC_NXOR) | |
1251 | rset = !rset; | |
1252 | ||
1253 | *mask &= ~(1 << i); | |
1254 | ||
1255 | if (rset) | |
1256 | *mask |= 1 << i; | |
1257 | } | |
1258 | } | |
1259 | ||
1260 | /* | |
1261 | * Build trigger LUTs used by 50 MHz and lower sample rates for supporting | |
1262 | * simple pin change and state triggers. Only two transitions (rise/fall) can be | |
1263 | * set at any time, but a full mask and value can be set (0/1). | |
1264 | */ | |
1265 | static int build_basic_trigger(struct triggerlut *lut, struct dev_context *devc) | |
1266 | { | |
1267 | int i,j; | |
1268 | uint16_t masks[2] = { 0, 0 }; | |
1269 | ||
1270 | memset(lut, 0, sizeof(struct triggerlut)); | |
1271 | ||
1272 | /* Contant for simple triggers. */ | |
1273 | lut->m4 = 0xa000; | |
1274 | ||
1275 | /* Value/mask trigger support. */ | |
1276 | build_lut_entry(devc->trigger.simplevalue, devc->trigger.simplemask, | |
1277 | lut->m2d); | |
1278 | ||
1279 | /* Rise/fall trigger support. */ | |
1280 | for (i = 0, j = 0; i < 16; ++i) { | |
1281 | if (devc->trigger.risingmask & (1 << i) || | |
1282 | devc->trigger.fallingmask & (1 << i)) | |
1283 | masks[j++] = 1 << i; | |
1284 | } | |
1285 | ||
1286 | build_lut_entry(masks[0], masks[0], lut->m0d); | |
1287 | build_lut_entry(masks[1], masks[1], lut->m1d); | |
1288 | ||
1289 | /* Add glue logic */ | |
1290 | if (masks[0] || masks[1]) { | |
1291 | /* Transition trigger. */ | |
1292 | if (masks[0] & devc->trigger.risingmask) | |
1293 | add_trigger_function(OP_RISE, FUNC_OR, 0, 0, &lut->m3); | |
1294 | if (masks[0] & devc->trigger.fallingmask) | |
1295 | add_trigger_function(OP_FALL, FUNC_OR, 0, 0, &lut->m3); | |
1296 | if (masks[1] & devc->trigger.risingmask) | |
1297 | add_trigger_function(OP_RISE, FUNC_OR, 1, 0, &lut->m3); | |
1298 | if (masks[1] & devc->trigger.fallingmask) | |
1299 | add_trigger_function(OP_FALL, FUNC_OR, 1, 0, &lut->m3); | |
1300 | } else { | |
1301 | /* Only value/mask trigger. */ | |
1302 | lut->m3 = 0xffff; | |
1303 | } | |
1304 | ||
1305 | /* Triggertype: event. */ | |
1306 | lut->params.selres = 3; | |
1307 | ||
1308 | return SR_OK; | |
1309 | } | |
1310 | ||
1311 | static int dev_acquisition_start(const struct sr_dev_inst *sdi, void *cb_data) | |
1312 | { | |
1313 | struct dev_context *devc; | |
1314 | struct clockselect_50 clockselect; | |
1315 | int frac, triggerpin, ret; | |
1316 | uint8_t triggerselect = 0; | |
1317 | struct triggerinout triggerinout_conf; | |
1318 | struct triggerlut lut; | |
1319 | ||
1320 | if (sdi->status != SR_ST_ACTIVE) | |
1321 | return SR_ERR_DEV_CLOSED; | |
1322 | ||
1323 | devc = sdi->priv; | |
1324 | ||
1325 | if (configure_channels(sdi) != SR_OK) { | |
1326 | sr_err("Failed to configure channels."); | |
1327 | return SR_ERR; | |
1328 | } | |
1329 | ||
1330 | /* If the samplerate has not been set, default to 200 kHz. */ | |
1331 | if (devc->cur_firmware == -1) { | |
1332 | if ((ret = set_samplerate(sdi, SR_KHZ(200))) != SR_OK) | |
1333 | return ret; | |
1334 | } | |
1335 | ||
1336 | /* Enter trigger programming mode. */ | |
1337 | sigma_set_register(WRITE_TRIGGER_SELECT1, 0x20, devc); | |
1338 | ||
1339 | /* 100 and 200 MHz mode. */ | |
1340 | if (devc->cur_samplerate >= SR_MHZ(100)) { | |
1341 | sigma_set_register(WRITE_TRIGGER_SELECT1, 0x81, devc); | |
1342 | ||
1343 | /* Find which pin to trigger on from mask. */ | |
1344 | for (triggerpin = 0; triggerpin < 8; ++triggerpin) | |
1345 | if ((devc->trigger.risingmask | devc->trigger.fallingmask) & | |
1346 | (1 << triggerpin)) | |
1347 | break; | |
1348 | ||
1349 | /* Set trigger pin and light LED on trigger. */ | |
1350 | triggerselect = (1 << LEDSEL1) | (triggerpin & 0x7); | |
1351 | ||
1352 | /* Default rising edge. */ | |
1353 | if (devc->trigger.fallingmask) | |
1354 | triggerselect |= 1 << 3; | |
1355 | ||
1356 | /* All other modes. */ | |
1357 | } else if (devc->cur_samplerate <= SR_MHZ(50)) { | |
1358 | build_basic_trigger(&lut, devc); | |
1359 | ||
1360 | sigma_write_trigger_lut(&lut, devc); | |
1361 | ||
1362 | triggerselect = (1 << LEDSEL1) | (1 << LEDSEL0); | |
1363 | } | |
1364 | ||
1365 | /* Setup trigger in and out pins to default values. */ | |
1366 | memset(&triggerinout_conf, 0, sizeof(struct triggerinout)); | |
1367 | triggerinout_conf.trgout_bytrigger = 1; | |
1368 | triggerinout_conf.trgout_enable = 1; | |
1369 | ||
1370 | sigma_write_register(WRITE_TRIGGER_OPTION, | |
1371 | (uint8_t *) &triggerinout_conf, | |
1372 | sizeof(struct triggerinout), devc); | |
1373 | ||
1374 | /* Go back to normal mode. */ | |
1375 | sigma_set_register(WRITE_TRIGGER_SELECT1, triggerselect, devc); | |
1376 | ||
1377 | /* Set clock select register. */ | |
1378 | if (devc->cur_samplerate == SR_MHZ(200)) | |
1379 | /* Enable 4 channels. */ | |
1380 | sigma_set_register(WRITE_CLOCK_SELECT, 0xf0, devc); | |
1381 | else if (devc->cur_samplerate == SR_MHZ(100)) | |
1382 | /* Enable 8 channels. */ | |
1383 | sigma_set_register(WRITE_CLOCK_SELECT, 0x00, devc); | |
1384 | else { | |
1385 | /* | |
1386 | * 50 MHz mode (or fraction thereof). Any fraction down to | |
1387 | * 50 MHz / 256 can be used, but is not supported by sigrok API. | |
1388 | */ | |
1389 | frac = SR_MHZ(50) / devc->cur_samplerate - 1; | |
1390 | ||
1391 | clockselect.async = 0; | |
1392 | clockselect.fraction = frac; | |
1393 | clockselect.disabled_channels = 0; | |
1394 | ||
1395 | sigma_write_register(WRITE_CLOCK_SELECT, | |
1396 | (uint8_t *) &clockselect, | |
1397 | sizeof(clockselect), devc); | |
1398 | } | |
1399 | ||
1400 | /* Setup maximum post trigger time. */ | |
1401 | sigma_set_register(WRITE_POST_TRIGGER, | |
1402 | (devc->capture_ratio * 255) / 100, devc); | |
1403 | ||
1404 | /* Start acqusition. */ | |
1405 | gettimeofday(&devc->start_tv, 0); | |
1406 | sigma_set_register(WRITE_MODE, 0x0d, devc); | |
1407 | ||
1408 | devc->cb_data = cb_data; | |
1409 | ||
1410 | /* Send header packet to the session bus. */ | |
1411 | std_session_send_df_header(cb_data, LOG_PREFIX); | |
1412 | ||
1413 | /* Add capture source. */ | |
1414 | sr_source_add(0, G_IO_IN, 10, receive_data, (void *)sdi); | |
1415 | ||
1416 | devc->state.state = SIGMA_CAPTURE; | |
1417 | ||
1418 | return SR_OK; | |
1419 | } | |
1420 | ||
1421 | static int dev_acquisition_stop(struct sr_dev_inst *sdi, void *cb_data) | |
1422 | { | |
1423 | struct dev_context *devc; | |
1424 | ||
1425 | (void)cb_data; | |
1426 | ||
1427 | devc = sdi->priv; | |
1428 | devc->state.state = SIGMA_IDLE; | |
1429 | ||
1430 | sr_source_remove(0); | |
1431 | ||
1432 | return SR_OK; | |
1433 | } | |
1434 | ||
1435 | SR_PRIV struct sr_dev_driver asix_sigma_driver_info = { | |
1436 | .name = "asix-sigma", | |
1437 | .longname = "ASIX SIGMA/SIGMA2", | |
1438 | .api_version = 1, | |
1439 | .init = init, | |
1440 | .cleanup = cleanup, | |
1441 | .scan = scan, | |
1442 | .dev_list = dev_list, | |
1443 | .dev_clear = dev_clear, | |
1444 | .config_get = config_get, | |
1445 | .config_set = config_set, | |
1446 | .config_list = config_list, | |
1447 | .dev_open = dev_open, | |
1448 | .dev_close = dev_close, | |
1449 | .dev_acquisition_start = dev_acquisition_start, | |
1450 | .dev_acquisition_stop = dev_acquisition_stop, | |
1451 | .priv = NULL, | |
1452 | }; |