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Commit | Line | Data |
---|---|---|
28a35d8a HE |
1 | /* |
2 | * This file is part of the sigrok project. | |
3 | * | |
911f1834 UH |
4 | * Copyright (C) 2010 Håvard Espeland <gus@ping.uio.no>, |
5 | * Copyright (C) 2010 Martin Stensgård <mastensg@ping.uio.no> | |
6 | * Copyright (C) 2010 Carl Henrik Lunde <chlunde@ping.uio.no> | |
28a35d8a HE |
7 | * |
8 | * This program is free software: you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation, either version 3 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
20 | */ | |
21 | ||
911f1834 | 22 | /* |
da0918aa | 23 | * ASIX SIGMA Logic Analyzer Driver |
911f1834 UH |
24 | */ |
25 | ||
3bbd9849 UH |
26 | #include <glib.h> |
27 | #include <glib/gstdio.h> | |
28a35d8a HE |
28 | #include <ftdi.h> |
29 | #include <string.h> | |
30 | #include <zlib.h> | |
b7f09cf8 UH |
31 | #include "sigrok.h" |
32 | #include "sigrok-internal.h" | |
28a35d8a HE |
33 | #include "asix-sigma.h" |
34 | ||
35 | #define USB_VENDOR 0xa600 | |
36 | #define USB_PRODUCT 0xa000 | |
37 | #define USB_DESCRIPTION "ASIX SIGMA" | |
38 | #define USB_VENDOR_NAME "ASIX" | |
39 | #define USB_MODEL_NAME "SIGMA" | |
40 | #define USB_MODEL_VERSION "" | |
ee492173 | 41 | #define TRIGGER_TYPES "rf10" |
464d12c7 | 42 | #define NUM_PROBES 16 |
28a35d8a | 43 | |
d68e2d1a | 44 | static GSList *dev_insts = NULL; |
28a35d8a | 45 | |
28a35d8a | 46 | static uint64_t supported_samplerates[] = { |
59df0c77 UH |
47 | SR_KHZ(200), |
48 | SR_KHZ(250), | |
49 | SR_KHZ(500), | |
50 | SR_MHZ(1), | |
51 | SR_MHZ(5), | |
52 | SR_MHZ(10), | |
53 | SR_MHZ(25), | |
54 | SR_MHZ(50), | |
55 | SR_MHZ(100), | |
56 | SR_MHZ(200), | |
28a35d8a HE |
57 | 0, |
58 | }; | |
59 | ||
c37d2b1b | 60 | static const char *probe_names[NUM_PROBES + 1] = { |
464d12c7 KS |
61 | "0", |
62 | "1", | |
63 | "2", | |
64 | "3", | |
65 | "4", | |
66 | "5", | |
67 | "6", | |
68 | "7", | |
69 | "8", | |
70 | "9", | |
71 | "10", | |
72 | "11", | |
73 | "12", | |
74 | "13", | |
75 | "14", | |
76 | "15", | |
77 | NULL, | |
78 | }; | |
79 | ||
60679b18 | 80 | static struct sr_samplerates samplerates = { |
59df0c77 UH |
81 | SR_KHZ(200), |
82 | SR_MHZ(200), | |
c9140419 | 83 | SR_HZ(0), |
28a35d8a HE |
84 | supported_samplerates, |
85 | }; | |
86 | ||
ffedd0bf | 87 | static int hwcaps[] = { |
5a2326a7 UH |
88 | SR_HWCAP_LOGIC_ANALYZER, |
89 | SR_HWCAP_SAMPLERATE, | |
90 | SR_HWCAP_CAPTURE_RATIO, | |
91 | SR_HWCAP_PROBECONFIG, | |
28a35d8a | 92 | |
5a2326a7 | 93 | SR_HWCAP_LIMIT_MSEC, |
28a35d8a HE |
94 | 0, |
95 | }; | |
96 | ||
fefa1800 UH |
97 | /* Force the FPGA to reboot. */ |
98 | static uint8_t suicide[] = { | |
99 | 0x84, 0x84, 0x88, 0x84, 0x88, 0x84, 0x88, 0x84, | |
100 | }; | |
101 | ||
102 | /* Prepare to upload firmware (FPGA specific). */ | |
103 | static uint8_t init[] = { | |
104 | 0x03, 0x03, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, | |
105 | }; | |
106 | ||
107 | /* Initialize the logic analyzer mode. */ | |
108 | static uint8_t logic_mode_start[] = { | |
109 | 0x00, 0x40, 0x0f, 0x25, 0x35, 0x40, | |
110 | 0x2a, 0x3a, 0x40, 0x03, 0x20, 0x38, | |
111 | }; | |
112 | ||
eec5275e | 113 | static const char *firmware_files[] = { |
a8116d76 HE |
114 | "asix-sigma-50.fw", /* 50 MHz, supports 8 bit fractions */ |
115 | "asix-sigma-100.fw", /* 100 MHz */ | |
116 | "asix-sigma-200.fw", /* 200 MHz */ | |
ed09fd07 | 117 | "asix-sigma-50sync.fw", /* Synchronous clock from pin */ |
a8116d76 | 118 | "asix-sigma-phasor.fw", /* Frequency counter */ |
f6564c8d HE |
119 | }; |
120 | ||
6b3dfec8 | 121 | static int hw_dev_acquisition_stop(int dev_index, gpointer session_data); |
6aac7737 | 122 | |
ea9cfed7 | 123 | static int sigma_read(void *buf, size_t size, struct context *ctx) |
28a35d8a HE |
124 | { |
125 | int ret; | |
fefa1800 | 126 | |
ea9cfed7 | 127 | ret = ftdi_read_data(&ctx->ftdic, (unsigned char *)buf, size); |
28a35d8a | 128 | if (ret < 0) { |
7b48d6e1 | 129 | sr_err("sigma: ftdi_read_data failed: %s", |
ea9cfed7 | 130 | ftdi_get_error_string(&ctx->ftdic)); |
28a35d8a HE |
131 | } |
132 | ||
133 | return ret; | |
134 | } | |
135 | ||
ea9cfed7 | 136 | static int sigma_write(void *buf, size_t size, struct context *ctx) |
28a35d8a HE |
137 | { |
138 | int ret; | |
fefa1800 | 139 | |
ea9cfed7 | 140 | ret = ftdi_write_data(&ctx->ftdic, (unsigned char *)buf, size); |
28a35d8a | 141 | if (ret < 0) { |
7b48d6e1 | 142 | sr_err("sigma: ftdi_write_data failed: %s", |
ea9cfed7 | 143 | ftdi_get_error_string(&ctx->ftdic)); |
fefa1800 | 144 | } else if ((size_t) ret != size) { |
7b48d6e1 | 145 | sr_err("sigma: ftdi_write_data did not complete write\n"); |
28a35d8a HE |
146 | } |
147 | ||
148 | return ret; | |
149 | } | |
150 | ||
99965709 | 151 | static int sigma_write_register(uint8_t reg, uint8_t *data, size_t len, |
ea9cfed7 | 152 | struct context *ctx) |
28a35d8a HE |
153 | { |
154 | size_t i; | |
155 | uint8_t buf[len + 2]; | |
156 | int idx = 0; | |
157 | ||
158 | buf[idx++] = REG_ADDR_LOW | (reg & 0xf); | |
159 | buf[idx++] = REG_ADDR_HIGH | (reg >> 4); | |
160 | ||
fefa1800 | 161 | for (i = 0; i < len; ++i) { |
28a35d8a HE |
162 | buf[idx++] = REG_DATA_LOW | (data[i] & 0xf); |
163 | buf[idx++] = REG_DATA_HIGH_WRITE | (data[i] >> 4); | |
164 | } | |
165 | ||
ea9cfed7 | 166 | return sigma_write(buf, idx, ctx); |
28a35d8a HE |
167 | } |
168 | ||
ea9cfed7 | 169 | static int sigma_set_register(uint8_t reg, uint8_t value, struct context *ctx) |
28a35d8a | 170 | { |
ea9cfed7 | 171 | return sigma_write_register(reg, &value, 1, ctx); |
28a35d8a HE |
172 | } |
173 | ||
99965709 | 174 | static int sigma_read_register(uint8_t reg, uint8_t *data, size_t len, |
ea9cfed7 | 175 | struct context *ctx) |
28a35d8a HE |
176 | { |
177 | uint8_t buf[3]; | |
fefa1800 | 178 | |
28a35d8a HE |
179 | buf[0] = REG_ADDR_LOW | (reg & 0xf); |
180 | buf[1] = REG_ADDR_HIGH | (reg >> 4); | |
28a35d8a HE |
181 | buf[2] = REG_READ_ADDR; |
182 | ||
ea9cfed7 | 183 | sigma_write(buf, sizeof(buf), ctx); |
28a35d8a | 184 | |
ea9cfed7 | 185 | return sigma_read(data, len, ctx); |
28a35d8a HE |
186 | } |
187 | ||
ea9cfed7 | 188 | static uint8_t sigma_get_register(uint8_t reg, struct context *ctx) |
28a35d8a HE |
189 | { |
190 | uint8_t value; | |
fefa1800 | 191 | |
ea9cfed7 | 192 | if (1 != sigma_read_register(reg, &value, 1, ctx)) { |
7b48d6e1 | 193 | sr_err("sigma: sigma_get_register: 1 byte expected"); |
28a35d8a HE |
194 | return 0; |
195 | } | |
196 | ||
197 | return value; | |
198 | } | |
199 | ||
99965709 | 200 | static int sigma_read_pos(uint32_t *stoppos, uint32_t *triggerpos, |
ea9cfed7 | 201 | struct context *ctx) |
28a35d8a HE |
202 | { |
203 | uint8_t buf[] = { | |
204 | REG_ADDR_LOW | READ_TRIGGER_POS_LOW, | |
205 | ||
206 | REG_READ_ADDR | NEXT_REG, | |
207 | REG_READ_ADDR | NEXT_REG, | |
208 | REG_READ_ADDR | NEXT_REG, | |
209 | REG_READ_ADDR | NEXT_REG, | |
210 | REG_READ_ADDR | NEXT_REG, | |
211 | REG_READ_ADDR | NEXT_REG, | |
212 | }; | |
28a35d8a HE |
213 | uint8_t result[6]; |
214 | ||
ea9cfed7 | 215 | sigma_write(buf, sizeof(buf), ctx); |
28a35d8a | 216 | |
ea9cfed7 | 217 | sigma_read(result, sizeof(result), ctx); |
28a35d8a HE |
218 | |
219 | *triggerpos = result[0] | (result[1] << 8) | (result[2] << 16); | |
220 | *stoppos = result[3] | (result[4] << 8) | (result[5] << 16); | |
221 | ||
57bbf56b HE |
222 | /* Not really sure why this must be done, but according to spec. */ |
223 | if ((--*stoppos & 0x1ff) == 0x1ff) | |
224 | stoppos -= 64; | |
225 | ||
226 | if ((*--triggerpos & 0x1ff) == 0x1ff) | |
227 | triggerpos -= 64; | |
228 | ||
28a35d8a HE |
229 | return 1; |
230 | } | |
231 | ||
99965709 | 232 | static int sigma_read_dram(uint16_t startchunk, size_t numchunks, |
ea9cfed7 | 233 | uint8_t *data, struct context *ctx) |
28a35d8a HE |
234 | { |
235 | size_t i; | |
236 | uint8_t buf[4096]; | |
237 | int idx = 0; | |
238 | ||
fefa1800 | 239 | /* Send the startchunk. Index start with 1. */ |
28a35d8a HE |
240 | buf[0] = startchunk >> 8; |
241 | buf[1] = startchunk & 0xff; | |
ea9cfed7 | 242 | sigma_write_register(WRITE_MEMROW, buf, 2, ctx); |
28a35d8a | 243 | |
fefa1800 | 244 | /* Read the DRAM. */ |
28a35d8a HE |
245 | buf[idx++] = REG_DRAM_BLOCK; |
246 | buf[idx++] = REG_DRAM_WAIT_ACK; | |
247 | ||
248 | for (i = 0; i < numchunks; ++i) { | |
fefa1800 UH |
249 | /* Alternate bit to copy from DRAM to cache. */ |
250 | if (i != (numchunks - 1)) | |
251 | buf[idx++] = REG_DRAM_BLOCK | (((i + 1) % 2) << 4); | |
28a35d8a HE |
252 | |
253 | buf[idx++] = REG_DRAM_BLOCK_DATA | ((i % 2) << 4); | |
254 | ||
fefa1800 | 255 | if (i != (numchunks - 1)) |
28a35d8a HE |
256 | buf[idx++] = REG_DRAM_WAIT_ACK; |
257 | } | |
258 | ||
ea9cfed7 | 259 | sigma_write(buf, idx, ctx); |
28a35d8a | 260 | |
ea9cfed7 | 261 | return sigma_read(data, numchunks * CHUNK_SIZE, ctx); |
28a35d8a HE |
262 | } |
263 | ||
4ae1f451 | 264 | /* Upload trigger look-up tables to Sigma. */ |
ea9cfed7 | 265 | static int sigma_write_trigger_lut(struct triggerlut *lut, struct context *ctx) |
ee492173 HE |
266 | { |
267 | int i; | |
268 | uint8_t tmp[2]; | |
269 | uint16_t bit; | |
270 | ||
271 | /* Transpose the table and send to Sigma. */ | |
272 | for (i = 0; i < 16; ++i) { | |
273 | bit = 1 << i; | |
274 | ||
275 | tmp[0] = tmp[1] = 0; | |
276 | ||
277 | if (lut->m2d[0] & bit) | |
278 | tmp[0] |= 0x01; | |
279 | if (lut->m2d[1] & bit) | |
280 | tmp[0] |= 0x02; | |
281 | if (lut->m2d[2] & bit) | |
282 | tmp[0] |= 0x04; | |
283 | if (lut->m2d[3] & bit) | |
284 | tmp[0] |= 0x08; | |
285 | ||
286 | if (lut->m3 & bit) | |
287 | tmp[0] |= 0x10; | |
288 | if (lut->m3s & bit) | |
289 | tmp[0] |= 0x20; | |
290 | if (lut->m4 & bit) | |
291 | tmp[0] |= 0x40; | |
292 | ||
293 | if (lut->m0d[0] & bit) | |
294 | tmp[1] |= 0x01; | |
295 | if (lut->m0d[1] & bit) | |
296 | tmp[1] |= 0x02; | |
297 | if (lut->m0d[2] & bit) | |
298 | tmp[1] |= 0x04; | |
299 | if (lut->m0d[3] & bit) | |
300 | tmp[1] |= 0x08; | |
301 | ||
302 | if (lut->m1d[0] & bit) | |
303 | tmp[1] |= 0x10; | |
304 | if (lut->m1d[1] & bit) | |
305 | tmp[1] |= 0x20; | |
306 | if (lut->m1d[2] & bit) | |
307 | tmp[1] |= 0x40; | |
308 | if (lut->m1d[3] & bit) | |
309 | tmp[1] |= 0x80; | |
310 | ||
99965709 | 311 | sigma_write_register(WRITE_TRIGGER_SELECT0, tmp, sizeof(tmp), |
ea9cfed7 UH |
312 | ctx); |
313 | sigma_set_register(WRITE_TRIGGER_SELECT1, 0x30 | i, ctx); | |
ee492173 HE |
314 | } |
315 | ||
316 | /* Send the parameters */ | |
317 | sigma_write_register(WRITE_TRIGGER_SELECT0, (uint8_t *) &lut->params, | |
ea9cfed7 | 318 | sizeof(lut->params), ctx); |
ee492173 | 319 | |
e46b8fb1 | 320 | return SR_OK; |
ee492173 HE |
321 | } |
322 | ||
fefa1800 | 323 | /* Generate the bitbang stream for programming the FPGA. */ |
28a35d8a | 324 | static int bin2bitbang(const char *filename, |
fefa1800 | 325 | unsigned char **buf, size_t *buf_size) |
28a35d8a | 326 | { |
fefa1800 | 327 | FILE *f; |
28a35d8a HE |
328 | long file_size; |
329 | unsigned long offset = 0; | |
330 | unsigned char *p; | |
331 | uint8_t *compressed_buf, *firmware; | |
332 | uLongf csize, fwsize; | |
333 | const int buffer_size = 65536; | |
334 | size_t i; | |
fefa1800 UH |
335 | int c, ret, bit, v; |
336 | uint32_t imm = 0x3f6df2ab; | |
28a35d8a | 337 | |
868d8cef | 338 | f = g_fopen(filename, "rb"); |
28a35d8a | 339 | if (!f) { |
7b48d6e1 | 340 | sr_err("sigma: g_fopen(\"%s\", \"rb\")", filename); |
b53738ba | 341 | return SR_ERR; |
28a35d8a HE |
342 | } |
343 | ||
344 | if (-1 == fseek(f, 0, SEEK_END)) { | |
7b48d6e1 | 345 | sr_err("sigma: fseek on %s failed", filename); |
28a35d8a | 346 | fclose(f); |
b53738ba | 347 | return SR_ERR; |
28a35d8a HE |
348 | } |
349 | ||
350 | file_size = ftell(f); | |
351 | ||
352 | fseek(f, 0, SEEK_SET); | |
353 | ||
b53738ba | 354 | if (!(compressed_buf = g_try_malloc(file_size))) { |
340cfac0 | 355 | sr_err("sigma: %s: compressed_buf malloc failed", __func__); |
12ad53f5 | 356 | fclose(f); |
b53738ba UH |
357 | return SR_ERR_MALLOC; |
358 | } | |
28a35d8a | 359 | |
b53738ba | 360 | if (!(firmware = g_try_malloc(buffer_size))) { |
340cfac0 | 361 | sr_err("sigma: %s: firmware malloc failed", __func__); |
12ad53f5 UH |
362 | fclose(f); |
363 | g_free(compressed_buf); | |
b53738ba | 364 | return SR_ERR_MALLOC; |
28a35d8a HE |
365 | } |
366 | ||
28a35d8a HE |
367 | csize = 0; |
368 | while ((c = getc(f)) != EOF) { | |
369 | imm = (imm + 0xa853753) % 177 + (imm * 0x8034052); | |
370 | compressed_buf[csize++] = c ^ imm; | |
371 | } | |
372 | fclose(f); | |
373 | ||
374 | fwsize = buffer_size; | |
375 | ret = uncompress(firmware, &fwsize, compressed_buf, csize); | |
376 | if (ret < 0) { | |
377 | g_free(compressed_buf); | |
378 | g_free(firmware); | |
7b48d6e1 UH |
379 | sr_err("sigma: Could not unpack Sigma firmware. " |
380 | "(Error %d)\n", ret); | |
b53738ba | 381 | return SR_ERR; |
28a35d8a HE |
382 | } |
383 | ||
384 | g_free(compressed_buf); | |
385 | ||
386 | *buf_size = fwsize * 2 * 8; | |
387 | ||
b53738ba | 388 | *buf = p = (unsigned char *)g_try_malloc(*buf_size); |
28a35d8a | 389 | if (!p) { |
340cfac0 | 390 | sr_err("sigma: %s: buf/p malloc failed", __func__); |
12ad53f5 UH |
391 | g_free(compressed_buf); |
392 | g_free(firmware); | |
b53738ba | 393 | return SR_ERR_MALLOC; |
28a35d8a HE |
394 | } |
395 | ||
396 | for (i = 0; i < fwsize; ++i) { | |
28a35d8a | 397 | for (bit = 7; bit >= 0; --bit) { |
fefa1800 | 398 | v = firmware[i] & 1 << bit ? 0x40 : 0x00; |
28a35d8a HE |
399 | p[offset++] = v | 0x01; |
400 | p[offset++] = v; | |
401 | } | |
402 | } | |
403 | ||
404 | g_free(firmware); | |
405 | ||
406 | if (offset != *buf_size) { | |
407 | g_free(*buf); | |
7b48d6e1 | 408 | sr_err("sigma: Error reading firmware %s " |
133a37bf UH |
409 | "offset=%ld, file_size=%ld, buf_size=%zd\n", |
410 | filename, offset, file_size, *buf_size); | |
28a35d8a | 411 | |
b53738ba | 412 | return SR_ERR; |
28a35d8a HE |
413 | } |
414 | ||
b53738ba | 415 | return SR_OK; |
28a35d8a HE |
416 | } |
417 | ||
bb7ef793 | 418 | static int hw_init(const char *devinfo) |
28a35d8a | 419 | { |
d68e2d1a | 420 | struct sr_dev_inst *sdi; |
ea9cfed7 | 421 | struct context *ctx; |
28a35d8a | 422 | |
b53738ba | 423 | /* Avoid compiler warnings. */ |
bb7ef793 | 424 | (void)devinfo; |
28a35d8a | 425 | |
ea9cfed7 UH |
426 | if (!(ctx = g_try_malloc(sizeof(struct context)))) { |
427 | sr_err("sigma: %s: ctx malloc failed", __func__); | |
b53738ba UH |
428 | return 0; /* FIXME: Should be SR_ERR_MALLOC. */ |
429 | } | |
99965709 | 430 | |
ea9cfed7 | 431 | ftdi_init(&ctx->ftdic); |
28a35d8a | 432 | |
fefa1800 | 433 | /* Look for SIGMAs. */ |
ea9cfed7 | 434 | if (ftdi_usb_open_desc(&ctx->ftdic, USB_VENDOR, USB_PRODUCT, |
fefa1800 | 435 | USB_DESCRIPTION, NULL) < 0) |
99965709 HE |
436 | goto free; |
437 | ||
ea9cfed7 UH |
438 | ctx->cur_samplerate = 0; |
439 | ctx->period_ps = 0; | |
440 | ctx->limit_msec = 0; | |
441 | ctx->cur_firmware = -1; | |
442 | ctx->num_probes = 0; | |
443 | ctx->samples_per_event = 0; | |
444 | ctx->capture_ratio = 50; | |
445 | ctx->use_triggers = 0; | |
28a35d8a | 446 | |
fefa1800 | 447 | /* Register SIGMA device. */ |
d68e2d1a UH |
448 | if (!(sdi = sr_dev_inst_new(0, SR_ST_INITIALIZING, USB_VENDOR_NAME, |
449 | USB_MODEL_NAME, USB_MODEL_VERSION))) { | |
450 | sr_err("sigma: %s: sdi was NULL", __func__); | |
99965709 | 451 | goto free; |
d68e2d1a | 452 | } |
99965709 | 453 | |
ea9cfed7 | 454 | sdi->priv = ctx; |
28a35d8a | 455 | |
d68e2d1a | 456 | dev_insts = g_slist_append(dev_insts, sdi); |
28a35d8a | 457 | |
fefa1800 | 458 | /* We will open the device again when we need it. */ |
ea9cfed7 | 459 | ftdi_usb_close(&ctx->ftdic); |
28a35d8a HE |
460 | |
461 | return 1; | |
ea9cfed7 | 462 | |
99965709 | 463 | free: |
ea9cfed7 | 464 | g_free(ctx); |
99965709 | 465 | return 0; |
28a35d8a HE |
466 | } |
467 | ||
ea9cfed7 | 468 | static int upload_firmware(int firmware_idx, struct context *ctx) |
28a35d8a HE |
469 | { |
470 | int ret; | |
471 | unsigned char *buf; | |
472 | unsigned char pins; | |
473 | size_t buf_size; | |
28a35d8a | 474 | unsigned char result[32]; |
e8397563 | 475 | char firmware_path[128]; |
28a35d8a | 476 | |
fefa1800 | 477 | /* Make sure it's an ASIX SIGMA. */ |
ea9cfed7 | 478 | if ((ret = ftdi_usb_open_desc(&ctx->ftdic, |
28a35d8a | 479 | USB_VENDOR, USB_PRODUCT, USB_DESCRIPTION, NULL)) < 0) { |
7b48d6e1 | 480 | sr_err("sigma: ftdi_usb_open failed: %s", |
ea9cfed7 | 481 | ftdi_get_error_string(&ctx->ftdic)); |
28a35d8a HE |
482 | return 0; |
483 | } | |
484 | ||
ea9cfed7 | 485 | if ((ret = ftdi_set_bitmode(&ctx->ftdic, 0xdf, BITMODE_BITBANG)) < 0) { |
7b48d6e1 | 486 | sr_err("sigma: ftdi_set_bitmode failed: %s", |
ea9cfed7 | 487 | ftdi_get_error_string(&ctx->ftdic)); |
28a35d8a HE |
488 | return 0; |
489 | } | |
490 | ||
fefa1800 | 491 | /* Four times the speed of sigmalogan - Works well. */ |
ea9cfed7 | 492 | if ((ret = ftdi_set_baudrate(&ctx->ftdic, 750000)) < 0) { |
7b48d6e1 | 493 | sr_err("sigma: ftdi_set_baudrate failed: %s", |
ea9cfed7 | 494 | ftdi_get_error_string(&ctx->ftdic)); |
28a35d8a HE |
495 | return 0; |
496 | } | |
497 | ||
fefa1800 | 498 | /* Force the FPGA to reboot. */ |
ea9cfed7 UH |
499 | sigma_write(suicide, sizeof(suicide), ctx); |
500 | sigma_write(suicide, sizeof(suicide), ctx); | |
501 | sigma_write(suicide, sizeof(suicide), ctx); | |
502 | sigma_write(suicide, sizeof(suicide), ctx); | |
28a35d8a | 503 | |
fefa1800 | 504 | /* Prepare to upload firmware (FPGA specific). */ |
ea9cfed7 | 505 | sigma_write(init, sizeof(init), ctx); |
28a35d8a | 506 | |
ea9cfed7 | 507 | ftdi_usb_purge_buffers(&ctx->ftdic); |
28a35d8a | 508 | |
fefa1800 | 509 | /* Wait until the FPGA asserts INIT_B. */ |
28a35d8a | 510 | while (1) { |
ea9cfed7 | 511 | ret = sigma_read(result, 1, ctx); |
28a35d8a HE |
512 | if (result[0] & 0x20) |
513 | break; | |
514 | } | |
515 | ||
9ddb2a12 | 516 | /* Prepare firmware. */ |
e8397563 | 517 | snprintf(firmware_path, sizeof(firmware_path), "%s/%s", FIRMWARE_DIR, |
f6564c8d HE |
518 | firmware_files[firmware_idx]); |
519 | ||
b53738ba | 520 | if ((ret = bin2bitbang(firmware_path, &buf, &buf_size)) != SR_OK) { |
7b48d6e1 | 521 | sr_err("sigma: An error occured while reading the firmware: %s", |
133a37bf | 522 | firmware_path); |
b53738ba | 523 | return ret; |
28a35d8a HE |
524 | } |
525 | ||
fefa1800 | 526 | /* Upload firmare. */ |
ea9cfed7 | 527 | sigma_write(buf, buf_size, ctx); |
28a35d8a HE |
528 | |
529 | g_free(buf); | |
530 | ||
ea9cfed7 | 531 | if ((ret = ftdi_set_bitmode(&ctx->ftdic, 0x00, BITMODE_RESET)) < 0) { |
7b48d6e1 | 532 | sr_err("sigma: ftdi_set_bitmode failed: %s", |
ea9cfed7 | 533 | ftdi_get_error_string(&ctx->ftdic)); |
e46b8fb1 | 534 | return SR_ERR; |
28a35d8a HE |
535 | } |
536 | ||
ea9cfed7 | 537 | ftdi_usb_purge_buffers(&ctx->ftdic); |
28a35d8a | 538 | |
fefa1800 | 539 | /* Discard garbage. */ |
ea9cfed7 | 540 | while (1 == sigma_read(&pins, 1, ctx)) |
28a35d8a HE |
541 | ; |
542 | ||
fefa1800 | 543 | /* Initialize the logic analyzer mode. */ |
ea9cfed7 | 544 | sigma_write(logic_mode_start, sizeof(logic_mode_start), ctx); |
28a35d8a | 545 | |
fefa1800 | 546 | /* Expect a 3 byte reply. */ |
ea9cfed7 | 547 | ret = sigma_read(result, 3, ctx); |
28a35d8a HE |
548 | if (ret != 3 || |
549 | result[0] != 0xa6 || result[1] != 0x55 || result[2] != 0xaa) { | |
7b48d6e1 | 550 | sr_err("sigma: Configuration failed. Invalid reply received."); |
e46b8fb1 | 551 | return SR_ERR; |
28a35d8a HE |
552 | } |
553 | ||
ea9cfed7 | 554 | ctx->cur_firmware = firmware_idx; |
f6564c8d | 555 | |
e46b8fb1 | 556 | return SR_OK; |
f6564c8d HE |
557 | } |
558 | ||
e7eb703f | 559 | static int hw_dev_open(int dev_index) |
f6564c8d | 560 | { |
d68e2d1a | 561 | struct sr_dev_inst *sdi; |
ea9cfed7 | 562 | struct context *ctx; |
f6564c8d HE |
563 | int ret; |
564 | ||
bb7ef793 | 565 | if (!(sdi = sr_dev_inst_get(dev_insts, dev_index))) |
e46b8fb1 | 566 | return SR_ERR; |
99965709 | 567 | |
ea9cfed7 | 568 | ctx = sdi->priv; |
99965709 | 569 | |
9ddb2a12 | 570 | /* Make sure it's an ASIX SIGMA. */ |
ea9cfed7 | 571 | if ((ret = ftdi_usb_open_desc(&ctx->ftdic, |
f6564c8d HE |
572 | USB_VENDOR, USB_PRODUCT, USB_DESCRIPTION, NULL)) < 0) { |
573 | ||
7b48d6e1 | 574 | sr_err("sigma: ftdi_usb_open failed: %s", |
ea9cfed7 | 575 | ftdi_get_error_string(&ctx->ftdic)); |
f6564c8d HE |
576 | |
577 | return 0; | |
578 | } | |
28a35d8a | 579 | |
5a2326a7 | 580 | sdi->status = SR_ST_ACTIVE; |
28a35d8a | 581 | |
e46b8fb1 | 582 | return SR_OK; |
f6564c8d HE |
583 | } |
584 | ||
d68e2d1a | 585 | static int set_samplerate(struct sr_dev_inst *sdi, uint64_t samplerate) |
f6564c8d | 586 | { |
e8397563 | 587 | int i, ret; |
ea9cfed7 | 588 | struct context *ctx = sdi->priv; |
f6564c8d HE |
589 | |
590 | for (i = 0; supported_samplerates[i]; i++) { | |
591 | if (supported_samplerates[i] == samplerate) | |
592 | break; | |
593 | } | |
594 | if (supported_samplerates[i] == 0) | |
e46b8fb1 | 595 | return SR_ERR_SAMPLERATE; |
f6564c8d | 596 | |
59df0c77 | 597 | if (samplerate <= SR_MHZ(50)) { |
ea9cfed7 UH |
598 | ret = upload_firmware(0, ctx); |
599 | ctx->num_probes = 16; | |
e8397563 | 600 | } |
59df0c77 | 601 | if (samplerate == SR_MHZ(100)) { |
ea9cfed7 UH |
602 | ret = upload_firmware(1, ctx); |
603 | ctx->num_probes = 8; | |
f78898e9 | 604 | } |
59df0c77 | 605 | else if (samplerate == SR_MHZ(200)) { |
ea9cfed7 UH |
606 | ret = upload_firmware(2, ctx); |
607 | ctx->num_probes = 4; | |
f78898e9 | 608 | } |
f6564c8d | 609 | |
ea9cfed7 UH |
610 | ctx->cur_samplerate = samplerate; |
611 | ctx->period_ps = 1000000000000 / samplerate; | |
612 | ctx->samples_per_event = 16 / ctx->num_probes; | |
613 | ctx->state.state = SIGMA_IDLE; | |
f6564c8d | 614 | |
7b48d6e1 | 615 | sr_info("sigma: Firmware uploaded"); |
28a35d8a | 616 | |
e8397563 | 617 | return ret; |
28a35d8a HE |
618 | } |
619 | ||
c53d793f HE |
620 | /* |
621 | * In 100 and 200 MHz mode, only a single pin rising/falling can be | |
622 | * set as trigger. In other modes, two rising/falling triggers can be set, | |
623 | * in addition to value/mask trigger for any number of probes. | |
624 | * | |
625 | * The Sigma supports complex triggers using boolean expressions, but this | |
626 | * has not been implemented yet. | |
627 | */ | |
d68e2d1a | 628 | static int configure_probes(struct sr_dev_inst *sdi, GSList *probes) |
57bbf56b | 629 | { |
ea9cfed7 | 630 | struct context *ctx = sdi->priv; |
1afe8989 | 631 | struct sr_probe *probe; |
57bbf56b HE |
632 | GSList *l; |
633 | int trigger_set = 0; | |
a42aec7f | 634 | int probebit; |
57bbf56b | 635 | |
ea9cfed7 | 636 | memset(&ctx->trigger, 0, sizeof(struct sigma_trigger)); |
eec5275e | 637 | |
57bbf56b | 638 | for (l = probes; l; l = l->next) { |
1afe8989 | 639 | probe = (struct sr_probe *)l->data; |
a42aec7f | 640 | probebit = 1 << (probe->index - 1); |
57bbf56b HE |
641 | |
642 | if (!probe->enabled || !probe->trigger) | |
643 | continue; | |
644 | ||
ea9cfed7 | 645 | if (ctx->cur_samplerate >= SR_MHZ(100)) { |
c53d793f | 646 | /* Fast trigger support. */ |
ee492173 | 647 | if (trigger_set) { |
7b48d6e1 | 648 | sr_err("sigma: ASIX SIGMA only supports a single " |
133a37bf | 649 | "pin trigger in 100 and 200MHz mode."); |
e46b8fb1 | 650 | return SR_ERR; |
ee492173 HE |
651 | } |
652 | if (probe->trigger[0] == 'f') | |
ea9cfed7 | 653 | ctx->trigger.fallingmask |= probebit; |
ee492173 | 654 | else if (probe->trigger[0] == 'r') |
ea9cfed7 | 655 | ctx->trigger.risingmask |= probebit; |
ee492173 | 656 | else { |
7b48d6e1 | 657 | sr_err("sigma: ASIX SIGMA only supports " |
133a37bf UH |
658 | "rising/falling trigger in 100 " |
659 | "and 200MHz mode."); | |
e46b8fb1 | 660 | return SR_ERR; |
ee492173 | 661 | } |
57bbf56b | 662 | |
c53d793f | 663 | ++trigger_set; |
ee492173 | 664 | } else { |
c53d793f HE |
665 | /* Simple trigger support (event). */ |
666 | if (probe->trigger[0] == '1') { | |
ea9cfed7 UH |
667 | ctx->trigger.simplevalue |= probebit; |
668 | ctx->trigger.simplemask |= probebit; | |
c53d793f HE |
669 | } |
670 | else if (probe->trigger[0] == '0') { | |
ea9cfed7 UH |
671 | ctx->trigger.simplevalue &= ~probebit; |
672 | ctx->trigger.simplemask |= probebit; | |
c53d793f HE |
673 | } |
674 | else if (probe->trigger[0] == 'f') { | |
ea9cfed7 | 675 | ctx->trigger.fallingmask |= probebit; |
c53d793f HE |
676 | ++trigger_set; |
677 | } | |
678 | else if (probe->trigger[0] == 'r') { | |
ea9cfed7 | 679 | ctx->trigger.risingmask |= probebit; |
c53d793f HE |
680 | ++trigger_set; |
681 | } | |
ee492173 | 682 | |
ea9cfed7 UH |
683 | /* |
684 | * Actually, Sigma supports 2 rising/falling triggers, | |
685 | * but they are ORed and the current trigger syntax | |
686 | * does not permit ORed triggers. | |
687 | */ | |
98b8cbc1 | 688 | if (trigger_set > 1) { |
7b48d6e1 UH |
689 | sr_err("sigma: ASIX SIGMA only supports 1 " |
690 | "rising/falling triggers."); | |
e46b8fb1 | 691 | return SR_ERR; |
ee492173 | 692 | } |
ee492173 | 693 | } |
5b5ea7c6 HE |
694 | |
695 | if (trigger_set) | |
ea9cfed7 | 696 | ctx->use_triggers = 1; |
57bbf56b HE |
697 | } |
698 | ||
e46b8fb1 | 699 | return SR_OK; |
57bbf56b HE |
700 | } |
701 | ||
e7eb703f | 702 | static int hw_dev_close(int dev_index) |
28a35d8a | 703 | { |
d68e2d1a | 704 | struct sr_dev_inst *sdi; |
ea9cfed7 | 705 | struct context *ctx; |
28a35d8a | 706 | |
bb7ef793 | 707 | if (!(sdi = sr_dev_inst_get(dev_insts, dev_index))) { |
340cfac0 | 708 | sr_err("sigma: %s: sdi was NULL", __func__); |
697785d1 UH |
709 | return SR_ERR; /* TODO: SR_ERR_ARG? */ |
710 | } | |
9be9893e | 711 | |
ea9cfed7 | 712 | if (!(ctx = sdi->priv)) { |
340cfac0 | 713 | sr_err("sigma: %s: sdi->priv was NULL", __func__); |
697785d1 | 714 | return SR_ERR; /* TODO: SR_ERR_ARG? */ |
9be9893e | 715 | } |
697785d1 UH |
716 | |
717 | /* TODO */ | |
718 | if (sdi->status == SR_ST_ACTIVE) | |
ea9cfed7 | 719 | ftdi_usb_close(&ctx->ftdic); |
697785d1 UH |
720 | |
721 | sdi->status = SR_ST_INACTIVE; | |
722 | ||
723 | return SR_OK; | |
28a35d8a HE |
724 | } |
725 | ||
57ab7d9f | 726 | static int hw_cleanup(void) |
28a35d8a | 727 | { |
99965709 | 728 | GSList *l; |
d68e2d1a | 729 | struct sr_dev_inst *sdi; |
57ab7d9f | 730 | int ret = SR_OK; |
99965709 HE |
731 | |
732 | /* Properly close all devices. */ | |
d68e2d1a | 733 | for (l = dev_insts; l; l = l->next) { |
57ab7d9f UH |
734 | if (!(sdi = l->data)) { |
735 | /* Log error, but continue cleaning up the rest. */ | |
7b48d6e1 | 736 | sr_err("sigma: %s: sdi was NULL, continuing", __func__); |
57ab7d9f UH |
737 | ret = SR_ERR_BUG; |
738 | continue; | |
739 | } | |
d3683c42 | 740 | sr_dev_inst_free(sdi); |
99965709 | 741 | } |
d68e2d1a UH |
742 | g_slist_free(dev_insts); |
743 | dev_insts = NULL; | |
57ab7d9f UH |
744 | |
745 | return ret; | |
28a35d8a HE |
746 | } |
747 | ||
5097b0d0 | 748 | static void *hw_dev_info_get(int dev_index, int dev_info_id) |
28a35d8a | 749 | { |
d68e2d1a | 750 | struct sr_dev_inst *sdi; |
ea9cfed7 | 751 | struct context *ctx; |
28a35d8a HE |
752 | void *info = NULL; |
753 | ||
bb7ef793 | 754 | if (!(sdi = sr_dev_inst_get(dev_insts, dev_index))) { |
7b48d6e1 | 755 | sr_err("sigma: %s: sdi was NULL", __func__); |
28a35d8a HE |
756 | return NULL; |
757 | } | |
758 | ||
ea9cfed7 | 759 | ctx = sdi->priv; |
99965709 | 760 | |
bb7ef793 | 761 | switch (dev_info_id) { |
1d9a8a5f | 762 | case SR_DI_INST: |
28a35d8a HE |
763 | info = sdi; |
764 | break; | |
5a2326a7 | 765 | case SR_DI_NUM_PROBES: |
464d12c7 KS |
766 | info = GINT_TO_POINTER(NUM_PROBES); |
767 | break; | |
768 | case SR_DI_PROBE_NAMES: | |
769 | info = probe_names; | |
28a35d8a | 770 | break; |
5a2326a7 | 771 | case SR_DI_SAMPLERATES: |
28a35d8a HE |
772 | info = &samplerates; |
773 | break; | |
5a2326a7 | 774 | case SR_DI_TRIGGER_TYPES: |
57bbf56b | 775 | info = (char *)TRIGGER_TYPES; |
28a35d8a | 776 | break; |
5a2326a7 | 777 | case SR_DI_CUR_SAMPLERATE: |
ea9cfed7 | 778 | info = &ctx->cur_samplerate; |
28a35d8a HE |
779 | break; |
780 | } | |
781 | ||
782 | return info; | |
783 | } | |
784 | ||
e7eb703f | 785 | static int hw_dev_status_get(int dev_index) |
28a35d8a | 786 | { |
d68e2d1a | 787 | struct sr_dev_inst *sdi; |
28a35d8a | 788 | |
bb7ef793 | 789 | sdi = sr_dev_inst_get(dev_insts, dev_index); |
28a35d8a HE |
790 | if (sdi) |
791 | return sdi->status; | |
792 | else | |
5a2326a7 | 793 | return SR_ST_NOT_FOUND; |
28a35d8a HE |
794 | } |
795 | ||
ffedd0bf | 796 | static int *hw_hwcap_get_all(void) |
28a35d8a | 797 | { |
ffedd0bf | 798 | return hwcaps; |
28a35d8a HE |
799 | } |
800 | ||
a9a245b4 | 801 | static int hw_dev_config_set(int dev_index, int hwcap, void *value) |
28a35d8a | 802 | { |
d68e2d1a | 803 | struct sr_dev_inst *sdi; |
ea9cfed7 | 804 | struct context *ctx; |
28a35d8a | 805 | int ret; |
f6564c8d | 806 | |
bb7ef793 | 807 | if (!(sdi = sr_dev_inst_get(dev_insts, dev_index))) |
e46b8fb1 | 808 | return SR_ERR; |
28a35d8a | 809 | |
ea9cfed7 | 810 | ctx = sdi->priv; |
99965709 | 811 | |
ffedd0bf | 812 | if (hwcap == SR_HWCAP_SAMPLERATE) { |
ea9cfed7 | 813 | ret = set_samplerate(sdi, *(uint64_t *)value); |
ffedd0bf | 814 | } else if (hwcap == SR_HWCAP_PROBECONFIG) { |
99965709 | 815 | ret = configure_probes(sdi, value); |
ffedd0bf | 816 | } else if (hwcap == SR_HWCAP_LIMIT_MSEC) { |
ea9cfed7 UH |
817 | ctx->limit_msec = *(uint64_t *)value; |
818 | if (ctx->limit_msec > 0) | |
e46b8fb1 | 819 | ret = SR_OK; |
94ba4bd6 | 820 | else |
e46b8fb1 | 821 | ret = SR_ERR; |
ffedd0bf | 822 | } else if (hwcap == SR_HWCAP_CAPTURE_RATIO) { |
ea9cfed7 UH |
823 | ctx->capture_ratio = *(uint64_t *)value; |
824 | if (ctx->capture_ratio < 0 || ctx->capture_ratio > 100) | |
e46b8fb1 | 825 | ret = SR_ERR; |
94ba4bd6 | 826 | else |
e46b8fb1 | 827 | ret = SR_OK; |
28a35d8a | 828 | } else { |
e46b8fb1 | 829 | ret = SR_ERR; |
28a35d8a HE |
830 | } |
831 | ||
832 | return ret; | |
833 | } | |
834 | ||
36b1c8e6 HE |
835 | /* Software trigger to determine exact trigger position. */ |
836 | static int get_trigger_offset(uint16_t *samples, uint16_t last_sample, | |
837 | struct sigma_trigger *t) | |
838 | { | |
839 | int i; | |
840 | ||
841 | for (i = 0; i < 8; ++i) { | |
842 | if (i > 0) | |
843 | last_sample = samples[i-1]; | |
844 | ||
845 | /* Simple triggers. */ | |
846 | if ((samples[i] & t->simplemask) != t->simplevalue) | |
847 | continue; | |
848 | ||
849 | /* Rising edge. */ | |
850 | if ((last_sample & t->risingmask) != 0 || (samples[i] & | |
851 | t->risingmask) != t->risingmask) | |
852 | continue; | |
853 | ||
854 | /* Falling edge. */ | |
bdfc7a89 HE |
855 | if ((last_sample & t->fallingmask) != t->fallingmask || |
856 | (samples[i] & t->fallingmask) != 0) | |
36b1c8e6 HE |
857 | continue; |
858 | ||
859 | break; | |
860 | } | |
861 | ||
862 | /* If we did not match, return original trigger pos. */ | |
863 | return i & 0x7; | |
864 | } | |
865 | ||
28a35d8a | 866 | /* |
fefa1800 UH |
867 | * Decode chunk of 1024 bytes, 64 clusters, 7 events per cluster. |
868 | * Each event is 20ns apart, and can contain multiple samples. | |
f78898e9 HE |
869 | * |
870 | * For 200 MHz, events contain 4 samples for each channel, spread 5 ns apart. | |
871 | * For 100 MHz, events contain 2 samples for each channel, spread 10 ns apart. | |
872 | * For 50 MHz and below, events contain one sample for each channel, | |
873 | * spread 20 ns apart. | |
28a35d8a HE |
874 | */ |
875 | static int decode_chunk_ts(uint8_t *buf, uint16_t *lastts, | |
88c51afe | 876 | uint16_t *lastsample, int triggerpos, |
9c939c51 | 877 | uint16_t limit_chunk, void *session_data) |
28a35d8a | 878 | { |
d68e2d1a | 879 | struct sr_dev_inst *sdi = session_data; |
ea9cfed7 | 880 | struct context *ctx = sdi->priv; |
fefa1800 | 881 | uint16_t tsdiff, ts; |
ea9cfed7 | 882 | uint16_t samples[65536 * ctx->samples_per_event]; |
b9c735a2 | 883 | struct sr_datafeed_packet packet; |
9c939c51 | 884 | struct sr_datafeed_logic logic; |
f78898e9 | 885 | int i, j, k, l, numpad, tosend; |
fefa1800 | 886 | size_t n = 0, sent = 0; |
ea9cfed7 | 887 | int clustersize = EVENTS_PER_CLUSTER * ctx->samples_per_event; |
fefa1800 | 888 | uint16_t *event; |
f78898e9 | 889 | uint16_t cur_sample; |
57bbf56b | 890 | int triggerts = -1; |
ee492173 | 891 | |
4ae1f451 | 892 | /* Check if trigger is in this chunk. */ |
ee492173 | 893 | if (triggerpos != -1) { |
ea9cfed7 | 894 | if (ctx->cur_samplerate <= SR_MHZ(50)) |
36b1c8e6 | 895 | triggerpos -= EVENTS_PER_CLUSTER - 1; |
ee492173 HE |
896 | |
897 | if (triggerpos < 0) | |
898 | triggerpos = 0; | |
57bbf56b | 899 | |
ee492173 HE |
900 | /* Find in which cluster the trigger occured. */ |
901 | triggerts = triggerpos / 7; | |
902 | } | |
28a35d8a | 903 | |
eec5275e | 904 | /* For each ts. */ |
28a35d8a | 905 | for (i = 0; i < 64; ++i) { |
fefa1800 | 906 | ts = *(uint16_t *) &buf[i * 16]; |
28a35d8a HE |
907 | tsdiff = ts - *lastts; |
908 | *lastts = ts; | |
909 | ||
88c51afe HE |
910 | /* Decode partial chunk. */ |
911 | if (limit_chunk && ts > limit_chunk) | |
e46b8fb1 | 912 | return SR_OK; |
88c51afe | 913 | |
fefa1800 | 914 | /* Pad last sample up to current point. */ |
ea9cfed7 | 915 | numpad = tsdiff * ctx->samples_per_event - clustersize; |
28a35d8a | 916 | if (numpad > 0) { |
f78898e9 HE |
917 | for (j = 0; j < numpad; ++j) |
918 | samples[j] = *lastsample; | |
919 | ||
920 | n = numpad; | |
28a35d8a HE |
921 | } |
922 | ||
57bbf56b HE |
923 | /* Send samples between previous and this timestamp to sigrok. */ |
924 | sent = 0; | |
925 | while (sent < n) { | |
926 | tosend = MIN(2048, n - sent); | |
927 | ||
5a2326a7 | 928 | packet.type = SR_DF_LOGIC; |
9c939c51 BV |
929 | packet.payload = &logic; |
930 | logic.length = tosend * sizeof(uint16_t); | |
931 | logic.unitsize = 2; | |
932 | logic.data = samples + sent; | |
ea9cfed7 | 933 | sr_session_bus(ctx->session_id, &packet); |
28a35d8a | 934 | |
57bbf56b HE |
935 | sent += tosend; |
936 | } | |
937 | n = 0; | |
938 | ||
939 | event = (uint16_t *) &buf[i * 16 + 2]; | |
f78898e9 HE |
940 | cur_sample = 0; |
941 | ||
942 | /* For each event in cluster. */ | |
28a35d8a | 943 | for (j = 0; j < 7; ++j) { |
f78898e9 HE |
944 | |
945 | /* For each sample in event. */ | |
ea9cfed7 | 946 | for (k = 0; k < ctx->samples_per_event; ++k) { |
f78898e9 HE |
947 | cur_sample = 0; |
948 | ||
949 | /* For each probe. */ | |
ea9cfed7 | 950 | for (l = 0; l < ctx->num_probes; ++l) |
edca2c5c | 951 | cur_sample |= (!!(event[j] & (1 << (l * |
ea9cfed7 | 952 | ctx->samples_per_event + k)))) << l; |
f78898e9 HE |
953 | |
954 | samples[n++] = cur_sample; | |
28a35d8a HE |
955 | } |
956 | } | |
957 | ||
eec5275e | 958 | /* Send data up to trigger point (if triggered). */ |
fefa1800 | 959 | sent = 0; |
57bbf56b HE |
960 | if (i == triggerts) { |
961 | /* | |
36b1c8e6 HE |
962 | * Trigger is not always accurate to sample because of |
963 | * pipeline delay. However, it always triggers before | |
964 | * the actual event. We therefore look at the next | |
965 | * samples to pinpoint the exact position of the trigger. | |
57bbf56b | 966 | */ |
bdfc7a89 | 967 | tosend = get_trigger_offset(samples, *lastsample, |
ea9cfed7 | 968 | &ctx->trigger); |
57bbf56b HE |
969 | |
970 | if (tosend > 0) { | |
5a2326a7 | 971 | packet.type = SR_DF_LOGIC; |
9c939c51 BV |
972 | packet.payload = &logic; |
973 | logic.length = tosend * sizeof(uint16_t); | |
974 | logic.unitsize = 2; | |
975 | logic.data = samples; | |
ea9cfed7 | 976 | sr_session_bus(ctx->session_id, &packet); |
57bbf56b HE |
977 | |
978 | sent += tosend; | |
979 | } | |
28a35d8a | 980 | |
5b5ea7c6 | 981 | /* Only send trigger if explicitly enabled. */ |
ea9cfed7 | 982 | if (ctx->use_triggers) { |
5a2326a7 | 983 | packet.type = SR_DF_TRIGGER; |
ea9cfed7 | 984 | sr_session_bus(ctx->session_id, &packet); |
5b5ea7c6 | 985 | } |
28a35d8a | 986 | } |
57bbf56b | 987 | |
eec5275e | 988 | /* Send rest of the chunk to sigrok. */ |
57bbf56b HE |
989 | tosend = n - sent; |
990 | ||
abda62ce | 991 | if (tosend > 0) { |
5a2326a7 | 992 | packet.type = SR_DF_LOGIC; |
9c939c51 BV |
993 | packet.payload = &logic; |
994 | logic.length = tosend * sizeof(uint16_t); | |
995 | logic.unitsize = 2; | |
996 | logic.data = samples + sent; | |
ea9cfed7 | 997 | sr_session_bus(ctx->session_id, &packet); |
abda62ce | 998 | } |
ee492173 HE |
999 | |
1000 | *lastsample = samples[n - 1]; | |
28a35d8a HE |
1001 | } |
1002 | ||
e46b8fb1 | 1003 | return SR_OK; |
28a35d8a HE |
1004 | } |
1005 | ||
9c939c51 | 1006 | static int receive_data(int fd, int revents, void *session_data) |
28a35d8a | 1007 | { |
d68e2d1a | 1008 | struct sr_dev_inst *sdi = session_data; |
ea9cfed7 | 1009 | struct context *ctx = sdi->priv; |
b9c735a2 | 1010 | struct sr_datafeed_packet packet; |
28a35d8a HE |
1011 | const int chunks_per_read = 32; |
1012 | unsigned char buf[chunks_per_read * CHUNK_SIZE]; | |
6aac7737 | 1013 | int bufsz, numchunks, i, newchunks; |
94ba4bd6 | 1014 | uint64_t running_msec; |
28a35d8a | 1015 | struct timeval tv; |
28a35d8a | 1016 | |
cb93f8a9 UH |
1017 | /* Avoid compiler warnings. */ |
1018 | (void)fd; | |
1019 | (void)revents; | |
28a35d8a | 1020 | |
ea9cfed7 | 1021 | numchunks = (ctx->state.stoppos + 511) / 512; |
28a35d8a | 1022 | |
ea9cfed7 | 1023 | if (ctx->state.state == SIGMA_IDLE) |
28a35d8a HE |
1024 | return FALSE; |
1025 | ||
ea9cfed7 | 1026 | if (ctx->state.state == SIGMA_CAPTURE) { |
6aac7737 HE |
1027 | /* Check if the timer has expired, or memory is full. */ |
1028 | gettimeofday(&tv, 0); | |
ea9cfed7 UH |
1029 | running_msec = (tv.tv_sec - ctx->start_tv.tv_sec) * 1000 + |
1030 | (tv.tv_usec - ctx->start_tv.tv_usec) / 1000; | |
28a35d8a | 1031 | |
ea9cfed7 | 1032 | if (running_msec < ctx->limit_msec && numchunks < 32767) |
6aac7737 | 1033 | return FALSE; |
28a35d8a | 1034 | |
6b3dfec8 | 1035 | hw_dev_acquisition_stop(sdi->index, session_data); |
6aac7737 HE |
1036 | |
1037 | return FALSE; | |
ea9cfed7 UH |
1038 | } else if (ctx->state.state == SIGMA_DOWNLOAD) { |
1039 | if (ctx->state.chunks_downloaded >= numchunks) { | |
6aac7737 | 1040 | /* End of samples. */ |
5a2326a7 | 1041 | packet.type = SR_DF_END; |
ea9cfed7 | 1042 | sr_session_bus(ctx->session_id, &packet); |
6aac7737 | 1043 | |
ea9cfed7 | 1044 | ctx->state.state = SIGMA_IDLE; |
f78898e9 | 1045 | |
6aac7737 HE |
1046 | return TRUE; |
1047 | } | |
1048 | ||
1049 | newchunks = MIN(chunks_per_read, | |
ea9cfed7 | 1050 | numchunks - ctx->state.chunks_downloaded); |
28a35d8a | 1051 | |
7b48d6e1 | 1052 | sr_info("sigma: Downloading sample data: %.0f %%", |
ea9cfed7 | 1053 | 100.0 * ctx->state.chunks_downloaded / numchunks); |
28a35d8a | 1054 | |
ea9cfed7 UH |
1055 | bufsz = sigma_read_dram(ctx->state.chunks_downloaded, |
1056 | newchunks, buf, ctx); | |
719c5a93 UH |
1057 | /* TODO: Check bufsz. For now, just avoid compiler warnings. */ |
1058 | (void)bufsz; | |
28a35d8a | 1059 | |
fefa1800 | 1060 | /* Find first ts. */ |
ea9cfed7 UH |
1061 | if (ctx->state.chunks_downloaded == 0) { |
1062 | ctx->state.lastts = *(uint16_t *) buf - 1; | |
1063 | ctx->state.lastsample = 0; | |
6aac7737 | 1064 | } |
28a35d8a | 1065 | |
fefa1800 | 1066 | /* Decode chunks and send them to sigrok. */ |
28a35d8a | 1067 | for (i = 0; i < newchunks; ++i) { |
88c51afe HE |
1068 | int limit_chunk = 0; |
1069 | ||
1070 | /* The last chunk may potentially be only in part. */ | |
ea9cfed7 | 1071 | if (ctx->state.chunks_downloaded == numchunks - 1) { |
88c51afe | 1072 | /* Find the last valid timestamp */ |
ea9cfed7 | 1073 | limit_chunk = ctx->state.stoppos % 512 + ctx->state.lastts; |
88c51afe HE |
1074 | } |
1075 | ||
ea9cfed7 | 1076 | if (ctx->state.chunks_downloaded + i == ctx->state.triggerchunk) |
57bbf56b | 1077 | decode_chunk_ts(buf + (i * CHUNK_SIZE), |
ea9cfed7 UH |
1078 | &ctx->state.lastts, |
1079 | &ctx->state.lastsample, | |
1080 | ctx->state.triggerpos & 0x1ff, | |
9c939c51 | 1081 | limit_chunk, session_data); |
57bbf56b HE |
1082 | else |
1083 | decode_chunk_ts(buf + (i * CHUNK_SIZE), | |
ea9cfed7 UH |
1084 | &ctx->state.lastts, |
1085 | &ctx->state.lastsample, | |
9c939c51 | 1086 | -1, limit_chunk, session_data); |
28a35d8a | 1087 | |
ea9cfed7 | 1088 | ++ctx->state.chunks_downloaded; |
88c51afe | 1089 | } |
28a35d8a HE |
1090 | } |
1091 | ||
28a35d8a HE |
1092 | return TRUE; |
1093 | } | |
1094 | ||
c53d793f HE |
1095 | /* Build a LUT entry used by the trigger functions. */ |
1096 | static void build_lut_entry(uint16_t value, uint16_t mask, uint16_t *entry) | |
ee492173 HE |
1097 | { |
1098 | int i, j, k, bit; | |
1099 | ||
f758d074 | 1100 | /* For each quad probe. */ |
ee492173 | 1101 | for (i = 0; i < 4; ++i) { |
c53d793f | 1102 | entry[i] = 0xffff; |
ee492173 | 1103 | |
f758d074 | 1104 | /* For each bit in LUT. */ |
ee492173 HE |
1105 | for (j = 0; j < 16; ++j) |
1106 | ||
f758d074 | 1107 | /* For each probe in quad. */ |
ee492173 HE |
1108 | for (k = 0; k < 4; ++k) { |
1109 | bit = 1 << (i * 4 + k); | |
1110 | ||
c53d793f HE |
1111 | /* Set bit in entry */ |
1112 | if ((mask & bit) && | |
1113 | ((!(value & bit)) != | |
4ae1f451 | 1114 | (!(j & (1 << k))))) |
c53d793f | 1115 | entry[i] &= ~(1 << j); |
ee492173 HE |
1116 | } |
1117 | } | |
c53d793f | 1118 | } |
ee492173 | 1119 | |
c53d793f HE |
1120 | /* Add a logical function to LUT mask. */ |
1121 | static void add_trigger_function(enum triggerop oper, enum triggerfunc func, | |
1122 | int index, int neg, uint16_t *mask) | |
1123 | { | |
1124 | int i, j; | |
1125 | int x[2][2], tmp, a, b, aset, bset, rset; | |
1126 | ||
1127 | memset(x, 0, 4 * sizeof(int)); | |
1128 | ||
1129 | /* Trigger detect condition. */ | |
1130 | switch (oper) { | |
1131 | case OP_LEVEL: | |
1132 | x[0][1] = 1; | |
1133 | x[1][1] = 1; | |
1134 | break; | |
1135 | case OP_NOT: | |
1136 | x[0][0] = 1; | |
1137 | x[1][0] = 1; | |
1138 | break; | |
1139 | case OP_RISE: | |
1140 | x[0][1] = 1; | |
1141 | break; | |
1142 | case OP_FALL: | |
1143 | x[1][0] = 1; | |
1144 | break; | |
1145 | case OP_RISEFALL: | |
1146 | x[0][1] = 1; | |
1147 | x[1][0] = 1; | |
1148 | break; | |
1149 | case OP_NOTRISE: | |
1150 | x[1][1] = 1; | |
1151 | x[0][0] = 1; | |
1152 | x[1][0] = 1; | |
1153 | break; | |
1154 | case OP_NOTFALL: | |
1155 | x[1][1] = 1; | |
1156 | x[0][0] = 1; | |
1157 | x[0][1] = 1; | |
1158 | break; | |
1159 | case OP_NOTRISEFALL: | |
1160 | x[1][1] = 1; | |
1161 | x[0][0] = 1; | |
1162 | break; | |
1163 | } | |
1164 | ||
1165 | /* Transpose if neg is set. */ | |
1166 | if (neg) { | |
ea9cfed7 | 1167 | for (i = 0; i < 2; ++i) { |
c53d793f HE |
1168 | for (j = 0; j < 2; ++j) { |
1169 | tmp = x[i][j]; | |
1170 | x[i][j] = x[1-i][1-j]; | |
1171 | x[1-i][1-j] = tmp; | |
1172 | } | |
ea9cfed7 | 1173 | } |
c53d793f HE |
1174 | } |
1175 | ||
1176 | /* Update mask with function. */ | |
1177 | for (i = 0; i < 16; ++i) { | |
1178 | a = (i >> (2 * index + 0)) & 1; | |
1179 | b = (i >> (2 * index + 1)) & 1; | |
1180 | ||
1181 | aset = (*mask >> i) & 1; | |
1182 | bset = x[b][a]; | |
1183 | ||
1184 | if (func == FUNC_AND || func == FUNC_NAND) | |
1185 | rset = aset & bset; | |
1186 | else if (func == FUNC_OR || func == FUNC_NOR) | |
1187 | rset = aset | bset; | |
1188 | else if (func == FUNC_XOR || func == FUNC_NXOR) | |
1189 | rset = aset ^ bset; | |
1190 | ||
1191 | if (func == FUNC_NAND || func == FUNC_NOR || func == FUNC_NXOR) | |
1192 | rset = !rset; | |
1193 | ||
1194 | *mask &= ~(1 << i); | |
1195 | ||
1196 | if (rset) | |
1197 | *mask |= 1 << i; | |
1198 | } | |
1199 | } | |
1200 | ||
1201 | /* | |
1202 | * Build trigger LUTs used by 50 MHz and lower sample rates for supporting | |
1203 | * simple pin change and state triggers. Only two transitions (rise/fall) can be | |
1204 | * set at any time, but a full mask and value can be set (0/1). | |
1205 | */ | |
ea9cfed7 | 1206 | static int build_basic_trigger(struct triggerlut *lut, struct context *ctx) |
c53d793f HE |
1207 | { |
1208 | int i,j; | |
4ae1f451 | 1209 | uint16_t masks[2] = { 0, 0 }; |
c53d793f HE |
1210 | |
1211 | memset(lut, 0, sizeof(struct triggerlut)); | |
1212 | ||
1213 | /* Contant for simple triggers. */ | |
1214 | lut->m4 = 0xa000; | |
1215 | ||
1216 | /* Value/mask trigger support. */ | |
ea9cfed7 | 1217 | build_lut_entry(ctx->trigger.simplevalue, ctx->trigger.simplemask, |
99965709 | 1218 | lut->m2d); |
c53d793f HE |
1219 | |
1220 | /* Rise/fall trigger support. */ | |
1221 | for (i = 0, j = 0; i < 16; ++i) { | |
ea9cfed7 UH |
1222 | if (ctx->trigger.risingmask & (1 << i) || |
1223 | ctx->trigger.fallingmask & (1 << i)) | |
c53d793f HE |
1224 | masks[j++] = 1 << i; |
1225 | } | |
1226 | ||
1227 | build_lut_entry(masks[0], masks[0], lut->m0d); | |
1228 | build_lut_entry(masks[1], masks[1], lut->m1d); | |
1229 | ||
1230 | /* Add glue logic */ | |
1231 | if (masks[0] || masks[1]) { | |
1232 | /* Transition trigger. */ | |
ea9cfed7 | 1233 | if (masks[0] & ctx->trigger.risingmask) |
c53d793f | 1234 | add_trigger_function(OP_RISE, FUNC_OR, 0, 0, &lut->m3); |
ea9cfed7 | 1235 | if (masks[0] & ctx->trigger.fallingmask) |
c53d793f | 1236 | add_trigger_function(OP_FALL, FUNC_OR, 0, 0, &lut->m3); |
ea9cfed7 | 1237 | if (masks[1] & ctx->trigger.risingmask) |
c53d793f | 1238 | add_trigger_function(OP_RISE, FUNC_OR, 1, 0, &lut->m3); |
ea9cfed7 | 1239 | if (masks[1] & ctx->trigger.fallingmask) |
c53d793f HE |
1240 | add_trigger_function(OP_FALL, FUNC_OR, 1, 0, &lut->m3); |
1241 | } else { | |
1242 | /* Only value/mask trigger. */ | |
1243 | lut->m3 = 0xffff; | |
1244 | } | |
ee492173 | 1245 | |
c53d793f | 1246 | /* Triggertype: event. */ |
ee492173 HE |
1247 | lut->params.selres = 3; |
1248 | ||
e46b8fb1 | 1249 | return SR_OK; |
ee492173 HE |
1250 | } |
1251 | ||
6b3dfec8 | 1252 | static int hw_dev_acquisition_start(int dev_index, gpointer session_data) |
28a35d8a | 1253 | { |
d68e2d1a | 1254 | struct sr_dev_inst *sdi; |
ea9cfed7 | 1255 | struct context *ctx; |
b9c735a2 UH |
1256 | struct sr_datafeed_packet packet; |
1257 | struct sr_datafeed_header header; | |
9ddb2a12 | 1258 | struct clockselect_50 clockselect; |
82957b65 | 1259 | int frac, triggerpin, ret; |
57bbf56b HE |
1260 | uint8_t triggerselect; |
1261 | struct triggerinout triggerinout_conf; | |
ee492173 | 1262 | struct triggerlut lut; |
28a35d8a | 1263 | |
cb93f8a9 UH |
1264 | /* Avoid compiler warnings. */ |
1265 | (void)session_data; | |
28a35d8a | 1266 | |
bb7ef793 | 1267 | if (!(sdi = sr_dev_inst_get(dev_insts, dev_index))) |
e46b8fb1 | 1268 | return SR_ERR; |
28a35d8a | 1269 | |
ea9cfed7 | 1270 | ctx = sdi->priv; |
28a35d8a | 1271 | |
ea9cfed7 UH |
1272 | /* If the samplerate has not been set, default to 200 kHz. */ |
1273 | if (ctx->cur_firmware == -1) { | |
82957b65 UH |
1274 | if ((ret = set_samplerate(sdi, SR_KHZ(200))) != SR_OK) |
1275 | return ret; | |
1276 | } | |
e8397563 | 1277 | |
eec5275e | 1278 | /* Enter trigger programming mode. */ |
ea9cfed7 | 1279 | sigma_set_register(WRITE_TRIGGER_SELECT1, 0x20, ctx); |
28a35d8a | 1280 | |
eec5275e | 1281 | /* 100 and 200 MHz mode. */ |
ea9cfed7 UH |
1282 | if (ctx->cur_samplerate >= SR_MHZ(100)) { |
1283 | sigma_set_register(WRITE_TRIGGER_SELECT1, 0x81, ctx); | |
57bbf56b | 1284 | |
a42aec7f HE |
1285 | /* Find which pin to trigger on from mask. */ |
1286 | for (triggerpin = 0; triggerpin < 8; ++triggerpin) | |
ea9cfed7 | 1287 | if ((ctx->trigger.risingmask | ctx->trigger.fallingmask) & |
a42aec7f HE |
1288 | (1 << triggerpin)) |
1289 | break; | |
1290 | ||
1291 | /* Set trigger pin and light LED on trigger. */ | |
1292 | triggerselect = (1 << LEDSEL1) | (triggerpin & 0x7); | |
1293 | ||
1294 | /* Default rising edge. */ | |
ea9cfed7 | 1295 | if (ctx->trigger.fallingmask) |
a42aec7f | 1296 | triggerselect |= 1 << 3; |
57bbf56b | 1297 | |
eec5275e | 1298 | /* All other modes. */ |
ea9cfed7 UH |
1299 | } else if (ctx->cur_samplerate <= SR_MHZ(50)) { |
1300 | build_basic_trigger(&lut, ctx); | |
ee492173 | 1301 | |
ea9cfed7 | 1302 | sigma_write_trigger_lut(&lut, ctx); |
57bbf56b HE |
1303 | |
1304 | triggerselect = (1 << LEDSEL1) | (1 << LEDSEL0); | |
1305 | } | |
1306 | ||
eec5275e | 1307 | /* Setup trigger in and out pins to default values. */ |
57bbf56b HE |
1308 | memset(&triggerinout_conf, 0, sizeof(struct triggerinout)); |
1309 | triggerinout_conf.trgout_bytrigger = 1; | |
1310 | triggerinout_conf.trgout_enable = 1; | |
1311 | ||
28a35d8a | 1312 | sigma_write_register(WRITE_TRIGGER_OPTION, |
57bbf56b | 1313 | (uint8_t *) &triggerinout_conf, |
ea9cfed7 | 1314 | sizeof(struct triggerinout), ctx); |
28a35d8a | 1315 | |
eec5275e | 1316 | /* Go back to normal mode. */ |
ea9cfed7 | 1317 | sigma_set_register(WRITE_TRIGGER_SELECT1, triggerselect, ctx); |
28a35d8a | 1318 | |
edca2c5c | 1319 | /* Set clock select register. */ |
ea9cfed7 | 1320 | if (ctx->cur_samplerate == SR_MHZ(200)) |
edca2c5c | 1321 | /* Enable 4 probes. */ |
ea9cfed7 UH |
1322 | sigma_set_register(WRITE_CLOCK_SELECT, 0xf0, ctx); |
1323 | else if (ctx->cur_samplerate == SR_MHZ(100)) | |
edca2c5c | 1324 | /* Enable 8 probes. */ |
ea9cfed7 | 1325 | sigma_set_register(WRITE_CLOCK_SELECT, 0x00, ctx); |
edca2c5c HE |
1326 | else { |
1327 | /* | |
9ddb2a12 | 1328 | * 50 MHz mode (or fraction thereof). Any fraction down to |
eec5275e | 1329 | * 50 MHz / 256 can be used, but is not supported by sigrok API. |
edca2c5c | 1330 | */ |
ea9cfed7 | 1331 | frac = SR_MHZ(50) / ctx->cur_samplerate - 1; |
edca2c5c | 1332 | |
9ddb2a12 UH |
1333 | clockselect.async = 0; |
1334 | clockselect.fraction = frac; | |
1335 | clockselect.disabled_probes = 0; | |
edca2c5c HE |
1336 | |
1337 | sigma_write_register(WRITE_CLOCK_SELECT, | |
9ddb2a12 | 1338 | (uint8_t *) &clockselect, |
ea9cfed7 | 1339 | sizeof(clockselect), ctx); |
edca2c5c HE |
1340 | } |
1341 | ||
fefa1800 | 1342 | /* Setup maximum post trigger time. */ |
99965709 | 1343 | sigma_set_register(WRITE_POST_TRIGGER, |
ea9cfed7 | 1344 | (ctx->capture_ratio * 255) / 100, ctx); |
28a35d8a | 1345 | |
eec5275e | 1346 | /* Start acqusition. */ |
ea9cfed7 UH |
1347 | gettimeofday(&ctx->start_tv, 0); |
1348 | sigma_set_register(WRITE_MODE, 0x0d, ctx); | |
99965709 | 1349 | |
ea9cfed7 | 1350 | ctx->session_id = session_data; |
28a35d8a | 1351 | |
28a35d8a | 1352 | /* Send header packet to the session bus. */ |
5a2326a7 | 1353 | packet.type = SR_DF_HEADER; |
28a35d8a HE |
1354 | packet.payload = &header; |
1355 | header.feed_version = 1; | |
1356 | gettimeofday(&header.starttime, NULL); | |
ea9cfed7 UH |
1357 | header.samplerate = ctx->cur_samplerate; |
1358 | header.num_logic_probes = ctx->num_probes; | |
9c939c51 | 1359 | sr_session_bus(session_data, &packet); |
28a35d8a | 1360 | |
57bbf56b | 1361 | /* Add capture source. */ |
6f1be0a2 | 1362 | sr_source_add(0, G_IO_IN, 10, receive_data, sdi); |
57bbf56b | 1363 | |
ea9cfed7 | 1364 | ctx->state.state = SIGMA_CAPTURE; |
6aac7737 | 1365 | |
e46b8fb1 | 1366 | return SR_OK; |
28a35d8a HE |
1367 | } |
1368 | ||
6b3dfec8 | 1369 | static int hw_dev_acquisition_stop(int dev_index, gpointer session_data) |
28a35d8a | 1370 | { |
d68e2d1a | 1371 | struct sr_dev_inst *sdi; |
ea9cfed7 | 1372 | struct context *ctx; |
6aac7737 HE |
1373 | uint8_t modestatus; |
1374 | ||
cb93f8a9 UH |
1375 | /* Avoid compiler warnings. */ |
1376 | (void)session_data; | |
28a35d8a | 1377 | |
bb7ef793 | 1378 | if (!(sdi = sr_dev_inst_get(dev_insts, dev_index))) { |
7b48d6e1 | 1379 | sr_err("sigma: %s: sdi was NULL", __func__); |
3010f21c UH |
1380 | return SR_ERR_BUG; |
1381 | } | |
1382 | ||
ea9cfed7 | 1383 | if (!(ctx = sdi->priv)) { |
7b48d6e1 | 1384 | sr_err("sigma: %s: sdi->priv was NULL", __func__); |
3010f21c UH |
1385 | return SR_ERR_BUG; |
1386 | } | |
1387 | ||
fefa1800 | 1388 | /* Stop acquisition. */ |
ea9cfed7 | 1389 | sigma_set_register(WRITE_MODE, 0x11, ctx); |
28a35d8a | 1390 | |
6aac7737 | 1391 | /* Set SDRAM Read Enable. */ |
ea9cfed7 | 1392 | sigma_set_register(WRITE_MODE, 0x02, ctx); |
6aac7737 HE |
1393 | |
1394 | /* Get the current position. */ | |
ea9cfed7 | 1395 | sigma_read_pos(&ctx->state.stoppos, &ctx->state.triggerpos, ctx); |
6aac7737 HE |
1396 | |
1397 | /* Check if trigger has fired. */ | |
ea9cfed7 | 1398 | modestatus = sigma_get_register(READ_MODE, ctx); |
3010f21c | 1399 | if (modestatus & 0x20) |
ea9cfed7 | 1400 | ctx->state.triggerchunk = ctx->state.triggerpos / 512; |
3010f21c | 1401 | else |
ea9cfed7 | 1402 | ctx->state.triggerchunk = -1; |
6aac7737 | 1403 | |
ea9cfed7 | 1404 | ctx->state.chunks_downloaded = 0; |
6aac7737 | 1405 | |
ea9cfed7 | 1406 | ctx->state.state = SIGMA_DOWNLOAD; |
3010f21c UH |
1407 | |
1408 | return SR_OK; | |
28a35d8a HE |
1409 | } |
1410 | ||
bb7ef793 | 1411 | SR_PRIV struct sr_dev_plugin asix_sigma_plugin_info = { |
e519ba86 UH |
1412 | .name = "asix-sigma", |
1413 | .longname = "ASIX SIGMA", | |
1414 | .api_version = 1, | |
1415 | .init = hw_init, | |
1416 | .cleanup = hw_cleanup, | |
e7eb703f UH |
1417 | .dev_open = hw_dev_open, |
1418 | .dev_close = hw_dev_close, | |
5097b0d0 | 1419 | .dev_info_get = hw_dev_info_get, |
e7eb703f | 1420 | .dev_status_get = hw_dev_status_get, |
ffedd0bf | 1421 | .hwcap_get_all = hw_hwcap_get_all, |
a9a245b4 | 1422 | .dev_config_set = hw_dev_config_set, |
6b3dfec8 UH |
1423 | .dev_acquisition_start = hw_dev_acquisition_start, |
1424 | .dev_acquisition_stop = hw_dev_acquisition_stop, | |
28a35d8a | 1425 | }; |