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Commit | Line | Data |
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28a35d8a HE |
1 | /* |
2 | * This file is part of the sigrok project. | |
3 | * | |
868501fa | 4 | * Copyright (C) 2010-2012 Håvard Espeland <gus@ping.uio.no>, |
911f1834 UH |
5 | * Copyright (C) 2010 Martin Stensgård <mastensg@ping.uio.no> |
6 | * Copyright (C) 2010 Carl Henrik Lunde <chlunde@ping.uio.no> | |
28a35d8a HE |
7 | * |
8 | * This program is free software: you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation, either version 3 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
20 | */ | |
21 | ||
911f1834 | 22 | /* |
6352d030 | 23 | * ASIX SIGMA/SIGMA2 logic analyzer driver |
911f1834 UH |
24 | */ |
25 | ||
3bbd9849 UH |
26 | #include <glib.h> |
27 | #include <glib/gstdio.h> | |
28a35d8a HE |
28 | #include <ftdi.h> |
29 | #include <string.h> | |
45c59c8b BV |
30 | #include "libsigrok.h" |
31 | #include "libsigrok-internal.h" | |
28a35d8a HE |
32 | #include "asix-sigma.h" |
33 | ||
34 | #define USB_VENDOR 0xa600 | |
35 | #define USB_PRODUCT 0xa000 | |
36 | #define USB_DESCRIPTION "ASIX SIGMA" | |
37 | #define USB_VENDOR_NAME "ASIX" | |
38 | #define USB_MODEL_NAME "SIGMA" | |
39 | #define USB_MODEL_VERSION "" | |
ee492173 | 40 | #define TRIGGER_TYPES "rf10" |
464d12c7 | 41 | #define NUM_PROBES 16 |
28a35d8a | 42 | |
ed300b9f BV |
43 | SR_PRIV struct sr_dev_driver asix_sigma_driver_info; |
44 | static struct sr_dev_driver *adi = &asix_sigma_driver_info; | |
69b07d14 | 45 | static int hw_dev_acquisition_stop(struct sr_dev_inst *sdi, void *cb_data); |
28a35d8a | 46 | |
a533743d | 47 | static const uint64_t supported_samplerates[] = { |
59df0c77 UH |
48 | SR_KHZ(200), |
49 | SR_KHZ(250), | |
50 | SR_KHZ(500), | |
51 | SR_MHZ(1), | |
52 | SR_MHZ(5), | |
53 | SR_MHZ(10), | |
54 | SR_MHZ(25), | |
55 | SR_MHZ(50), | |
56 | SR_MHZ(100), | |
57 | SR_MHZ(200), | |
28a35d8a HE |
58 | 0, |
59 | }; | |
60 | ||
d261dbbf UH |
61 | /* |
62 | * Probe numbers seem to go from 1-16, according to this image: | |
63 | * http://tools.asix.net/img/sigma_sigmacab_pins_720.jpg | |
64 | * (the cable has two additional GND pins, and a TI and TO pin) | |
65 | */ | |
c37d2b1b | 66 | static const char *probe_names[NUM_PROBES + 1] = { |
464d12c7 KS |
67 | "1", |
68 | "2", | |
69 | "3", | |
70 | "4", | |
71 | "5", | |
72 | "6", | |
73 | "7", | |
74 | "8", | |
75 | "9", | |
76 | "10", | |
77 | "11", | |
78 | "12", | |
79 | "13", | |
80 | "14", | |
81 | "15", | |
d261dbbf | 82 | "16", |
464d12c7 KS |
83 | NULL, |
84 | }; | |
85 | ||
a533743d | 86 | static const struct sr_samplerates samplerates = { |
590b9f9a UH |
87 | 0, |
88 | 0, | |
89 | 0, | |
28a35d8a HE |
90 | supported_samplerates, |
91 | }; | |
92 | ||
915f7cc8 | 93 | static const int hwcaps[] = { |
5a2326a7 UH |
94 | SR_HWCAP_LOGIC_ANALYZER, |
95 | SR_HWCAP_SAMPLERATE, | |
96 | SR_HWCAP_CAPTURE_RATIO, | |
28a35d8a | 97 | |
5a2326a7 | 98 | SR_HWCAP_LIMIT_MSEC, |
28a35d8a HE |
99 | 0, |
100 | }; | |
101 | ||
fefa1800 UH |
102 | /* Force the FPGA to reboot. */ |
103 | static uint8_t suicide[] = { | |
104 | 0x84, 0x84, 0x88, 0x84, 0x88, 0x84, 0x88, 0x84, | |
105 | }; | |
106 | ||
107 | /* Prepare to upload firmware (FPGA specific). */ | |
108 | static uint8_t init[] = { | |
109 | 0x03, 0x03, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, | |
110 | }; | |
111 | ||
112 | /* Initialize the logic analyzer mode. */ | |
113 | static uint8_t logic_mode_start[] = { | |
114 | 0x00, 0x40, 0x0f, 0x25, 0x35, 0x40, | |
115 | 0x2a, 0x3a, 0x40, 0x03, 0x20, 0x38, | |
116 | }; | |
117 | ||
eec5275e | 118 | static const char *firmware_files[] = { |
a8116d76 HE |
119 | "asix-sigma-50.fw", /* 50 MHz, supports 8 bit fractions */ |
120 | "asix-sigma-100.fw", /* 100 MHz */ | |
121 | "asix-sigma-200.fw", /* 200 MHz */ | |
ed09fd07 | 122 | "asix-sigma-50sync.fw", /* Synchronous clock from pin */ |
a8116d76 | 123 | "asix-sigma-phasor.fw", /* Frequency counter */ |
f6564c8d HE |
124 | }; |
125 | ||
0e1357e8 | 126 | static int sigma_read(void *buf, size_t size, struct dev_context *devc) |
28a35d8a HE |
127 | { |
128 | int ret; | |
fefa1800 | 129 | |
0e1357e8 | 130 | ret = ftdi_read_data(&devc->ftdic, (unsigned char *)buf, size); |
28a35d8a | 131 | if (ret < 0) { |
47f4f073 | 132 | sr_err("ftdi_read_data failed: %s", |
0e1357e8 | 133 | ftdi_get_error_string(&devc->ftdic)); |
28a35d8a HE |
134 | } |
135 | ||
136 | return ret; | |
137 | } | |
138 | ||
0e1357e8 | 139 | static int sigma_write(void *buf, size_t size, struct dev_context *devc) |
28a35d8a HE |
140 | { |
141 | int ret; | |
fefa1800 | 142 | |
0e1357e8 | 143 | ret = ftdi_write_data(&devc->ftdic, (unsigned char *)buf, size); |
28a35d8a | 144 | if (ret < 0) { |
47f4f073 | 145 | sr_err("ftdi_write_data failed: %s", |
0e1357e8 | 146 | ftdi_get_error_string(&devc->ftdic)); |
fefa1800 | 147 | } else if ((size_t) ret != size) { |
47f4f073 | 148 | sr_err("ftdi_write_data did not complete write."); |
28a35d8a HE |
149 | } |
150 | ||
151 | return ret; | |
152 | } | |
153 | ||
99965709 | 154 | static int sigma_write_register(uint8_t reg, uint8_t *data, size_t len, |
0e1357e8 | 155 | struct dev_context *devc) |
28a35d8a HE |
156 | { |
157 | size_t i; | |
158 | uint8_t buf[len + 2]; | |
159 | int idx = 0; | |
160 | ||
161 | buf[idx++] = REG_ADDR_LOW | (reg & 0xf); | |
162 | buf[idx++] = REG_ADDR_HIGH | (reg >> 4); | |
163 | ||
fefa1800 | 164 | for (i = 0; i < len; ++i) { |
28a35d8a HE |
165 | buf[idx++] = REG_DATA_LOW | (data[i] & 0xf); |
166 | buf[idx++] = REG_DATA_HIGH_WRITE | (data[i] >> 4); | |
167 | } | |
168 | ||
0e1357e8 | 169 | return sigma_write(buf, idx, devc); |
28a35d8a HE |
170 | } |
171 | ||
0e1357e8 | 172 | static int sigma_set_register(uint8_t reg, uint8_t value, struct dev_context *devc) |
28a35d8a | 173 | { |
0e1357e8 | 174 | return sigma_write_register(reg, &value, 1, devc); |
28a35d8a HE |
175 | } |
176 | ||
99965709 | 177 | static int sigma_read_register(uint8_t reg, uint8_t *data, size_t len, |
0e1357e8 | 178 | struct dev_context *devc) |
28a35d8a HE |
179 | { |
180 | uint8_t buf[3]; | |
fefa1800 | 181 | |
28a35d8a HE |
182 | buf[0] = REG_ADDR_LOW | (reg & 0xf); |
183 | buf[1] = REG_ADDR_HIGH | (reg >> 4); | |
28a35d8a HE |
184 | buf[2] = REG_READ_ADDR; |
185 | ||
0e1357e8 | 186 | sigma_write(buf, sizeof(buf), devc); |
28a35d8a | 187 | |
0e1357e8 | 188 | return sigma_read(data, len, devc); |
28a35d8a HE |
189 | } |
190 | ||
0e1357e8 | 191 | static uint8_t sigma_get_register(uint8_t reg, struct dev_context *devc) |
28a35d8a HE |
192 | { |
193 | uint8_t value; | |
fefa1800 | 194 | |
0e1357e8 | 195 | if (1 != sigma_read_register(reg, &value, 1, devc)) { |
47f4f073 | 196 | sr_err("sigma_get_register: 1 byte expected"); |
28a35d8a HE |
197 | return 0; |
198 | } | |
199 | ||
200 | return value; | |
201 | } | |
202 | ||
99965709 | 203 | static int sigma_read_pos(uint32_t *stoppos, uint32_t *triggerpos, |
0e1357e8 | 204 | struct dev_context *devc) |
28a35d8a HE |
205 | { |
206 | uint8_t buf[] = { | |
207 | REG_ADDR_LOW | READ_TRIGGER_POS_LOW, | |
208 | ||
209 | REG_READ_ADDR | NEXT_REG, | |
210 | REG_READ_ADDR | NEXT_REG, | |
211 | REG_READ_ADDR | NEXT_REG, | |
212 | REG_READ_ADDR | NEXT_REG, | |
213 | REG_READ_ADDR | NEXT_REG, | |
214 | REG_READ_ADDR | NEXT_REG, | |
215 | }; | |
28a35d8a HE |
216 | uint8_t result[6]; |
217 | ||
0e1357e8 | 218 | sigma_write(buf, sizeof(buf), devc); |
28a35d8a | 219 | |
0e1357e8 | 220 | sigma_read(result, sizeof(result), devc); |
28a35d8a HE |
221 | |
222 | *triggerpos = result[0] | (result[1] << 8) | (result[2] << 16); | |
223 | *stoppos = result[3] | (result[4] << 8) | (result[5] << 16); | |
224 | ||
57bbf56b HE |
225 | /* Not really sure why this must be done, but according to spec. */ |
226 | if ((--*stoppos & 0x1ff) == 0x1ff) | |
227 | stoppos -= 64; | |
228 | ||
229 | if ((*--triggerpos & 0x1ff) == 0x1ff) | |
230 | triggerpos -= 64; | |
231 | ||
28a35d8a HE |
232 | return 1; |
233 | } | |
234 | ||
99965709 | 235 | static int sigma_read_dram(uint16_t startchunk, size_t numchunks, |
0e1357e8 | 236 | uint8_t *data, struct dev_context *devc) |
28a35d8a HE |
237 | { |
238 | size_t i; | |
239 | uint8_t buf[4096]; | |
240 | int idx = 0; | |
241 | ||
fefa1800 | 242 | /* Send the startchunk. Index start with 1. */ |
28a35d8a HE |
243 | buf[0] = startchunk >> 8; |
244 | buf[1] = startchunk & 0xff; | |
0e1357e8 | 245 | sigma_write_register(WRITE_MEMROW, buf, 2, devc); |
28a35d8a | 246 | |
fefa1800 | 247 | /* Read the DRAM. */ |
28a35d8a HE |
248 | buf[idx++] = REG_DRAM_BLOCK; |
249 | buf[idx++] = REG_DRAM_WAIT_ACK; | |
250 | ||
251 | for (i = 0; i < numchunks; ++i) { | |
fefa1800 UH |
252 | /* Alternate bit to copy from DRAM to cache. */ |
253 | if (i != (numchunks - 1)) | |
254 | buf[idx++] = REG_DRAM_BLOCK | (((i + 1) % 2) << 4); | |
28a35d8a HE |
255 | |
256 | buf[idx++] = REG_DRAM_BLOCK_DATA | ((i % 2) << 4); | |
257 | ||
fefa1800 | 258 | if (i != (numchunks - 1)) |
28a35d8a HE |
259 | buf[idx++] = REG_DRAM_WAIT_ACK; |
260 | } | |
261 | ||
0e1357e8 | 262 | sigma_write(buf, idx, devc); |
28a35d8a | 263 | |
0e1357e8 | 264 | return sigma_read(data, numchunks * CHUNK_SIZE, devc); |
28a35d8a HE |
265 | } |
266 | ||
4ae1f451 | 267 | /* Upload trigger look-up tables to Sigma. */ |
0e1357e8 | 268 | static int sigma_write_trigger_lut(struct triggerlut *lut, struct dev_context *devc) |
ee492173 HE |
269 | { |
270 | int i; | |
271 | uint8_t tmp[2]; | |
272 | uint16_t bit; | |
273 | ||
274 | /* Transpose the table and send to Sigma. */ | |
275 | for (i = 0; i < 16; ++i) { | |
276 | bit = 1 << i; | |
277 | ||
278 | tmp[0] = tmp[1] = 0; | |
279 | ||
280 | if (lut->m2d[0] & bit) | |
281 | tmp[0] |= 0x01; | |
282 | if (lut->m2d[1] & bit) | |
283 | tmp[0] |= 0x02; | |
284 | if (lut->m2d[2] & bit) | |
285 | tmp[0] |= 0x04; | |
286 | if (lut->m2d[3] & bit) | |
287 | tmp[0] |= 0x08; | |
288 | ||
289 | if (lut->m3 & bit) | |
290 | tmp[0] |= 0x10; | |
291 | if (lut->m3s & bit) | |
292 | tmp[0] |= 0x20; | |
293 | if (lut->m4 & bit) | |
294 | tmp[0] |= 0x40; | |
295 | ||
296 | if (lut->m0d[0] & bit) | |
297 | tmp[1] |= 0x01; | |
298 | if (lut->m0d[1] & bit) | |
299 | tmp[1] |= 0x02; | |
300 | if (lut->m0d[2] & bit) | |
301 | tmp[1] |= 0x04; | |
302 | if (lut->m0d[3] & bit) | |
303 | tmp[1] |= 0x08; | |
304 | ||
305 | if (lut->m1d[0] & bit) | |
306 | tmp[1] |= 0x10; | |
307 | if (lut->m1d[1] & bit) | |
308 | tmp[1] |= 0x20; | |
309 | if (lut->m1d[2] & bit) | |
310 | tmp[1] |= 0x40; | |
311 | if (lut->m1d[3] & bit) | |
312 | tmp[1] |= 0x80; | |
313 | ||
99965709 | 314 | sigma_write_register(WRITE_TRIGGER_SELECT0, tmp, sizeof(tmp), |
0e1357e8 BV |
315 | devc); |
316 | sigma_set_register(WRITE_TRIGGER_SELECT1, 0x30 | i, devc); | |
ee492173 HE |
317 | } |
318 | ||
319 | /* Send the parameters */ | |
320 | sigma_write_register(WRITE_TRIGGER_SELECT0, (uint8_t *) &lut->params, | |
0e1357e8 | 321 | sizeof(lut->params), devc); |
ee492173 | 322 | |
e46b8fb1 | 323 | return SR_OK; |
ee492173 HE |
324 | } |
325 | ||
fefa1800 | 326 | /* Generate the bitbang stream for programming the FPGA. */ |
28a35d8a | 327 | static int bin2bitbang(const char *filename, |
fefa1800 | 328 | unsigned char **buf, size_t *buf_size) |
28a35d8a | 329 | { |
fefa1800 | 330 | FILE *f; |
e3fff420 | 331 | unsigned long file_size; |
28a35d8a HE |
332 | unsigned long offset = 0; |
333 | unsigned char *p; | |
e3fff420 HE |
334 | uint8_t *firmware; |
335 | unsigned long fwsize = 0; | |
28a35d8a HE |
336 | const int buffer_size = 65536; |
337 | size_t i; | |
e3fff420 | 338 | int c, bit, v; |
fefa1800 | 339 | uint32_t imm = 0x3f6df2ab; |
28a35d8a | 340 | |
868d8cef | 341 | f = g_fopen(filename, "rb"); |
28a35d8a | 342 | if (!f) { |
47f4f073 | 343 | sr_err("g_fopen(\"%s\", \"rb\")", filename); |
b53738ba | 344 | return SR_ERR; |
28a35d8a HE |
345 | } |
346 | ||
347 | if (-1 == fseek(f, 0, SEEK_END)) { | |
47f4f073 | 348 | sr_err("fseek on %s failed", filename); |
28a35d8a | 349 | fclose(f); |
b53738ba | 350 | return SR_ERR; |
28a35d8a HE |
351 | } |
352 | ||
353 | file_size = ftell(f); | |
354 | ||
355 | fseek(f, 0, SEEK_SET); | |
356 | ||
b53738ba | 357 | if (!(firmware = g_try_malloc(buffer_size))) { |
47f4f073 | 358 | sr_err("%s: firmware malloc failed", __func__); |
12ad53f5 | 359 | fclose(f); |
b53738ba | 360 | return SR_ERR_MALLOC; |
28a35d8a HE |
361 | } |
362 | ||
28a35d8a HE |
363 | while ((c = getc(f)) != EOF) { |
364 | imm = (imm + 0xa853753) % 177 + (imm * 0x8034052); | |
e3fff420 | 365 | firmware[fwsize++] = c ^ imm; |
28a35d8a HE |
366 | } |
367 | fclose(f); | |
368 | ||
e3fff420 | 369 | if(fwsize != file_size) { |
47f4f073 | 370 | sr_err("%s: Error reading firmware", filename); |
e3fff420 HE |
371 | fclose(f); |
372 | g_free(firmware); | |
373 | return SR_ERR; | |
28a35d8a HE |
374 | } |
375 | ||
28a35d8a HE |
376 | *buf_size = fwsize * 2 * 8; |
377 | ||
b53738ba | 378 | *buf = p = (unsigned char *)g_try_malloc(*buf_size); |
28a35d8a | 379 | if (!p) { |
47f4f073 | 380 | sr_err("%s: buf/p malloc failed", __func__); |
12ad53f5 | 381 | g_free(firmware); |
b53738ba | 382 | return SR_ERR_MALLOC; |
28a35d8a HE |
383 | } |
384 | ||
385 | for (i = 0; i < fwsize; ++i) { | |
28a35d8a | 386 | for (bit = 7; bit >= 0; --bit) { |
fefa1800 | 387 | v = firmware[i] & 1 << bit ? 0x40 : 0x00; |
28a35d8a HE |
388 | p[offset++] = v | 0x01; |
389 | p[offset++] = v; | |
390 | } | |
391 | } | |
392 | ||
393 | g_free(firmware); | |
394 | ||
395 | if (offset != *buf_size) { | |
396 | g_free(*buf); | |
47f4f073 | 397 | sr_err("Error reading firmware %s " |
0aeb0ccd | 398 | "offset=%ld, file_size=%ld, buf_size=%zd.", |
133a37bf | 399 | filename, offset, file_size, *buf_size); |
28a35d8a | 400 | |
b53738ba | 401 | return SR_ERR; |
28a35d8a HE |
402 | } |
403 | ||
b53738ba | 404 | return SR_OK; |
28a35d8a HE |
405 | } |
406 | ||
811deee4 | 407 | static int clear_instances(void) |
0448d110 BV |
408 | { |
409 | GSList *l; | |
410 | struct sr_dev_inst *sdi; | |
0e1357e8 BV |
411 | struct drv_context *drvc; |
412 | struct dev_context *devc; | |
413 | ||
414 | drvc = adi->priv; | |
0448d110 BV |
415 | |
416 | /* Properly close all devices. */ | |
0e1357e8 | 417 | for (l = drvc->instances; l; l = l->next) { |
0448d110 BV |
418 | if (!(sdi = l->data)) { |
419 | /* Log error, but continue cleaning up the rest. */ | |
47f4f073 | 420 | sr_err("%s: sdi was NULL, continuing", __func__); |
0448d110 BV |
421 | continue; |
422 | } | |
423 | if (sdi->priv) { | |
0e1357e8 BV |
424 | devc = sdi->priv; |
425 | ftdi_free(&devc->ftdic); | |
0448d110 BV |
426 | } |
427 | sr_dev_inst_free(sdi); | |
428 | } | |
0e1357e8 BV |
429 | g_slist_free(drvc->instances); |
430 | drvc->instances = NULL; | |
0448d110 | 431 | |
811deee4 | 432 | return SR_OK; |
0448d110 BV |
433 | } |
434 | ||
40dda2c3 | 435 | static int hw_init(void) |
61136ea6 | 436 | { |
b32503cc | 437 | struct drv_context *drvc; |
61136ea6 | 438 | |
b32503cc | 439 | if (!(drvc = g_try_malloc0(sizeof(struct drv_context)))) { |
47f4f073 | 440 | sr_err("Driver context malloc failed."); |
886a52b6 | 441 | return SR_ERR_MALLOC; |
b32503cc BV |
442 | } |
443 | adi->priv = drvc; | |
61136ea6 BV |
444 | |
445 | return SR_OK; | |
446 | } | |
447 | ||
0448d110 | 448 | static GSList *hw_scan(GSList *options) |
28a35d8a | 449 | { |
d68e2d1a | 450 | struct sr_dev_inst *sdi; |
87ca93c5 | 451 | struct sr_probe *probe; |
0e1357e8 BV |
452 | struct drv_context *drvc; |
453 | struct dev_context *devc; | |
0448d110 | 454 | GSList *devices; |
e3fff420 HE |
455 | struct ftdi_device_list *devlist; |
456 | char serial_txt[10]; | |
457 | uint32_t serial; | |
87ca93c5 | 458 | int ret, i; |
28a35d8a | 459 | |
0448d110 | 460 | (void)options; |
0e1357e8 | 461 | drvc = adi->priv; |
0448d110 BV |
462 | devices = NULL; |
463 | clear_instances(); | |
464 | ||
0e1357e8 | 465 | if (!(devc = g_try_malloc(sizeof(struct dev_context)))) { |
47f4f073 | 466 | sr_err("%s: devc malloc failed", __func__); |
0448d110 | 467 | return NULL; |
b53738ba | 468 | } |
99965709 | 469 | |
0e1357e8 | 470 | ftdi_init(&devc->ftdic); |
28a35d8a | 471 | |
fefa1800 | 472 | /* Look for SIGMAs. */ |
e3fff420 | 473 | |
0e1357e8 | 474 | if ((ret = ftdi_usb_find_all(&devc->ftdic, &devlist, |
eec944c5 BV |
475 | USB_VENDOR, USB_PRODUCT)) <= 0) { |
476 | if (ret < 0) | |
477 | sr_err("ftdi_usb_find_all(): %d", ret); | |
99965709 | 478 | goto free; |
eec944c5 | 479 | } |
99965709 | 480 | |
e3fff420 | 481 | /* Make sure it's a version 1 or 2 SIGMA. */ |
0e1357e8 | 482 | ftdi_usb_get_strings(&devc->ftdic, devlist->dev, NULL, 0, NULL, 0, |
6352d030 | 483 | serial_txt, sizeof(serial_txt)); |
e3fff420 HE |
484 | sscanf(serial_txt, "%x", &serial); |
485 | ||
6352d030 | 486 | if (serial < 0xa6010000 || serial > 0xa602ffff) { |
47f4f073 UH |
487 | sr_err("Only SIGMA and SIGMA2 are supported " |
488 | "in this version of libsigrok."); | |
e3fff420 HE |
489 | goto free; |
490 | } | |
491 | ||
492 | sr_info("Found ASIX SIGMA - Serial: %s", serial_txt); | |
493 | ||
0e1357e8 BV |
494 | devc->cur_samplerate = 0; |
495 | devc->period_ps = 0; | |
496 | devc->limit_msec = 0; | |
497 | devc->cur_firmware = -1; | |
498 | devc->num_probes = 0; | |
499 | devc->samples_per_event = 0; | |
500 | devc->capture_ratio = 50; | |
501 | devc->use_triggers = 0; | |
28a35d8a | 502 | |
fefa1800 | 503 | /* Register SIGMA device. */ |
d68e2d1a UH |
504 | if (!(sdi = sr_dev_inst_new(0, SR_ST_INITIALIZING, USB_VENDOR_NAME, |
505 | USB_MODEL_NAME, USB_MODEL_VERSION))) { | |
47f4f073 | 506 | sr_err("%s: sdi was NULL", __func__); |
99965709 | 507 | goto free; |
d68e2d1a | 508 | } |
d7bbecfd | 509 | sdi->driver = adi; |
87ca93c5 BV |
510 | |
511 | for (i = 0; probe_names[i]; i++) { | |
512 | if (!(probe = sr_probe_new(i, SR_PROBE_ANALOG, TRUE, | |
513 | probe_names[i]))) | |
514 | return NULL; | |
515 | sdi->probes = g_slist_append(sdi->probes, probe); | |
516 | } | |
517 | ||
0448d110 | 518 | devices = g_slist_append(devices, sdi); |
0e1357e8 BV |
519 | drvc->instances = g_slist_append(drvc->instances, sdi); |
520 | sdi->priv = devc; | |
28a35d8a | 521 | |
fefa1800 | 522 | /* We will open the device again when we need it. */ |
e3fff420 | 523 | ftdi_list_free(&devlist); |
28a35d8a | 524 | |
0448d110 | 525 | return devices; |
ea9cfed7 | 526 | |
99965709 | 527 | free: |
0e1357e8 BV |
528 | ftdi_deinit(&devc->ftdic); |
529 | g_free(devc); | |
0448d110 | 530 | return NULL; |
28a35d8a HE |
531 | } |
532 | ||
811deee4 BV |
533 | static GSList *hw_dev_list(void) |
534 | { | |
535 | struct drv_context *drvc; | |
536 | ||
537 | drvc = adi->priv; | |
538 | ||
539 | return drvc->instances; | |
540 | } | |
541 | ||
0e1357e8 | 542 | static int upload_firmware(int firmware_idx, struct dev_context *devc) |
28a35d8a HE |
543 | { |
544 | int ret; | |
545 | unsigned char *buf; | |
546 | unsigned char pins; | |
547 | size_t buf_size; | |
28a35d8a | 548 | unsigned char result[32]; |
e8397563 | 549 | char firmware_path[128]; |
28a35d8a | 550 | |
fefa1800 | 551 | /* Make sure it's an ASIX SIGMA. */ |
0e1357e8 | 552 | if ((ret = ftdi_usb_open_desc(&devc->ftdic, |
28a35d8a | 553 | USB_VENDOR, USB_PRODUCT, USB_DESCRIPTION, NULL)) < 0) { |
47f4f073 | 554 | sr_err("ftdi_usb_open failed: %s", |
0e1357e8 | 555 | ftdi_get_error_string(&devc->ftdic)); |
28a35d8a HE |
556 | return 0; |
557 | } | |
558 | ||
0e1357e8 | 559 | if ((ret = ftdi_set_bitmode(&devc->ftdic, 0xdf, BITMODE_BITBANG)) < 0) { |
47f4f073 | 560 | sr_err("ftdi_set_bitmode failed: %s", |
0e1357e8 | 561 | ftdi_get_error_string(&devc->ftdic)); |
28a35d8a HE |
562 | return 0; |
563 | } | |
564 | ||
fefa1800 | 565 | /* Four times the speed of sigmalogan - Works well. */ |
0e1357e8 | 566 | if ((ret = ftdi_set_baudrate(&devc->ftdic, 750000)) < 0) { |
47f4f073 | 567 | sr_err("ftdi_set_baudrate failed: %s", |
0e1357e8 | 568 | ftdi_get_error_string(&devc->ftdic)); |
28a35d8a HE |
569 | return 0; |
570 | } | |
571 | ||
fefa1800 | 572 | /* Force the FPGA to reboot. */ |
0e1357e8 BV |
573 | sigma_write(suicide, sizeof(suicide), devc); |
574 | sigma_write(suicide, sizeof(suicide), devc); | |
575 | sigma_write(suicide, sizeof(suicide), devc); | |
576 | sigma_write(suicide, sizeof(suicide), devc); | |
28a35d8a | 577 | |
fefa1800 | 578 | /* Prepare to upload firmware (FPGA specific). */ |
0e1357e8 | 579 | sigma_write(init, sizeof(init), devc); |
28a35d8a | 580 | |
0e1357e8 | 581 | ftdi_usb_purge_buffers(&devc->ftdic); |
28a35d8a | 582 | |
fefa1800 | 583 | /* Wait until the FPGA asserts INIT_B. */ |
28a35d8a | 584 | while (1) { |
0e1357e8 | 585 | ret = sigma_read(result, 1, devc); |
28a35d8a HE |
586 | if (result[0] & 0x20) |
587 | break; | |
588 | } | |
589 | ||
9ddb2a12 | 590 | /* Prepare firmware. */ |
e8397563 | 591 | snprintf(firmware_path, sizeof(firmware_path), "%s/%s", FIRMWARE_DIR, |
f6564c8d HE |
592 | firmware_files[firmware_idx]); |
593 | ||
b53738ba | 594 | if ((ret = bin2bitbang(firmware_path, &buf, &buf_size)) != SR_OK) { |
47f4f073 | 595 | sr_err("An error occured while reading the firmware: %s", |
133a37bf | 596 | firmware_path); |
b53738ba | 597 | return ret; |
28a35d8a HE |
598 | } |
599 | ||
fefa1800 | 600 | /* Upload firmare. */ |
47f4f073 | 601 | sr_info("Uploading firmware file '%s'.", firmware_files[firmware_idx]); |
0e1357e8 | 602 | sigma_write(buf, buf_size, devc); |
28a35d8a HE |
603 | |
604 | g_free(buf); | |
605 | ||
0e1357e8 | 606 | if ((ret = ftdi_set_bitmode(&devc->ftdic, 0x00, BITMODE_RESET)) < 0) { |
47f4f073 | 607 | sr_err("ftdi_set_bitmode failed: %s", |
0e1357e8 | 608 | ftdi_get_error_string(&devc->ftdic)); |
e46b8fb1 | 609 | return SR_ERR; |
28a35d8a HE |
610 | } |
611 | ||
0e1357e8 | 612 | ftdi_usb_purge_buffers(&devc->ftdic); |
28a35d8a | 613 | |
fefa1800 | 614 | /* Discard garbage. */ |
0e1357e8 | 615 | while (1 == sigma_read(&pins, 1, devc)) |
28a35d8a HE |
616 | ; |
617 | ||
fefa1800 | 618 | /* Initialize the logic analyzer mode. */ |
0e1357e8 | 619 | sigma_write(logic_mode_start, sizeof(logic_mode_start), devc); |
28a35d8a | 620 | |
fefa1800 | 621 | /* Expect a 3 byte reply. */ |
0e1357e8 | 622 | ret = sigma_read(result, 3, devc); |
28a35d8a HE |
623 | if (ret != 3 || |
624 | result[0] != 0xa6 || result[1] != 0x55 || result[2] != 0xaa) { | |
47f4f073 | 625 | sr_err("Configuration failed. Invalid reply received."); |
e46b8fb1 | 626 | return SR_ERR; |
28a35d8a HE |
627 | } |
628 | ||
0e1357e8 | 629 | devc->cur_firmware = firmware_idx; |
f6564c8d | 630 | |
47f4f073 | 631 | sr_info("Firmware uploaded."); |
e3fff420 | 632 | |
e46b8fb1 | 633 | return SR_OK; |
f6564c8d HE |
634 | } |
635 | ||
25a0f108 | 636 | static int hw_dev_open(struct sr_dev_inst *sdi) |
f6564c8d | 637 | { |
0e1357e8 | 638 | struct dev_context *devc; |
f6564c8d HE |
639 | int ret; |
640 | ||
0e1357e8 | 641 | devc = sdi->priv; |
99965709 | 642 | |
9ddb2a12 | 643 | /* Make sure it's an ASIX SIGMA. */ |
0e1357e8 | 644 | if ((ret = ftdi_usb_open_desc(&devc->ftdic, |
f6564c8d HE |
645 | USB_VENDOR, USB_PRODUCT, USB_DESCRIPTION, NULL)) < 0) { |
646 | ||
47f4f073 | 647 | sr_err("ftdi_usb_open failed: %s", |
0e1357e8 | 648 | ftdi_get_error_string(&devc->ftdic)); |
f6564c8d HE |
649 | |
650 | return 0; | |
651 | } | |
28a35d8a | 652 | |
5a2326a7 | 653 | sdi->status = SR_ST_ACTIVE; |
28a35d8a | 654 | |
e46b8fb1 | 655 | return SR_OK; |
f6564c8d HE |
656 | } |
657 | ||
6f4b1868 | 658 | static int set_samplerate(const struct sr_dev_inst *sdi, uint64_t samplerate) |
f6564c8d | 659 | { |
e8397563 | 660 | int i, ret; |
0e1357e8 | 661 | struct dev_context *devc = sdi->priv; |
f6564c8d HE |
662 | |
663 | for (i = 0; supported_samplerates[i]; i++) { | |
664 | if (supported_samplerates[i] == samplerate) | |
665 | break; | |
666 | } | |
667 | if (supported_samplerates[i] == 0) | |
e46b8fb1 | 668 | return SR_ERR_SAMPLERATE; |
f6564c8d | 669 | |
59df0c77 | 670 | if (samplerate <= SR_MHZ(50)) { |
0e1357e8 BV |
671 | ret = upload_firmware(0, devc); |
672 | devc->num_probes = 16; | |
e8397563 | 673 | } |
59df0c77 | 674 | if (samplerate == SR_MHZ(100)) { |
0e1357e8 BV |
675 | ret = upload_firmware(1, devc); |
676 | devc->num_probes = 8; | |
f78898e9 | 677 | } |
59df0c77 | 678 | else if (samplerate == SR_MHZ(200)) { |
0e1357e8 BV |
679 | ret = upload_firmware(2, devc); |
680 | devc->num_probes = 4; | |
f78898e9 | 681 | } |
f6564c8d | 682 | |
0e1357e8 BV |
683 | devc->cur_samplerate = samplerate; |
684 | devc->period_ps = 1000000000000 / samplerate; | |
685 | devc->samples_per_event = 16 / devc->num_probes; | |
686 | devc->state.state = SIGMA_IDLE; | |
f6564c8d | 687 | |
e8397563 | 688 | return ret; |
28a35d8a HE |
689 | } |
690 | ||
c53d793f HE |
691 | /* |
692 | * In 100 and 200 MHz mode, only a single pin rising/falling can be | |
693 | * set as trigger. In other modes, two rising/falling triggers can be set, | |
694 | * in addition to value/mask trigger for any number of probes. | |
695 | * | |
696 | * The Sigma supports complex triggers using boolean expressions, but this | |
697 | * has not been implemented yet. | |
698 | */ | |
014359e3 | 699 | static int configure_probes(const struct sr_dev_inst *sdi) |
57bbf56b | 700 | { |
0e1357e8 | 701 | struct dev_context *devc = sdi->priv; |
1b79df2f JH |
702 | const struct sr_probe *probe; |
703 | const GSList *l; | |
57bbf56b | 704 | int trigger_set = 0; |
a42aec7f | 705 | int probebit; |
57bbf56b | 706 | |
0e1357e8 | 707 | memset(&devc->trigger, 0, sizeof(struct sigma_trigger)); |
eec5275e | 708 | |
014359e3 | 709 | for (l = sdi->probes; l; l = l->next) { |
1afe8989 | 710 | probe = (struct sr_probe *)l->data; |
b35c8293 | 711 | probebit = 1 << (probe->index); |
57bbf56b HE |
712 | |
713 | if (!probe->enabled || !probe->trigger) | |
714 | continue; | |
715 | ||
0e1357e8 | 716 | if (devc->cur_samplerate >= SR_MHZ(100)) { |
c53d793f | 717 | /* Fast trigger support. */ |
ee492173 | 718 | if (trigger_set) { |
47f4f073 UH |
719 | sr_err("Only a single pin trigger in 100 and " |
720 | "200MHz mode is supported."); | |
e46b8fb1 | 721 | return SR_ERR; |
ee492173 HE |
722 | } |
723 | if (probe->trigger[0] == 'f') | |
0e1357e8 | 724 | devc->trigger.fallingmask |= probebit; |
ee492173 | 725 | else if (probe->trigger[0] == 'r') |
0e1357e8 | 726 | devc->trigger.risingmask |= probebit; |
ee492173 | 727 | else { |
47f4f073 UH |
728 | sr_err("Only rising/falling trigger in 100 " |
729 | "and 200MHz mode is supported."); | |
e46b8fb1 | 730 | return SR_ERR; |
ee492173 | 731 | } |
57bbf56b | 732 | |
c53d793f | 733 | ++trigger_set; |
ee492173 | 734 | } else { |
c53d793f HE |
735 | /* Simple trigger support (event). */ |
736 | if (probe->trigger[0] == '1') { | |
0e1357e8 BV |
737 | devc->trigger.simplevalue |= probebit; |
738 | devc->trigger.simplemask |= probebit; | |
c53d793f HE |
739 | } |
740 | else if (probe->trigger[0] == '0') { | |
0e1357e8 BV |
741 | devc->trigger.simplevalue &= ~probebit; |
742 | devc->trigger.simplemask |= probebit; | |
c53d793f HE |
743 | } |
744 | else if (probe->trigger[0] == 'f') { | |
0e1357e8 | 745 | devc->trigger.fallingmask |= probebit; |
c53d793f HE |
746 | ++trigger_set; |
747 | } | |
748 | else if (probe->trigger[0] == 'r') { | |
0e1357e8 | 749 | devc->trigger.risingmask |= probebit; |
c53d793f HE |
750 | ++trigger_set; |
751 | } | |
ee492173 | 752 | |
ea9cfed7 UH |
753 | /* |
754 | * Actually, Sigma supports 2 rising/falling triggers, | |
755 | * but they are ORed and the current trigger syntax | |
756 | * does not permit ORed triggers. | |
757 | */ | |
98b8cbc1 | 758 | if (trigger_set > 1) { |
47f4f073 UH |
759 | sr_err("Only 1 rising/falling trigger " |
760 | "is supported."); | |
e46b8fb1 | 761 | return SR_ERR; |
ee492173 | 762 | } |
ee492173 | 763 | } |
5b5ea7c6 HE |
764 | |
765 | if (trigger_set) | |
0e1357e8 | 766 | devc->use_triggers = 1; |
57bbf56b HE |
767 | } |
768 | ||
e46b8fb1 | 769 | return SR_OK; |
57bbf56b HE |
770 | } |
771 | ||
25a0f108 | 772 | static int hw_dev_close(struct sr_dev_inst *sdi) |
28a35d8a | 773 | { |
0e1357e8 | 774 | struct dev_context *devc; |
28a35d8a | 775 | |
0e1357e8 | 776 | if (!(devc = sdi->priv)) { |
47f4f073 | 777 | sr_err("%s: sdi->priv was NULL", __func__); |
0abee507 | 778 | return SR_ERR_BUG; |
9be9893e | 779 | } |
697785d1 UH |
780 | |
781 | /* TODO */ | |
782 | if (sdi->status == SR_ST_ACTIVE) | |
0e1357e8 | 783 | ftdi_usb_close(&devc->ftdic); |
697785d1 UH |
784 | |
785 | sdi->status = SR_ST_INACTIVE; | |
786 | ||
787 | return SR_OK; | |
28a35d8a HE |
788 | } |
789 | ||
57ab7d9f | 790 | static int hw_cleanup(void) |
28a35d8a | 791 | { |
b32503cc BV |
792 | if (!adi->priv) |
793 | return SR_OK; | |
794 | ||
0448d110 | 795 | clear_instances(); |
57ab7d9f | 796 | |
0448d110 | 797 | return SR_OK; |
28a35d8a HE |
798 | } |
799 | ||
41479605 | 800 | static int hw_info_get(int info_id, const void **data, |
47f4f073 | 801 | const struct sr_dev_inst *sdi) |
28a35d8a | 802 | { |
0e1357e8 | 803 | struct dev_context *devc; |
99965709 | 804 | |
41479605 | 805 | switch (info_id) { |
b2b5445c BV |
806 | case SR_DI_HWCAPS: |
807 | *data = hwcaps; | |
808 | break; | |
5a2326a7 | 809 | case SR_DI_NUM_PROBES: |
41479605 | 810 | *data = GINT_TO_POINTER(NUM_PROBES); |
464d12c7 KS |
811 | break; |
812 | case SR_DI_PROBE_NAMES: | |
41479605 | 813 | *data = probe_names; |
28a35d8a | 814 | break; |
5a2326a7 | 815 | case SR_DI_SAMPLERATES: |
41479605 | 816 | *data = &samplerates; |
28a35d8a | 817 | break; |
5a2326a7 | 818 | case SR_DI_TRIGGER_TYPES: |
41479605 | 819 | *data = (char *)TRIGGER_TYPES; |
28a35d8a | 820 | break; |
5a2326a7 | 821 | case SR_DI_CUR_SAMPLERATE: |
41479605 | 822 | if (sdi) { |
0e1357e8 BV |
823 | devc = sdi->priv; |
824 | *data = &devc->cur_samplerate; | |
41479605 BV |
825 | } else |
826 | return SR_ERR; | |
28a35d8a | 827 | break; |
d7bbecfd BV |
828 | default: |
829 | return SR_ERR_ARG; | |
28a35d8a HE |
830 | } |
831 | ||
41479605 | 832 | return SR_OK; |
28a35d8a HE |
833 | } |
834 | ||
6f4b1868 | 835 | static int hw_dev_config_set(const struct sr_dev_inst *sdi, int hwcap, |
47f4f073 | 836 | const void *value) |
28a35d8a | 837 | { |
0e1357e8 | 838 | struct dev_context *devc; |
28a35d8a | 839 | int ret; |
f6564c8d | 840 | |
0e1357e8 | 841 | devc = sdi->priv; |
99965709 | 842 | |
ffedd0bf | 843 | if (hwcap == SR_HWCAP_SAMPLERATE) { |
1b79df2f | 844 | ret = set_samplerate(sdi, *(const uint64_t *)value); |
ffedd0bf | 845 | } else if (hwcap == SR_HWCAP_LIMIT_MSEC) { |
0e1357e8 BV |
846 | devc->limit_msec = *(const uint64_t *)value; |
847 | if (devc->limit_msec > 0) | |
e46b8fb1 | 848 | ret = SR_OK; |
94ba4bd6 | 849 | else |
e46b8fb1 | 850 | ret = SR_ERR; |
ffedd0bf | 851 | } else if (hwcap == SR_HWCAP_CAPTURE_RATIO) { |
0e1357e8 BV |
852 | devc->capture_ratio = *(const uint64_t *)value; |
853 | if (devc->capture_ratio < 0 || devc->capture_ratio > 100) | |
e46b8fb1 | 854 | ret = SR_ERR; |
94ba4bd6 | 855 | else |
e46b8fb1 | 856 | ret = SR_OK; |
28a35d8a | 857 | } else { |
e46b8fb1 | 858 | ret = SR_ERR; |
28a35d8a HE |
859 | } |
860 | ||
861 | return ret; | |
862 | } | |
863 | ||
36b1c8e6 HE |
864 | /* Software trigger to determine exact trigger position. */ |
865 | static int get_trigger_offset(uint16_t *samples, uint16_t last_sample, | |
866 | struct sigma_trigger *t) | |
867 | { | |
868 | int i; | |
869 | ||
870 | for (i = 0; i < 8; ++i) { | |
871 | if (i > 0) | |
872 | last_sample = samples[i-1]; | |
873 | ||
874 | /* Simple triggers. */ | |
875 | if ((samples[i] & t->simplemask) != t->simplevalue) | |
876 | continue; | |
877 | ||
878 | /* Rising edge. */ | |
879 | if ((last_sample & t->risingmask) != 0 || (samples[i] & | |
880 | t->risingmask) != t->risingmask) | |
881 | continue; | |
882 | ||
883 | /* Falling edge. */ | |
bdfc7a89 HE |
884 | if ((last_sample & t->fallingmask) != t->fallingmask || |
885 | (samples[i] & t->fallingmask) != 0) | |
36b1c8e6 HE |
886 | continue; |
887 | ||
888 | break; | |
889 | } | |
890 | ||
891 | /* If we did not match, return original trigger pos. */ | |
892 | return i & 0x7; | |
893 | } | |
894 | ||
28a35d8a | 895 | /* |
fefa1800 UH |
896 | * Decode chunk of 1024 bytes, 64 clusters, 7 events per cluster. |
897 | * Each event is 20ns apart, and can contain multiple samples. | |
f78898e9 HE |
898 | * |
899 | * For 200 MHz, events contain 4 samples for each channel, spread 5 ns apart. | |
900 | * For 100 MHz, events contain 2 samples for each channel, spread 10 ns apart. | |
901 | * For 50 MHz and below, events contain one sample for each channel, | |
902 | * spread 20 ns apart. | |
28a35d8a HE |
903 | */ |
904 | static int decode_chunk_ts(uint8_t *buf, uint16_t *lastts, | |
88c51afe | 905 | uint16_t *lastsample, int triggerpos, |
3cd3a20b | 906 | uint16_t limit_chunk, void *cb_data) |
28a35d8a | 907 | { |
3cd3a20b | 908 | struct sr_dev_inst *sdi = cb_data; |
0e1357e8 | 909 | struct dev_context *devc = sdi->priv; |
fefa1800 | 910 | uint16_t tsdiff, ts; |
0e1357e8 | 911 | uint16_t samples[65536 * devc->samples_per_event]; |
b9c735a2 | 912 | struct sr_datafeed_packet packet; |
9c939c51 | 913 | struct sr_datafeed_logic logic; |
f78898e9 | 914 | int i, j, k, l, numpad, tosend; |
fefa1800 | 915 | size_t n = 0, sent = 0; |
0e1357e8 | 916 | int clustersize = EVENTS_PER_CLUSTER * devc->samples_per_event; |
fefa1800 | 917 | uint16_t *event; |
f78898e9 | 918 | uint16_t cur_sample; |
57bbf56b | 919 | int triggerts = -1; |
ee492173 | 920 | |
4ae1f451 | 921 | /* Check if trigger is in this chunk. */ |
ee492173 | 922 | if (triggerpos != -1) { |
0e1357e8 | 923 | if (devc->cur_samplerate <= SR_MHZ(50)) |
36b1c8e6 | 924 | triggerpos -= EVENTS_PER_CLUSTER - 1; |
ee492173 HE |
925 | |
926 | if (triggerpos < 0) | |
927 | triggerpos = 0; | |
57bbf56b | 928 | |
ee492173 HE |
929 | /* Find in which cluster the trigger occured. */ |
930 | triggerts = triggerpos / 7; | |
931 | } | |
28a35d8a | 932 | |
eec5275e | 933 | /* For each ts. */ |
28a35d8a | 934 | for (i = 0; i < 64; ++i) { |
fefa1800 | 935 | ts = *(uint16_t *) &buf[i * 16]; |
28a35d8a HE |
936 | tsdiff = ts - *lastts; |
937 | *lastts = ts; | |
938 | ||
88c51afe HE |
939 | /* Decode partial chunk. */ |
940 | if (limit_chunk && ts > limit_chunk) | |
e46b8fb1 | 941 | return SR_OK; |
88c51afe | 942 | |
fefa1800 | 943 | /* Pad last sample up to current point. */ |
0e1357e8 | 944 | numpad = tsdiff * devc->samples_per_event - clustersize; |
28a35d8a | 945 | if (numpad > 0) { |
f78898e9 HE |
946 | for (j = 0; j < numpad; ++j) |
947 | samples[j] = *lastsample; | |
948 | ||
949 | n = numpad; | |
28a35d8a HE |
950 | } |
951 | ||
57bbf56b HE |
952 | /* Send samples between previous and this timestamp to sigrok. */ |
953 | sent = 0; | |
954 | while (sent < n) { | |
955 | tosend = MIN(2048, n - sent); | |
956 | ||
5a2326a7 | 957 | packet.type = SR_DF_LOGIC; |
9c939c51 BV |
958 | packet.payload = &logic; |
959 | logic.length = tosend * sizeof(uint16_t); | |
960 | logic.unitsize = 2; | |
961 | logic.data = samples + sent; | |
0e1357e8 | 962 | sr_session_send(devc->session_dev_id, &packet); |
28a35d8a | 963 | |
57bbf56b HE |
964 | sent += tosend; |
965 | } | |
966 | n = 0; | |
967 | ||
968 | event = (uint16_t *) &buf[i * 16 + 2]; | |
f78898e9 HE |
969 | cur_sample = 0; |
970 | ||
971 | /* For each event in cluster. */ | |
28a35d8a | 972 | for (j = 0; j < 7; ++j) { |
f78898e9 HE |
973 | |
974 | /* For each sample in event. */ | |
0e1357e8 | 975 | for (k = 0; k < devc->samples_per_event; ++k) { |
f78898e9 HE |
976 | cur_sample = 0; |
977 | ||
978 | /* For each probe. */ | |
0e1357e8 | 979 | for (l = 0; l < devc->num_probes; ++l) |
edca2c5c | 980 | cur_sample |= (!!(event[j] & (1 << (l * |
0e1357e8 | 981 | devc->samples_per_event + k)))) << l; |
f78898e9 HE |
982 | |
983 | samples[n++] = cur_sample; | |
28a35d8a HE |
984 | } |
985 | } | |
986 | ||
eec5275e | 987 | /* Send data up to trigger point (if triggered). */ |
fefa1800 | 988 | sent = 0; |
57bbf56b HE |
989 | if (i == triggerts) { |
990 | /* | |
36b1c8e6 HE |
991 | * Trigger is not always accurate to sample because of |
992 | * pipeline delay. However, it always triggers before | |
993 | * the actual event. We therefore look at the next | |
994 | * samples to pinpoint the exact position of the trigger. | |
57bbf56b | 995 | */ |
bdfc7a89 | 996 | tosend = get_trigger_offset(samples, *lastsample, |
0e1357e8 | 997 | &devc->trigger); |
57bbf56b HE |
998 | |
999 | if (tosend > 0) { | |
5a2326a7 | 1000 | packet.type = SR_DF_LOGIC; |
9c939c51 BV |
1001 | packet.payload = &logic; |
1002 | logic.length = tosend * sizeof(uint16_t); | |
1003 | logic.unitsize = 2; | |
1004 | logic.data = samples; | |
0e1357e8 | 1005 | sr_session_send(devc->session_dev_id, &packet); |
57bbf56b HE |
1006 | |
1007 | sent += tosend; | |
1008 | } | |
28a35d8a | 1009 | |
5b5ea7c6 | 1010 | /* Only send trigger if explicitly enabled. */ |
0e1357e8 | 1011 | if (devc->use_triggers) { |
5a2326a7 | 1012 | packet.type = SR_DF_TRIGGER; |
0e1357e8 | 1013 | sr_session_send(devc->session_dev_id, &packet); |
5b5ea7c6 | 1014 | } |
28a35d8a | 1015 | } |
57bbf56b | 1016 | |
eec5275e | 1017 | /* Send rest of the chunk to sigrok. */ |
57bbf56b HE |
1018 | tosend = n - sent; |
1019 | ||
abda62ce | 1020 | if (tosend > 0) { |
5a2326a7 | 1021 | packet.type = SR_DF_LOGIC; |
9c939c51 BV |
1022 | packet.payload = &logic; |
1023 | logic.length = tosend * sizeof(uint16_t); | |
1024 | logic.unitsize = 2; | |
1025 | logic.data = samples + sent; | |
0e1357e8 | 1026 | sr_session_send(devc->session_dev_id, &packet); |
abda62ce | 1027 | } |
ee492173 HE |
1028 | |
1029 | *lastsample = samples[n - 1]; | |
28a35d8a HE |
1030 | } |
1031 | ||
e46b8fb1 | 1032 | return SR_OK; |
28a35d8a HE |
1033 | } |
1034 | ||
1f9813eb | 1035 | static int receive_data(int fd, int revents, void *cb_data) |
28a35d8a | 1036 | { |
1f9813eb | 1037 | struct sr_dev_inst *sdi = cb_data; |
0e1357e8 | 1038 | struct dev_context *devc = sdi->priv; |
b9c735a2 | 1039 | struct sr_datafeed_packet packet; |
28a35d8a HE |
1040 | const int chunks_per_read = 32; |
1041 | unsigned char buf[chunks_per_read * CHUNK_SIZE]; | |
6aac7737 | 1042 | int bufsz, numchunks, i, newchunks; |
94ba4bd6 | 1043 | uint64_t running_msec; |
28a35d8a | 1044 | struct timeval tv; |
28a35d8a | 1045 | |
cb93f8a9 UH |
1046 | (void)fd; |
1047 | (void)revents; | |
28a35d8a | 1048 | |
805919b0 | 1049 | /* Get the current position. */ |
0e1357e8 | 1050 | sigma_read_pos(&devc->state.stoppos, &devc->state.triggerpos, devc); |
805919b0 | 1051 | |
0e1357e8 | 1052 | numchunks = (devc->state.stoppos + 511) / 512; |
28a35d8a | 1053 | |
0e1357e8 | 1054 | if (devc->state.state == SIGMA_IDLE) |
805919b0 | 1055 | return TRUE; |
28a35d8a | 1056 | |
0e1357e8 | 1057 | if (devc->state.state == SIGMA_CAPTURE) { |
6aac7737 HE |
1058 | /* Check if the timer has expired, or memory is full. */ |
1059 | gettimeofday(&tv, 0); | |
0e1357e8 BV |
1060 | running_msec = (tv.tv_sec - devc->start_tv.tv_sec) * 1000 + |
1061 | (tv.tv_usec - devc->start_tv.tv_usec) / 1000; | |
28a35d8a | 1062 | |
0e1357e8 | 1063 | if (running_msec < devc->limit_msec && numchunks < 32767) |
805919b0 | 1064 | return TRUE; /* While capturing... */ |
e3fff420 | 1065 | else |
3ffb6964 | 1066 | hw_dev_acquisition_stop(sdi, sdi); |
6aac7737 | 1067 | |
0e1357e8 BV |
1068 | } else if (devc->state.state == SIGMA_DOWNLOAD) { |
1069 | if (devc->state.chunks_downloaded >= numchunks) { | |
6aac7737 | 1070 | /* End of samples. */ |
5a2326a7 | 1071 | packet.type = SR_DF_END; |
0e1357e8 | 1072 | sr_session_send(devc->session_dev_id, &packet); |
6aac7737 | 1073 | |
0e1357e8 | 1074 | devc->state.state = SIGMA_IDLE; |
f78898e9 | 1075 | |
6aac7737 HE |
1076 | return TRUE; |
1077 | } | |
1078 | ||
1079 | newchunks = MIN(chunks_per_read, | |
0e1357e8 | 1080 | numchunks - devc->state.chunks_downloaded); |
28a35d8a | 1081 | |
47f4f073 | 1082 | sr_info("Downloading sample data: %.0f %%.", |
0e1357e8 | 1083 | 100.0 * devc->state.chunks_downloaded / numchunks); |
28a35d8a | 1084 | |
0e1357e8 BV |
1085 | bufsz = sigma_read_dram(devc->state.chunks_downloaded, |
1086 | newchunks, buf, devc); | |
719c5a93 UH |
1087 | /* TODO: Check bufsz. For now, just avoid compiler warnings. */ |
1088 | (void)bufsz; | |
28a35d8a | 1089 | |
fefa1800 | 1090 | /* Find first ts. */ |
0e1357e8 BV |
1091 | if (devc->state.chunks_downloaded == 0) { |
1092 | devc->state.lastts = *(uint16_t *) buf - 1; | |
1093 | devc->state.lastsample = 0; | |
6aac7737 | 1094 | } |
28a35d8a | 1095 | |
fefa1800 | 1096 | /* Decode chunks and send them to sigrok. */ |
28a35d8a | 1097 | for (i = 0; i < newchunks; ++i) { |
88c51afe HE |
1098 | int limit_chunk = 0; |
1099 | ||
1100 | /* The last chunk may potentially be only in part. */ | |
0e1357e8 | 1101 | if (devc->state.chunks_downloaded == numchunks - 1) { |
88c51afe | 1102 | /* Find the last valid timestamp */ |
0e1357e8 | 1103 | limit_chunk = devc->state.stoppos % 512 + devc->state.lastts; |
88c51afe HE |
1104 | } |
1105 | ||
0e1357e8 | 1106 | if (devc->state.chunks_downloaded + i == devc->state.triggerchunk) |
57bbf56b | 1107 | decode_chunk_ts(buf + (i * CHUNK_SIZE), |
0e1357e8 BV |
1108 | &devc->state.lastts, |
1109 | &devc->state.lastsample, | |
1110 | devc->state.triggerpos & 0x1ff, | |
1f9813eb | 1111 | limit_chunk, sdi); |
57bbf56b HE |
1112 | else |
1113 | decode_chunk_ts(buf + (i * CHUNK_SIZE), | |
0e1357e8 BV |
1114 | &devc->state.lastts, |
1115 | &devc->state.lastsample, | |
1f9813eb | 1116 | -1, limit_chunk, sdi); |
28a35d8a | 1117 | |
0e1357e8 | 1118 | ++devc->state.chunks_downloaded; |
88c51afe | 1119 | } |
28a35d8a HE |
1120 | } |
1121 | ||
28a35d8a HE |
1122 | return TRUE; |
1123 | } | |
1124 | ||
c53d793f HE |
1125 | /* Build a LUT entry used by the trigger functions. */ |
1126 | static void build_lut_entry(uint16_t value, uint16_t mask, uint16_t *entry) | |
ee492173 HE |
1127 | { |
1128 | int i, j, k, bit; | |
1129 | ||
f758d074 | 1130 | /* For each quad probe. */ |
ee492173 | 1131 | for (i = 0; i < 4; ++i) { |
c53d793f | 1132 | entry[i] = 0xffff; |
ee492173 | 1133 | |
f758d074 | 1134 | /* For each bit in LUT. */ |
ee492173 HE |
1135 | for (j = 0; j < 16; ++j) |
1136 | ||
f758d074 | 1137 | /* For each probe in quad. */ |
ee492173 HE |
1138 | for (k = 0; k < 4; ++k) { |
1139 | bit = 1 << (i * 4 + k); | |
1140 | ||
c53d793f HE |
1141 | /* Set bit in entry */ |
1142 | if ((mask & bit) && | |
1143 | ((!(value & bit)) != | |
4ae1f451 | 1144 | (!(j & (1 << k))))) |
c53d793f | 1145 | entry[i] &= ~(1 << j); |
ee492173 HE |
1146 | } |
1147 | } | |
c53d793f | 1148 | } |
ee492173 | 1149 | |
c53d793f HE |
1150 | /* Add a logical function to LUT mask. */ |
1151 | static void add_trigger_function(enum triggerop oper, enum triggerfunc func, | |
1152 | int index, int neg, uint16_t *mask) | |
1153 | { | |
1154 | int i, j; | |
1155 | int x[2][2], tmp, a, b, aset, bset, rset; | |
1156 | ||
1157 | memset(x, 0, 4 * sizeof(int)); | |
1158 | ||
1159 | /* Trigger detect condition. */ | |
1160 | switch (oper) { | |
1161 | case OP_LEVEL: | |
1162 | x[0][1] = 1; | |
1163 | x[1][1] = 1; | |
1164 | break; | |
1165 | case OP_NOT: | |
1166 | x[0][0] = 1; | |
1167 | x[1][0] = 1; | |
1168 | break; | |
1169 | case OP_RISE: | |
1170 | x[0][1] = 1; | |
1171 | break; | |
1172 | case OP_FALL: | |
1173 | x[1][0] = 1; | |
1174 | break; | |
1175 | case OP_RISEFALL: | |
1176 | x[0][1] = 1; | |
1177 | x[1][0] = 1; | |
1178 | break; | |
1179 | case OP_NOTRISE: | |
1180 | x[1][1] = 1; | |
1181 | x[0][0] = 1; | |
1182 | x[1][0] = 1; | |
1183 | break; | |
1184 | case OP_NOTFALL: | |
1185 | x[1][1] = 1; | |
1186 | x[0][0] = 1; | |
1187 | x[0][1] = 1; | |
1188 | break; | |
1189 | case OP_NOTRISEFALL: | |
1190 | x[1][1] = 1; | |
1191 | x[0][0] = 1; | |
1192 | break; | |
1193 | } | |
1194 | ||
1195 | /* Transpose if neg is set. */ | |
1196 | if (neg) { | |
ea9cfed7 | 1197 | for (i = 0; i < 2; ++i) { |
c53d793f HE |
1198 | for (j = 0; j < 2; ++j) { |
1199 | tmp = x[i][j]; | |
1200 | x[i][j] = x[1-i][1-j]; | |
1201 | x[1-i][1-j] = tmp; | |
1202 | } | |
ea9cfed7 | 1203 | } |
c53d793f HE |
1204 | } |
1205 | ||
1206 | /* Update mask with function. */ | |
1207 | for (i = 0; i < 16; ++i) { | |
1208 | a = (i >> (2 * index + 0)) & 1; | |
1209 | b = (i >> (2 * index + 1)) & 1; | |
1210 | ||
1211 | aset = (*mask >> i) & 1; | |
1212 | bset = x[b][a]; | |
1213 | ||
1214 | if (func == FUNC_AND || func == FUNC_NAND) | |
1215 | rset = aset & bset; | |
1216 | else if (func == FUNC_OR || func == FUNC_NOR) | |
1217 | rset = aset | bset; | |
1218 | else if (func == FUNC_XOR || func == FUNC_NXOR) | |
1219 | rset = aset ^ bset; | |
1220 | ||
1221 | if (func == FUNC_NAND || func == FUNC_NOR || func == FUNC_NXOR) | |
1222 | rset = !rset; | |
1223 | ||
1224 | *mask &= ~(1 << i); | |
1225 | ||
1226 | if (rset) | |
1227 | *mask |= 1 << i; | |
1228 | } | |
1229 | } | |
1230 | ||
1231 | /* | |
1232 | * Build trigger LUTs used by 50 MHz and lower sample rates for supporting | |
1233 | * simple pin change and state triggers. Only two transitions (rise/fall) can be | |
1234 | * set at any time, but a full mask and value can be set (0/1). | |
1235 | */ | |
0e1357e8 | 1236 | static int build_basic_trigger(struct triggerlut *lut, struct dev_context *devc) |
c53d793f HE |
1237 | { |
1238 | int i,j; | |
4ae1f451 | 1239 | uint16_t masks[2] = { 0, 0 }; |
c53d793f HE |
1240 | |
1241 | memset(lut, 0, sizeof(struct triggerlut)); | |
1242 | ||
1243 | /* Contant for simple triggers. */ | |
1244 | lut->m4 = 0xa000; | |
1245 | ||
1246 | /* Value/mask trigger support. */ | |
0e1357e8 | 1247 | build_lut_entry(devc->trigger.simplevalue, devc->trigger.simplemask, |
99965709 | 1248 | lut->m2d); |
c53d793f HE |
1249 | |
1250 | /* Rise/fall trigger support. */ | |
1251 | for (i = 0, j = 0; i < 16; ++i) { | |
0e1357e8 BV |
1252 | if (devc->trigger.risingmask & (1 << i) || |
1253 | devc->trigger.fallingmask & (1 << i)) | |
c53d793f HE |
1254 | masks[j++] = 1 << i; |
1255 | } | |
1256 | ||
1257 | build_lut_entry(masks[0], masks[0], lut->m0d); | |
1258 | build_lut_entry(masks[1], masks[1], lut->m1d); | |
1259 | ||
1260 | /* Add glue logic */ | |
1261 | if (masks[0] || masks[1]) { | |
1262 | /* Transition trigger. */ | |
0e1357e8 | 1263 | if (masks[0] & devc->trigger.risingmask) |
c53d793f | 1264 | add_trigger_function(OP_RISE, FUNC_OR, 0, 0, &lut->m3); |
0e1357e8 | 1265 | if (masks[0] & devc->trigger.fallingmask) |
c53d793f | 1266 | add_trigger_function(OP_FALL, FUNC_OR, 0, 0, &lut->m3); |
0e1357e8 | 1267 | if (masks[1] & devc->trigger.risingmask) |
c53d793f | 1268 | add_trigger_function(OP_RISE, FUNC_OR, 1, 0, &lut->m3); |
0e1357e8 | 1269 | if (masks[1] & devc->trigger.fallingmask) |
c53d793f HE |
1270 | add_trigger_function(OP_FALL, FUNC_OR, 1, 0, &lut->m3); |
1271 | } else { | |
1272 | /* Only value/mask trigger. */ | |
1273 | lut->m3 = 0xffff; | |
1274 | } | |
ee492173 | 1275 | |
c53d793f | 1276 | /* Triggertype: event. */ |
ee492173 HE |
1277 | lut->params.selres = 3; |
1278 | ||
e46b8fb1 | 1279 | return SR_OK; |
ee492173 HE |
1280 | } |
1281 | ||
3ffb6964 BV |
1282 | static int hw_dev_acquisition_start(const struct sr_dev_inst *sdi, |
1283 | void *cb_data) | |
28a35d8a | 1284 | { |
0e1357e8 | 1285 | struct dev_context *devc; |
3c36c403 HE |
1286 | struct sr_datafeed_packet *packet; |
1287 | struct sr_datafeed_header *header; | |
f366e86c | 1288 | struct sr_datafeed_meta_logic meta; |
9ddb2a12 | 1289 | struct clockselect_50 clockselect; |
82957b65 | 1290 | int frac, triggerpin, ret; |
57bbf56b HE |
1291 | uint8_t triggerselect; |
1292 | struct triggerinout triggerinout_conf; | |
ee492173 | 1293 | struct triggerlut lut; |
28a35d8a | 1294 | |
0e1357e8 | 1295 | devc = sdi->priv; |
28a35d8a | 1296 | |
014359e3 | 1297 | if (configure_probes(sdi) != SR_OK) { |
47f4f073 | 1298 | sr_err("Failed to configure probes."); |
014359e3 BV |
1299 | return SR_ERR; |
1300 | } | |
1301 | ||
ea9cfed7 | 1302 | /* If the samplerate has not been set, default to 200 kHz. */ |
0e1357e8 | 1303 | if (devc->cur_firmware == -1) { |
82957b65 UH |
1304 | if ((ret = set_samplerate(sdi, SR_KHZ(200))) != SR_OK) |
1305 | return ret; | |
1306 | } | |
e8397563 | 1307 | |
eec5275e | 1308 | /* Enter trigger programming mode. */ |
0e1357e8 | 1309 | sigma_set_register(WRITE_TRIGGER_SELECT1, 0x20, devc); |
28a35d8a | 1310 | |
eec5275e | 1311 | /* 100 and 200 MHz mode. */ |
0e1357e8 BV |
1312 | if (devc->cur_samplerate >= SR_MHZ(100)) { |
1313 | sigma_set_register(WRITE_TRIGGER_SELECT1, 0x81, devc); | |
57bbf56b | 1314 | |
a42aec7f HE |
1315 | /* Find which pin to trigger on from mask. */ |
1316 | for (triggerpin = 0; triggerpin < 8; ++triggerpin) | |
0e1357e8 | 1317 | if ((devc->trigger.risingmask | devc->trigger.fallingmask) & |
a42aec7f HE |
1318 | (1 << triggerpin)) |
1319 | break; | |
1320 | ||
1321 | /* Set trigger pin and light LED on trigger. */ | |
1322 | triggerselect = (1 << LEDSEL1) | (triggerpin & 0x7); | |
1323 | ||
1324 | /* Default rising edge. */ | |
0e1357e8 | 1325 | if (devc->trigger.fallingmask) |
a42aec7f | 1326 | triggerselect |= 1 << 3; |
57bbf56b | 1327 | |
eec5275e | 1328 | /* All other modes. */ |
0e1357e8 BV |
1329 | } else if (devc->cur_samplerate <= SR_MHZ(50)) { |
1330 | build_basic_trigger(&lut, devc); | |
ee492173 | 1331 | |
0e1357e8 | 1332 | sigma_write_trigger_lut(&lut, devc); |
57bbf56b HE |
1333 | |
1334 | triggerselect = (1 << LEDSEL1) | (1 << LEDSEL0); | |
1335 | } | |
1336 | ||
eec5275e | 1337 | /* Setup trigger in and out pins to default values. */ |
57bbf56b HE |
1338 | memset(&triggerinout_conf, 0, sizeof(struct triggerinout)); |
1339 | triggerinout_conf.trgout_bytrigger = 1; | |
1340 | triggerinout_conf.trgout_enable = 1; | |
1341 | ||
28a35d8a | 1342 | sigma_write_register(WRITE_TRIGGER_OPTION, |
57bbf56b | 1343 | (uint8_t *) &triggerinout_conf, |
0e1357e8 | 1344 | sizeof(struct triggerinout), devc); |
28a35d8a | 1345 | |
eec5275e | 1346 | /* Go back to normal mode. */ |
0e1357e8 | 1347 | sigma_set_register(WRITE_TRIGGER_SELECT1, triggerselect, devc); |
28a35d8a | 1348 | |
edca2c5c | 1349 | /* Set clock select register. */ |
0e1357e8 | 1350 | if (devc->cur_samplerate == SR_MHZ(200)) |
edca2c5c | 1351 | /* Enable 4 probes. */ |
0e1357e8 BV |
1352 | sigma_set_register(WRITE_CLOCK_SELECT, 0xf0, devc); |
1353 | else if (devc->cur_samplerate == SR_MHZ(100)) | |
edca2c5c | 1354 | /* Enable 8 probes. */ |
0e1357e8 | 1355 | sigma_set_register(WRITE_CLOCK_SELECT, 0x00, devc); |
edca2c5c HE |
1356 | else { |
1357 | /* | |
9ddb2a12 | 1358 | * 50 MHz mode (or fraction thereof). Any fraction down to |
eec5275e | 1359 | * 50 MHz / 256 can be used, but is not supported by sigrok API. |
edca2c5c | 1360 | */ |
0e1357e8 | 1361 | frac = SR_MHZ(50) / devc->cur_samplerate - 1; |
edca2c5c | 1362 | |
9ddb2a12 UH |
1363 | clockselect.async = 0; |
1364 | clockselect.fraction = frac; | |
1365 | clockselect.disabled_probes = 0; | |
edca2c5c HE |
1366 | |
1367 | sigma_write_register(WRITE_CLOCK_SELECT, | |
9ddb2a12 | 1368 | (uint8_t *) &clockselect, |
0e1357e8 | 1369 | sizeof(clockselect), devc); |
edca2c5c HE |
1370 | } |
1371 | ||
fefa1800 | 1372 | /* Setup maximum post trigger time. */ |
99965709 | 1373 | sigma_set_register(WRITE_POST_TRIGGER, |
0e1357e8 | 1374 | (devc->capture_ratio * 255) / 100, devc); |
28a35d8a | 1375 | |
eec5275e | 1376 | /* Start acqusition. */ |
0e1357e8 BV |
1377 | gettimeofday(&devc->start_tv, 0); |
1378 | sigma_set_register(WRITE_MODE, 0x0d, devc); | |
99965709 | 1379 | |
0e1357e8 | 1380 | devc->session_dev_id = cb_data; |
28a35d8a | 1381 | |
3c36c403 | 1382 | if (!(packet = g_try_malloc(sizeof(struct sr_datafeed_packet)))) { |
47f4f073 | 1383 | sr_err("%s: packet malloc failed.", __func__); |
3c36c403 HE |
1384 | return SR_ERR_MALLOC; |
1385 | } | |
1386 | ||
1387 | if (!(header = g_try_malloc(sizeof(struct sr_datafeed_header)))) { | |
47f4f073 | 1388 | sr_err("%s: header malloc failed.", __func__); |
3c36c403 HE |
1389 | return SR_ERR_MALLOC; |
1390 | } | |
28a35d8a | 1391 | |
3c36c403 HE |
1392 | /* Send header packet to the session bus. */ |
1393 | packet->type = SR_DF_HEADER; | |
1394 | packet->payload = header; | |
1395 | header->feed_version = 1; | |
1396 | gettimeofday(&header->starttime, NULL); | |
0e1357e8 | 1397 | sr_session_send(devc->session_dev_id, packet); |
f366e86c BV |
1398 | |
1399 | /* Send metadata about the SR_DF_LOGIC packets to come. */ | |
1400 | packet->type = SR_DF_META_LOGIC; | |
1401 | packet->payload = &meta; | |
0e1357e8 BV |
1402 | meta.samplerate = devc->cur_samplerate; |
1403 | meta.num_probes = devc->num_probes; | |
1404 | sr_session_send(devc->session_dev_id, packet); | |
f366e86c BV |
1405 | |
1406 | /* Add capture source. */ | |
3ffb6964 | 1407 | sr_source_add(0, G_IO_IN, 10, receive_data, (void *)sdi); |
f366e86c | 1408 | |
3c36c403 HE |
1409 | g_free(header); |
1410 | g_free(packet); | |
1411 | ||
0e1357e8 | 1412 | devc->state.state = SIGMA_CAPTURE; |
6aac7737 | 1413 | |
e46b8fb1 | 1414 | return SR_OK; |
28a35d8a HE |
1415 | } |
1416 | ||
69b07d14 | 1417 | static int hw_dev_acquisition_stop(struct sr_dev_inst *sdi, void *cb_data) |
28a35d8a | 1418 | { |
0e1357e8 | 1419 | struct dev_context *devc; |
6aac7737 HE |
1420 | uint8_t modestatus; |
1421 | ||
cb93f8a9 | 1422 | /* Avoid compiler warnings. */ |
3cd3a20b | 1423 | (void)cb_data; |
28a35d8a | 1424 | |
503c4afb BV |
1425 | sr_source_remove(0); |
1426 | ||
0e1357e8 | 1427 | if (!(devc = sdi->priv)) { |
47f4f073 | 1428 | sr_err("%s: sdi->priv was NULL", __func__); |
3010f21c UH |
1429 | return SR_ERR_BUG; |
1430 | } | |
1431 | ||
fefa1800 | 1432 | /* Stop acquisition. */ |
0e1357e8 | 1433 | sigma_set_register(WRITE_MODE, 0x11, devc); |
28a35d8a | 1434 | |
6aac7737 | 1435 | /* Set SDRAM Read Enable. */ |
0e1357e8 | 1436 | sigma_set_register(WRITE_MODE, 0x02, devc); |
6aac7737 HE |
1437 | |
1438 | /* Get the current position. */ | |
0e1357e8 | 1439 | sigma_read_pos(&devc->state.stoppos, &devc->state.triggerpos, devc); |
6aac7737 HE |
1440 | |
1441 | /* Check if trigger has fired. */ | |
0e1357e8 | 1442 | modestatus = sigma_get_register(READ_MODE, devc); |
3010f21c | 1443 | if (modestatus & 0x20) |
0e1357e8 | 1444 | devc->state.triggerchunk = devc->state.triggerpos / 512; |
3010f21c | 1445 | else |
0e1357e8 | 1446 | devc->state.triggerchunk = -1; |
6aac7737 | 1447 | |
0e1357e8 | 1448 | devc->state.chunks_downloaded = 0; |
6aac7737 | 1449 | |
0e1357e8 | 1450 | devc->state.state = SIGMA_DOWNLOAD; |
3010f21c UH |
1451 | |
1452 | return SR_OK; | |
28a35d8a HE |
1453 | } |
1454 | ||
c09f0b57 | 1455 | SR_PRIV struct sr_dev_driver asix_sigma_driver_info = { |
e519ba86 | 1456 | .name = "asix-sigma", |
6352d030 | 1457 | .longname = "ASIX SIGMA/SIGMA2", |
e519ba86 UH |
1458 | .api_version = 1, |
1459 | .init = hw_init, | |
1460 | .cleanup = hw_cleanup, | |
61136ea6 | 1461 | .scan = hw_scan, |
811deee4 BV |
1462 | .dev_list = hw_dev_list, |
1463 | .dev_clear = clear_instances, | |
e7eb703f UH |
1464 | .dev_open = hw_dev_open, |
1465 | .dev_close = hw_dev_close, | |
41479605 | 1466 | .info_get = hw_info_get, |
a9a245b4 | 1467 | .dev_config_set = hw_dev_config_set, |
6b3dfec8 UH |
1468 | .dev_acquisition_start = hw_dev_acquisition_start, |
1469 | .dev_acquisition_stop = hw_dev_acquisition_stop, | |
0e1357e8 | 1470 | .priv = NULL, |
28a35d8a | 1471 | }; |