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Commit | Line | Data |
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28a35d8a HE |
1 | /* |
2 | * This file is part of the sigrok project. | |
3 | * | |
868501fa | 4 | * Copyright (C) 2010-2012 Håvard Espeland <gus@ping.uio.no>, |
911f1834 UH |
5 | * Copyright (C) 2010 Martin Stensgård <mastensg@ping.uio.no> |
6 | * Copyright (C) 2010 Carl Henrik Lunde <chlunde@ping.uio.no> | |
28a35d8a HE |
7 | * |
8 | * This program is free software: you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation, either version 3 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
20 | */ | |
21 | ||
911f1834 | 22 | /* |
6352d030 | 23 | * ASIX SIGMA/SIGMA2 logic analyzer driver |
911f1834 UH |
24 | */ |
25 | ||
3bbd9849 UH |
26 | #include <glib.h> |
27 | #include <glib/gstdio.h> | |
28a35d8a HE |
28 | #include <ftdi.h> |
29 | #include <string.h> | |
45c59c8b BV |
30 | #include "libsigrok.h" |
31 | #include "libsigrok-internal.h" | |
28a35d8a HE |
32 | #include "asix-sigma.h" |
33 | ||
34 | #define USB_VENDOR 0xa600 | |
35 | #define USB_PRODUCT 0xa000 | |
36 | #define USB_DESCRIPTION "ASIX SIGMA" | |
37 | #define USB_VENDOR_NAME "ASIX" | |
38 | #define USB_MODEL_NAME "SIGMA" | |
39 | #define USB_MODEL_VERSION "" | |
ee492173 | 40 | #define TRIGGER_TYPES "rf10" |
464d12c7 | 41 | #define NUM_PROBES 16 |
28a35d8a | 42 | |
ed300b9f | 43 | SR_PRIV struct sr_dev_driver asix_sigma_driver_info; |
a873c594 | 44 | static struct sr_dev_driver *di = &asix_sigma_driver_info; |
69b07d14 | 45 | static int hw_dev_acquisition_stop(struct sr_dev_inst *sdi, void *cb_data); |
28a35d8a | 46 | |
a533743d | 47 | static const uint64_t supported_samplerates[] = { |
59df0c77 UH |
48 | SR_KHZ(200), |
49 | SR_KHZ(250), | |
50 | SR_KHZ(500), | |
51 | SR_MHZ(1), | |
52 | SR_MHZ(5), | |
53 | SR_MHZ(10), | |
54 | SR_MHZ(25), | |
55 | SR_MHZ(50), | |
56 | SR_MHZ(100), | |
57 | SR_MHZ(200), | |
28a35d8a HE |
58 | 0, |
59 | }; | |
60 | ||
d261dbbf UH |
61 | /* |
62 | * Probe numbers seem to go from 1-16, according to this image: | |
63 | * http://tools.asix.net/img/sigma_sigmacab_pins_720.jpg | |
64 | * (the cable has two additional GND pins, and a TI and TO pin) | |
65 | */ | |
c37d2b1b | 66 | static const char *probe_names[NUM_PROBES + 1] = { |
78693401 UH |
67 | "1", "2", "3", "4", "5", "6", "7", "8", |
68 | "9", "10", "11", "12", "13", "14", "15", "16", | |
464d12c7 KS |
69 | NULL, |
70 | }; | |
71 | ||
a533743d | 72 | static const struct sr_samplerates samplerates = { |
590b9f9a UH |
73 | 0, |
74 | 0, | |
75 | 0, | |
28a35d8a HE |
76 | supported_samplerates, |
77 | }; | |
78 | ||
915f7cc8 | 79 | static const int hwcaps[] = { |
5a2326a7 UH |
80 | SR_HWCAP_LOGIC_ANALYZER, |
81 | SR_HWCAP_SAMPLERATE, | |
82 | SR_HWCAP_CAPTURE_RATIO, | |
28a35d8a | 83 | |
5a2326a7 | 84 | SR_HWCAP_LIMIT_MSEC, |
28a35d8a HE |
85 | 0, |
86 | }; | |
87 | ||
fefa1800 UH |
88 | /* Force the FPGA to reboot. */ |
89 | static uint8_t suicide[] = { | |
90 | 0x84, 0x84, 0x88, 0x84, 0x88, 0x84, 0x88, 0x84, | |
91 | }; | |
92 | ||
93 | /* Prepare to upload firmware (FPGA specific). */ | |
94 | static uint8_t init[] = { | |
95 | 0x03, 0x03, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, | |
96 | }; | |
97 | ||
98 | /* Initialize the logic analyzer mode. */ | |
99 | static uint8_t logic_mode_start[] = { | |
100 | 0x00, 0x40, 0x0f, 0x25, 0x35, 0x40, | |
101 | 0x2a, 0x3a, 0x40, 0x03, 0x20, 0x38, | |
102 | }; | |
103 | ||
eec5275e | 104 | static const char *firmware_files[] = { |
a8116d76 HE |
105 | "asix-sigma-50.fw", /* 50 MHz, supports 8 bit fractions */ |
106 | "asix-sigma-100.fw", /* 100 MHz */ | |
107 | "asix-sigma-200.fw", /* 200 MHz */ | |
ed09fd07 | 108 | "asix-sigma-50sync.fw", /* Synchronous clock from pin */ |
a8116d76 | 109 | "asix-sigma-phasor.fw", /* Frequency counter */ |
f6564c8d HE |
110 | }; |
111 | ||
0e1357e8 | 112 | static int sigma_read(void *buf, size_t size, struct dev_context *devc) |
28a35d8a HE |
113 | { |
114 | int ret; | |
fefa1800 | 115 | |
0e1357e8 | 116 | ret = ftdi_read_data(&devc->ftdic, (unsigned char *)buf, size); |
28a35d8a | 117 | if (ret < 0) { |
47f4f073 | 118 | sr_err("ftdi_read_data failed: %s", |
0e1357e8 | 119 | ftdi_get_error_string(&devc->ftdic)); |
28a35d8a HE |
120 | } |
121 | ||
122 | return ret; | |
123 | } | |
124 | ||
0e1357e8 | 125 | static int sigma_write(void *buf, size_t size, struct dev_context *devc) |
28a35d8a HE |
126 | { |
127 | int ret; | |
fefa1800 | 128 | |
0e1357e8 | 129 | ret = ftdi_write_data(&devc->ftdic, (unsigned char *)buf, size); |
28a35d8a | 130 | if (ret < 0) { |
47f4f073 | 131 | sr_err("ftdi_write_data failed: %s", |
0e1357e8 | 132 | ftdi_get_error_string(&devc->ftdic)); |
fefa1800 | 133 | } else if ((size_t) ret != size) { |
47f4f073 | 134 | sr_err("ftdi_write_data did not complete write."); |
28a35d8a HE |
135 | } |
136 | ||
137 | return ret; | |
138 | } | |
139 | ||
99965709 | 140 | static int sigma_write_register(uint8_t reg, uint8_t *data, size_t len, |
0e1357e8 | 141 | struct dev_context *devc) |
28a35d8a HE |
142 | { |
143 | size_t i; | |
144 | uint8_t buf[len + 2]; | |
145 | int idx = 0; | |
146 | ||
147 | buf[idx++] = REG_ADDR_LOW | (reg & 0xf); | |
148 | buf[idx++] = REG_ADDR_HIGH | (reg >> 4); | |
149 | ||
fefa1800 | 150 | for (i = 0; i < len; ++i) { |
28a35d8a HE |
151 | buf[idx++] = REG_DATA_LOW | (data[i] & 0xf); |
152 | buf[idx++] = REG_DATA_HIGH_WRITE | (data[i] >> 4); | |
153 | } | |
154 | ||
0e1357e8 | 155 | return sigma_write(buf, idx, devc); |
28a35d8a HE |
156 | } |
157 | ||
0e1357e8 | 158 | static int sigma_set_register(uint8_t reg, uint8_t value, struct dev_context *devc) |
28a35d8a | 159 | { |
0e1357e8 | 160 | return sigma_write_register(reg, &value, 1, devc); |
28a35d8a HE |
161 | } |
162 | ||
99965709 | 163 | static int sigma_read_register(uint8_t reg, uint8_t *data, size_t len, |
0e1357e8 | 164 | struct dev_context *devc) |
28a35d8a HE |
165 | { |
166 | uint8_t buf[3]; | |
fefa1800 | 167 | |
28a35d8a HE |
168 | buf[0] = REG_ADDR_LOW | (reg & 0xf); |
169 | buf[1] = REG_ADDR_HIGH | (reg >> 4); | |
28a35d8a HE |
170 | buf[2] = REG_READ_ADDR; |
171 | ||
0e1357e8 | 172 | sigma_write(buf, sizeof(buf), devc); |
28a35d8a | 173 | |
0e1357e8 | 174 | return sigma_read(data, len, devc); |
28a35d8a HE |
175 | } |
176 | ||
0e1357e8 | 177 | static uint8_t sigma_get_register(uint8_t reg, struct dev_context *devc) |
28a35d8a HE |
178 | { |
179 | uint8_t value; | |
fefa1800 | 180 | |
0e1357e8 | 181 | if (1 != sigma_read_register(reg, &value, 1, devc)) { |
47f4f073 | 182 | sr_err("sigma_get_register: 1 byte expected"); |
28a35d8a HE |
183 | return 0; |
184 | } | |
185 | ||
186 | return value; | |
187 | } | |
188 | ||
99965709 | 189 | static int sigma_read_pos(uint32_t *stoppos, uint32_t *triggerpos, |
0e1357e8 | 190 | struct dev_context *devc) |
28a35d8a HE |
191 | { |
192 | uint8_t buf[] = { | |
193 | REG_ADDR_LOW | READ_TRIGGER_POS_LOW, | |
194 | ||
195 | REG_READ_ADDR | NEXT_REG, | |
196 | REG_READ_ADDR | NEXT_REG, | |
197 | REG_READ_ADDR | NEXT_REG, | |
198 | REG_READ_ADDR | NEXT_REG, | |
199 | REG_READ_ADDR | NEXT_REG, | |
200 | REG_READ_ADDR | NEXT_REG, | |
201 | }; | |
28a35d8a HE |
202 | uint8_t result[6]; |
203 | ||
0e1357e8 | 204 | sigma_write(buf, sizeof(buf), devc); |
28a35d8a | 205 | |
0e1357e8 | 206 | sigma_read(result, sizeof(result), devc); |
28a35d8a HE |
207 | |
208 | *triggerpos = result[0] | (result[1] << 8) | (result[2] << 16); | |
209 | *stoppos = result[3] | (result[4] << 8) | (result[5] << 16); | |
210 | ||
57bbf56b HE |
211 | /* Not really sure why this must be done, but according to spec. */ |
212 | if ((--*stoppos & 0x1ff) == 0x1ff) | |
213 | stoppos -= 64; | |
214 | ||
215 | if ((*--triggerpos & 0x1ff) == 0x1ff) | |
216 | triggerpos -= 64; | |
217 | ||
28a35d8a HE |
218 | return 1; |
219 | } | |
220 | ||
99965709 | 221 | static int sigma_read_dram(uint16_t startchunk, size_t numchunks, |
0e1357e8 | 222 | uint8_t *data, struct dev_context *devc) |
28a35d8a HE |
223 | { |
224 | size_t i; | |
225 | uint8_t buf[4096]; | |
226 | int idx = 0; | |
227 | ||
fefa1800 | 228 | /* Send the startchunk. Index start with 1. */ |
28a35d8a HE |
229 | buf[0] = startchunk >> 8; |
230 | buf[1] = startchunk & 0xff; | |
0e1357e8 | 231 | sigma_write_register(WRITE_MEMROW, buf, 2, devc); |
28a35d8a | 232 | |
fefa1800 | 233 | /* Read the DRAM. */ |
28a35d8a HE |
234 | buf[idx++] = REG_DRAM_BLOCK; |
235 | buf[idx++] = REG_DRAM_WAIT_ACK; | |
236 | ||
237 | for (i = 0; i < numchunks; ++i) { | |
fefa1800 UH |
238 | /* Alternate bit to copy from DRAM to cache. */ |
239 | if (i != (numchunks - 1)) | |
240 | buf[idx++] = REG_DRAM_BLOCK | (((i + 1) % 2) << 4); | |
28a35d8a HE |
241 | |
242 | buf[idx++] = REG_DRAM_BLOCK_DATA | ((i % 2) << 4); | |
243 | ||
fefa1800 | 244 | if (i != (numchunks - 1)) |
28a35d8a HE |
245 | buf[idx++] = REG_DRAM_WAIT_ACK; |
246 | } | |
247 | ||
0e1357e8 | 248 | sigma_write(buf, idx, devc); |
28a35d8a | 249 | |
0e1357e8 | 250 | return sigma_read(data, numchunks * CHUNK_SIZE, devc); |
28a35d8a HE |
251 | } |
252 | ||
4ae1f451 | 253 | /* Upload trigger look-up tables to Sigma. */ |
0e1357e8 | 254 | static int sigma_write_trigger_lut(struct triggerlut *lut, struct dev_context *devc) |
ee492173 HE |
255 | { |
256 | int i; | |
257 | uint8_t tmp[2]; | |
258 | uint16_t bit; | |
259 | ||
260 | /* Transpose the table and send to Sigma. */ | |
261 | for (i = 0; i < 16; ++i) { | |
262 | bit = 1 << i; | |
263 | ||
264 | tmp[0] = tmp[1] = 0; | |
265 | ||
266 | if (lut->m2d[0] & bit) | |
267 | tmp[0] |= 0x01; | |
268 | if (lut->m2d[1] & bit) | |
269 | tmp[0] |= 0x02; | |
270 | if (lut->m2d[2] & bit) | |
271 | tmp[0] |= 0x04; | |
272 | if (lut->m2d[3] & bit) | |
273 | tmp[0] |= 0x08; | |
274 | ||
275 | if (lut->m3 & bit) | |
276 | tmp[0] |= 0x10; | |
277 | if (lut->m3s & bit) | |
278 | tmp[0] |= 0x20; | |
279 | if (lut->m4 & bit) | |
280 | tmp[0] |= 0x40; | |
281 | ||
282 | if (lut->m0d[0] & bit) | |
283 | tmp[1] |= 0x01; | |
284 | if (lut->m0d[1] & bit) | |
285 | tmp[1] |= 0x02; | |
286 | if (lut->m0d[2] & bit) | |
287 | tmp[1] |= 0x04; | |
288 | if (lut->m0d[3] & bit) | |
289 | tmp[1] |= 0x08; | |
290 | ||
291 | if (lut->m1d[0] & bit) | |
292 | tmp[1] |= 0x10; | |
293 | if (lut->m1d[1] & bit) | |
294 | tmp[1] |= 0x20; | |
295 | if (lut->m1d[2] & bit) | |
296 | tmp[1] |= 0x40; | |
297 | if (lut->m1d[3] & bit) | |
298 | tmp[1] |= 0x80; | |
299 | ||
99965709 | 300 | sigma_write_register(WRITE_TRIGGER_SELECT0, tmp, sizeof(tmp), |
0e1357e8 BV |
301 | devc); |
302 | sigma_set_register(WRITE_TRIGGER_SELECT1, 0x30 | i, devc); | |
ee492173 HE |
303 | } |
304 | ||
305 | /* Send the parameters */ | |
306 | sigma_write_register(WRITE_TRIGGER_SELECT0, (uint8_t *) &lut->params, | |
0e1357e8 | 307 | sizeof(lut->params), devc); |
ee492173 | 308 | |
e46b8fb1 | 309 | return SR_OK; |
ee492173 HE |
310 | } |
311 | ||
fefa1800 | 312 | /* Generate the bitbang stream for programming the FPGA. */ |
28a35d8a | 313 | static int bin2bitbang(const char *filename, |
fefa1800 | 314 | unsigned char **buf, size_t *buf_size) |
28a35d8a | 315 | { |
fefa1800 | 316 | FILE *f; |
e3fff420 | 317 | unsigned long file_size; |
28a35d8a HE |
318 | unsigned long offset = 0; |
319 | unsigned char *p; | |
e3fff420 HE |
320 | uint8_t *firmware; |
321 | unsigned long fwsize = 0; | |
28a35d8a HE |
322 | const int buffer_size = 65536; |
323 | size_t i; | |
e3fff420 | 324 | int c, bit, v; |
fefa1800 | 325 | uint32_t imm = 0x3f6df2ab; |
28a35d8a | 326 | |
868d8cef | 327 | f = g_fopen(filename, "rb"); |
28a35d8a | 328 | if (!f) { |
47f4f073 | 329 | sr_err("g_fopen(\"%s\", \"rb\")", filename); |
b53738ba | 330 | return SR_ERR; |
28a35d8a HE |
331 | } |
332 | ||
333 | if (-1 == fseek(f, 0, SEEK_END)) { | |
47f4f073 | 334 | sr_err("fseek on %s failed", filename); |
28a35d8a | 335 | fclose(f); |
b53738ba | 336 | return SR_ERR; |
28a35d8a HE |
337 | } |
338 | ||
339 | file_size = ftell(f); | |
340 | ||
341 | fseek(f, 0, SEEK_SET); | |
342 | ||
b53738ba | 343 | if (!(firmware = g_try_malloc(buffer_size))) { |
47f4f073 | 344 | sr_err("%s: firmware malloc failed", __func__); |
12ad53f5 | 345 | fclose(f); |
b53738ba | 346 | return SR_ERR_MALLOC; |
28a35d8a HE |
347 | } |
348 | ||
28a35d8a HE |
349 | while ((c = getc(f)) != EOF) { |
350 | imm = (imm + 0xa853753) % 177 + (imm * 0x8034052); | |
e3fff420 | 351 | firmware[fwsize++] = c ^ imm; |
28a35d8a HE |
352 | } |
353 | fclose(f); | |
354 | ||
e3fff420 | 355 | if(fwsize != file_size) { |
47f4f073 | 356 | sr_err("%s: Error reading firmware", filename); |
e3fff420 HE |
357 | fclose(f); |
358 | g_free(firmware); | |
359 | return SR_ERR; | |
28a35d8a HE |
360 | } |
361 | ||
28a35d8a HE |
362 | *buf_size = fwsize * 2 * 8; |
363 | ||
b53738ba | 364 | *buf = p = (unsigned char *)g_try_malloc(*buf_size); |
28a35d8a | 365 | if (!p) { |
47f4f073 | 366 | sr_err("%s: buf/p malloc failed", __func__); |
12ad53f5 | 367 | g_free(firmware); |
b53738ba | 368 | return SR_ERR_MALLOC; |
28a35d8a HE |
369 | } |
370 | ||
371 | for (i = 0; i < fwsize; ++i) { | |
28a35d8a | 372 | for (bit = 7; bit >= 0; --bit) { |
fefa1800 | 373 | v = firmware[i] & 1 << bit ? 0x40 : 0x00; |
28a35d8a HE |
374 | p[offset++] = v | 0x01; |
375 | p[offset++] = v; | |
376 | } | |
377 | } | |
378 | ||
379 | g_free(firmware); | |
380 | ||
381 | if (offset != *buf_size) { | |
382 | g_free(*buf); | |
47f4f073 | 383 | sr_err("Error reading firmware %s " |
0aeb0ccd | 384 | "offset=%ld, file_size=%ld, buf_size=%zd.", |
133a37bf | 385 | filename, offset, file_size, *buf_size); |
28a35d8a | 386 | |
b53738ba | 387 | return SR_ERR; |
28a35d8a HE |
388 | } |
389 | ||
b53738ba | 390 | return SR_OK; |
28a35d8a HE |
391 | } |
392 | ||
811deee4 | 393 | static int clear_instances(void) |
0448d110 BV |
394 | { |
395 | GSList *l; | |
396 | struct sr_dev_inst *sdi; | |
0e1357e8 BV |
397 | struct drv_context *drvc; |
398 | struct dev_context *devc; | |
399 | ||
a873c594 | 400 | drvc = di->priv; |
0448d110 BV |
401 | |
402 | /* Properly close all devices. */ | |
0e1357e8 | 403 | for (l = drvc->instances; l; l = l->next) { |
0448d110 BV |
404 | if (!(sdi = l->data)) { |
405 | /* Log error, but continue cleaning up the rest. */ | |
47f4f073 | 406 | sr_err("%s: sdi was NULL, continuing", __func__); |
0448d110 BV |
407 | continue; |
408 | } | |
409 | if (sdi->priv) { | |
0e1357e8 BV |
410 | devc = sdi->priv; |
411 | ftdi_free(&devc->ftdic); | |
0448d110 BV |
412 | } |
413 | sr_dev_inst_free(sdi); | |
414 | } | |
0e1357e8 BV |
415 | g_slist_free(drvc->instances); |
416 | drvc->instances = NULL; | |
0448d110 | 417 | |
811deee4 | 418 | return SR_OK; |
0448d110 BV |
419 | } |
420 | ||
34f06b90 | 421 | static int hw_init(struct sr_context *sr_ctx) |
61136ea6 | 422 | { |
b32503cc | 423 | struct drv_context *drvc; |
61136ea6 | 424 | |
b32503cc | 425 | if (!(drvc = g_try_malloc0(sizeof(struct drv_context)))) { |
47f4f073 | 426 | sr_err("Driver context malloc failed."); |
886a52b6 | 427 | return SR_ERR_MALLOC; |
b32503cc | 428 | } |
1ebe4b4e | 429 | drvc->sr_ctx = sr_ctx; |
a873c594 | 430 | di->priv = drvc; |
61136ea6 BV |
431 | |
432 | return SR_OK; | |
433 | } | |
434 | ||
0448d110 | 435 | static GSList *hw_scan(GSList *options) |
28a35d8a | 436 | { |
d68e2d1a | 437 | struct sr_dev_inst *sdi; |
87ca93c5 | 438 | struct sr_probe *probe; |
0e1357e8 BV |
439 | struct drv_context *drvc; |
440 | struct dev_context *devc; | |
0448d110 | 441 | GSList *devices; |
e3fff420 HE |
442 | struct ftdi_device_list *devlist; |
443 | char serial_txt[10]; | |
444 | uint32_t serial; | |
87ca93c5 | 445 | int ret, i; |
28a35d8a | 446 | |
0448d110 | 447 | (void)options; |
64d33dc2 | 448 | |
a873c594 | 449 | drvc = di->priv; |
0448d110 BV |
450 | devices = NULL; |
451 | clear_instances(); | |
452 | ||
0e1357e8 | 453 | if (!(devc = g_try_malloc(sizeof(struct dev_context)))) { |
47f4f073 | 454 | sr_err("%s: devc malloc failed", __func__); |
0448d110 | 455 | return NULL; |
b53738ba | 456 | } |
99965709 | 457 | |
0e1357e8 | 458 | ftdi_init(&devc->ftdic); |
28a35d8a | 459 | |
fefa1800 | 460 | /* Look for SIGMAs. */ |
e3fff420 | 461 | |
0e1357e8 | 462 | if ((ret = ftdi_usb_find_all(&devc->ftdic, &devlist, |
eec944c5 BV |
463 | USB_VENDOR, USB_PRODUCT)) <= 0) { |
464 | if (ret < 0) | |
465 | sr_err("ftdi_usb_find_all(): %d", ret); | |
99965709 | 466 | goto free; |
eec944c5 | 467 | } |
99965709 | 468 | |
e3fff420 | 469 | /* Make sure it's a version 1 or 2 SIGMA. */ |
0e1357e8 | 470 | ftdi_usb_get_strings(&devc->ftdic, devlist->dev, NULL, 0, NULL, 0, |
6352d030 | 471 | serial_txt, sizeof(serial_txt)); |
e3fff420 HE |
472 | sscanf(serial_txt, "%x", &serial); |
473 | ||
6352d030 | 474 | if (serial < 0xa6010000 || serial > 0xa602ffff) { |
47f4f073 UH |
475 | sr_err("Only SIGMA and SIGMA2 are supported " |
476 | "in this version of libsigrok."); | |
e3fff420 HE |
477 | goto free; |
478 | } | |
479 | ||
480 | sr_info("Found ASIX SIGMA - Serial: %s", serial_txt); | |
481 | ||
0e1357e8 BV |
482 | devc->cur_samplerate = 0; |
483 | devc->period_ps = 0; | |
484 | devc->limit_msec = 0; | |
485 | devc->cur_firmware = -1; | |
486 | devc->num_probes = 0; | |
487 | devc->samples_per_event = 0; | |
488 | devc->capture_ratio = 50; | |
489 | devc->use_triggers = 0; | |
28a35d8a | 490 | |
fefa1800 | 491 | /* Register SIGMA device. */ |
d68e2d1a UH |
492 | if (!(sdi = sr_dev_inst_new(0, SR_ST_INITIALIZING, USB_VENDOR_NAME, |
493 | USB_MODEL_NAME, USB_MODEL_VERSION))) { | |
47f4f073 | 494 | sr_err("%s: sdi was NULL", __func__); |
99965709 | 495 | goto free; |
d68e2d1a | 496 | } |
a873c594 | 497 | sdi->driver = di; |
87ca93c5 BV |
498 | |
499 | for (i = 0; probe_names[i]; i++) { | |
de6e0eca | 500 | if (!(probe = sr_probe_new(i, SR_PROBE_LOGIC, TRUE, |
87ca93c5 BV |
501 | probe_names[i]))) |
502 | return NULL; | |
503 | sdi->probes = g_slist_append(sdi->probes, probe); | |
504 | } | |
505 | ||
0448d110 | 506 | devices = g_slist_append(devices, sdi); |
0e1357e8 BV |
507 | drvc->instances = g_slist_append(drvc->instances, sdi); |
508 | sdi->priv = devc; | |
28a35d8a | 509 | |
fefa1800 | 510 | /* We will open the device again when we need it. */ |
e3fff420 | 511 | ftdi_list_free(&devlist); |
28a35d8a | 512 | |
0448d110 | 513 | return devices; |
ea9cfed7 | 514 | |
99965709 | 515 | free: |
0e1357e8 BV |
516 | ftdi_deinit(&devc->ftdic); |
517 | g_free(devc); | |
0448d110 | 518 | return NULL; |
28a35d8a HE |
519 | } |
520 | ||
811deee4 BV |
521 | static GSList *hw_dev_list(void) |
522 | { | |
523 | struct drv_context *drvc; | |
524 | ||
a873c594 | 525 | drvc = di->priv; |
811deee4 BV |
526 | |
527 | return drvc->instances; | |
528 | } | |
529 | ||
0e1357e8 | 530 | static int upload_firmware(int firmware_idx, struct dev_context *devc) |
28a35d8a HE |
531 | { |
532 | int ret; | |
533 | unsigned char *buf; | |
534 | unsigned char pins; | |
535 | size_t buf_size; | |
28a35d8a | 536 | unsigned char result[32]; |
e8397563 | 537 | char firmware_path[128]; |
28a35d8a | 538 | |
fefa1800 | 539 | /* Make sure it's an ASIX SIGMA. */ |
0e1357e8 | 540 | if ((ret = ftdi_usb_open_desc(&devc->ftdic, |
28a35d8a | 541 | USB_VENDOR, USB_PRODUCT, USB_DESCRIPTION, NULL)) < 0) { |
47f4f073 | 542 | sr_err("ftdi_usb_open failed: %s", |
0e1357e8 | 543 | ftdi_get_error_string(&devc->ftdic)); |
28a35d8a HE |
544 | return 0; |
545 | } | |
546 | ||
0e1357e8 | 547 | if ((ret = ftdi_set_bitmode(&devc->ftdic, 0xdf, BITMODE_BITBANG)) < 0) { |
47f4f073 | 548 | sr_err("ftdi_set_bitmode failed: %s", |
0e1357e8 | 549 | ftdi_get_error_string(&devc->ftdic)); |
28a35d8a HE |
550 | return 0; |
551 | } | |
552 | ||
fefa1800 | 553 | /* Four times the speed of sigmalogan - Works well. */ |
0e1357e8 | 554 | if ((ret = ftdi_set_baudrate(&devc->ftdic, 750000)) < 0) { |
47f4f073 | 555 | sr_err("ftdi_set_baudrate failed: %s", |
0e1357e8 | 556 | ftdi_get_error_string(&devc->ftdic)); |
28a35d8a HE |
557 | return 0; |
558 | } | |
559 | ||
fefa1800 | 560 | /* Force the FPGA to reboot. */ |
0e1357e8 BV |
561 | sigma_write(suicide, sizeof(suicide), devc); |
562 | sigma_write(suicide, sizeof(suicide), devc); | |
563 | sigma_write(suicide, sizeof(suicide), devc); | |
564 | sigma_write(suicide, sizeof(suicide), devc); | |
28a35d8a | 565 | |
fefa1800 | 566 | /* Prepare to upload firmware (FPGA specific). */ |
0e1357e8 | 567 | sigma_write(init, sizeof(init), devc); |
28a35d8a | 568 | |
0e1357e8 | 569 | ftdi_usb_purge_buffers(&devc->ftdic); |
28a35d8a | 570 | |
fefa1800 | 571 | /* Wait until the FPGA asserts INIT_B. */ |
28a35d8a | 572 | while (1) { |
0e1357e8 | 573 | ret = sigma_read(result, 1, devc); |
28a35d8a HE |
574 | if (result[0] & 0x20) |
575 | break; | |
576 | } | |
577 | ||
9ddb2a12 | 578 | /* Prepare firmware. */ |
e8397563 | 579 | snprintf(firmware_path, sizeof(firmware_path), "%s/%s", FIRMWARE_DIR, |
f6564c8d HE |
580 | firmware_files[firmware_idx]); |
581 | ||
b53738ba | 582 | if ((ret = bin2bitbang(firmware_path, &buf, &buf_size)) != SR_OK) { |
47f4f073 | 583 | sr_err("An error occured while reading the firmware: %s", |
133a37bf | 584 | firmware_path); |
b53738ba | 585 | return ret; |
28a35d8a HE |
586 | } |
587 | ||
fefa1800 | 588 | /* Upload firmare. */ |
47f4f073 | 589 | sr_info("Uploading firmware file '%s'.", firmware_files[firmware_idx]); |
0e1357e8 | 590 | sigma_write(buf, buf_size, devc); |
28a35d8a HE |
591 | |
592 | g_free(buf); | |
593 | ||
0e1357e8 | 594 | if ((ret = ftdi_set_bitmode(&devc->ftdic, 0x00, BITMODE_RESET)) < 0) { |
47f4f073 | 595 | sr_err("ftdi_set_bitmode failed: %s", |
0e1357e8 | 596 | ftdi_get_error_string(&devc->ftdic)); |
e46b8fb1 | 597 | return SR_ERR; |
28a35d8a HE |
598 | } |
599 | ||
0e1357e8 | 600 | ftdi_usb_purge_buffers(&devc->ftdic); |
28a35d8a | 601 | |
fefa1800 | 602 | /* Discard garbage. */ |
0e1357e8 | 603 | while (1 == sigma_read(&pins, 1, devc)) |
28a35d8a HE |
604 | ; |
605 | ||
fefa1800 | 606 | /* Initialize the logic analyzer mode. */ |
0e1357e8 | 607 | sigma_write(logic_mode_start, sizeof(logic_mode_start), devc); |
28a35d8a | 608 | |
fefa1800 | 609 | /* Expect a 3 byte reply. */ |
0e1357e8 | 610 | ret = sigma_read(result, 3, devc); |
28a35d8a HE |
611 | if (ret != 3 || |
612 | result[0] != 0xa6 || result[1] != 0x55 || result[2] != 0xaa) { | |
47f4f073 | 613 | sr_err("Configuration failed. Invalid reply received."); |
e46b8fb1 | 614 | return SR_ERR; |
28a35d8a HE |
615 | } |
616 | ||
0e1357e8 | 617 | devc->cur_firmware = firmware_idx; |
f6564c8d | 618 | |
47f4f073 | 619 | sr_info("Firmware uploaded."); |
e3fff420 | 620 | |
e46b8fb1 | 621 | return SR_OK; |
f6564c8d HE |
622 | } |
623 | ||
25a0f108 | 624 | static int hw_dev_open(struct sr_dev_inst *sdi) |
f6564c8d | 625 | { |
0e1357e8 | 626 | struct dev_context *devc; |
f6564c8d HE |
627 | int ret; |
628 | ||
0e1357e8 | 629 | devc = sdi->priv; |
99965709 | 630 | |
9ddb2a12 | 631 | /* Make sure it's an ASIX SIGMA. */ |
0e1357e8 | 632 | if ((ret = ftdi_usb_open_desc(&devc->ftdic, |
f6564c8d HE |
633 | USB_VENDOR, USB_PRODUCT, USB_DESCRIPTION, NULL)) < 0) { |
634 | ||
47f4f073 | 635 | sr_err("ftdi_usb_open failed: %s", |
0e1357e8 | 636 | ftdi_get_error_string(&devc->ftdic)); |
f6564c8d HE |
637 | |
638 | return 0; | |
639 | } | |
28a35d8a | 640 | |
5a2326a7 | 641 | sdi->status = SR_ST_ACTIVE; |
28a35d8a | 642 | |
e46b8fb1 | 643 | return SR_OK; |
f6564c8d HE |
644 | } |
645 | ||
6f4b1868 | 646 | static int set_samplerate(const struct sr_dev_inst *sdi, uint64_t samplerate) |
f6564c8d | 647 | { |
e8397563 | 648 | int i, ret; |
0e1357e8 | 649 | struct dev_context *devc = sdi->priv; |
f6564c8d | 650 | |
f4abaa9f UH |
651 | ret = SR_OK; |
652 | ||
f6564c8d HE |
653 | for (i = 0; supported_samplerates[i]; i++) { |
654 | if (supported_samplerates[i] == samplerate) | |
655 | break; | |
656 | } | |
657 | if (supported_samplerates[i] == 0) | |
e46b8fb1 | 658 | return SR_ERR_SAMPLERATE; |
f6564c8d | 659 | |
59df0c77 | 660 | if (samplerate <= SR_MHZ(50)) { |
0e1357e8 BV |
661 | ret = upload_firmware(0, devc); |
662 | devc->num_probes = 16; | |
e8397563 | 663 | } |
59df0c77 | 664 | if (samplerate == SR_MHZ(100)) { |
0e1357e8 BV |
665 | ret = upload_firmware(1, devc); |
666 | devc->num_probes = 8; | |
f78898e9 | 667 | } |
59df0c77 | 668 | else if (samplerate == SR_MHZ(200)) { |
0e1357e8 BV |
669 | ret = upload_firmware(2, devc); |
670 | devc->num_probes = 4; | |
f78898e9 | 671 | } |
f6564c8d | 672 | |
0e1357e8 BV |
673 | devc->cur_samplerate = samplerate; |
674 | devc->period_ps = 1000000000000 / samplerate; | |
675 | devc->samples_per_event = 16 / devc->num_probes; | |
676 | devc->state.state = SIGMA_IDLE; | |
f6564c8d | 677 | |
e8397563 | 678 | return ret; |
28a35d8a HE |
679 | } |
680 | ||
c53d793f HE |
681 | /* |
682 | * In 100 and 200 MHz mode, only a single pin rising/falling can be | |
683 | * set as trigger. In other modes, two rising/falling triggers can be set, | |
684 | * in addition to value/mask trigger for any number of probes. | |
685 | * | |
686 | * The Sigma supports complex triggers using boolean expressions, but this | |
687 | * has not been implemented yet. | |
688 | */ | |
014359e3 | 689 | static int configure_probes(const struct sr_dev_inst *sdi) |
57bbf56b | 690 | { |
0e1357e8 | 691 | struct dev_context *devc = sdi->priv; |
1b79df2f JH |
692 | const struct sr_probe *probe; |
693 | const GSList *l; | |
57bbf56b | 694 | int trigger_set = 0; |
a42aec7f | 695 | int probebit; |
57bbf56b | 696 | |
0e1357e8 | 697 | memset(&devc->trigger, 0, sizeof(struct sigma_trigger)); |
eec5275e | 698 | |
014359e3 | 699 | for (l = sdi->probes; l; l = l->next) { |
1afe8989 | 700 | probe = (struct sr_probe *)l->data; |
b35c8293 | 701 | probebit = 1 << (probe->index); |
57bbf56b HE |
702 | |
703 | if (!probe->enabled || !probe->trigger) | |
704 | continue; | |
705 | ||
0e1357e8 | 706 | if (devc->cur_samplerate >= SR_MHZ(100)) { |
c53d793f | 707 | /* Fast trigger support. */ |
ee492173 | 708 | if (trigger_set) { |
47f4f073 UH |
709 | sr_err("Only a single pin trigger in 100 and " |
710 | "200MHz mode is supported."); | |
e46b8fb1 | 711 | return SR_ERR; |
ee492173 HE |
712 | } |
713 | if (probe->trigger[0] == 'f') | |
0e1357e8 | 714 | devc->trigger.fallingmask |= probebit; |
ee492173 | 715 | else if (probe->trigger[0] == 'r') |
0e1357e8 | 716 | devc->trigger.risingmask |= probebit; |
ee492173 | 717 | else { |
47f4f073 UH |
718 | sr_err("Only rising/falling trigger in 100 " |
719 | "and 200MHz mode is supported."); | |
e46b8fb1 | 720 | return SR_ERR; |
ee492173 | 721 | } |
57bbf56b | 722 | |
c53d793f | 723 | ++trigger_set; |
ee492173 | 724 | } else { |
c53d793f HE |
725 | /* Simple trigger support (event). */ |
726 | if (probe->trigger[0] == '1') { | |
0e1357e8 BV |
727 | devc->trigger.simplevalue |= probebit; |
728 | devc->trigger.simplemask |= probebit; | |
c53d793f HE |
729 | } |
730 | else if (probe->trigger[0] == '0') { | |
0e1357e8 BV |
731 | devc->trigger.simplevalue &= ~probebit; |
732 | devc->trigger.simplemask |= probebit; | |
c53d793f HE |
733 | } |
734 | else if (probe->trigger[0] == 'f') { | |
0e1357e8 | 735 | devc->trigger.fallingmask |= probebit; |
c53d793f HE |
736 | ++trigger_set; |
737 | } | |
738 | else if (probe->trigger[0] == 'r') { | |
0e1357e8 | 739 | devc->trigger.risingmask |= probebit; |
c53d793f HE |
740 | ++trigger_set; |
741 | } | |
ee492173 | 742 | |
ea9cfed7 UH |
743 | /* |
744 | * Actually, Sigma supports 2 rising/falling triggers, | |
745 | * but they are ORed and the current trigger syntax | |
746 | * does not permit ORed triggers. | |
747 | */ | |
98b8cbc1 | 748 | if (trigger_set > 1) { |
47f4f073 UH |
749 | sr_err("Only 1 rising/falling trigger " |
750 | "is supported."); | |
e46b8fb1 | 751 | return SR_ERR; |
ee492173 | 752 | } |
ee492173 | 753 | } |
5b5ea7c6 HE |
754 | |
755 | if (trigger_set) | |
0e1357e8 | 756 | devc->use_triggers = 1; |
57bbf56b HE |
757 | } |
758 | ||
e46b8fb1 | 759 | return SR_OK; |
57bbf56b HE |
760 | } |
761 | ||
25a0f108 | 762 | static int hw_dev_close(struct sr_dev_inst *sdi) |
28a35d8a | 763 | { |
0e1357e8 | 764 | struct dev_context *devc; |
28a35d8a | 765 | |
0e1357e8 | 766 | if (!(devc = sdi->priv)) { |
47f4f073 | 767 | sr_err("%s: sdi->priv was NULL", __func__); |
0abee507 | 768 | return SR_ERR_BUG; |
9be9893e | 769 | } |
697785d1 UH |
770 | |
771 | /* TODO */ | |
772 | if (sdi->status == SR_ST_ACTIVE) | |
0e1357e8 | 773 | ftdi_usb_close(&devc->ftdic); |
697785d1 UH |
774 | |
775 | sdi->status = SR_ST_INACTIVE; | |
776 | ||
777 | return SR_OK; | |
28a35d8a HE |
778 | } |
779 | ||
57ab7d9f | 780 | static int hw_cleanup(void) |
28a35d8a | 781 | { |
a873c594 | 782 | if (!di->priv) |
b32503cc BV |
783 | return SR_OK; |
784 | ||
0448d110 | 785 | clear_instances(); |
57ab7d9f | 786 | |
0448d110 | 787 | return SR_OK; |
28a35d8a HE |
788 | } |
789 | ||
41479605 | 790 | static int hw_info_get(int info_id, const void **data, |
47f4f073 | 791 | const struct sr_dev_inst *sdi) |
28a35d8a | 792 | { |
0e1357e8 | 793 | struct dev_context *devc; |
99965709 | 794 | |
41479605 | 795 | switch (info_id) { |
b2b5445c BV |
796 | case SR_DI_HWCAPS: |
797 | *data = hwcaps; | |
798 | break; | |
5a2326a7 | 799 | case SR_DI_NUM_PROBES: |
41479605 | 800 | *data = GINT_TO_POINTER(NUM_PROBES); |
464d12c7 KS |
801 | break; |
802 | case SR_DI_PROBE_NAMES: | |
41479605 | 803 | *data = probe_names; |
28a35d8a | 804 | break; |
5a2326a7 | 805 | case SR_DI_SAMPLERATES: |
41479605 | 806 | *data = &samplerates; |
28a35d8a | 807 | break; |
5a2326a7 | 808 | case SR_DI_TRIGGER_TYPES: |
41479605 | 809 | *data = (char *)TRIGGER_TYPES; |
28a35d8a | 810 | break; |
5a2326a7 | 811 | case SR_DI_CUR_SAMPLERATE: |
41479605 | 812 | if (sdi) { |
0e1357e8 BV |
813 | devc = sdi->priv; |
814 | *data = &devc->cur_samplerate; | |
41479605 BV |
815 | } else |
816 | return SR_ERR; | |
28a35d8a | 817 | break; |
d7bbecfd BV |
818 | default: |
819 | return SR_ERR_ARG; | |
28a35d8a HE |
820 | } |
821 | ||
41479605 | 822 | return SR_OK; |
28a35d8a HE |
823 | } |
824 | ||
6f4b1868 | 825 | static int hw_dev_config_set(const struct sr_dev_inst *sdi, int hwcap, |
47f4f073 | 826 | const void *value) |
28a35d8a | 827 | { |
0e1357e8 | 828 | struct dev_context *devc; |
28a35d8a | 829 | int ret; |
f6564c8d | 830 | |
0e1357e8 | 831 | devc = sdi->priv; |
99965709 | 832 | |
ffedd0bf | 833 | if (hwcap == SR_HWCAP_SAMPLERATE) { |
1b79df2f | 834 | ret = set_samplerate(sdi, *(const uint64_t *)value); |
ffedd0bf | 835 | } else if (hwcap == SR_HWCAP_LIMIT_MSEC) { |
0e1357e8 BV |
836 | devc->limit_msec = *(const uint64_t *)value; |
837 | if (devc->limit_msec > 0) | |
e46b8fb1 | 838 | ret = SR_OK; |
94ba4bd6 | 839 | else |
e46b8fb1 | 840 | ret = SR_ERR; |
ffedd0bf | 841 | } else if (hwcap == SR_HWCAP_CAPTURE_RATIO) { |
0e1357e8 BV |
842 | devc->capture_ratio = *(const uint64_t *)value; |
843 | if (devc->capture_ratio < 0 || devc->capture_ratio > 100) | |
e46b8fb1 | 844 | ret = SR_ERR; |
94ba4bd6 | 845 | else |
e46b8fb1 | 846 | ret = SR_OK; |
28a35d8a | 847 | } else { |
e46b8fb1 | 848 | ret = SR_ERR; |
28a35d8a HE |
849 | } |
850 | ||
851 | return ret; | |
852 | } | |
853 | ||
36b1c8e6 HE |
854 | /* Software trigger to determine exact trigger position. */ |
855 | static int get_trigger_offset(uint16_t *samples, uint16_t last_sample, | |
856 | struct sigma_trigger *t) | |
857 | { | |
858 | int i; | |
859 | ||
860 | for (i = 0; i < 8; ++i) { | |
861 | if (i > 0) | |
862 | last_sample = samples[i-1]; | |
863 | ||
864 | /* Simple triggers. */ | |
865 | if ((samples[i] & t->simplemask) != t->simplevalue) | |
866 | continue; | |
867 | ||
868 | /* Rising edge. */ | |
869 | if ((last_sample & t->risingmask) != 0 || (samples[i] & | |
870 | t->risingmask) != t->risingmask) | |
871 | continue; | |
872 | ||
873 | /* Falling edge. */ | |
bdfc7a89 HE |
874 | if ((last_sample & t->fallingmask) != t->fallingmask || |
875 | (samples[i] & t->fallingmask) != 0) | |
36b1c8e6 HE |
876 | continue; |
877 | ||
878 | break; | |
879 | } | |
880 | ||
881 | /* If we did not match, return original trigger pos. */ | |
882 | return i & 0x7; | |
883 | } | |
884 | ||
28a35d8a | 885 | /* |
fefa1800 UH |
886 | * Decode chunk of 1024 bytes, 64 clusters, 7 events per cluster. |
887 | * Each event is 20ns apart, and can contain multiple samples. | |
f78898e9 HE |
888 | * |
889 | * For 200 MHz, events contain 4 samples for each channel, spread 5 ns apart. | |
890 | * For 100 MHz, events contain 2 samples for each channel, spread 10 ns apart. | |
891 | * For 50 MHz and below, events contain one sample for each channel, | |
892 | * spread 20 ns apart. | |
28a35d8a HE |
893 | */ |
894 | static int decode_chunk_ts(uint8_t *buf, uint16_t *lastts, | |
88c51afe | 895 | uint16_t *lastsample, int triggerpos, |
3cd3a20b | 896 | uint16_t limit_chunk, void *cb_data) |
28a35d8a | 897 | { |
3cd3a20b | 898 | struct sr_dev_inst *sdi = cb_data; |
0e1357e8 | 899 | struct dev_context *devc = sdi->priv; |
fefa1800 | 900 | uint16_t tsdiff, ts; |
0e1357e8 | 901 | uint16_t samples[65536 * devc->samples_per_event]; |
b9c735a2 | 902 | struct sr_datafeed_packet packet; |
9c939c51 | 903 | struct sr_datafeed_logic logic; |
f78898e9 | 904 | int i, j, k, l, numpad, tosend; |
fefa1800 | 905 | size_t n = 0, sent = 0; |
0e1357e8 | 906 | int clustersize = EVENTS_PER_CLUSTER * devc->samples_per_event; |
fefa1800 | 907 | uint16_t *event; |
f78898e9 | 908 | uint16_t cur_sample; |
57bbf56b | 909 | int triggerts = -1; |
ee492173 | 910 | |
4ae1f451 | 911 | /* Check if trigger is in this chunk. */ |
ee492173 | 912 | if (triggerpos != -1) { |
0e1357e8 | 913 | if (devc->cur_samplerate <= SR_MHZ(50)) |
36b1c8e6 | 914 | triggerpos -= EVENTS_PER_CLUSTER - 1; |
ee492173 HE |
915 | |
916 | if (triggerpos < 0) | |
917 | triggerpos = 0; | |
57bbf56b | 918 | |
ee492173 HE |
919 | /* Find in which cluster the trigger occured. */ |
920 | triggerts = triggerpos / 7; | |
921 | } | |
28a35d8a | 922 | |
eec5275e | 923 | /* For each ts. */ |
28a35d8a | 924 | for (i = 0; i < 64; ++i) { |
fefa1800 | 925 | ts = *(uint16_t *) &buf[i * 16]; |
28a35d8a HE |
926 | tsdiff = ts - *lastts; |
927 | *lastts = ts; | |
928 | ||
88c51afe HE |
929 | /* Decode partial chunk. */ |
930 | if (limit_chunk && ts > limit_chunk) | |
e46b8fb1 | 931 | return SR_OK; |
88c51afe | 932 | |
fefa1800 | 933 | /* Pad last sample up to current point. */ |
0e1357e8 | 934 | numpad = tsdiff * devc->samples_per_event - clustersize; |
28a35d8a | 935 | if (numpad > 0) { |
f78898e9 HE |
936 | for (j = 0; j < numpad; ++j) |
937 | samples[j] = *lastsample; | |
938 | ||
939 | n = numpad; | |
28a35d8a HE |
940 | } |
941 | ||
57bbf56b HE |
942 | /* Send samples between previous and this timestamp to sigrok. */ |
943 | sent = 0; | |
944 | while (sent < n) { | |
945 | tosend = MIN(2048, n - sent); | |
946 | ||
5a2326a7 | 947 | packet.type = SR_DF_LOGIC; |
9c939c51 BV |
948 | packet.payload = &logic; |
949 | logic.length = tosend * sizeof(uint16_t); | |
950 | logic.unitsize = 2; | |
951 | logic.data = samples + sent; | |
0e1357e8 | 952 | sr_session_send(devc->session_dev_id, &packet); |
28a35d8a | 953 | |
57bbf56b HE |
954 | sent += tosend; |
955 | } | |
956 | n = 0; | |
957 | ||
958 | event = (uint16_t *) &buf[i * 16 + 2]; | |
f78898e9 HE |
959 | cur_sample = 0; |
960 | ||
961 | /* For each event in cluster. */ | |
28a35d8a | 962 | for (j = 0; j < 7; ++j) { |
f78898e9 HE |
963 | |
964 | /* For each sample in event. */ | |
0e1357e8 | 965 | for (k = 0; k < devc->samples_per_event; ++k) { |
f78898e9 HE |
966 | cur_sample = 0; |
967 | ||
968 | /* For each probe. */ | |
0e1357e8 | 969 | for (l = 0; l < devc->num_probes; ++l) |
edca2c5c | 970 | cur_sample |= (!!(event[j] & (1 << (l * |
0e1357e8 | 971 | devc->samples_per_event + k)))) << l; |
f78898e9 HE |
972 | |
973 | samples[n++] = cur_sample; | |
28a35d8a HE |
974 | } |
975 | } | |
976 | ||
eec5275e | 977 | /* Send data up to trigger point (if triggered). */ |
fefa1800 | 978 | sent = 0; |
57bbf56b HE |
979 | if (i == triggerts) { |
980 | /* | |
36b1c8e6 HE |
981 | * Trigger is not always accurate to sample because of |
982 | * pipeline delay. However, it always triggers before | |
983 | * the actual event. We therefore look at the next | |
984 | * samples to pinpoint the exact position of the trigger. | |
57bbf56b | 985 | */ |
bdfc7a89 | 986 | tosend = get_trigger_offset(samples, *lastsample, |
0e1357e8 | 987 | &devc->trigger); |
57bbf56b HE |
988 | |
989 | if (tosend > 0) { | |
5a2326a7 | 990 | packet.type = SR_DF_LOGIC; |
9c939c51 BV |
991 | packet.payload = &logic; |
992 | logic.length = tosend * sizeof(uint16_t); | |
993 | logic.unitsize = 2; | |
994 | logic.data = samples; | |
0e1357e8 | 995 | sr_session_send(devc->session_dev_id, &packet); |
57bbf56b HE |
996 | |
997 | sent += tosend; | |
998 | } | |
28a35d8a | 999 | |
5b5ea7c6 | 1000 | /* Only send trigger if explicitly enabled. */ |
0e1357e8 | 1001 | if (devc->use_triggers) { |
5a2326a7 | 1002 | packet.type = SR_DF_TRIGGER; |
0e1357e8 | 1003 | sr_session_send(devc->session_dev_id, &packet); |
5b5ea7c6 | 1004 | } |
28a35d8a | 1005 | } |
57bbf56b | 1006 | |
eec5275e | 1007 | /* Send rest of the chunk to sigrok. */ |
57bbf56b HE |
1008 | tosend = n - sent; |
1009 | ||
abda62ce | 1010 | if (tosend > 0) { |
5a2326a7 | 1011 | packet.type = SR_DF_LOGIC; |
9c939c51 BV |
1012 | packet.payload = &logic; |
1013 | logic.length = tosend * sizeof(uint16_t); | |
1014 | logic.unitsize = 2; | |
1015 | logic.data = samples + sent; | |
0e1357e8 | 1016 | sr_session_send(devc->session_dev_id, &packet); |
abda62ce | 1017 | } |
ee492173 HE |
1018 | |
1019 | *lastsample = samples[n - 1]; | |
28a35d8a HE |
1020 | } |
1021 | ||
e46b8fb1 | 1022 | return SR_OK; |
28a35d8a HE |
1023 | } |
1024 | ||
1f9813eb | 1025 | static int receive_data(int fd, int revents, void *cb_data) |
28a35d8a | 1026 | { |
1f9813eb | 1027 | struct sr_dev_inst *sdi = cb_data; |
0e1357e8 | 1028 | struct dev_context *devc = sdi->priv; |
b9c735a2 | 1029 | struct sr_datafeed_packet packet; |
28a35d8a HE |
1030 | const int chunks_per_read = 32; |
1031 | unsigned char buf[chunks_per_read * CHUNK_SIZE]; | |
6aac7737 | 1032 | int bufsz, numchunks, i, newchunks; |
94ba4bd6 | 1033 | uint64_t running_msec; |
28a35d8a | 1034 | struct timeval tv; |
28a35d8a | 1035 | |
cb93f8a9 UH |
1036 | (void)fd; |
1037 | (void)revents; | |
28a35d8a | 1038 | |
805919b0 | 1039 | /* Get the current position. */ |
0e1357e8 | 1040 | sigma_read_pos(&devc->state.stoppos, &devc->state.triggerpos, devc); |
805919b0 | 1041 | |
0e1357e8 | 1042 | numchunks = (devc->state.stoppos + 511) / 512; |
28a35d8a | 1043 | |
0e1357e8 | 1044 | if (devc->state.state == SIGMA_IDLE) |
805919b0 | 1045 | return TRUE; |
28a35d8a | 1046 | |
0e1357e8 | 1047 | if (devc->state.state == SIGMA_CAPTURE) { |
6aac7737 HE |
1048 | /* Check if the timer has expired, or memory is full. */ |
1049 | gettimeofday(&tv, 0); | |
0e1357e8 BV |
1050 | running_msec = (tv.tv_sec - devc->start_tv.tv_sec) * 1000 + |
1051 | (tv.tv_usec - devc->start_tv.tv_usec) / 1000; | |
28a35d8a | 1052 | |
0e1357e8 | 1053 | if (running_msec < devc->limit_msec && numchunks < 32767) |
805919b0 | 1054 | return TRUE; /* While capturing... */ |
e3fff420 | 1055 | else |
3ffb6964 | 1056 | hw_dev_acquisition_stop(sdi, sdi); |
6aac7737 | 1057 | |
dc890b8f UH |
1058 | } |
1059 | ||
1060 | if (devc->state.state == SIGMA_DOWNLOAD) { | |
0e1357e8 | 1061 | if (devc->state.chunks_downloaded >= numchunks) { |
6aac7737 | 1062 | /* End of samples. */ |
5a2326a7 | 1063 | packet.type = SR_DF_END; |
0e1357e8 | 1064 | sr_session_send(devc->session_dev_id, &packet); |
6aac7737 | 1065 | |
0e1357e8 | 1066 | devc->state.state = SIGMA_IDLE; |
f78898e9 | 1067 | |
6aac7737 HE |
1068 | return TRUE; |
1069 | } | |
1070 | ||
1071 | newchunks = MIN(chunks_per_read, | |
0e1357e8 | 1072 | numchunks - devc->state.chunks_downloaded); |
28a35d8a | 1073 | |
47f4f073 | 1074 | sr_info("Downloading sample data: %.0f %%.", |
0e1357e8 | 1075 | 100.0 * devc->state.chunks_downloaded / numchunks); |
28a35d8a | 1076 | |
0e1357e8 BV |
1077 | bufsz = sigma_read_dram(devc->state.chunks_downloaded, |
1078 | newchunks, buf, devc); | |
719c5a93 UH |
1079 | /* TODO: Check bufsz. For now, just avoid compiler warnings. */ |
1080 | (void)bufsz; | |
28a35d8a | 1081 | |
fefa1800 | 1082 | /* Find first ts. */ |
0e1357e8 BV |
1083 | if (devc->state.chunks_downloaded == 0) { |
1084 | devc->state.lastts = *(uint16_t *) buf - 1; | |
1085 | devc->state.lastsample = 0; | |
6aac7737 | 1086 | } |
28a35d8a | 1087 | |
fefa1800 | 1088 | /* Decode chunks and send them to sigrok. */ |
28a35d8a | 1089 | for (i = 0; i < newchunks; ++i) { |
88c51afe HE |
1090 | int limit_chunk = 0; |
1091 | ||
1092 | /* The last chunk may potentially be only in part. */ | |
0e1357e8 | 1093 | if (devc->state.chunks_downloaded == numchunks - 1) { |
88c51afe | 1094 | /* Find the last valid timestamp */ |
0e1357e8 | 1095 | limit_chunk = devc->state.stoppos % 512 + devc->state.lastts; |
88c51afe HE |
1096 | } |
1097 | ||
0e1357e8 | 1098 | if (devc->state.chunks_downloaded + i == devc->state.triggerchunk) |
57bbf56b | 1099 | decode_chunk_ts(buf + (i * CHUNK_SIZE), |
0e1357e8 BV |
1100 | &devc->state.lastts, |
1101 | &devc->state.lastsample, | |
1102 | devc->state.triggerpos & 0x1ff, | |
1f9813eb | 1103 | limit_chunk, sdi); |
57bbf56b HE |
1104 | else |
1105 | decode_chunk_ts(buf + (i * CHUNK_SIZE), | |
0e1357e8 BV |
1106 | &devc->state.lastts, |
1107 | &devc->state.lastsample, | |
1f9813eb | 1108 | -1, limit_chunk, sdi); |
28a35d8a | 1109 | |
0e1357e8 | 1110 | ++devc->state.chunks_downloaded; |
88c51afe | 1111 | } |
28a35d8a HE |
1112 | } |
1113 | ||
28a35d8a HE |
1114 | return TRUE; |
1115 | } | |
1116 | ||
c53d793f HE |
1117 | /* Build a LUT entry used by the trigger functions. */ |
1118 | static void build_lut_entry(uint16_t value, uint16_t mask, uint16_t *entry) | |
ee492173 HE |
1119 | { |
1120 | int i, j, k, bit; | |
1121 | ||
f758d074 | 1122 | /* For each quad probe. */ |
ee492173 | 1123 | for (i = 0; i < 4; ++i) { |
c53d793f | 1124 | entry[i] = 0xffff; |
ee492173 | 1125 | |
f758d074 | 1126 | /* For each bit in LUT. */ |
ee492173 HE |
1127 | for (j = 0; j < 16; ++j) |
1128 | ||
f758d074 | 1129 | /* For each probe in quad. */ |
ee492173 HE |
1130 | for (k = 0; k < 4; ++k) { |
1131 | bit = 1 << (i * 4 + k); | |
1132 | ||
c53d793f HE |
1133 | /* Set bit in entry */ |
1134 | if ((mask & bit) && | |
1135 | ((!(value & bit)) != | |
4ae1f451 | 1136 | (!(j & (1 << k))))) |
c53d793f | 1137 | entry[i] &= ~(1 << j); |
ee492173 HE |
1138 | } |
1139 | } | |
c53d793f | 1140 | } |
ee492173 | 1141 | |
c53d793f HE |
1142 | /* Add a logical function to LUT mask. */ |
1143 | static void add_trigger_function(enum triggerop oper, enum triggerfunc func, | |
1144 | int index, int neg, uint16_t *mask) | |
1145 | { | |
1146 | int i, j; | |
1147 | int x[2][2], tmp, a, b, aset, bset, rset; | |
1148 | ||
1149 | memset(x, 0, 4 * sizeof(int)); | |
1150 | ||
1151 | /* Trigger detect condition. */ | |
1152 | switch (oper) { | |
1153 | case OP_LEVEL: | |
1154 | x[0][1] = 1; | |
1155 | x[1][1] = 1; | |
1156 | break; | |
1157 | case OP_NOT: | |
1158 | x[0][0] = 1; | |
1159 | x[1][0] = 1; | |
1160 | break; | |
1161 | case OP_RISE: | |
1162 | x[0][1] = 1; | |
1163 | break; | |
1164 | case OP_FALL: | |
1165 | x[1][0] = 1; | |
1166 | break; | |
1167 | case OP_RISEFALL: | |
1168 | x[0][1] = 1; | |
1169 | x[1][0] = 1; | |
1170 | break; | |
1171 | case OP_NOTRISE: | |
1172 | x[1][1] = 1; | |
1173 | x[0][0] = 1; | |
1174 | x[1][0] = 1; | |
1175 | break; | |
1176 | case OP_NOTFALL: | |
1177 | x[1][1] = 1; | |
1178 | x[0][0] = 1; | |
1179 | x[0][1] = 1; | |
1180 | break; | |
1181 | case OP_NOTRISEFALL: | |
1182 | x[1][1] = 1; | |
1183 | x[0][0] = 1; | |
1184 | break; | |
1185 | } | |
1186 | ||
1187 | /* Transpose if neg is set. */ | |
1188 | if (neg) { | |
ea9cfed7 | 1189 | for (i = 0; i < 2; ++i) { |
c53d793f HE |
1190 | for (j = 0; j < 2; ++j) { |
1191 | tmp = x[i][j]; | |
1192 | x[i][j] = x[1-i][1-j]; | |
1193 | x[1-i][1-j] = tmp; | |
1194 | } | |
ea9cfed7 | 1195 | } |
c53d793f HE |
1196 | } |
1197 | ||
1198 | /* Update mask with function. */ | |
1199 | for (i = 0; i < 16; ++i) { | |
1200 | a = (i >> (2 * index + 0)) & 1; | |
1201 | b = (i >> (2 * index + 1)) & 1; | |
1202 | ||
1203 | aset = (*mask >> i) & 1; | |
1204 | bset = x[b][a]; | |
1205 | ||
1206 | if (func == FUNC_AND || func == FUNC_NAND) | |
1207 | rset = aset & bset; | |
1208 | else if (func == FUNC_OR || func == FUNC_NOR) | |
1209 | rset = aset | bset; | |
1210 | else if (func == FUNC_XOR || func == FUNC_NXOR) | |
1211 | rset = aset ^ bset; | |
1212 | ||
1213 | if (func == FUNC_NAND || func == FUNC_NOR || func == FUNC_NXOR) | |
1214 | rset = !rset; | |
1215 | ||
1216 | *mask &= ~(1 << i); | |
1217 | ||
1218 | if (rset) | |
1219 | *mask |= 1 << i; | |
1220 | } | |
1221 | } | |
1222 | ||
1223 | /* | |
1224 | * Build trigger LUTs used by 50 MHz and lower sample rates for supporting | |
1225 | * simple pin change and state triggers. Only two transitions (rise/fall) can be | |
1226 | * set at any time, but a full mask and value can be set (0/1). | |
1227 | */ | |
0e1357e8 | 1228 | static int build_basic_trigger(struct triggerlut *lut, struct dev_context *devc) |
c53d793f HE |
1229 | { |
1230 | int i,j; | |
4ae1f451 | 1231 | uint16_t masks[2] = { 0, 0 }; |
c53d793f HE |
1232 | |
1233 | memset(lut, 0, sizeof(struct triggerlut)); | |
1234 | ||
1235 | /* Contant for simple triggers. */ | |
1236 | lut->m4 = 0xa000; | |
1237 | ||
1238 | /* Value/mask trigger support. */ | |
0e1357e8 | 1239 | build_lut_entry(devc->trigger.simplevalue, devc->trigger.simplemask, |
99965709 | 1240 | lut->m2d); |
c53d793f HE |
1241 | |
1242 | /* Rise/fall trigger support. */ | |
1243 | for (i = 0, j = 0; i < 16; ++i) { | |
0e1357e8 BV |
1244 | if (devc->trigger.risingmask & (1 << i) || |
1245 | devc->trigger.fallingmask & (1 << i)) | |
c53d793f HE |
1246 | masks[j++] = 1 << i; |
1247 | } | |
1248 | ||
1249 | build_lut_entry(masks[0], masks[0], lut->m0d); | |
1250 | build_lut_entry(masks[1], masks[1], lut->m1d); | |
1251 | ||
1252 | /* Add glue logic */ | |
1253 | if (masks[0] || masks[1]) { | |
1254 | /* Transition trigger. */ | |
0e1357e8 | 1255 | if (masks[0] & devc->trigger.risingmask) |
c53d793f | 1256 | add_trigger_function(OP_RISE, FUNC_OR, 0, 0, &lut->m3); |
0e1357e8 | 1257 | if (masks[0] & devc->trigger.fallingmask) |
c53d793f | 1258 | add_trigger_function(OP_FALL, FUNC_OR, 0, 0, &lut->m3); |
0e1357e8 | 1259 | if (masks[1] & devc->trigger.risingmask) |
c53d793f | 1260 | add_trigger_function(OP_RISE, FUNC_OR, 1, 0, &lut->m3); |
0e1357e8 | 1261 | if (masks[1] & devc->trigger.fallingmask) |
c53d793f HE |
1262 | add_trigger_function(OP_FALL, FUNC_OR, 1, 0, &lut->m3); |
1263 | } else { | |
1264 | /* Only value/mask trigger. */ | |
1265 | lut->m3 = 0xffff; | |
1266 | } | |
ee492173 | 1267 | |
c53d793f | 1268 | /* Triggertype: event. */ |
ee492173 HE |
1269 | lut->params.selres = 3; |
1270 | ||
e46b8fb1 | 1271 | return SR_OK; |
ee492173 HE |
1272 | } |
1273 | ||
3ffb6964 BV |
1274 | static int hw_dev_acquisition_start(const struct sr_dev_inst *sdi, |
1275 | void *cb_data) | |
28a35d8a | 1276 | { |
0e1357e8 | 1277 | struct dev_context *devc; |
3c36c403 HE |
1278 | struct sr_datafeed_packet *packet; |
1279 | struct sr_datafeed_header *header; | |
f366e86c | 1280 | struct sr_datafeed_meta_logic meta; |
9ddb2a12 | 1281 | struct clockselect_50 clockselect; |
82957b65 | 1282 | int frac, triggerpin, ret; |
f4abaa9f | 1283 | uint8_t triggerselect = 0; |
57bbf56b | 1284 | struct triggerinout triggerinout_conf; |
ee492173 | 1285 | struct triggerlut lut; |
28a35d8a | 1286 | |
0e1357e8 | 1287 | devc = sdi->priv; |
28a35d8a | 1288 | |
014359e3 | 1289 | if (configure_probes(sdi) != SR_OK) { |
47f4f073 | 1290 | sr_err("Failed to configure probes."); |
014359e3 BV |
1291 | return SR_ERR; |
1292 | } | |
1293 | ||
ea9cfed7 | 1294 | /* If the samplerate has not been set, default to 200 kHz. */ |
0e1357e8 | 1295 | if (devc->cur_firmware == -1) { |
82957b65 UH |
1296 | if ((ret = set_samplerate(sdi, SR_KHZ(200))) != SR_OK) |
1297 | return ret; | |
1298 | } | |
e8397563 | 1299 | |
eec5275e | 1300 | /* Enter trigger programming mode. */ |
0e1357e8 | 1301 | sigma_set_register(WRITE_TRIGGER_SELECT1, 0x20, devc); |
28a35d8a | 1302 | |
eec5275e | 1303 | /* 100 and 200 MHz mode. */ |
0e1357e8 BV |
1304 | if (devc->cur_samplerate >= SR_MHZ(100)) { |
1305 | sigma_set_register(WRITE_TRIGGER_SELECT1, 0x81, devc); | |
57bbf56b | 1306 | |
a42aec7f HE |
1307 | /* Find which pin to trigger on from mask. */ |
1308 | for (triggerpin = 0; triggerpin < 8; ++triggerpin) | |
0e1357e8 | 1309 | if ((devc->trigger.risingmask | devc->trigger.fallingmask) & |
a42aec7f HE |
1310 | (1 << triggerpin)) |
1311 | break; | |
1312 | ||
1313 | /* Set trigger pin and light LED on trigger. */ | |
1314 | triggerselect = (1 << LEDSEL1) | (triggerpin & 0x7); | |
1315 | ||
1316 | /* Default rising edge. */ | |
0e1357e8 | 1317 | if (devc->trigger.fallingmask) |
a42aec7f | 1318 | triggerselect |= 1 << 3; |
57bbf56b | 1319 | |
eec5275e | 1320 | /* All other modes. */ |
0e1357e8 BV |
1321 | } else if (devc->cur_samplerate <= SR_MHZ(50)) { |
1322 | build_basic_trigger(&lut, devc); | |
ee492173 | 1323 | |
0e1357e8 | 1324 | sigma_write_trigger_lut(&lut, devc); |
57bbf56b HE |
1325 | |
1326 | triggerselect = (1 << LEDSEL1) | (1 << LEDSEL0); | |
1327 | } | |
1328 | ||
eec5275e | 1329 | /* Setup trigger in and out pins to default values. */ |
57bbf56b HE |
1330 | memset(&triggerinout_conf, 0, sizeof(struct triggerinout)); |
1331 | triggerinout_conf.trgout_bytrigger = 1; | |
1332 | triggerinout_conf.trgout_enable = 1; | |
1333 | ||
28a35d8a | 1334 | sigma_write_register(WRITE_TRIGGER_OPTION, |
57bbf56b | 1335 | (uint8_t *) &triggerinout_conf, |
0e1357e8 | 1336 | sizeof(struct triggerinout), devc); |
28a35d8a | 1337 | |
eec5275e | 1338 | /* Go back to normal mode. */ |
0e1357e8 | 1339 | sigma_set_register(WRITE_TRIGGER_SELECT1, triggerselect, devc); |
28a35d8a | 1340 | |
edca2c5c | 1341 | /* Set clock select register. */ |
0e1357e8 | 1342 | if (devc->cur_samplerate == SR_MHZ(200)) |
edca2c5c | 1343 | /* Enable 4 probes. */ |
0e1357e8 BV |
1344 | sigma_set_register(WRITE_CLOCK_SELECT, 0xf0, devc); |
1345 | else if (devc->cur_samplerate == SR_MHZ(100)) | |
edca2c5c | 1346 | /* Enable 8 probes. */ |
0e1357e8 | 1347 | sigma_set_register(WRITE_CLOCK_SELECT, 0x00, devc); |
edca2c5c HE |
1348 | else { |
1349 | /* | |
9ddb2a12 | 1350 | * 50 MHz mode (or fraction thereof). Any fraction down to |
eec5275e | 1351 | * 50 MHz / 256 can be used, but is not supported by sigrok API. |
edca2c5c | 1352 | */ |
0e1357e8 | 1353 | frac = SR_MHZ(50) / devc->cur_samplerate - 1; |
edca2c5c | 1354 | |
9ddb2a12 UH |
1355 | clockselect.async = 0; |
1356 | clockselect.fraction = frac; | |
1357 | clockselect.disabled_probes = 0; | |
edca2c5c HE |
1358 | |
1359 | sigma_write_register(WRITE_CLOCK_SELECT, | |
9ddb2a12 | 1360 | (uint8_t *) &clockselect, |
0e1357e8 | 1361 | sizeof(clockselect), devc); |
edca2c5c HE |
1362 | } |
1363 | ||
fefa1800 | 1364 | /* Setup maximum post trigger time. */ |
99965709 | 1365 | sigma_set_register(WRITE_POST_TRIGGER, |
0e1357e8 | 1366 | (devc->capture_ratio * 255) / 100, devc); |
28a35d8a | 1367 | |
eec5275e | 1368 | /* Start acqusition. */ |
0e1357e8 BV |
1369 | gettimeofday(&devc->start_tv, 0); |
1370 | sigma_set_register(WRITE_MODE, 0x0d, devc); | |
99965709 | 1371 | |
0e1357e8 | 1372 | devc->session_dev_id = cb_data; |
28a35d8a | 1373 | |
3c36c403 | 1374 | if (!(packet = g_try_malloc(sizeof(struct sr_datafeed_packet)))) { |
47f4f073 | 1375 | sr_err("%s: packet malloc failed.", __func__); |
3c36c403 HE |
1376 | return SR_ERR_MALLOC; |
1377 | } | |
1378 | ||
1379 | if (!(header = g_try_malloc(sizeof(struct sr_datafeed_header)))) { | |
47f4f073 | 1380 | sr_err("%s: header malloc failed.", __func__); |
3c36c403 HE |
1381 | return SR_ERR_MALLOC; |
1382 | } | |
28a35d8a | 1383 | |
3c36c403 HE |
1384 | /* Send header packet to the session bus. */ |
1385 | packet->type = SR_DF_HEADER; | |
1386 | packet->payload = header; | |
1387 | header->feed_version = 1; | |
1388 | gettimeofday(&header->starttime, NULL); | |
0e1357e8 | 1389 | sr_session_send(devc->session_dev_id, packet); |
f366e86c BV |
1390 | |
1391 | /* Send metadata about the SR_DF_LOGIC packets to come. */ | |
1392 | packet->type = SR_DF_META_LOGIC; | |
1393 | packet->payload = &meta; | |
0e1357e8 BV |
1394 | meta.samplerate = devc->cur_samplerate; |
1395 | meta.num_probes = devc->num_probes; | |
1396 | sr_session_send(devc->session_dev_id, packet); | |
f366e86c BV |
1397 | |
1398 | /* Add capture source. */ | |
3ffb6964 | 1399 | sr_source_add(0, G_IO_IN, 10, receive_data, (void *)sdi); |
f366e86c | 1400 | |
3c36c403 HE |
1401 | g_free(header); |
1402 | g_free(packet); | |
1403 | ||
0e1357e8 | 1404 | devc->state.state = SIGMA_CAPTURE; |
6aac7737 | 1405 | |
e46b8fb1 | 1406 | return SR_OK; |
28a35d8a HE |
1407 | } |
1408 | ||
69b07d14 | 1409 | static int hw_dev_acquisition_stop(struct sr_dev_inst *sdi, void *cb_data) |
28a35d8a | 1410 | { |
0e1357e8 | 1411 | struct dev_context *devc; |
6aac7737 HE |
1412 | uint8_t modestatus; |
1413 | ||
3cd3a20b | 1414 | (void)cb_data; |
28a35d8a | 1415 | |
503c4afb BV |
1416 | sr_source_remove(0); |
1417 | ||
0e1357e8 | 1418 | if (!(devc = sdi->priv)) { |
47f4f073 | 1419 | sr_err("%s: sdi->priv was NULL", __func__); |
3010f21c UH |
1420 | return SR_ERR_BUG; |
1421 | } | |
1422 | ||
fefa1800 | 1423 | /* Stop acquisition. */ |
0e1357e8 | 1424 | sigma_set_register(WRITE_MODE, 0x11, devc); |
28a35d8a | 1425 | |
6aac7737 | 1426 | /* Set SDRAM Read Enable. */ |
0e1357e8 | 1427 | sigma_set_register(WRITE_MODE, 0x02, devc); |
6aac7737 HE |
1428 | |
1429 | /* Get the current position. */ | |
0e1357e8 | 1430 | sigma_read_pos(&devc->state.stoppos, &devc->state.triggerpos, devc); |
6aac7737 HE |
1431 | |
1432 | /* Check if trigger has fired. */ | |
0e1357e8 | 1433 | modestatus = sigma_get_register(READ_MODE, devc); |
3010f21c | 1434 | if (modestatus & 0x20) |
0e1357e8 | 1435 | devc->state.triggerchunk = devc->state.triggerpos / 512; |
3010f21c | 1436 | else |
0e1357e8 | 1437 | devc->state.triggerchunk = -1; |
6aac7737 | 1438 | |
0e1357e8 | 1439 | devc->state.chunks_downloaded = 0; |
6aac7737 | 1440 | |
0e1357e8 | 1441 | devc->state.state = SIGMA_DOWNLOAD; |
3010f21c UH |
1442 | |
1443 | return SR_OK; | |
28a35d8a HE |
1444 | } |
1445 | ||
c09f0b57 | 1446 | SR_PRIV struct sr_dev_driver asix_sigma_driver_info = { |
e519ba86 | 1447 | .name = "asix-sigma", |
6352d030 | 1448 | .longname = "ASIX SIGMA/SIGMA2", |
e519ba86 UH |
1449 | .api_version = 1, |
1450 | .init = hw_init, | |
1451 | .cleanup = hw_cleanup, | |
61136ea6 | 1452 | .scan = hw_scan, |
811deee4 BV |
1453 | .dev_list = hw_dev_list, |
1454 | .dev_clear = clear_instances, | |
e7eb703f UH |
1455 | .dev_open = hw_dev_open, |
1456 | .dev_close = hw_dev_close, | |
41479605 | 1457 | .info_get = hw_info_get, |
a9a245b4 | 1458 | .dev_config_set = hw_dev_config_set, |
6b3dfec8 UH |
1459 | .dev_acquisition_start = hw_dev_acquisition_start, |
1460 | .dev_acquisition_stop = hw_dev_acquisition_stop, | |
0e1357e8 | 1461 | .priv = NULL, |
28a35d8a | 1462 | }; |