]>
Commit | Line | Data |
---|---|---|
28a35d8a HE |
1 | /* |
2 | * This file is part of the sigrok project. | |
3 | * | |
868501fa | 4 | * Copyright (C) 2010-2012 Håvard Espeland <gus@ping.uio.no>, |
911f1834 UH |
5 | * Copyright (C) 2010 Martin Stensgård <mastensg@ping.uio.no> |
6 | * Copyright (C) 2010 Carl Henrik Lunde <chlunde@ping.uio.no> | |
28a35d8a HE |
7 | * |
8 | * This program is free software: you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation, either version 3 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
20 | */ | |
21 | ||
911f1834 | 22 | /* |
6352d030 | 23 | * ASIX SIGMA/SIGMA2 logic analyzer driver |
911f1834 UH |
24 | */ |
25 | ||
3bbd9849 UH |
26 | #include <glib.h> |
27 | #include <glib/gstdio.h> | |
28a35d8a HE |
28 | #include <ftdi.h> |
29 | #include <string.h> | |
45c59c8b BV |
30 | #include "libsigrok.h" |
31 | #include "libsigrok-internal.h" | |
28a35d8a HE |
32 | #include "asix-sigma.h" |
33 | ||
34 | #define USB_VENDOR 0xa600 | |
35 | #define USB_PRODUCT 0xa000 | |
36 | #define USB_DESCRIPTION "ASIX SIGMA" | |
37 | #define USB_VENDOR_NAME "ASIX" | |
38 | #define USB_MODEL_NAME "SIGMA" | |
39 | #define USB_MODEL_VERSION "" | |
ee492173 | 40 | #define TRIGGER_TYPES "rf10" |
464d12c7 | 41 | #define NUM_PROBES 16 |
28a35d8a | 42 | |
ed300b9f BV |
43 | SR_PRIV struct sr_dev_driver asix_sigma_driver_info; |
44 | static struct sr_dev_driver *adi = &asix_sigma_driver_info; | |
28a35d8a | 45 | |
a533743d | 46 | static const uint64_t supported_samplerates[] = { |
59df0c77 UH |
47 | SR_KHZ(200), |
48 | SR_KHZ(250), | |
49 | SR_KHZ(500), | |
50 | SR_MHZ(1), | |
51 | SR_MHZ(5), | |
52 | SR_MHZ(10), | |
53 | SR_MHZ(25), | |
54 | SR_MHZ(50), | |
55 | SR_MHZ(100), | |
56 | SR_MHZ(200), | |
28a35d8a HE |
57 | 0, |
58 | }; | |
59 | ||
d261dbbf UH |
60 | /* |
61 | * Probe numbers seem to go from 1-16, according to this image: | |
62 | * http://tools.asix.net/img/sigma_sigmacab_pins_720.jpg | |
63 | * (the cable has two additional GND pins, and a TI and TO pin) | |
64 | */ | |
c37d2b1b | 65 | static const char *probe_names[NUM_PROBES + 1] = { |
464d12c7 KS |
66 | "1", |
67 | "2", | |
68 | "3", | |
69 | "4", | |
70 | "5", | |
71 | "6", | |
72 | "7", | |
73 | "8", | |
74 | "9", | |
75 | "10", | |
76 | "11", | |
77 | "12", | |
78 | "13", | |
79 | "14", | |
80 | "15", | |
d261dbbf | 81 | "16", |
464d12c7 KS |
82 | NULL, |
83 | }; | |
84 | ||
a533743d | 85 | static const struct sr_samplerates samplerates = { |
590b9f9a UH |
86 | 0, |
87 | 0, | |
88 | 0, | |
28a35d8a HE |
89 | supported_samplerates, |
90 | }; | |
91 | ||
915f7cc8 | 92 | static const int hwcaps[] = { |
5a2326a7 UH |
93 | SR_HWCAP_LOGIC_ANALYZER, |
94 | SR_HWCAP_SAMPLERATE, | |
95 | SR_HWCAP_CAPTURE_RATIO, | |
96 | SR_HWCAP_PROBECONFIG, | |
28a35d8a | 97 | |
5a2326a7 | 98 | SR_HWCAP_LIMIT_MSEC, |
28a35d8a HE |
99 | 0, |
100 | }; | |
101 | ||
fefa1800 UH |
102 | /* Force the FPGA to reboot. */ |
103 | static uint8_t suicide[] = { | |
104 | 0x84, 0x84, 0x88, 0x84, 0x88, 0x84, 0x88, 0x84, | |
105 | }; | |
106 | ||
107 | /* Prepare to upload firmware (FPGA specific). */ | |
108 | static uint8_t init[] = { | |
109 | 0x03, 0x03, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, | |
110 | }; | |
111 | ||
112 | /* Initialize the logic analyzer mode. */ | |
113 | static uint8_t logic_mode_start[] = { | |
114 | 0x00, 0x40, 0x0f, 0x25, 0x35, 0x40, | |
115 | 0x2a, 0x3a, 0x40, 0x03, 0x20, 0x38, | |
116 | }; | |
117 | ||
eec5275e | 118 | static const char *firmware_files[] = { |
a8116d76 HE |
119 | "asix-sigma-50.fw", /* 50 MHz, supports 8 bit fractions */ |
120 | "asix-sigma-100.fw", /* 100 MHz */ | |
121 | "asix-sigma-200.fw", /* 200 MHz */ | |
ed09fd07 | 122 | "asix-sigma-50sync.fw", /* Synchronous clock from pin */ |
a8116d76 | 123 | "asix-sigma-phasor.fw", /* Frequency counter */ |
f6564c8d HE |
124 | }; |
125 | ||
3ffb6964 BV |
126 | static int hw_dev_acquisition_stop(const struct sr_dev_inst *sdi, |
127 | void *cb_data); | |
6aac7737 | 128 | |
0e1357e8 | 129 | static int sigma_read(void *buf, size_t size, struct dev_context *devc) |
28a35d8a HE |
130 | { |
131 | int ret; | |
fefa1800 | 132 | |
0e1357e8 | 133 | ret = ftdi_read_data(&devc->ftdic, (unsigned char *)buf, size); |
28a35d8a | 134 | if (ret < 0) { |
7b48d6e1 | 135 | sr_err("sigma: ftdi_read_data failed: %s", |
0e1357e8 | 136 | ftdi_get_error_string(&devc->ftdic)); |
28a35d8a HE |
137 | } |
138 | ||
139 | return ret; | |
140 | } | |
141 | ||
0e1357e8 | 142 | static int sigma_write(void *buf, size_t size, struct dev_context *devc) |
28a35d8a HE |
143 | { |
144 | int ret; | |
fefa1800 | 145 | |
0e1357e8 | 146 | ret = ftdi_write_data(&devc->ftdic, (unsigned char *)buf, size); |
28a35d8a | 147 | if (ret < 0) { |
7b48d6e1 | 148 | sr_err("sigma: ftdi_write_data failed: %s", |
0e1357e8 | 149 | ftdi_get_error_string(&devc->ftdic)); |
fefa1800 | 150 | } else if ((size_t) ret != size) { |
0aeb0ccd | 151 | sr_err("sigma: ftdi_write_data did not complete write."); |
28a35d8a HE |
152 | } |
153 | ||
154 | return ret; | |
155 | } | |
156 | ||
99965709 | 157 | static int sigma_write_register(uint8_t reg, uint8_t *data, size_t len, |
0e1357e8 | 158 | struct dev_context *devc) |
28a35d8a HE |
159 | { |
160 | size_t i; | |
161 | uint8_t buf[len + 2]; | |
162 | int idx = 0; | |
163 | ||
164 | buf[idx++] = REG_ADDR_LOW | (reg & 0xf); | |
165 | buf[idx++] = REG_ADDR_HIGH | (reg >> 4); | |
166 | ||
fefa1800 | 167 | for (i = 0; i < len; ++i) { |
28a35d8a HE |
168 | buf[idx++] = REG_DATA_LOW | (data[i] & 0xf); |
169 | buf[idx++] = REG_DATA_HIGH_WRITE | (data[i] >> 4); | |
170 | } | |
171 | ||
0e1357e8 | 172 | return sigma_write(buf, idx, devc); |
28a35d8a HE |
173 | } |
174 | ||
0e1357e8 | 175 | static int sigma_set_register(uint8_t reg, uint8_t value, struct dev_context *devc) |
28a35d8a | 176 | { |
0e1357e8 | 177 | return sigma_write_register(reg, &value, 1, devc); |
28a35d8a HE |
178 | } |
179 | ||
99965709 | 180 | static int sigma_read_register(uint8_t reg, uint8_t *data, size_t len, |
0e1357e8 | 181 | struct dev_context *devc) |
28a35d8a HE |
182 | { |
183 | uint8_t buf[3]; | |
fefa1800 | 184 | |
28a35d8a HE |
185 | buf[0] = REG_ADDR_LOW | (reg & 0xf); |
186 | buf[1] = REG_ADDR_HIGH | (reg >> 4); | |
28a35d8a HE |
187 | buf[2] = REG_READ_ADDR; |
188 | ||
0e1357e8 | 189 | sigma_write(buf, sizeof(buf), devc); |
28a35d8a | 190 | |
0e1357e8 | 191 | return sigma_read(data, len, devc); |
28a35d8a HE |
192 | } |
193 | ||
0e1357e8 | 194 | static uint8_t sigma_get_register(uint8_t reg, struct dev_context *devc) |
28a35d8a HE |
195 | { |
196 | uint8_t value; | |
fefa1800 | 197 | |
0e1357e8 | 198 | if (1 != sigma_read_register(reg, &value, 1, devc)) { |
7b48d6e1 | 199 | sr_err("sigma: sigma_get_register: 1 byte expected"); |
28a35d8a HE |
200 | return 0; |
201 | } | |
202 | ||
203 | return value; | |
204 | } | |
205 | ||
99965709 | 206 | static int sigma_read_pos(uint32_t *stoppos, uint32_t *triggerpos, |
0e1357e8 | 207 | struct dev_context *devc) |
28a35d8a HE |
208 | { |
209 | uint8_t buf[] = { | |
210 | REG_ADDR_LOW | READ_TRIGGER_POS_LOW, | |
211 | ||
212 | REG_READ_ADDR | NEXT_REG, | |
213 | REG_READ_ADDR | NEXT_REG, | |
214 | REG_READ_ADDR | NEXT_REG, | |
215 | REG_READ_ADDR | NEXT_REG, | |
216 | REG_READ_ADDR | NEXT_REG, | |
217 | REG_READ_ADDR | NEXT_REG, | |
218 | }; | |
28a35d8a HE |
219 | uint8_t result[6]; |
220 | ||
0e1357e8 | 221 | sigma_write(buf, sizeof(buf), devc); |
28a35d8a | 222 | |
0e1357e8 | 223 | sigma_read(result, sizeof(result), devc); |
28a35d8a HE |
224 | |
225 | *triggerpos = result[0] | (result[1] << 8) | (result[2] << 16); | |
226 | *stoppos = result[3] | (result[4] << 8) | (result[5] << 16); | |
227 | ||
57bbf56b HE |
228 | /* Not really sure why this must be done, but according to spec. */ |
229 | if ((--*stoppos & 0x1ff) == 0x1ff) | |
230 | stoppos -= 64; | |
231 | ||
232 | if ((*--triggerpos & 0x1ff) == 0x1ff) | |
233 | triggerpos -= 64; | |
234 | ||
28a35d8a HE |
235 | return 1; |
236 | } | |
237 | ||
99965709 | 238 | static int sigma_read_dram(uint16_t startchunk, size_t numchunks, |
0e1357e8 | 239 | uint8_t *data, struct dev_context *devc) |
28a35d8a HE |
240 | { |
241 | size_t i; | |
242 | uint8_t buf[4096]; | |
243 | int idx = 0; | |
244 | ||
fefa1800 | 245 | /* Send the startchunk. Index start with 1. */ |
28a35d8a HE |
246 | buf[0] = startchunk >> 8; |
247 | buf[1] = startchunk & 0xff; | |
0e1357e8 | 248 | sigma_write_register(WRITE_MEMROW, buf, 2, devc); |
28a35d8a | 249 | |
fefa1800 | 250 | /* Read the DRAM. */ |
28a35d8a HE |
251 | buf[idx++] = REG_DRAM_BLOCK; |
252 | buf[idx++] = REG_DRAM_WAIT_ACK; | |
253 | ||
254 | for (i = 0; i < numchunks; ++i) { | |
fefa1800 UH |
255 | /* Alternate bit to copy from DRAM to cache. */ |
256 | if (i != (numchunks - 1)) | |
257 | buf[idx++] = REG_DRAM_BLOCK | (((i + 1) % 2) << 4); | |
28a35d8a HE |
258 | |
259 | buf[idx++] = REG_DRAM_BLOCK_DATA | ((i % 2) << 4); | |
260 | ||
fefa1800 | 261 | if (i != (numchunks - 1)) |
28a35d8a HE |
262 | buf[idx++] = REG_DRAM_WAIT_ACK; |
263 | } | |
264 | ||
0e1357e8 | 265 | sigma_write(buf, idx, devc); |
28a35d8a | 266 | |
0e1357e8 | 267 | return sigma_read(data, numchunks * CHUNK_SIZE, devc); |
28a35d8a HE |
268 | } |
269 | ||
4ae1f451 | 270 | /* Upload trigger look-up tables to Sigma. */ |
0e1357e8 | 271 | static int sigma_write_trigger_lut(struct triggerlut *lut, struct dev_context *devc) |
ee492173 HE |
272 | { |
273 | int i; | |
274 | uint8_t tmp[2]; | |
275 | uint16_t bit; | |
276 | ||
277 | /* Transpose the table and send to Sigma. */ | |
278 | for (i = 0; i < 16; ++i) { | |
279 | bit = 1 << i; | |
280 | ||
281 | tmp[0] = tmp[1] = 0; | |
282 | ||
283 | if (lut->m2d[0] & bit) | |
284 | tmp[0] |= 0x01; | |
285 | if (lut->m2d[1] & bit) | |
286 | tmp[0] |= 0x02; | |
287 | if (lut->m2d[2] & bit) | |
288 | tmp[0] |= 0x04; | |
289 | if (lut->m2d[3] & bit) | |
290 | tmp[0] |= 0x08; | |
291 | ||
292 | if (lut->m3 & bit) | |
293 | tmp[0] |= 0x10; | |
294 | if (lut->m3s & bit) | |
295 | tmp[0] |= 0x20; | |
296 | if (lut->m4 & bit) | |
297 | tmp[0] |= 0x40; | |
298 | ||
299 | if (lut->m0d[0] & bit) | |
300 | tmp[1] |= 0x01; | |
301 | if (lut->m0d[1] & bit) | |
302 | tmp[1] |= 0x02; | |
303 | if (lut->m0d[2] & bit) | |
304 | tmp[1] |= 0x04; | |
305 | if (lut->m0d[3] & bit) | |
306 | tmp[1] |= 0x08; | |
307 | ||
308 | if (lut->m1d[0] & bit) | |
309 | tmp[1] |= 0x10; | |
310 | if (lut->m1d[1] & bit) | |
311 | tmp[1] |= 0x20; | |
312 | if (lut->m1d[2] & bit) | |
313 | tmp[1] |= 0x40; | |
314 | if (lut->m1d[3] & bit) | |
315 | tmp[1] |= 0x80; | |
316 | ||
99965709 | 317 | sigma_write_register(WRITE_TRIGGER_SELECT0, tmp, sizeof(tmp), |
0e1357e8 BV |
318 | devc); |
319 | sigma_set_register(WRITE_TRIGGER_SELECT1, 0x30 | i, devc); | |
ee492173 HE |
320 | } |
321 | ||
322 | /* Send the parameters */ | |
323 | sigma_write_register(WRITE_TRIGGER_SELECT0, (uint8_t *) &lut->params, | |
0e1357e8 | 324 | sizeof(lut->params), devc); |
ee492173 | 325 | |
e46b8fb1 | 326 | return SR_OK; |
ee492173 HE |
327 | } |
328 | ||
fefa1800 | 329 | /* Generate the bitbang stream for programming the FPGA. */ |
28a35d8a | 330 | static int bin2bitbang(const char *filename, |
fefa1800 | 331 | unsigned char **buf, size_t *buf_size) |
28a35d8a | 332 | { |
fefa1800 | 333 | FILE *f; |
e3fff420 | 334 | unsigned long file_size; |
28a35d8a HE |
335 | unsigned long offset = 0; |
336 | unsigned char *p; | |
e3fff420 HE |
337 | uint8_t *firmware; |
338 | unsigned long fwsize = 0; | |
28a35d8a HE |
339 | const int buffer_size = 65536; |
340 | size_t i; | |
e3fff420 | 341 | int c, bit, v; |
fefa1800 | 342 | uint32_t imm = 0x3f6df2ab; |
28a35d8a | 343 | |
868d8cef | 344 | f = g_fopen(filename, "rb"); |
28a35d8a | 345 | if (!f) { |
7b48d6e1 | 346 | sr_err("sigma: g_fopen(\"%s\", \"rb\")", filename); |
b53738ba | 347 | return SR_ERR; |
28a35d8a HE |
348 | } |
349 | ||
350 | if (-1 == fseek(f, 0, SEEK_END)) { | |
7b48d6e1 | 351 | sr_err("sigma: fseek on %s failed", filename); |
28a35d8a | 352 | fclose(f); |
b53738ba | 353 | return SR_ERR; |
28a35d8a HE |
354 | } |
355 | ||
356 | file_size = ftell(f); | |
357 | ||
358 | fseek(f, 0, SEEK_SET); | |
359 | ||
b53738ba | 360 | if (!(firmware = g_try_malloc(buffer_size))) { |
340cfac0 | 361 | sr_err("sigma: %s: firmware malloc failed", __func__); |
12ad53f5 | 362 | fclose(f); |
b53738ba | 363 | return SR_ERR_MALLOC; |
28a35d8a HE |
364 | } |
365 | ||
28a35d8a HE |
366 | while ((c = getc(f)) != EOF) { |
367 | imm = (imm + 0xa853753) % 177 + (imm * 0x8034052); | |
e3fff420 | 368 | firmware[fwsize++] = c ^ imm; |
28a35d8a HE |
369 | } |
370 | fclose(f); | |
371 | ||
e3fff420 HE |
372 | if(fwsize != file_size) { |
373 | sr_err("sigma: %s: Error reading firmware", filename); | |
374 | fclose(f); | |
375 | g_free(firmware); | |
376 | return SR_ERR; | |
28a35d8a HE |
377 | } |
378 | ||
28a35d8a HE |
379 | *buf_size = fwsize * 2 * 8; |
380 | ||
b53738ba | 381 | *buf = p = (unsigned char *)g_try_malloc(*buf_size); |
28a35d8a | 382 | if (!p) { |
340cfac0 | 383 | sr_err("sigma: %s: buf/p malloc failed", __func__); |
12ad53f5 | 384 | g_free(firmware); |
b53738ba | 385 | return SR_ERR_MALLOC; |
28a35d8a HE |
386 | } |
387 | ||
388 | for (i = 0; i < fwsize; ++i) { | |
28a35d8a | 389 | for (bit = 7; bit >= 0; --bit) { |
fefa1800 | 390 | v = firmware[i] & 1 << bit ? 0x40 : 0x00; |
28a35d8a HE |
391 | p[offset++] = v | 0x01; |
392 | p[offset++] = v; | |
393 | } | |
394 | } | |
395 | ||
396 | g_free(firmware); | |
397 | ||
398 | if (offset != *buf_size) { | |
399 | g_free(*buf); | |
7b48d6e1 | 400 | sr_err("sigma: Error reading firmware %s " |
0aeb0ccd | 401 | "offset=%ld, file_size=%ld, buf_size=%zd.", |
133a37bf | 402 | filename, offset, file_size, *buf_size); |
28a35d8a | 403 | |
b53738ba | 404 | return SR_ERR; |
28a35d8a HE |
405 | } |
406 | ||
b53738ba | 407 | return SR_OK; |
28a35d8a HE |
408 | } |
409 | ||
0448d110 BV |
410 | static void clear_instances(void) |
411 | { | |
412 | GSList *l; | |
413 | struct sr_dev_inst *sdi; | |
0e1357e8 BV |
414 | struct drv_context *drvc; |
415 | struct dev_context *devc; | |
416 | ||
417 | drvc = adi->priv; | |
0448d110 BV |
418 | |
419 | /* Properly close all devices. */ | |
0e1357e8 | 420 | for (l = drvc->instances; l; l = l->next) { |
0448d110 BV |
421 | if (!(sdi = l->data)) { |
422 | /* Log error, but continue cleaning up the rest. */ | |
423 | sr_err("sigma: %s: sdi was NULL, continuing", __func__); | |
424 | continue; | |
425 | } | |
426 | if (sdi->priv) { | |
0e1357e8 BV |
427 | devc = sdi->priv; |
428 | ftdi_free(&devc->ftdic); | |
429 | g_free(devc); | |
0448d110 BV |
430 | } |
431 | sr_dev_inst_free(sdi); | |
432 | } | |
0e1357e8 BV |
433 | g_slist_free(drvc->instances); |
434 | drvc->instances = NULL; | |
0448d110 BV |
435 | |
436 | } | |
437 | ||
40dda2c3 | 438 | static int hw_init(void) |
61136ea6 | 439 | { |
b32503cc | 440 | struct drv_context *drvc; |
61136ea6 | 441 | |
b32503cc BV |
442 | if (!(drvc = g_try_malloc0(sizeof(struct drv_context)))) { |
443 | sr_err("asix-sigma: driver context malloc failed."); | |
444 | return SR_ERR; | |
445 | } | |
446 | adi->priv = drvc; | |
61136ea6 BV |
447 | |
448 | return SR_OK; | |
449 | } | |
450 | ||
0448d110 | 451 | static GSList *hw_scan(GSList *options) |
28a35d8a | 452 | { |
d68e2d1a | 453 | struct sr_dev_inst *sdi; |
87ca93c5 | 454 | struct sr_probe *probe; |
0e1357e8 BV |
455 | struct drv_context *drvc; |
456 | struct dev_context *devc; | |
0448d110 | 457 | GSList *devices; |
e3fff420 HE |
458 | struct ftdi_device_list *devlist; |
459 | char serial_txt[10]; | |
460 | uint32_t serial; | |
87ca93c5 | 461 | int ret, i; |
28a35d8a | 462 | |
0448d110 | 463 | (void)options; |
0e1357e8 | 464 | drvc = adi->priv; |
0448d110 BV |
465 | devices = NULL; |
466 | clear_instances(); | |
467 | ||
0e1357e8 BV |
468 | if (!(devc = g_try_malloc(sizeof(struct dev_context)))) { |
469 | sr_err("sigma: %s: devc malloc failed", __func__); | |
0448d110 | 470 | return NULL; |
b53738ba | 471 | } |
99965709 | 472 | |
0e1357e8 | 473 | ftdi_init(&devc->ftdic); |
28a35d8a | 474 | |
fefa1800 | 475 | /* Look for SIGMAs. */ |
e3fff420 | 476 | |
0e1357e8 | 477 | if ((ret = ftdi_usb_find_all(&devc->ftdic, &devlist, |
eec944c5 BV |
478 | USB_VENDOR, USB_PRODUCT)) <= 0) { |
479 | if (ret < 0) | |
480 | sr_err("ftdi_usb_find_all(): %d", ret); | |
99965709 | 481 | goto free; |
eec944c5 | 482 | } |
99965709 | 483 | |
e3fff420 | 484 | /* Make sure it's a version 1 or 2 SIGMA. */ |
0e1357e8 | 485 | ftdi_usb_get_strings(&devc->ftdic, devlist->dev, NULL, 0, NULL, 0, |
6352d030 | 486 | serial_txt, sizeof(serial_txt)); |
e3fff420 HE |
487 | sscanf(serial_txt, "%x", &serial); |
488 | ||
6352d030 | 489 | if (serial < 0xa6010000 || serial > 0xa602ffff) { |
e3fff420 | 490 | sr_err("sigma: Only SIGMA and SIGMA2 are supported " |
6352d030 | 491 | "in this version of sigrok."); |
e3fff420 HE |
492 | goto free; |
493 | } | |
494 | ||
495 | sr_info("Found ASIX SIGMA - Serial: %s", serial_txt); | |
496 | ||
0e1357e8 BV |
497 | devc->cur_samplerate = 0; |
498 | devc->period_ps = 0; | |
499 | devc->limit_msec = 0; | |
500 | devc->cur_firmware = -1; | |
501 | devc->num_probes = 0; | |
502 | devc->samples_per_event = 0; | |
503 | devc->capture_ratio = 50; | |
504 | devc->use_triggers = 0; | |
28a35d8a | 505 | |
fefa1800 | 506 | /* Register SIGMA device. */ |
d68e2d1a UH |
507 | if (!(sdi = sr_dev_inst_new(0, SR_ST_INITIALIZING, USB_VENDOR_NAME, |
508 | USB_MODEL_NAME, USB_MODEL_VERSION))) { | |
509 | sr_err("sigma: %s: sdi was NULL", __func__); | |
99965709 | 510 | goto free; |
d68e2d1a | 511 | } |
d7bbecfd | 512 | sdi->driver = adi; |
87ca93c5 BV |
513 | |
514 | for (i = 0; probe_names[i]; i++) { | |
515 | if (!(probe = sr_probe_new(i, SR_PROBE_ANALOG, TRUE, | |
516 | probe_names[i]))) | |
517 | return NULL; | |
518 | sdi->probes = g_slist_append(sdi->probes, probe); | |
519 | } | |
520 | ||
0448d110 | 521 | devices = g_slist_append(devices, sdi); |
0e1357e8 BV |
522 | drvc->instances = g_slist_append(drvc->instances, sdi); |
523 | sdi->priv = devc; | |
28a35d8a | 524 | |
fefa1800 | 525 | /* We will open the device again when we need it. */ |
e3fff420 | 526 | ftdi_list_free(&devlist); |
28a35d8a | 527 | |
0448d110 | 528 | return devices; |
ea9cfed7 | 529 | |
99965709 | 530 | free: |
0e1357e8 BV |
531 | ftdi_deinit(&devc->ftdic); |
532 | g_free(devc); | |
0448d110 | 533 | return NULL; |
28a35d8a HE |
534 | } |
535 | ||
0e1357e8 | 536 | static int upload_firmware(int firmware_idx, struct dev_context *devc) |
28a35d8a HE |
537 | { |
538 | int ret; | |
539 | unsigned char *buf; | |
540 | unsigned char pins; | |
541 | size_t buf_size; | |
28a35d8a | 542 | unsigned char result[32]; |
e8397563 | 543 | char firmware_path[128]; |
28a35d8a | 544 | |
fefa1800 | 545 | /* Make sure it's an ASIX SIGMA. */ |
0e1357e8 | 546 | if ((ret = ftdi_usb_open_desc(&devc->ftdic, |
28a35d8a | 547 | USB_VENDOR, USB_PRODUCT, USB_DESCRIPTION, NULL)) < 0) { |
7b48d6e1 | 548 | sr_err("sigma: ftdi_usb_open failed: %s", |
0e1357e8 | 549 | ftdi_get_error_string(&devc->ftdic)); |
28a35d8a HE |
550 | return 0; |
551 | } | |
552 | ||
0e1357e8 | 553 | if ((ret = ftdi_set_bitmode(&devc->ftdic, 0xdf, BITMODE_BITBANG)) < 0) { |
7b48d6e1 | 554 | sr_err("sigma: ftdi_set_bitmode failed: %s", |
0e1357e8 | 555 | ftdi_get_error_string(&devc->ftdic)); |
28a35d8a HE |
556 | return 0; |
557 | } | |
558 | ||
fefa1800 | 559 | /* Four times the speed of sigmalogan - Works well. */ |
0e1357e8 | 560 | if ((ret = ftdi_set_baudrate(&devc->ftdic, 750000)) < 0) { |
7b48d6e1 | 561 | sr_err("sigma: ftdi_set_baudrate failed: %s", |
0e1357e8 | 562 | ftdi_get_error_string(&devc->ftdic)); |
28a35d8a HE |
563 | return 0; |
564 | } | |
565 | ||
fefa1800 | 566 | /* Force the FPGA to reboot. */ |
0e1357e8 BV |
567 | sigma_write(suicide, sizeof(suicide), devc); |
568 | sigma_write(suicide, sizeof(suicide), devc); | |
569 | sigma_write(suicide, sizeof(suicide), devc); | |
570 | sigma_write(suicide, sizeof(suicide), devc); | |
28a35d8a | 571 | |
fefa1800 | 572 | /* Prepare to upload firmware (FPGA specific). */ |
0e1357e8 | 573 | sigma_write(init, sizeof(init), devc); |
28a35d8a | 574 | |
0e1357e8 | 575 | ftdi_usb_purge_buffers(&devc->ftdic); |
28a35d8a | 576 | |
fefa1800 | 577 | /* Wait until the FPGA asserts INIT_B. */ |
28a35d8a | 578 | while (1) { |
0e1357e8 | 579 | ret = sigma_read(result, 1, devc); |
28a35d8a HE |
580 | if (result[0] & 0x20) |
581 | break; | |
582 | } | |
583 | ||
9ddb2a12 | 584 | /* Prepare firmware. */ |
e8397563 | 585 | snprintf(firmware_path, sizeof(firmware_path), "%s/%s", FIRMWARE_DIR, |
f6564c8d HE |
586 | firmware_files[firmware_idx]); |
587 | ||
b53738ba | 588 | if ((ret = bin2bitbang(firmware_path, &buf, &buf_size)) != SR_OK) { |
7b48d6e1 | 589 | sr_err("sigma: An error occured while reading the firmware: %s", |
133a37bf | 590 | firmware_path); |
b53738ba | 591 | return ret; |
28a35d8a HE |
592 | } |
593 | ||
fefa1800 | 594 | /* Upload firmare. */ |
e3fff420 | 595 | sr_info("sigma: Uploading firmware %s", firmware_files[firmware_idx]); |
0e1357e8 | 596 | sigma_write(buf, buf_size, devc); |
28a35d8a HE |
597 | |
598 | g_free(buf); | |
599 | ||
0e1357e8 | 600 | if ((ret = ftdi_set_bitmode(&devc->ftdic, 0x00, BITMODE_RESET)) < 0) { |
7b48d6e1 | 601 | sr_err("sigma: ftdi_set_bitmode failed: %s", |
0e1357e8 | 602 | ftdi_get_error_string(&devc->ftdic)); |
e46b8fb1 | 603 | return SR_ERR; |
28a35d8a HE |
604 | } |
605 | ||
0e1357e8 | 606 | ftdi_usb_purge_buffers(&devc->ftdic); |
28a35d8a | 607 | |
fefa1800 | 608 | /* Discard garbage. */ |
0e1357e8 | 609 | while (1 == sigma_read(&pins, 1, devc)) |
28a35d8a HE |
610 | ; |
611 | ||
fefa1800 | 612 | /* Initialize the logic analyzer mode. */ |
0e1357e8 | 613 | sigma_write(logic_mode_start, sizeof(logic_mode_start), devc); |
28a35d8a | 614 | |
fefa1800 | 615 | /* Expect a 3 byte reply. */ |
0e1357e8 | 616 | ret = sigma_read(result, 3, devc); |
28a35d8a HE |
617 | if (ret != 3 || |
618 | result[0] != 0xa6 || result[1] != 0x55 || result[2] != 0xaa) { | |
7b48d6e1 | 619 | sr_err("sigma: Configuration failed. Invalid reply received."); |
e46b8fb1 | 620 | return SR_ERR; |
28a35d8a HE |
621 | } |
622 | ||
0e1357e8 | 623 | devc->cur_firmware = firmware_idx; |
f6564c8d | 624 | |
e3fff420 HE |
625 | sr_info("sigma: Firmware uploaded"); |
626 | ||
e46b8fb1 | 627 | return SR_OK; |
f6564c8d HE |
628 | } |
629 | ||
25a0f108 | 630 | static int hw_dev_open(struct sr_dev_inst *sdi) |
f6564c8d | 631 | { |
0e1357e8 | 632 | struct dev_context *devc; |
f6564c8d HE |
633 | int ret; |
634 | ||
0e1357e8 | 635 | devc = sdi->priv; |
99965709 | 636 | |
9ddb2a12 | 637 | /* Make sure it's an ASIX SIGMA. */ |
0e1357e8 | 638 | if ((ret = ftdi_usb_open_desc(&devc->ftdic, |
f6564c8d HE |
639 | USB_VENDOR, USB_PRODUCT, USB_DESCRIPTION, NULL)) < 0) { |
640 | ||
7b48d6e1 | 641 | sr_err("sigma: ftdi_usb_open failed: %s", |
0e1357e8 | 642 | ftdi_get_error_string(&devc->ftdic)); |
f6564c8d HE |
643 | |
644 | return 0; | |
645 | } | |
28a35d8a | 646 | |
5a2326a7 | 647 | sdi->status = SR_ST_ACTIVE; |
28a35d8a | 648 | |
e46b8fb1 | 649 | return SR_OK; |
f6564c8d HE |
650 | } |
651 | ||
6f4b1868 | 652 | static int set_samplerate(const struct sr_dev_inst *sdi, uint64_t samplerate) |
f6564c8d | 653 | { |
e8397563 | 654 | int i, ret; |
0e1357e8 | 655 | struct dev_context *devc = sdi->priv; |
f6564c8d HE |
656 | |
657 | for (i = 0; supported_samplerates[i]; i++) { | |
658 | if (supported_samplerates[i] == samplerate) | |
659 | break; | |
660 | } | |
661 | if (supported_samplerates[i] == 0) | |
e46b8fb1 | 662 | return SR_ERR_SAMPLERATE; |
f6564c8d | 663 | |
59df0c77 | 664 | if (samplerate <= SR_MHZ(50)) { |
0e1357e8 BV |
665 | ret = upload_firmware(0, devc); |
666 | devc->num_probes = 16; | |
e8397563 | 667 | } |
59df0c77 | 668 | if (samplerate == SR_MHZ(100)) { |
0e1357e8 BV |
669 | ret = upload_firmware(1, devc); |
670 | devc->num_probes = 8; | |
f78898e9 | 671 | } |
59df0c77 | 672 | else if (samplerate == SR_MHZ(200)) { |
0e1357e8 BV |
673 | ret = upload_firmware(2, devc); |
674 | devc->num_probes = 4; | |
f78898e9 | 675 | } |
f6564c8d | 676 | |
0e1357e8 BV |
677 | devc->cur_samplerate = samplerate; |
678 | devc->period_ps = 1000000000000 / samplerate; | |
679 | devc->samples_per_event = 16 / devc->num_probes; | |
680 | devc->state.state = SIGMA_IDLE; | |
f6564c8d | 681 | |
e8397563 | 682 | return ret; |
28a35d8a HE |
683 | } |
684 | ||
c53d793f HE |
685 | /* |
686 | * In 100 and 200 MHz mode, only a single pin rising/falling can be | |
687 | * set as trigger. In other modes, two rising/falling triggers can be set, | |
688 | * in addition to value/mask trigger for any number of probes. | |
689 | * | |
690 | * The Sigma supports complex triggers using boolean expressions, but this | |
691 | * has not been implemented yet. | |
692 | */ | |
6f4b1868 | 693 | static int configure_probes(const struct sr_dev_inst *sdi, const GSList *probes) |
57bbf56b | 694 | { |
0e1357e8 | 695 | struct dev_context *devc = sdi->priv; |
1b79df2f JH |
696 | const struct sr_probe *probe; |
697 | const GSList *l; | |
57bbf56b | 698 | int trigger_set = 0; |
a42aec7f | 699 | int probebit; |
57bbf56b | 700 | |
0e1357e8 | 701 | memset(&devc->trigger, 0, sizeof(struct sigma_trigger)); |
eec5275e | 702 | |
57bbf56b | 703 | for (l = probes; l; l = l->next) { |
1afe8989 | 704 | probe = (struct sr_probe *)l->data; |
b35c8293 | 705 | probebit = 1 << (probe->index); |
57bbf56b HE |
706 | |
707 | if (!probe->enabled || !probe->trigger) | |
708 | continue; | |
709 | ||
0e1357e8 | 710 | if (devc->cur_samplerate >= SR_MHZ(100)) { |
c53d793f | 711 | /* Fast trigger support. */ |
ee492173 | 712 | if (trigger_set) { |
7b48d6e1 | 713 | sr_err("sigma: ASIX SIGMA only supports a single " |
133a37bf | 714 | "pin trigger in 100 and 200MHz mode."); |
e46b8fb1 | 715 | return SR_ERR; |
ee492173 HE |
716 | } |
717 | if (probe->trigger[0] == 'f') | |
0e1357e8 | 718 | devc->trigger.fallingmask |= probebit; |
ee492173 | 719 | else if (probe->trigger[0] == 'r') |
0e1357e8 | 720 | devc->trigger.risingmask |= probebit; |
ee492173 | 721 | else { |
7b48d6e1 | 722 | sr_err("sigma: ASIX SIGMA only supports " |
133a37bf UH |
723 | "rising/falling trigger in 100 " |
724 | "and 200MHz mode."); | |
e46b8fb1 | 725 | return SR_ERR; |
ee492173 | 726 | } |
57bbf56b | 727 | |
c53d793f | 728 | ++trigger_set; |
ee492173 | 729 | } else { |
c53d793f HE |
730 | /* Simple trigger support (event). */ |
731 | if (probe->trigger[0] == '1') { | |
0e1357e8 BV |
732 | devc->trigger.simplevalue |= probebit; |
733 | devc->trigger.simplemask |= probebit; | |
c53d793f HE |
734 | } |
735 | else if (probe->trigger[0] == '0') { | |
0e1357e8 BV |
736 | devc->trigger.simplevalue &= ~probebit; |
737 | devc->trigger.simplemask |= probebit; | |
c53d793f HE |
738 | } |
739 | else if (probe->trigger[0] == 'f') { | |
0e1357e8 | 740 | devc->trigger.fallingmask |= probebit; |
c53d793f HE |
741 | ++trigger_set; |
742 | } | |
743 | else if (probe->trigger[0] == 'r') { | |
0e1357e8 | 744 | devc->trigger.risingmask |= probebit; |
c53d793f HE |
745 | ++trigger_set; |
746 | } | |
ee492173 | 747 | |
ea9cfed7 UH |
748 | /* |
749 | * Actually, Sigma supports 2 rising/falling triggers, | |
750 | * but they are ORed and the current trigger syntax | |
751 | * does not permit ORed triggers. | |
752 | */ | |
98b8cbc1 | 753 | if (trigger_set > 1) { |
7b48d6e1 UH |
754 | sr_err("sigma: ASIX SIGMA only supports 1 " |
755 | "rising/falling triggers."); | |
e46b8fb1 | 756 | return SR_ERR; |
ee492173 | 757 | } |
ee492173 | 758 | } |
5b5ea7c6 HE |
759 | |
760 | if (trigger_set) | |
0e1357e8 | 761 | devc->use_triggers = 1; |
57bbf56b HE |
762 | } |
763 | ||
e46b8fb1 | 764 | return SR_OK; |
57bbf56b HE |
765 | } |
766 | ||
25a0f108 | 767 | static int hw_dev_close(struct sr_dev_inst *sdi) |
28a35d8a | 768 | { |
0e1357e8 | 769 | struct dev_context *devc; |
28a35d8a | 770 | |
0e1357e8 | 771 | if (!(devc = sdi->priv)) { |
340cfac0 | 772 | sr_err("sigma: %s: sdi->priv was NULL", __func__); |
0abee507 | 773 | return SR_ERR_BUG; |
9be9893e | 774 | } |
697785d1 UH |
775 | |
776 | /* TODO */ | |
777 | if (sdi->status == SR_ST_ACTIVE) | |
0e1357e8 | 778 | ftdi_usb_close(&devc->ftdic); |
697785d1 UH |
779 | |
780 | sdi->status = SR_ST_INACTIVE; | |
781 | ||
782 | return SR_OK; | |
28a35d8a HE |
783 | } |
784 | ||
57ab7d9f | 785 | static int hw_cleanup(void) |
28a35d8a | 786 | { |
99965709 | 787 | |
b32503cc BV |
788 | if (!adi->priv) |
789 | return SR_OK; | |
790 | ||
0448d110 | 791 | clear_instances(); |
57ab7d9f | 792 | |
0448d110 | 793 | return SR_OK; |
28a35d8a HE |
794 | } |
795 | ||
41479605 BV |
796 | static int hw_info_get(int info_id, const void **data, |
797 | const struct sr_dev_inst *sdi) | |
28a35d8a | 798 | { |
0e1357e8 | 799 | struct dev_context *devc; |
99965709 | 800 | |
41479605 | 801 | switch (info_id) { |
b2b5445c BV |
802 | case SR_DI_HWCAPS: |
803 | *data = hwcaps; | |
804 | break; | |
5a2326a7 | 805 | case SR_DI_NUM_PROBES: |
41479605 | 806 | *data = GINT_TO_POINTER(NUM_PROBES); |
464d12c7 KS |
807 | break; |
808 | case SR_DI_PROBE_NAMES: | |
41479605 | 809 | *data = probe_names; |
28a35d8a | 810 | break; |
5a2326a7 | 811 | case SR_DI_SAMPLERATES: |
41479605 | 812 | *data = &samplerates; |
28a35d8a | 813 | break; |
5a2326a7 | 814 | case SR_DI_TRIGGER_TYPES: |
41479605 | 815 | *data = (char *)TRIGGER_TYPES; |
28a35d8a | 816 | break; |
5a2326a7 | 817 | case SR_DI_CUR_SAMPLERATE: |
41479605 | 818 | if (sdi) { |
0e1357e8 BV |
819 | devc = sdi->priv; |
820 | *data = &devc->cur_samplerate; | |
41479605 BV |
821 | } else |
822 | return SR_ERR; | |
28a35d8a | 823 | break; |
d7bbecfd BV |
824 | default: |
825 | return SR_ERR_ARG; | |
28a35d8a HE |
826 | } |
827 | ||
41479605 | 828 | return SR_OK; |
28a35d8a HE |
829 | } |
830 | ||
6f4b1868 BV |
831 | static int hw_dev_config_set(const struct sr_dev_inst *sdi, int hwcap, |
832 | const void *value) | |
28a35d8a | 833 | { |
0e1357e8 | 834 | struct dev_context *devc; |
28a35d8a | 835 | int ret; |
f6564c8d | 836 | |
0e1357e8 | 837 | devc = sdi->priv; |
99965709 | 838 | |
ffedd0bf | 839 | if (hwcap == SR_HWCAP_SAMPLERATE) { |
1b79df2f | 840 | ret = set_samplerate(sdi, *(const uint64_t *)value); |
ffedd0bf | 841 | } else if (hwcap == SR_HWCAP_PROBECONFIG) { |
99965709 | 842 | ret = configure_probes(sdi, value); |
ffedd0bf | 843 | } else if (hwcap == SR_HWCAP_LIMIT_MSEC) { |
0e1357e8 BV |
844 | devc->limit_msec = *(const uint64_t *)value; |
845 | if (devc->limit_msec > 0) | |
e46b8fb1 | 846 | ret = SR_OK; |
94ba4bd6 | 847 | else |
e46b8fb1 | 848 | ret = SR_ERR; |
ffedd0bf | 849 | } else if (hwcap == SR_HWCAP_CAPTURE_RATIO) { |
0e1357e8 BV |
850 | devc->capture_ratio = *(const uint64_t *)value; |
851 | if (devc->capture_ratio < 0 || devc->capture_ratio > 100) | |
e46b8fb1 | 852 | ret = SR_ERR; |
94ba4bd6 | 853 | else |
e46b8fb1 | 854 | ret = SR_OK; |
28a35d8a | 855 | } else { |
e46b8fb1 | 856 | ret = SR_ERR; |
28a35d8a HE |
857 | } |
858 | ||
859 | return ret; | |
860 | } | |
861 | ||
36b1c8e6 HE |
862 | /* Software trigger to determine exact trigger position. */ |
863 | static int get_trigger_offset(uint16_t *samples, uint16_t last_sample, | |
864 | struct sigma_trigger *t) | |
865 | { | |
866 | int i; | |
867 | ||
868 | for (i = 0; i < 8; ++i) { | |
869 | if (i > 0) | |
870 | last_sample = samples[i-1]; | |
871 | ||
872 | /* Simple triggers. */ | |
873 | if ((samples[i] & t->simplemask) != t->simplevalue) | |
874 | continue; | |
875 | ||
876 | /* Rising edge. */ | |
877 | if ((last_sample & t->risingmask) != 0 || (samples[i] & | |
878 | t->risingmask) != t->risingmask) | |
879 | continue; | |
880 | ||
881 | /* Falling edge. */ | |
bdfc7a89 HE |
882 | if ((last_sample & t->fallingmask) != t->fallingmask || |
883 | (samples[i] & t->fallingmask) != 0) | |
36b1c8e6 HE |
884 | continue; |
885 | ||
886 | break; | |
887 | } | |
888 | ||
889 | /* If we did not match, return original trigger pos. */ | |
890 | return i & 0x7; | |
891 | } | |
892 | ||
28a35d8a | 893 | /* |
fefa1800 UH |
894 | * Decode chunk of 1024 bytes, 64 clusters, 7 events per cluster. |
895 | * Each event is 20ns apart, and can contain multiple samples. | |
f78898e9 HE |
896 | * |
897 | * For 200 MHz, events contain 4 samples for each channel, spread 5 ns apart. | |
898 | * For 100 MHz, events contain 2 samples for each channel, spread 10 ns apart. | |
899 | * For 50 MHz and below, events contain one sample for each channel, | |
900 | * spread 20 ns apart. | |
28a35d8a HE |
901 | */ |
902 | static int decode_chunk_ts(uint8_t *buf, uint16_t *lastts, | |
88c51afe | 903 | uint16_t *lastsample, int triggerpos, |
3cd3a20b | 904 | uint16_t limit_chunk, void *cb_data) |
28a35d8a | 905 | { |
3cd3a20b | 906 | struct sr_dev_inst *sdi = cb_data; |
0e1357e8 | 907 | struct dev_context *devc = sdi->priv; |
fefa1800 | 908 | uint16_t tsdiff, ts; |
0e1357e8 | 909 | uint16_t samples[65536 * devc->samples_per_event]; |
b9c735a2 | 910 | struct sr_datafeed_packet packet; |
9c939c51 | 911 | struct sr_datafeed_logic logic; |
f78898e9 | 912 | int i, j, k, l, numpad, tosend; |
fefa1800 | 913 | size_t n = 0, sent = 0; |
0e1357e8 | 914 | int clustersize = EVENTS_PER_CLUSTER * devc->samples_per_event; |
fefa1800 | 915 | uint16_t *event; |
f78898e9 | 916 | uint16_t cur_sample; |
57bbf56b | 917 | int triggerts = -1; |
ee492173 | 918 | |
4ae1f451 | 919 | /* Check if trigger is in this chunk. */ |
ee492173 | 920 | if (triggerpos != -1) { |
0e1357e8 | 921 | if (devc->cur_samplerate <= SR_MHZ(50)) |
36b1c8e6 | 922 | triggerpos -= EVENTS_PER_CLUSTER - 1; |
ee492173 HE |
923 | |
924 | if (triggerpos < 0) | |
925 | triggerpos = 0; | |
57bbf56b | 926 | |
ee492173 HE |
927 | /* Find in which cluster the trigger occured. */ |
928 | triggerts = triggerpos / 7; | |
929 | } | |
28a35d8a | 930 | |
eec5275e | 931 | /* For each ts. */ |
28a35d8a | 932 | for (i = 0; i < 64; ++i) { |
fefa1800 | 933 | ts = *(uint16_t *) &buf[i * 16]; |
28a35d8a HE |
934 | tsdiff = ts - *lastts; |
935 | *lastts = ts; | |
936 | ||
88c51afe HE |
937 | /* Decode partial chunk. */ |
938 | if (limit_chunk && ts > limit_chunk) | |
e46b8fb1 | 939 | return SR_OK; |
88c51afe | 940 | |
fefa1800 | 941 | /* Pad last sample up to current point. */ |
0e1357e8 | 942 | numpad = tsdiff * devc->samples_per_event - clustersize; |
28a35d8a | 943 | if (numpad > 0) { |
f78898e9 HE |
944 | for (j = 0; j < numpad; ++j) |
945 | samples[j] = *lastsample; | |
946 | ||
947 | n = numpad; | |
28a35d8a HE |
948 | } |
949 | ||
57bbf56b HE |
950 | /* Send samples between previous and this timestamp to sigrok. */ |
951 | sent = 0; | |
952 | while (sent < n) { | |
953 | tosend = MIN(2048, n - sent); | |
954 | ||
5a2326a7 | 955 | packet.type = SR_DF_LOGIC; |
9c939c51 BV |
956 | packet.payload = &logic; |
957 | logic.length = tosend * sizeof(uint16_t); | |
958 | logic.unitsize = 2; | |
959 | logic.data = samples + sent; | |
0e1357e8 | 960 | sr_session_send(devc->session_dev_id, &packet); |
28a35d8a | 961 | |
57bbf56b HE |
962 | sent += tosend; |
963 | } | |
964 | n = 0; | |
965 | ||
966 | event = (uint16_t *) &buf[i * 16 + 2]; | |
f78898e9 HE |
967 | cur_sample = 0; |
968 | ||
969 | /* For each event in cluster. */ | |
28a35d8a | 970 | for (j = 0; j < 7; ++j) { |
f78898e9 HE |
971 | |
972 | /* For each sample in event. */ | |
0e1357e8 | 973 | for (k = 0; k < devc->samples_per_event; ++k) { |
f78898e9 HE |
974 | cur_sample = 0; |
975 | ||
976 | /* For each probe. */ | |
0e1357e8 | 977 | for (l = 0; l < devc->num_probes; ++l) |
edca2c5c | 978 | cur_sample |= (!!(event[j] & (1 << (l * |
0e1357e8 | 979 | devc->samples_per_event + k)))) << l; |
f78898e9 HE |
980 | |
981 | samples[n++] = cur_sample; | |
28a35d8a HE |
982 | } |
983 | } | |
984 | ||
eec5275e | 985 | /* Send data up to trigger point (if triggered). */ |
fefa1800 | 986 | sent = 0; |
57bbf56b HE |
987 | if (i == triggerts) { |
988 | /* | |
36b1c8e6 HE |
989 | * Trigger is not always accurate to sample because of |
990 | * pipeline delay. However, it always triggers before | |
991 | * the actual event. We therefore look at the next | |
992 | * samples to pinpoint the exact position of the trigger. | |
57bbf56b | 993 | */ |
bdfc7a89 | 994 | tosend = get_trigger_offset(samples, *lastsample, |
0e1357e8 | 995 | &devc->trigger); |
57bbf56b HE |
996 | |
997 | if (tosend > 0) { | |
5a2326a7 | 998 | packet.type = SR_DF_LOGIC; |
9c939c51 BV |
999 | packet.payload = &logic; |
1000 | logic.length = tosend * sizeof(uint16_t); | |
1001 | logic.unitsize = 2; | |
1002 | logic.data = samples; | |
0e1357e8 | 1003 | sr_session_send(devc->session_dev_id, &packet); |
57bbf56b HE |
1004 | |
1005 | sent += tosend; | |
1006 | } | |
28a35d8a | 1007 | |
5b5ea7c6 | 1008 | /* Only send trigger if explicitly enabled. */ |
0e1357e8 | 1009 | if (devc->use_triggers) { |
5a2326a7 | 1010 | packet.type = SR_DF_TRIGGER; |
0e1357e8 | 1011 | sr_session_send(devc->session_dev_id, &packet); |
5b5ea7c6 | 1012 | } |
28a35d8a | 1013 | } |
57bbf56b | 1014 | |
eec5275e | 1015 | /* Send rest of the chunk to sigrok. */ |
57bbf56b HE |
1016 | tosend = n - sent; |
1017 | ||
abda62ce | 1018 | if (tosend > 0) { |
5a2326a7 | 1019 | packet.type = SR_DF_LOGIC; |
9c939c51 BV |
1020 | packet.payload = &logic; |
1021 | logic.length = tosend * sizeof(uint16_t); | |
1022 | logic.unitsize = 2; | |
1023 | logic.data = samples + sent; | |
0e1357e8 | 1024 | sr_session_send(devc->session_dev_id, &packet); |
abda62ce | 1025 | } |
ee492173 HE |
1026 | |
1027 | *lastsample = samples[n - 1]; | |
28a35d8a HE |
1028 | } |
1029 | ||
e46b8fb1 | 1030 | return SR_OK; |
28a35d8a HE |
1031 | } |
1032 | ||
1f9813eb | 1033 | static int receive_data(int fd, int revents, void *cb_data) |
28a35d8a | 1034 | { |
1f9813eb | 1035 | struct sr_dev_inst *sdi = cb_data; |
0e1357e8 | 1036 | struct dev_context *devc = sdi->priv; |
b9c735a2 | 1037 | struct sr_datafeed_packet packet; |
28a35d8a HE |
1038 | const int chunks_per_read = 32; |
1039 | unsigned char buf[chunks_per_read * CHUNK_SIZE]; | |
6aac7737 | 1040 | int bufsz, numchunks, i, newchunks; |
94ba4bd6 | 1041 | uint64_t running_msec; |
28a35d8a | 1042 | struct timeval tv; |
28a35d8a | 1043 | |
cb93f8a9 UH |
1044 | /* Avoid compiler warnings. */ |
1045 | (void)fd; | |
1046 | (void)revents; | |
28a35d8a | 1047 | |
805919b0 | 1048 | /* Get the current position. */ |
0e1357e8 | 1049 | sigma_read_pos(&devc->state.stoppos, &devc->state.triggerpos, devc); |
805919b0 | 1050 | |
0e1357e8 | 1051 | numchunks = (devc->state.stoppos + 511) / 512; |
28a35d8a | 1052 | |
0e1357e8 | 1053 | if (devc->state.state == SIGMA_IDLE) |
805919b0 | 1054 | return TRUE; |
28a35d8a | 1055 | |
0e1357e8 | 1056 | if (devc->state.state == SIGMA_CAPTURE) { |
6aac7737 HE |
1057 | /* Check if the timer has expired, or memory is full. */ |
1058 | gettimeofday(&tv, 0); | |
0e1357e8 BV |
1059 | running_msec = (tv.tv_sec - devc->start_tv.tv_sec) * 1000 + |
1060 | (tv.tv_usec - devc->start_tv.tv_usec) / 1000; | |
28a35d8a | 1061 | |
0e1357e8 | 1062 | if (running_msec < devc->limit_msec && numchunks < 32767) |
805919b0 | 1063 | return TRUE; /* While capturing... */ |
e3fff420 | 1064 | else |
3ffb6964 | 1065 | hw_dev_acquisition_stop(sdi, sdi); |
6aac7737 | 1066 | |
0e1357e8 BV |
1067 | } else if (devc->state.state == SIGMA_DOWNLOAD) { |
1068 | if (devc->state.chunks_downloaded >= numchunks) { | |
6aac7737 | 1069 | /* End of samples. */ |
5a2326a7 | 1070 | packet.type = SR_DF_END; |
0e1357e8 | 1071 | sr_session_send(devc->session_dev_id, &packet); |
6aac7737 | 1072 | |
0e1357e8 | 1073 | devc->state.state = SIGMA_IDLE; |
f78898e9 | 1074 | |
6aac7737 HE |
1075 | return TRUE; |
1076 | } | |
1077 | ||
1078 | newchunks = MIN(chunks_per_read, | |
0e1357e8 | 1079 | numchunks - devc->state.chunks_downloaded); |
28a35d8a | 1080 | |
7b48d6e1 | 1081 | sr_info("sigma: Downloading sample data: %.0f %%", |
0e1357e8 | 1082 | 100.0 * devc->state.chunks_downloaded / numchunks); |
28a35d8a | 1083 | |
0e1357e8 BV |
1084 | bufsz = sigma_read_dram(devc->state.chunks_downloaded, |
1085 | newchunks, buf, devc); | |
719c5a93 UH |
1086 | /* TODO: Check bufsz. For now, just avoid compiler warnings. */ |
1087 | (void)bufsz; | |
28a35d8a | 1088 | |
fefa1800 | 1089 | /* Find first ts. */ |
0e1357e8 BV |
1090 | if (devc->state.chunks_downloaded == 0) { |
1091 | devc->state.lastts = *(uint16_t *) buf - 1; | |
1092 | devc->state.lastsample = 0; | |
6aac7737 | 1093 | } |
28a35d8a | 1094 | |
fefa1800 | 1095 | /* Decode chunks and send them to sigrok. */ |
28a35d8a | 1096 | for (i = 0; i < newchunks; ++i) { |
88c51afe HE |
1097 | int limit_chunk = 0; |
1098 | ||
1099 | /* The last chunk may potentially be only in part. */ | |
0e1357e8 | 1100 | if (devc->state.chunks_downloaded == numchunks - 1) { |
88c51afe | 1101 | /* Find the last valid timestamp */ |
0e1357e8 | 1102 | limit_chunk = devc->state.stoppos % 512 + devc->state.lastts; |
88c51afe HE |
1103 | } |
1104 | ||
0e1357e8 | 1105 | if (devc->state.chunks_downloaded + i == devc->state.triggerchunk) |
57bbf56b | 1106 | decode_chunk_ts(buf + (i * CHUNK_SIZE), |
0e1357e8 BV |
1107 | &devc->state.lastts, |
1108 | &devc->state.lastsample, | |
1109 | devc->state.triggerpos & 0x1ff, | |
1f9813eb | 1110 | limit_chunk, sdi); |
57bbf56b HE |
1111 | else |
1112 | decode_chunk_ts(buf + (i * CHUNK_SIZE), | |
0e1357e8 BV |
1113 | &devc->state.lastts, |
1114 | &devc->state.lastsample, | |
1f9813eb | 1115 | -1, limit_chunk, sdi); |
28a35d8a | 1116 | |
0e1357e8 | 1117 | ++devc->state.chunks_downloaded; |
88c51afe | 1118 | } |
28a35d8a HE |
1119 | } |
1120 | ||
28a35d8a HE |
1121 | return TRUE; |
1122 | } | |
1123 | ||
c53d793f HE |
1124 | /* Build a LUT entry used by the trigger functions. */ |
1125 | static void build_lut_entry(uint16_t value, uint16_t mask, uint16_t *entry) | |
ee492173 HE |
1126 | { |
1127 | int i, j, k, bit; | |
1128 | ||
f758d074 | 1129 | /* For each quad probe. */ |
ee492173 | 1130 | for (i = 0; i < 4; ++i) { |
c53d793f | 1131 | entry[i] = 0xffff; |
ee492173 | 1132 | |
f758d074 | 1133 | /* For each bit in LUT. */ |
ee492173 HE |
1134 | for (j = 0; j < 16; ++j) |
1135 | ||
f758d074 | 1136 | /* For each probe in quad. */ |
ee492173 HE |
1137 | for (k = 0; k < 4; ++k) { |
1138 | bit = 1 << (i * 4 + k); | |
1139 | ||
c53d793f HE |
1140 | /* Set bit in entry */ |
1141 | if ((mask & bit) && | |
1142 | ((!(value & bit)) != | |
4ae1f451 | 1143 | (!(j & (1 << k))))) |
c53d793f | 1144 | entry[i] &= ~(1 << j); |
ee492173 HE |
1145 | } |
1146 | } | |
c53d793f | 1147 | } |
ee492173 | 1148 | |
c53d793f HE |
1149 | /* Add a logical function to LUT mask. */ |
1150 | static void add_trigger_function(enum triggerop oper, enum triggerfunc func, | |
1151 | int index, int neg, uint16_t *mask) | |
1152 | { | |
1153 | int i, j; | |
1154 | int x[2][2], tmp, a, b, aset, bset, rset; | |
1155 | ||
1156 | memset(x, 0, 4 * sizeof(int)); | |
1157 | ||
1158 | /* Trigger detect condition. */ | |
1159 | switch (oper) { | |
1160 | case OP_LEVEL: | |
1161 | x[0][1] = 1; | |
1162 | x[1][1] = 1; | |
1163 | break; | |
1164 | case OP_NOT: | |
1165 | x[0][0] = 1; | |
1166 | x[1][0] = 1; | |
1167 | break; | |
1168 | case OP_RISE: | |
1169 | x[0][1] = 1; | |
1170 | break; | |
1171 | case OP_FALL: | |
1172 | x[1][0] = 1; | |
1173 | break; | |
1174 | case OP_RISEFALL: | |
1175 | x[0][1] = 1; | |
1176 | x[1][0] = 1; | |
1177 | break; | |
1178 | case OP_NOTRISE: | |
1179 | x[1][1] = 1; | |
1180 | x[0][0] = 1; | |
1181 | x[1][0] = 1; | |
1182 | break; | |
1183 | case OP_NOTFALL: | |
1184 | x[1][1] = 1; | |
1185 | x[0][0] = 1; | |
1186 | x[0][1] = 1; | |
1187 | break; | |
1188 | case OP_NOTRISEFALL: | |
1189 | x[1][1] = 1; | |
1190 | x[0][0] = 1; | |
1191 | break; | |
1192 | } | |
1193 | ||
1194 | /* Transpose if neg is set. */ | |
1195 | if (neg) { | |
ea9cfed7 | 1196 | for (i = 0; i < 2; ++i) { |
c53d793f HE |
1197 | for (j = 0; j < 2; ++j) { |
1198 | tmp = x[i][j]; | |
1199 | x[i][j] = x[1-i][1-j]; | |
1200 | x[1-i][1-j] = tmp; | |
1201 | } | |
ea9cfed7 | 1202 | } |
c53d793f HE |
1203 | } |
1204 | ||
1205 | /* Update mask with function. */ | |
1206 | for (i = 0; i < 16; ++i) { | |
1207 | a = (i >> (2 * index + 0)) & 1; | |
1208 | b = (i >> (2 * index + 1)) & 1; | |
1209 | ||
1210 | aset = (*mask >> i) & 1; | |
1211 | bset = x[b][a]; | |
1212 | ||
1213 | if (func == FUNC_AND || func == FUNC_NAND) | |
1214 | rset = aset & bset; | |
1215 | else if (func == FUNC_OR || func == FUNC_NOR) | |
1216 | rset = aset | bset; | |
1217 | else if (func == FUNC_XOR || func == FUNC_NXOR) | |
1218 | rset = aset ^ bset; | |
1219 | ||
1220 | if (func == FUNC_NAND || func == FUNC_NOR || func == FUNC_NXOR) | |
1221 | rset = !rset; | |
1222 | ||
1223 | *mask &= ~(1 << i); | |
1224 | ||
1225 | if (rset) | |
1226 | *mask |= 1 << i; | |
1227 | } | |
1228 | } | |
1229 | ||
1230 | /* | |
1231 | * Build trigger LUTs used by 50 MHz and lower sample rates for supporting | |
1232 | * simple pin change and state triggers. Only two transitions (rise/fall) can be | |
1233 | * set at any time, but a full mask and value can be set (0/1). | |
1234 | */ | |
0e1357e8 | 1235 | static int build_basic_trigger(struct triggerlut *lut, struct dev_context *devc) |
c53d793f HE |
1236 | { |
1237 | int i,j; | |
4ae1f451 | 1238 | uint16_t masks[2] = { 0, 0 }; |
c53d793f HE |
1239 | |
1240 | memset(lut, 0, sizeof(struct triggerlut)); | |
1241 | ||
1242 | /* Contant for simple triggers. */ | |
1243 | lut->m4 = 0xa000; | |
1244 | ||
1245 | /* Value/mask trigger support. */ | |
0e1357e8 | 1246 | build_lut_entry(devc->trigger.simplevalue, devc->trigger.simplemask, |
99965709 | 1247 | lut->m2d); |
c53d793f HE |
1248 | |
1249 | /* Rise/fall trigger support. */ | |
1250 | for (i = 0, j = 0; i < 16; ++i) { | |
0e1357e8 BV |
1251 | if (devc->trigger.risingmask & (1 << i) || |
1252 | devc->trigger.fallingmask & (1 << i)) | |
c53d793f HE |
1253 | masks[j++] = 1 << i; |
1254 | } | |
1255 | ||
1256 | build_lut_entry(masks[0], masks[0], lut->m0d); | |
1257 | build_lut_entry(masks[1], masks[1], lut->m1d); | |
1258 | ||
1259 | /* Add glue logic */ | |
1260 | if (masks[0] || masks[1]) { | |
1261 | /* Transition trigger. */ | |
0e1357e8 | 1262 | if (masks[0] & devc->trigger.risingmask) |
c53d793f | 1263 | add_trigger_function(OP_RISE, FUNC_OR, 0, 0, &lut->m3); |
0e1357e8 | 1264 | if (masks[0] & devc->trigger.fallingmask) |
c53d793f | 1265 | add_trigger_function(OP_FALL, FUNC_OR, 0, 0, &lut->m3); |
0e1357e8 | 1266 | if (masks[1] & devc->trigger.risingmask) |
c53d793f | 1267 | add_trigger_function(OP_RISE, FUNC_OR, 1, 0, &lut->m3); |
0e1357e8 | 1268 | if (masks[1] & devc->trigger.fallingmask) |
c53d793f HE |
1269 | add_trigger_function(OP_FALL, FUNC_OR, 1, 0, &lut->m3); |
1270 | } else { | |
1271 | /* Only value/mask trigger. */ | |
1272 | lut->m3 = 0xffff; | |
1273 | } | |
ee492173 | 1274 | |
c53d793f | 1275 | /* Triggertype: event. */ |
ee492173 HE |
1276 | lut->params.selres = 3; |
1277 | ||
e46b8fb1 | 1278 | return SR_OK; |
ee492173 HE |
1279 | } |
1280 | ||
3ffb6964 BV |
1281 | static int hw_dev_acquisition_start(const struct sr_dev_inst *sdi, |
1282 | void *cb_data) | |
28a35d8a | 1283 | { |
0e1357e8 | 1284 | struct dev_context *devc; |
3c36c403 HE |
1285 | struct sr_datafeed_packet *packet; |
1286 | struct sr_datafeed_header *header; | |
f366e86c | 1287 | struct sr_datafeed_meta_logic meta; |
9ddb2a12 | 1288 | struct clockselect_50 clockselect; |
82957b65 | 1289 | int frac, triggerpin, ret; |
57bbf56b HE |
1290 | uint8_t triggerselect; |
1291 | struct triggerinout triggerinout_conf; | |
ee492173 | 1292 | struct triggerlut lut; |
28a35d8a | 1293 | |
0e1357e8 | 1294 | devc = sdi->priv; |
28a35d8a | 1295 | |
ea9cfed7 | 1296 | /* If the samplerate has not been set, default to 200 kHz. */ |
0e1357e8 | 1297 | if (devc->cur_firmware == -1) { |
82957b65 UH |
1298 | if ((ret = set_samplerate(sdi, SR_KHZ(200))) != SR_OK) |
1299 | return ret; | |
1300 | } | |
e8397563 | 1301 | |
eec5275e | 1302 | /* Enter trigger programming mode. */ |
0e1357e8 | 1303 | sigma_set_register(WRITE_TRIGGER_SELECT1, 0x20, devc); |
28a35d8a | 1304 | |
eec5275e | 1305 | /* 100 and 200 MHz mode. */ |
0e1357e8 BV |
1306 | if (devc->cur_samplerate >= SR_MHZ(100)) { |
1307 | sigma_set_register(WRITE_TRIGGER_SELECT1, 0x81, devc); | |
57bbf56b | 1308 | |
a42aec7f HE |
1309 | /* Find which pin to trigger on from mask. */ |
1310 | for (triggerpin = 0; triggerpin < 8; ++triggerpin) | |
0e1357e8 | 1311 | if ((devc->trigger.risingmask | devc->trigger.fallingmask) & |
a42aec7f HE |
1312 | (1 << triggerpin)) |
1313 | break; | |
1314 | ||
1315 | /* Set trigger pin and light LED on trigger. */ | |
1316 | triggerselect = (1 << LEDSEL1) | (triggerpin & 0x7); | |
1317 | ||
1318 | /* Default rising edge. */ | |
0e1357e8 | 1319 | if (devc->trigger.fallingmask) |
a42aec7f | 1320 | triggerselect |= 1 << 3; |
57bbf56b | 1321 | |
eec5275e | 1322 | /* All other modes. */ |
0e1357e8 BV |
1323 | } else if (devc->cur_samplerate <= SR_MHZ(50)) { |
1324 | build_basic_trigger(&lut, devc); | |
ee492173 | 1325 | |
0e1357e8 | 1326 | sigma_write_trigger_lut(&lut, devc); |
57bbf56b HE |
1327 | |
1328 | triggerselect = (1 << LEDSEL1) | (1 << LEDSEL0); | |
1329 | } | |
1330 | ||
eec5275e | 1331 | /* Setup trigger in and out pins to default values. */ |
57bbf56b HE |
1332 | memset(&triggerinout_conf, 0, sizeof(struct triggerinout)); |
1333 | triggerinout_conf.trgout_bytrigger = 1; | |
1334 | triggerinout_conf.trgout_enable = 1; | |
1335 | ||
28a35d8a | 1336 | sigma_write_register(WRITE_TRIGGER_OPTION, |
57bbf56b | 1337 | (uint8_t *) &triggerinout_conf, |
0e1357e8 | 1338 | sizeof(struct triggerinout), devc); |
28a35d8a | 1339 | |
eec5275e | 1340 | /* Go back to normal mode. */ |
0e1357e8 | 1341 | sigma_set_register(WRITE_TRIGGER_SELECT1, triggerselect, devc); |
28a35d8a | 1342 | |
edca2c5c | 1343 | /* Set clock select register. */ |
0e1357e8 | 1344 | if (devc->cur_samplerate == SR_MHZ(200)) |
edca2c5c | 1345 | /* Enable 4 probes. */ |
0e1357e8 BV |
1346 | sigma_set_register(WRITE_CLOCK_SELECT, 0xf0, devc); |
1347 | else if (devc->cur_samplerate == SR_MHZ(100)) | |
edca2c5c | 1348 | /* Enable 8 probes. */ |
0e1357e8 | 1349 | sigma_set_register(WRITE_CLOCK_SELECT, 0x00, devc); |
edca2c5c HE |
1350 | else { |
1351 | /* | |
9ddb2a12 | 1352 | * 50 MHz mode (or fraction thereof). Any fraction down to |
eec5275e | 1353 | * 50 MHz / 256 can be used, but is not supported by sigrok API. |
edca2c5c | 1354 | */ |
0e1357e8 | 1355 | frac = SR_MHZ(50) / devc->cur_samplerate - 1; |
edca2c5c | 1356 | |
9ddb2a12 UH |
1357 | clockselect.async = 0; |
1358 | clockselect.fraction = frac; | |
1359 | clockselect.disabled_probes = 0; | |
edca2c5c HE |
1360 | |
1361 | sigma_write_register(WRITE_CLOCK_SELECT, | |
9ddb2a12 | 1362 | (uint8_t *) &clockselect, |
0e1357e8 | 1363 | sizeof(clockselect), devc); |
edca2c5c HE |
1364 | } |
1365 | ||
fefa1800 | 1366 | /* Setup maximum post trigger time. */ |
99965709 | 1367 | sigma_set_register(WRITE_POST_TRIGGER, |
0e1357e8 | 1368 | (devc->capture_ratio * 255) / 100, devc); |
28a35d8a | 1369 | |
eec5275e | 1370 | /* Start acqusition. */ |
0e1357e8 BV |
1371 | gettimeofday(&devc->start_tv, 0); |
1372 | sigma_set_register(WRITE_MODE, 0x0d, devc); | |
99965709 | 1373 | |
0e1357e8 | 1374 | devc->session_dev_id = cb_data; |
28a35d8a | 1375 | |
3c36c403 HE |
1376 | if (!(packet = g_try_malloc(sizeof(struct sr_datafeed_packet)))) { |
1377 | sr_err("sigma: %s: packet malloc failed.", __func__); | |
1378 | return SR_ERR_MALLOC; | |
1379 | } | |
1380 | ||
1381 | if (!(header = g_try_malloc(sizeof(struct sr_datafeed_header)))) { | |
1382 | sr_err("sigma: %s: header malloc failed.", __func__); | |
1383 | return SR_ERR_MALLOC; | |
1384 | } | |
28a35d8a | 1385 | |
3c36c403 HE |
1386 | /* Send header packet to the session bus. */ |
1387 | packet->type = SR_DF_HEADER; | |
1388 | packet->payload = header; | |
1389 | header->feed_version = 1; | |
1390 | gettimeofday(&header->starttime, NULL); | |
0e1357e8 | 1391 | sr_session_send(devc->session_dev_id, packet); |
f366e86c BV |
1392 | |
1393 | /* Send metadata about the SR_DF_LOGIC packets to come. */ | |
1394 | packet->type = SR_DF_META_LOGIC; | |
1395 | packet->payload = &meta; | |
0e1357e8 BV |
1396 | meta.samplerate = devc->cur_samplerate; |
1397 | meta.num_probes = devc->num_probes; | |
1398 | sr_session_send(devc->session_dev_id, packet); | |
f366e86c BV |
1399 | |
1400 | /* Add capture source. */ | |
3ffb6964 | 1401 | sr_source_add(0, G_IO_IN, 10, receive_data, (void *)sdi); |
f366e86c | 1402 | |
3c36c403 HE |
1403 | g_free(header); |
1404 | g_free(packet); | |
1405 | ||
0e1357e8 | 1406 | devc->state.state = SIGMA_CAPTURE; |
6aac7737 | 1407 | |
e46b8fb1 | 1408 | return SR_OK; |
28a35d8a HE |
1409 | } |
1410 | ||
3ffb6964 BV |
1411 | static int hw_dev_acquisition_stop(const struct sr_dev_inst *sdi, |
1412 | void *cb_data) | |
28a35d8a | 1413 | { |
0e1357e8 | 1414 | struct dev_context *devc; |
6aac7737 HE |
1415 | uint8_t modestatus; |
1416 | ||
cb93f8a9 | 1417 | /* Avoid compiler warnings. */ |
3cd3a20b | 1418 | (void)cb_data; |
28a35d8a | 1419 | |
0e1357e8 | 1420 | if (!(devc = sdi->priv)) { |
7b48d6e1 | 1421 | sr_err("sigma: %s: sdi->priv was NULL", __func__); |
3010f21c UH |
1422 | return SR_ERR_BUG; |
1423 | } | |
1424 | ||
fefa1800 | 1425 | /* Stop acquisition. */ |
0e1357e8 | 1426 | sigma_set_register(WRITE_MODE, 0x11, devc); |
28a35d8a | 1427 | |
6aac7737 | 1428 | /* Set SDRAM Read Enable. */ |
0e1357e8 | 1429 | sigma_set_register(WRITE_MODE, 0x02, devc); |
6aac7737 HE |
1430 | |
1431 | /* Get the current position. */ | |
0e1357e8 | 1432 | sigma_read_pos(&devc->state.stoppos, &devc->state.triggerpos, devc); |
6aac7737 HE |
1433 | |
1434 | /* Check if trigger has fired. */ | |
0e1357e8 | 1435 | modestatus = sigma_get_register(READ_MODE, devc); |
3010f21c | 1436 | if (modestatus & 0x20) |
0e1357e8 | 1437 | devc->state.triggerchunk = devc->state.triggerpos / 512; |
3010f21c | 1438 | else |
0e1357e8 | 1439 | devc->state.triggerchunk = -1; |
6aac7737 | 1440 | |
0e1357e8 | 1441 | devc->state.chunks_downloaded = 0; |
6aac7737 | 1442 | |
0e1357e8 | 1443 | devc->state.state = SIGMA_DOWNLOAD; |
3010f21c UH |
1444 | |
1445 | return SR_OK; | |
28a35d8a HE |
1446 | } |
1447 | ||
c09f0b57 | 1448 | SR_PRIV struct sr_dev_driver asix_sigma_driver_info = { |
e519ba86 | 1449 | .name = "asix-sigma", |
6352d030 | 1450 | .longname = "ASIX SIGMA/SIGMA2", |
e519ba86 UH |
1451 | .api_version = 1, |
1452 | .init = hw_init, | |
1453 | .cleanup = hw_cleanup, | |
61136ea6 | 1454 | .scan = hw_scan, |
e7eb703f UH |
1455 | .dev_open = hw_dev_open, |
1456 | .dev_close = hw_dev_close, | |
41479605 | 1457 | .info_get = hw_info_get, |
a9a245b4 | 1458 | .dev_config_set = hw_dev_config_set, |
6b3dfec8 UH |
1459 | .dev_acquisition_start = hw_dev_acquisition_start, |
1460 | .dev_acquisition_stop = hw_dev_acquisition_stop, | |
0e1357e8 | 1461 | .priv = NULL, |
28a35d8a | 1462 | }; |