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Commit | Line | Data |
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28a35d8a HE |
1 | /* |
2 | * This file is part of the sigrok project. | |
3 | * | |
911f1834 UH |
4 | * Copyright (C) 2010 Håvard Espeland <gus@ping.uio.no>, |
5 | * Copyright (C) 2010 Martin Stensgård <mastensg@ping.uio.no> | |
6 | * Copyright (C) 2010 Carl Henrik Lunde <chlunde@ping.uio.no> | |
28a35d8a HE |
7 | * |
8 | * This program is free software: you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation, either version 3 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
20 | */ | |
21 | ||
911f1834 UH |
22 | /* |
23 | * ASIX Sigma Logic Analyzer Driver | |
24 | */ | |
25 | ||
28a35d8a HE |
26 | #include <ftdi.h> |
27 | #include <string.h> | |
28 | #include <zlib.h> | |
fefa1800 | 29 | #include <sigrok.h> |
28a35d8a HE |
30 | #include "asix-sigma.h" |
31 | ||
32 | #define USB_VENDOR 0xa600 | |
33 | #define USB_PRODUCT 0xa000 | |
34 | #define USB_DESCRIPTION "ASIX SIGMA" | |
35 | #define USB_VENDOR_NAME "ASIX" | |
36 | #define USB_MODEL_NAME "SIGMA" | |
37 | #define USB_MODEL_VERSION "" | |
28a35d8a HE |
38 | |
39 | static GSList *device_instances = NULL; | |
40 | ||
41 | // XXX These should be per device | |
42 | static struct ftdi_context ftdic; | |
43 | static uint64_t cur_samplerate = MHZ(200); | |
44 | static uint32_t limit_msec = 0; | |
45 | static struct timeval start_tv; | |
f6564c8d | 46 | static int cur_firmware = -1; |
28a35d8a HE |
47 | |
48 | static uint64_t supported_samplerates[] = { | |
e8397563 HE |
49 | MHZ(50), |
50 | MHZ(100), | |
28a35d8a HE |
51 | MHZ(200), |
52 | 0, | |
53 | }; | |
54 | ||
55 | static struct samplerates samplerates = { | |
e8397563 | 56 | MHZ(50), |
28a35d8a HE |
57 | MHZ(200), |
58 | 0, | |
59 | supported_samplerates, | |
60 | }; | |
61 | ||
62 | static int capabilities[] = { | |
63 | HWCAP_LOGIC_ANALYZER, | |
64 | HWCAP_SAMPLERATE, | |
65 | ||
66 | /* These are really implemented in the driver, not the hardware. */ | |
67 | HWCAP_LIMIT_MSEC, | |
68 | 0, | |
69 | }; | |
70 | ||
fefa1800 UH |
71 | /* Force the FPGA to reboot. */ |
72 | static uint8_t suicide[] = { | |
73 | 0x84, 0x84, 0x88, 0x84, 0x88, 0x84, 0x88, 0x84, | |
74 | }; | |
75 | ||
76 | /* Prepare to upload firmware (FPGA specific). */ | |
77 | static uint8_t init[] = { | |
78 | 0x03, 0x03, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, | |
79 | }; | |
80 | ||
81 | /* Initialize the logic analyzer mode. */ | |
82 | static uint8_t logic_mode_start[] = { | |
83 | 0x00, 0x40, 0x0f, 0x25, 0x35, 0x40, | |
84 | 0x2a, 0x3a, 0x40, 0x03, 0x20, 0x38, | |
85 | }; | |
86 | ||
f6564c8d HE |
87 | static const char *firmware_files[] = |
88 | { | |
89 | "asix-sigma-50.firmware", /* Supports fractions (8 bits) */ | |
f6564c8d HE |
90 | "asix-sigma-100.firmware", /* 100 MHz */ |
91 | "asix-sigma-200.firmware", /* 200 MHz */ | |
e8397563 | 92 | "asix-sigma-50sync.firmware", /* Asynchronous sampling */ |
f6564c8d HE |
93 | "asix-sigma-phasor.firmware", /* Frequency counter */ |
94 | }; | |
95 | ||
96 | static int sigma_read(void* buf, size_t size) | |
28a35d8a HE |
97 | { |
98 | int ret; | |
fefa1800 UH |
99 | |
100 | ret = ftdi_read_data(&ftdic, (unsigned char *)buf, size); | |
28a35d8a HE |
101 | if (ret < 0) { |
102 | g_warning("ftdi_read_data failed: %s", | |
fefa1800 | 103 | ftdi_get_error_string(&ftdic)); |
28a35d8a HE |
104 | } |
105 | ||
106 | return ret; | |
107 | } | |
108 | ||
fefa1800 | 109 | static int sigma_write(void *buf, size_t size) |
28a35d8a HE |
110 | { |
111 | int ret; | |
fefa1800 UH |
112 | |
113 | ret = ftdi_write_data(&ftdic, (unsigned char *)buf, size); | |
28a35d8a HE |
114 | if (ret < 0) { |
115 | g_warning("ftdi_write_data failed: %s", | |
fefa1800 UH |
116 | ftdi_get_error_string(&ftdic)); |
117 | } else if ((size_t) ret != size) { | |
28a35d8a HE |
118 | g_warning("ftdi_write_data did not complete write\n"); |
119 | } | |
120 | ||
121 | return ret; | |
122 | } | |
123 | ||
124 | static int sigma_write_register(uint8_t reg, uint8_t *data, size_t len) | |
125 | { | |
126 | size_t i; | |
127 | uint8_t buf[len + 2]; | |
128 | int idx = 0; | |
129 | ||
130 | buf[idx++] = REG_ADDR_LOW | (reg & 0xf); | |
131 | buf[idx++] = REG_ADDR_HIGH | (reg >> 4); | |
132 | ||
fefa1800 | 133 | for (i = 0; i < len; ++i) { |
28a35d8a HE |
134 | buf[idx++] = REG_DATA_LOW | (data[i] & 0xf); |
135 | buf[idx++] = REG_DATA_HIGH_WRITE | (data[i] >> 4); | |
136 | } | |
137 | ||
138 | return sigma_write(buf, idx); | |
139 | } | |
140 | ||
141 | static int sigma_set_register(uint8_t reg, uint8_t value) | |
142 | { | |
143 | return sigma_write_register(reg, &value, 1); | |
144 | } | |
145 | ||
146 | static int sigma_read_register(uint8_t reg, uint8_t *data, size_t len) | |
147 | { | |
148 | uint8_t buf[3]; | |
fefa1800 | 149 | |
28a35d8a HE |
150 | buf[0] = REG_ADDR_LOW | (reg & 0xf); |
151 | buf[1] = REG_ADDR_HIGH | (reg >> 4); | |
28a35d8a HE |
152 | buf[2] = REG_READ_ADDR; |
153 | ||
154 | sigma_write(buf, sizeof(buf)); | |
155 | ||
156 | return sigma_read(data, len); | |
157 | } | |
158 | ||
159 | static uint8_t sigma_get_register(uint8_t reg) | |
160 | { | |
161 | uint8_t value; | |
fefa1800 | 162 | |
28a35d8a HE |
163 | if (1 != sigma_read_register(reg, &value, 1)) { |
164 | g_warning("Sigma_get_register: 1 byte expected"); | |
165 | return 0; | |
166 | } | |
167 | ||
168 | return value; | |
169 | } | |
170 | ||
171 | static int sigma_read_pos(uint32_t *stoppos, uint32_t *triggerpos) | |
172 | { | |
173 | uint8_t buf[] = { | |
174 | REG_ADDR_LOW | READ_TRIGGER_POS_LOW, | |
175 | ||
176 | REG_READ_ADDR | NEXT_REG, | |
177 | REG_READ_ADDR | NEXT_REG, | |
178 | REG_READ_ADDR | NEXT_REG, | |
179 | REG_READ_ADDR | NEXT_REG, | |
180 | REG_READ_ADDR | NEXT_REG, | |
181 | REG_READ_ADDR | NEXT_REG, | |
182 | }; | |
28a35d8a HE |
183 | uint8_t result[6]; |
184 | ||
185 | sigma_write(buf, sizeof(buf)); | |
186 | ||
187 | sigma_read(result, sizeof(result)); | |
188 | ||
189 | *triggerpos = result[0] | (result[1] << 8) | (result[2] << 16); | |
190 | *stoppos = result[3] | (result[4] << 8) | (result[5] << 16); | |
191 | ||
192 | return 1; | |
193 | } | |
194 | ||
195 | static int sigma_read_dram(uint16_t startchunk, size_t numchunks, uint8_t *data) | |
196 | { | |
197 | size_t i; | |
198 | uint8_t buf[4096]; | |
199 | int idx = 0; | |
200 | ||
fefa1800 | 201 | /* Send the startchunk. Index start with 1. */ |
28a35d8a HE |
202 | buf[0] = startchunk >> 8; |
203 | buf[1] = startchunk & 0xff; | |
204 | sigma_write_register(WRITE_MEMROW, buf, 2); | |
205 | ||
fefa1800 | 206 | /* Read the DRAM. */ |
28a35d8a HE |
207 | buf[idx++] = REG_DRAM_BLOCK; |
208 | buf[idx++] = REG_DRAM_WAIT_ACK; | |
209 | ||
210 | for (i = 0; i < numchunks; ++i) { | |
fefa1800 UH |
211 | /* Alternate bit to copy from DRAM to cache. */ |
212 | if (i != (numchunks - 1)) | |
213 | buf[idx++] = REG_DRAM_BLOCK | (((i + 1) % 2) << 4); | |
28a35d8a HE |
214 | |
215 | buf[idx++] = REG_DRAM_BLOCK_DATA | ((i % 2) << 4); | |
216 | ||
fefa1800 | 217 | if (i != (numchunks - 1)) |
28a35d8a HE |
218 | buf[idx++] = REG_DRAM_WAIT_ACK; |
219 | } | |
220 | ||
221 | sigma_write(buf, idx); | |
222 | ||
223 | return sigma_read(data, numchunks * CHUNK_SIZE); | |
224 | } | |
225 | ||
fefa1800 | 226 | /* Generate the bitbang stream for programming the FPGA. */ |
28a35d8a | 227 | static int bin2bitbang(const char *filename, |
fefa1800 | 228 | unsigned char **buf, size_t *buf_size) |
28a35d8a | 229 | { |
fefa1800 | 230 | FILE *f; |
28a35d8a HE |
231 | long file_size; |
232 | unsigned long offset = 0; | |
233 | unsigned char *p; | |
234 | uint8_t *compressed_buf, *firmware; | |
235 | uLongf csize, fwsize; | |
236 | const int buffer_size = 65536; | |
237 | size_t i; | |
fefa1800 UH |
238 | int c, ret, bit, v; |
239 | uint32_t imm = 0x3f6df2ab; | |
28a35d8a | 240 | |
fefa1800 | 241 | f = fopen(filename, "r"); |
28a35d8a HE |
242 | if (!f) { |
243 | g_warning("fopen(\"%s\", \"r\")", filename); | |
244 | return -1; | |
245 | } | |
246 | ||
247 | if (-1 == fseek(f, 0, SEEK_END)) { | |
248 | g_warning("fseek on %s failed", filename); | |
249 | fclose(f); | |
250 | return -1; | |
251 | } | |
252 | ||
253 | file_size = ftell(f); | |
254 | ||
255 | fseek(f, 0, SEEK_SET); | |
256 | ||
28a35d8a HE |
257 | compressed_buf = g_malloc(file_size); |
258 | firmware = g_malloc(buffer_size); | |
259 | ||
260 | if (!compressed_buf || !firmware) { | |
261 | g_warning("Error allocating buffers"); | |
262 | return -1; | |
263 | } | |
264 | ||
28a35d8a HE |
265 | csize = 0; |
266 | while ((c = getc(f)) != EOF) { | |
267 | imm = (imm + 0xa853753) % 177 + (imm * 0x8034052); | |
268 | compressed_buf[csize++] = c ^ imm; | |
269 | } | |
270 | fclose(f); | |
271 | ||
272 | fwsize = buffer_size; | |
273 | ret = uncompress(firmware, &fwsize, compressed_buf, csize); | |
274 | if (ret < 0) { | |
275 | g_free(compressed_buf); | |
276 | g_free(firmware); | |
277 | g_warning("Could not unpack Sigma firmware. (Error %d)\n", ret); | |
278 | return -1; | |
279 | } | |
280 | ||
281 | g_free(compressed_buf); | |
282 | ||
283 | *buf_size = fwsize * 2 * 8; | |
284 | ||
fefa1800 | 285 | *buf = p = (unsigned char *)g_malloc(*buf_size); |
28a35d8a HE |
286 | |
287 | if (!p) { | |
288 | g_warning("Error allocating buffers"); | |
289 | return -1; | |
290 | } | |
291 | ||
292 | for (i = 0; i < fwsize; ++i) { | |
28a35d8a | 293 | for (bit = 7; bit >= 0; --bit) { |
fefa1800 | 294 | v = firmware[i] & 1 << bit ? 0x40 : 0x00; |
28a35d8a HE |
295 | p[offset++] = v | 0x01; |
296 | p[offset++] = v; | |
297 | } | |
298 | } | |
299 | ||
300 | g_free(firmware); | |
301 | ||
302 | if (offset != *buf_size) { | |
303 | g_free(*buf); | |
304 | g_warning("Error reading firmware %s " | |
fefa1800 UH |
305 | "offset=%ld, file_size=%ld, buf_size=%zd\n", |
306 | filename, offset, file_size, *buf_size); | |
28a35d8a HE |
307 | |
308 | return -1; | |
309 | } | |
310 | ||
311 | return 0; | |
312 | } | |
313 | ||
314 | static int hw_init(char *deviceinfo) | |
315 | { | |
316 | struct sigrok_device_instance *sdi; | |
317 | ||
318 | deviceinfo = deviceinfo; | |
319 | ||
320 | ftdi_init(&ftdic); | |
321 | ||
fefa1800 UH |
322 | /* Look for SIGMAs. */ |
323 | if (ftdi_usb_open_desc(&ftdic, USB_VENDOR, USB_PRODUCT, | |
324 | USB_DESCRIPTION, NULL) < 0) | |
28a35d8a HE |
325 | return 0; |
326 | ||
fefa1800 | 327 | /* Register SIGMA device. */ |
28a35d8a HE |
328 | sdi = sigrok_device_instance_new(0, ST_INITIALIZING, |
329 | USB_VENDOR_NAME, USB_MODEL_NAME, USB_MODEL_VERSION); | |
330 | if (!sdi) | |
331 | return 0; | |
332 | ||
333 | device_instances = g_slist_append(device_instances, sdi); | |
334 | ||
fefa1800 | 335 | /* We will open the device again when we need it. */ |
28a35d8a HE |
336 | ftdi_usb_close(&ftdic); |
337 | ||
338 | return 1; | |
339 | } | |
340 | ||
f6564c8d | 341 | static int upload_firmware(int firmware_idx) |
28a35d8a HE |
342 | { |
343 | int ret; | |
344 | unsigned char *buf; | |
345 | unsigned char pins; | |
346 | size_t buf_size; | |
28a35d8a | 347 | unsigned char result[32]; |
e8397563 | 348 | char firmware_path[128]; |
28a35d8a | 349 | |
fefa1800 | 350 | /* Make sure it's an ASIX SIGMA. */ |
28a35d8a HE |
351 | if ((ret = ftdi_usb_open_desc(&ftdic, |
352 | USB_VENDOR, USB_PRODUCT, USB_DESCRIPTION, NULL)) < 0) { | |
28a35d8a | 353 | g_warning("ftdi_usb_open failed: %s", |
fefa1800 | 354 | ftdi_get_error_string(&ftdic)); |
28a35d8a HE |
355 | return 0; |
356 | } | |
357 | ||
358 | if ((ret = ftdi_set_bitmode(&ftdic, 0xdf, BITMODE_BITBANG)) < 0) { | |
359 | g_warning("ftdi_set_bitmode failed: %s", | |
fefa1800 | 360 | ftdi_get_error_string(&ftdic)); |
28a35d8a HE |
361 | return 0; |
362 | } | |
363 | ||
fefa1800 | 364 | /* Four times the speed of sigmalogan - Works well. */ |
28a35d8a HE |
365 | if ((ret = ftdi_set_baudrate(&ftdic, 750000)) < 0) { |
366 | g_warning("ftdi_set_baudrate failed: %s", | |
fefa1800 | 367 | ftdi_get_error_string(&ftdic)); |
28a35d8a HE |
368 | return 0; |
369 | } | |
370 | ||
fefa1800 | 371 | /* Force the FPGA to reboot. */ |
28a35d8a HE |
372 | sigma_write(suicide, sizeof(suicide)); |
373 | sigma_write(suicide, sizeof(suicide)); | |
374 | sigma_write(suicide, sizeof(suicide)); | |
375 | sigma_write(suicide, sizeof(suicide)); | |
376 | ||
fefa1800 | 377 | /* Prepare to upload firmware (FPGA specific). */ |
28a35d8a HE |
378 | sigma_write(init, sizeof(init)); |
379 | ||
380 | ftdi_usb_purge_buffers(&ftdic); | |
381 | ||
fefa1800 | 382 | /* Wait until the FPGA asserts INIT_B. */ |
28a35d8a HE |
383 | while (1) { |
384 | ret = sigma_read(result, 1); | |
385 | if (result[0] & 0x20) | |
386 | break; | |
387 | } | |
388 | ||
f6564c8d | 389 | /* Prepare firmware */ |
e8397563 | 390 | snprintf(firmware_path, sizeof(firmware_path), "%s/%s", FIRMWARE_DIR, |
f6564c8d HE |
391 | firmware_files[firmware_idx]); |
392 | ||
e8397563 | 393 | if (-1 == bin2bitbang(firmware_path, &buf, &buf_size)) { |
28a35d8a | 394 | g_warning("An error occured while reading the firmware: %s", |
e8397563 | 395 | firmware_path); |
28a35d8a HE |
396 | return SIGROK_ERR; |
397 | } | |
398 | ||
fefa1800 | 399 | /* Upload firmare. */ |
28a35d8a HE |
400 | sigma_write(buf, buf_size); |
401 | ||
402 | g_free(buf); | |
403 | ||
404 | if ((ret = ftdi_set_bitmode(&ftdic, 0x00, BITMODE_RESET)) < 0) { | |
f6564c8d | 405 | g_warning("ftdi_set_bitmode failed: %s", |
fefa1800 | 406 | ftdi_get_error_string(&ftdic)); |
28a35d8a HE |
407 | return SIGROK_ERR; |
408 | } | |
409 | ||
410 | ftdi_usb_purge_buffers(&ftdic); | |
411 | ||
fefa1800 | 412 | /* Discard garbage. */ |
28a35d8a HE |
413 | while (1 == sigma_read(&pins, 1)) |
414 | ; | |
415 | ||
fefa1800 | 416 | /* Initialize the logic analyzer mode. */ |
28a35d8a HE |
417 | sigma_write(logic_mode_start, sizeof(logic_mode_start)); |
418 | ||
fefa1800 | 419 | /* Expect a 3 byte reply. */ |
28a35d8a HE |
420 | ret = sigma_read(result, 3); |
421 | if (ret != 3 || | |
422 | result[0] != 0xa6 || result[1] != 0x55 || result[2] != 0xaa) { | |
fefa1800 | 423 | g_warning("Configuration failed. Invalid reply received."); |
28a35d8a HE |
424 | return SIGROK_ERR; |
425 | } | |
426 | ||
f6564c8d HE |
427 | cur_firmware = firmware_idx; |
428 | ||
429 | return SIGROK_OK; | |
430 | } | |
431 | ||
432 | static int hw_opendev(int device_index) | |
433 | { | |
434 | struct sigrok_device_instance *sdi; | |
435 | int ret; | |
436 | ||
437 | /* Make sure it's an ASIX SIGMA */ | |
438 | if ((ret = ftdi_usb_open_desc(&ftdic, | |
439 | USB_VENDOR, USB_PRODUCT, USB_DESCRIPTION, NULL)) < 0) { | |
440 | ||
441 | g_warning("ftdi_usb_open failed: %s", | |
442 | ftdi_get_error_string(&ftdic)); | |
443 | ||
444 | return 0; | |
445 | } | |
28a35d8a HE |
446 | |
447 | if (!(sdi = get_sigrok_device_instance(device_instances, device_index))) | |
448 | return SIGROK_ERR; | |
449 | ||
450 | sdi->status = ST_ACTIVE; | |
451 | ||
f6564c8d HE |
452 | return SIGROK_OK; |
453 | } | |
454 | ||
455 | static int set_samplerate(struct sigrok_device_instance *sdi, uint64_t samplerate) | |
456 | { | |
e8397563 | 457 | int i, ret; |
f6564c8d HE |
458 | |
459 | sdi = sdi; | |
460 | ||
461 | for (i = 0; supported_samplerates[i]; i++) { | |
462 | if (supported_samplerates[i] == samplerate) | |
463 | break; | |
464 | } | |
465 | if (supported_samplerates[i] == 0) | |
466 | return SIGROK_ERR_SAMPLERATE; | |
467 | ||
e8397563 HE |
468 | if (samplerate <= MHZ(50)) { |
469 | ret = upload_firmware(0); | |
470 | // XXX: Setup divider | |
471 | } | |
472 | if (samplerate == MHZ(100)) | |
473 | ret = upload_firmware(1); | |
474 | else if (samplerate == MHZ(200)) | |
475 | ret = upload_firmware(2); | |
f6564c8d | 476 | |
e8397563 | 477 | cur_samplerate = samplerate; |
f6564c8d | 478 | |
28a35d8a HE |
479 | g_message("Firmware uploaded"); |
480 | ||
e8397563 | 481 | return ret; |
28a35d8a HE |
482 | } |
483 | ||
28a35d8a HE |
484 | static void hw_closedev(int device_index) |
485 | { | |
486 | device_index = device_index; | |
487 | ||
488 | ftdi_usb_close(&ftdic); | |
489 | } | |
490 | ||
28a35d8a HE |
491 | static void hw_cleanup(void) |
492 | { | |
493 | } | |
494 | ||
28a35d8a HE |
495 | static void *hw_get_device_info(int device_index, int device_info_id) |
496 | { | |
497 | struct sigrok_device_instance *sdi; | |
498 | void *info = NULL; | |
499 | ||
500 | if (!(sdi = get_sigrok_device_instance(device_instances, device_index))) { | |
501 | fprintf(stderr, "It's NULL.\n"); | |
502 | return NULL; | |
503 | } | |
504 | ||
505 | switch (device_info_id) { | |
506 | case DI_INSTANCE: | |
507 | info = sdi; | |
508 | break; | |
509 | case DI_NUM_PROBES: | |
510 | info = GINT_TO_POINTER(4); | |
511 | break; | |
512 | case DI_SAMPLERATES: | |
513 | info = &samplerates; | |
514 | break; | |
515 | case DI_TRIGGER_TYPES: | |
fefa1800 | 516 | info = 0; //TRIGGER_TYPES; |
28a35d8a HE |
517 | break; |
518 | case DI_CUR_SAMPLERATE: | |
519 | info = &cur_samplerate; | |
520 | break; | |
521 | } | |
522 | ||
523 | return info; | |
524 | } | |
525 | ||
28a35d8a HE |
526 | static int hw_get_status(int device_index) |
527 | { | |
528 | struct sigrok_device_instance *sdi; | |
529 | ||
530 | sdi = get_sigrok_device_instance(device_instances, device_index); | |
531 | if (sdi) | |
532 | return sdi->status; | |
533 | else | |
534 | return ST_NOT_FOUND; | |
535 | } | |
536 | ||
28a35d8a HE |
537 | static int *hw_get_capabilities(void) |
538 | { | |
539 | return capabilities; | |
540 | } | |
541 | ||
542 | static int hw_set_configuration(int device_index, int capability, void *value) | |
543 | { | |
544 | struct sigrok_device_instance *sdi; | |
545 | int ret; | |
f6564c8d | 546 | |
28a35d8a HE |
547 | if (!(sdi = get_sigrok_device_instance(device_instances, device_index))) |
548 | return SIGROK_ERR; | |
549 | ||
550 | if (capability == HWCAP_SAMPLERATE) { | |
f6564c8d | 551 | ret = set_samplerate(sdi, *(uint64_t*) value); |
28a35d8a HE |
552 | } else if (capability == HWCAP_PROBECONFIG) { |
553 | ret = SIGROK_OK; | |
554 | } else if (capability == HWCAP_LIMIT_MSEC) { | |
555 | limit_msec = strtoull(value, NULL, 10); | |
556 | ret = SIGROK_OK; | |
557 | } else { | |
558 | ret = SIGROK_ERR; | |
559 | } | |
560 | ||
561 | return ret; | |
562 | } | |
563 | ||
28a35d8a | 564 | /* |
fefa1800 UH |
565 | * Decode chunk of 1024 bytes, 64 clusters, 7 events per cluster. |
566 | * Each event is 20ns apart, and can contain multiple samples. | |
567 | * For 200 MHz, an event contains 4 samples for each channel, | |
568 | * spread 5 ns apart. | |
28a35d8a HE |
569 | */ |
570 | static int decode_chunk_ts(uint8_t *buf, uint16_t *lastts, | |
571 | uint8_t *lastsample, void *user_data) | |
572 | { | |
573 | const int samples_per_event = 4; | |
fefa1800 | 574 | uint16_t tsdiff, ts; |
28a35d8a | 575 | uint8_t samples[65536 * samples_per_event]; |
28a35d8a | 576 | struct datafeed_packet packet; |
fefa1800 UH |
577 | int i, j, k, numpad, tosend; |
578 | size_t n = 0, sent = 0; | |
28a35d8a | 579 | int clustersize = EVENTS_PER_CLUSTER * samples_per_event; /* 4 for 200 MHz */ |
fefa1800 | 580 | uint16_t *event; |
28a35d8a HE |
581 | |
582 | /* For each ts */ | |
583 | for (i = 0; i < 64; ++i) { | |
fefa1800 | 584 | ts = *(uint16_t *) &buf[i * 16]; |
28a35d8a HE |
585 | tsdiff = ts - *lastts; |
586 | *lastts = ts; | |
587 | ||
fefa1800 UH |
588 | /* Pad last sample up to current point. */ |
589 | numpad = tsdiff * samples_per_event - clustersize; | |
28a35d8a HE |
590 | if (numpad > 0) { |
591 | memset(samples, *lastsample, | |
fefa1800 UH |
592 | tsdiff * samples_per_event - clustersize); |
593 | n = tsdiff * samples_per_event - clustersize; | |
28a35d8a HE |
594 | } |
595 | ||
fefa1800 | 596 | event = (uint16_t *) &buf[i * 16 + 2]; |
28a35d8a | 597 | |
fefa1800 | 598 | /* For each sample in cluster. */ |
28a35d8a HE |
599 | for (j = 0; j < 7; ++j) { |
600 | for (k = 0; k < samples_per_event; ++k) { | |
fefa1800 UH |
601 | /* |
602 | * Extract samples from bytestream. | |
603 | * Samples are packed together in a short. | |
604 | */ | |
28a35d8a | 605 | samples[n++] = |
fefa1800 UH |
606 | ((!!(event[j] & (1 << (k + 0x0)))) << 0) | |
607 | ((!!(event[j] & (1 << (k + 0x4)))) << 1) | | |
608 | ((!!(event[j] & (1 << (k + 0x8)))) << 2) | | |
609 | ((!!(event[j] & (1 << (k + 0xc)))) << 3); | |
28a35d8a HE |
610 | } |
611 | } | |
612 | ||
fefa1800 | 613 | *lastsample = samples[n - 1]; |
28a35d8a | 614 | |
fefa1800 UH |
615 | /* Send to sigrok. */ |
616 | sent = 0; | |
28a35d8a | 617 | while (sent < n) { |
fefa1800 | 618 | tosend = MIN(4096, n - sent); |
28a35d8a HE |
619 | |
620 | packet.type = DF_LOGIC8; | |
621 | packet.length = tosend; | |
fefa1800 | 622 | packet.payload = samples + sent; |
28a35d8a HE |
623 | session_bus(user_data, &packet); |
624 | ||
625 | sent += tosend; | |
626 | } | |
627 | } | |
628 | ||
629 | return 0; | |
630 | } | |
631 | ||
632 | static int receive_data(int fd, int revents, void *user_data) | |
633 | { | |
634 | struct datafeed_packet packet; | |
28a35d8a HE |
635 | const int chunks_per_read = 32; |
636 | unsigned char buf[chunks_per_read * CHUNK_SIZE]; | |
fefa1800 UH |
637 | int bufsz, numchunks, curchunk, i, newchunks; |
638 | uint32_t triggerpos, stoppos, running_msec; | |
28a35d8a | 639 | struct timeval tv; |
28a35d8a HE |
640 | uint16_t lastts = 0; |
641 | uint8_t lastsample = 0; | |
28a35d8a HE |
642 | |
643 | fd = fd; | |
644 | revents = revents; | |
645 | ||
fefa1800 | 646 | /* Get the current position. */ |
28a35d8a HE |
647 | sigma_read_pos(&stoppos, &triggerpos); |
648 | numchunks = stoppos / 512; | |
649 | ||
fefa1800 | 650 | /* Check if the has expired, or memory is full. */ |
28a35d8a HE |
651 | gettimeofday(&tv, 0); |
652 | running_msec = (tv.tv_sec - start_tv.tv_sec) * 1000 + | |
fefa1800 | 653 | (tv.tv_usec - start_tv.tv_usec) / 1000; |
28a35d8a HE |
654 | |
655 | if (running_msec < limit_msec && numchunks < 32767) | |
656 | return FALSE; | |
657 | ||
fefa1800 | 658 | /* Stop acqusition. */ |
28a35d8a HE |
659 | sigma_set_register(WRITE_MODE, 0x11); |
660 | ||
fefa1800 | 661 | /* Set SDRAM Read Enable. */ |
28a35d8a HE |
662 | sigma_set_register(WRITE_MODE, 0x02); |
663 | ||
fefa1800 | 664 | /* Get the current position. */ |
28a35d8a HE |
665 | sigma_read_pos(&stoppos, &triggerpos); |
666 | ||
fefa1800 | 667 | /* Download sample data. */ |
28a35d8a | 668 | for (curchunk = 0; curchunk < numchunks;) { |
fefa1800 | 669 | newchunks = MIN(chunks_per_read, numchunks - curchunk); |
28a35d8a HE |
670 | |
671 | g_message("Downloading sample data: %.0f %%", | |
fefa1800 | 672 | 100.0 * curchunk / numchunks); |
28a35d8a HE |
673 | |
674 | bufsz = sigma_read_dram(curchunk, newchunks, buf); | |
675 | ||
fefa1800 UH |
676 | /* Find first ts. */ |
677 | if (curchunk == 0) | |
678 | lastts = *(uint16_t *) buf - 1; | |
28a35d8a | 679 | |
fefa1800 | 680 | /* Decode chunks and send them to sigrok. */ |
28a35d8a HE |
681 | for (i = 0; i < newchunks; ++i) { |
682 | decode_chunk_ts(buf + (i * CHUNK_SIZE), | |
683 | &lastts, &lastsample, user_data); | |
684 | } | |
685 | ||
686 | curchunk += newchunks; | |
687 | } | |
688 | ||
689 | /* End of data */ | |
690 | packet.type = DF_END; | |
691 | packet.length = 0; | |
692 | session_bus(user_data, &packet); | |
693 | ||
694 | return TRUE; | |
695 | } | |
696 | ||
697 | static int hw_start_acquisition(int device_index, gpointer session_device_id) | |
698 | { | |
699 | struct sigrok_device_instance *sdi; | |
700 | struct datafeed_packet packet; | |
701 | struct datafeed_header header; | |
fefa1800 | 702 | uint8_t trigger_option[2] = { 0x38, 0x00 }; |
28a35d8a HE |
703 | |
704 | session_device_id = session_device_id; | |
705 | ||
706 | if (!(sdi = get_sigrok_device_instance(device_instances, device_index))) | |
707 | return SIGROK_ERR; | |
708 | ||
709 | device_index = device_index; | |
710 | ||
e8397563 HE |
711 | if (cur_firmware == -1) { |
712 | /* Samplerate has not been set. Default to 200 MHz */ | |
713 | set_samplerate(sdi, 200); | |
714 | } | |
715 | ||
fefa1800 | 716 | /* Setup trigger (by trigger-in). */ |
28a35d8a HE |
717 | sigma_set_register(WRITE_TRIGGER_SELECT1, 0x20); |
718 | ||
fefa1800 | 719 | /* More trigger setup. */ |
28a35d8a | 720 | sigma_write_register(WRITE_TRIGGER_OPTION, |
fefa1800 | 721 | trigger_option, sizeof(trigger_option)); |
28a35d8a | 722 | |
fefa1800 | 723 | /* Trigger normal (falling edge). */ |
28a35d8a HE |
724 | sigma_set_register(WRITE_TRIGGER_SELECT1, 0x08); |
725 | ||
fefa1800 | 726 | /* Enable pins (200 MHz, 4 pins). */ |
28a35d8a HE |
727 | sigma_set_register(WRITE_CLOCK_SELECT, 0xf0); |
728 | ||
fefa1800 | 729 | /* Setup maximum post trigger time. */ |
28a35d8a HE |
730 | sigma_set_register(WRITE_POST_TRIGGER, 0xff); |
731 | ||
fefa1800 | 732 | /* Start acqusition (software trigger start). */ |
28a35d8a HE |
733 | gettimeofday(&start_tv, 0); |
734 | sigma_set_register(WRITE_MODE, 0x0d); | |
735 | ||
fefa1800 | 736 | /* Add capture source. */ |
28a35d8a HE |
737 | source_add(0, G_IO_IN, 10, receive_data, session_device_id); |
738 | ||
739 | receive_data(0, 1, session_device_id); | |
740 | ||
741 | /* Send header packet to the session bus. */ | |
742 | packet.type = DF_HEADER; | |
743 | packet.length = sizeof(struct datafeed_header); | |
744 | packet.payload = &header; | |
745 | header.feed_version = 1; | |
746 | gettimeofday(&header.starttime, NULL); | |
747 | header.samplerate = cur_samplerate; | |
748 | header.protocol_id = PROTO_RAW; | |
749 | header.num_probes = 4; | |
750 | session_bus(session_device_id, &packet); | |
751 | ||
752 | return SIGROK_OK; | |
753 | } | |
754 | ||
28a35d8a HE |
755 | static void hw_stop_acquisition(int device_index, gpointer session_device_id) |
756 | { | |
757 | device_index = device_index; | |
758 | session_device_id = session_device_id; | |
759 | ||
fefa1800 | 760 | /* Stop acquisition. */ |
28a35d8a HE |
761 | sigma_set_register(WRITE_MODE, 0x11); |
762 | ||
763 | // XXX Set some state to indicate that data should be sent to sigrok | |
764 | // Now, we just wait for timeout | |
765 | } | |
766 | ||
28a35d8a HE |
767 | struct device_plugin asix_sigma_plugin_info = { |
768 | "asix-sigma", | |
769 | 1, | |
770 | hw_init, | |
771 | hw_cleanup, | |
28a35d8a HE |
772 | hw_opendev, |
773 | hw_closedev, | |
774 | hw_get_device_info, | |
775 | hw_get_status, | |
776 | hw_get_capabilities, | |
777 | hw_set_configuration, | |
778 | hw_start_acquisition, | |
779 | hw_stop_acquisition | |
780 | }; |