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Commit | Line | Data |
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28a35d8a HE |
1 | /* |
2 | * This file is part of the sigrok project. | |
3 | * | |
868501fa | 4 | * Copyright (C) 2010-2012 Håvard Espeland <gus@ping.uio.no>, |
911f1834 UH |
5 | * Copyright (C) 2010 Martin Stensgård <mastensg@ping.uio.no> |
6 | * Copyright (C) 2010 Carl Henrik Lunde <chlunde@ping.uio.no> | |
28a35d8a HE |
7 | * |
8 | * This program is free software: you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation, either version 3 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
20 | */ | |
21 | ||
911f1834 | 22 | /* |
6352d030 | 23 | * ASIX SIGMA/SIGMA2 logic analyzer driver |
911f1834 UH |
24 | */ |
25 | ||
3bbd9849 UH |
26 | #include <glib.h> |
27 | #include <glib/gstdio.h> | |
28a35d8a HE |
28 | #include <ftdi.h> |
29 | #include <string.h> | |
45c59c8b BV |
30 | #include "libsigrok.h" |
31 | #include "libsigrok-internal.h" | |
28a35d8a HE |
32 | #include "asix-sigma.h" |
33 | ||
34 | #define USB_VENDOR 0xa600 | |
35 | #define USB_PRODUCT 0xa000 | |
36 | #define USB_DESCRIPTION "ASIX SIGMA" | |
37 | #define USB_VENDOR_NAME "ASIX" | |
38 | #define USB_MODEL_NAME "SIGMA" | |
39 | #define USB_MODEL_VERSION "" | |
ee492173 | 40 | #define TRIGGER_TYPES "rf10" |
464d12c7 | 41 | #define NUM_PROBES 16 |
28a35d8a | 42 | |
ed300b9f BV |
43 | SR_PRIV struct sr_dev_driver asix_sigma_driver_info; |
44 | static struct sr_dev_driver *adi = &asix_sigma_driver_info; | |
28a35d8a | 45 | |
a533743d | 46 | static const uint64_t supported_samplerates[] = { |
59df0c77 UH |
47 | SR_KHZ(200), |
48 | SR_KHZ(250), | |
49 | SR_KHZ(500), | |
50 | SR_MHZ(1), | |
51 | SR_MHZ(5), | |
52 | SR_MHZ(10), | |
53 | SR_MHZ(25), | |
54 | SR_MHZ(50), | |
55 | SR_MHZ(100), | |
56 | SR_MHZ(200), | |
28a35d8a HE |
57 | 0, |
58 | }; | |
59 | ||
d261dbbf UH |
60 | /* |
61 | * Probe numbers seem to go from 1-16, according to this image: | |
62 | * http://tools.asix.net/img/sigma_sigmacab_pins_720.jpg | |
63 | * (the cable has two additional GND pins, and a TI and TO pin) | |
64 | */ | |
c37d2b1b | 65 | static const char *probe_names[NUM_PROBES + 1] = { |
464d12c7 KS |
66 | "1", |
67 | "2", | |
68 | "3", | |
69 | "4", | |
70 | "5", | |
71 | "6", | |
72 | "7", | |
73 | "8", | |
74 | "9", | |
75 | "10", | |
76 | "11", | |
77 | "12", | |
78 | "13", | |
79 | "14", | |
80 | "15", | |
d261dbbf | 81 | "16", |
464d12c7 KS |
82 | NULL, |
83 | }; | |
84 | ||
a533743d | 85 | static const struct sr_samplerates samplerates = { |
590b9f9a UH |
86 | 0, |
87 | 0, | |
88 | 0, | |
28a35d8a HE |
89 | supported_samplerates, |
90 | }; | |
91 | ||
915f7cc8 | 92 | static const int hwcaps[] = { |
5a2326a7 UH |
93 | SR_HWCAP_LOGIC_ANALYZER, |
94 | SR_HWCAP_SAMPLERATE, | |
95 | SR_HWCAP_CAPTURE_RATIO, | |
96 | SR_HWCAP_PROBECONFIG, | |
28a35d8a | 97 | |
5a2326a7 | 98 | SR_HWCAP_LIMIT_MSEC, |
28a35d8a HE |
99 | 0, |
100 | }; | |
101 | ||
fefa1800 UH |
102 | /* Force the FPGA to reboot. */ |
103 | static uint8_t suicide[] = { | |
104 | 0x84, 0x84, 0x88, 0x84, 0x88, 0x84, 0x88, 0x84, | |
105 | }; | |
106 | ||
107 | /* Prepare to upload firmware (FPGA specific). */ | |
108 | static uint8_t init[] = { | |
109 | 0x03, 0x03, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, | |
110 | }; | |
111 | ||
112 | /* Initialize the logic analyzer mode. */ | |
113 | static uint8_t logic_mode_start[] = { | |
114 | 0x00, 0x40, 0x0f, 0x25, 0x35, 0x40, | |
115 | 0x2a, 0x3a, 0x40, 0x03, 0x20, 0x38, | |
116 | }; | |
117 | ||
eec5275e | 118 | static const char *firmware_files[] = { |
a8116d76 HE |
119 | "asix-sigma-50.fw", /* 50 MHz, supports 8 bit fractions */ |
120 | "asix-sigma-100.fw", /* 100 MHz */ | |
121 | "asix-sigma-200.fw", /* 200 MHz */ | |
ed09fd07 | 122 | "asix-sigma-50sync.fw", /* Synchronous clock from pin */ |
a8116d76 | 123 | "asix-sigma-phasor.fw", /* Frequency counter */ |
f6564c8d HE |
124 | }; |
125 | ||
3ffb6964 BV |
126 | static int hw_dev_acquisition_stop(const struct sr_dev_inst *sdi, |
127 | void *cb_data); | |
6aac7737 | 128 | |
0e1357e8 | 129 | static int sigma_read(void *buf, size_t size, struct dev_context *devc) |
28a35d8a HE |
130 | { |
131 | int ret; | |
fefa1800 | 132 | |
0e1357e8 | 133 | ret = ftdi_read_data(&devc->ftdic, (unsigned char *)buf, size); |
28a35d8a | 134 | if (ret < 0) { |
7b48d6e1 | 135 | sr_err("sigma: ftdi_read_data failed: %s", |
0e1357e8 | 136 | ftdi_get_error_string(&devc->ftdic)); |
28a35d8a HE |
137 | } |
138 | ||
139 | return ret; | |
140 | } | |
141 | ||
0e1357e8 | 142 | static int sigma_write(void *buf, size_t size, struct dev_context *devc) |
28a35d8a HE |
143 | { |
144 | int ret; | |
fefa1800 | 145 | |
0e1357e8 | 146 | ret = ftdi_write_data(&devc->ftdic, (unsigned char *)buf, size); |
28a35d8a | 147 | if (ret < 0) { |
7b48d6e1 | 148 | sr_err("sigma: ftdi_write_data failed: %s", |
0e1357e8 | 149 | ftdi_get_error_string(&devc->ftdic)); |
fefa1800 | 150 | } else if ((size_t) ret != size) { |
0aeb0ccd | 151 | sr_err("sigma: ftdi_write_data did not complete write."); |
28a35d8a HE |
152 | } |
153 | ||
154 | return ret; | |
155 | } | |
156 | ||
99965709 | 157 | static int sigma_write_register(uint8_t reg, uint8_t *data, size_t len, |
0e1357e8 | 158 | struct dev_context *devc) |
28a35d8a HE |
159 | { |
160 | size_t i; | |
161 | uint8_t buf[len + 2]; | |
162 | int idx = 0; | |
163 | ||
164 | buf[idx++] = REG_ADDR_LOW | (reg & 0xf); | |
165 | buf[idx++] = REG_ADDR_HIGH | (reg >> 4); | |
166 | ||
fefa1800 | 167 | for (i = 0; i < len; ++i) { |
28a35d8a HE |
168 | buf[idx++] = REG_DATA_LOW | (data[i] & 0xf); |
169 | buf[idx++] = REG_DATA_HIGH_WRITE | (data[i] >> 4); | |
170 | } | |
171 | ||
0e1357e8 | 172 | return sigma_write(buf, idx, devc); |
28a35d8a HE |
173 | } |
174 | ||
0e1357e8 | 175 | static int sigma_set_register(uint8_t reg, uint8_t value, struct dev_context *devc) |
28a35d8a | 176 | { |
0e1357e8 | 177 | return sigma_write_register(reg, &value, 1, devc); |
28a35d8a HE |
178 | } |
179 | ||
99965709 | 180 | static int sigma_read_register(uint8_t reg, uint8_t *data, size_t len, |
0e1357e8 | 181 | struct dev_context *devc) |
28a35d8a HE |
182 | { |
183 | uint8_t buf[3]; | |
fefa1800 | 184 | |
28a35d8a HE |
185 | buf[0] = REG_ADDR_LOW | (reg & 0xf); |
186 | buf[1] = REG_ADDR_HIGH | (reg >> 4); | |
28a35d8a HE |
187 | buf[2] = REG_READ_ADDR; |
188 | ||
0e1357e8 | 189 | sigma_write(buf, sizeof(buf), devc); |
28a35d8a | 190 | |
0e1357e8 | 191 | return sigma_read(data, len, devc); |
28a35d8a HE |
192 | } |
193 | ||
0e1357e8 | 194 | static uint8_t sigma_get_register(uint8_t reg, struct dev_context *devc) |
28a35d8a HE |
195 | { |
196 | uint8_t value; | |
fefa1800 | 197 | |
0e1357e8 | 198 | if (1 != sigma_read_register(reg, &value, 1, devc)) { |
7b48d6e1 | 199 | sr_err("sigma: sigma_get_register: 1 byte expected"); |
28a35d8a HE |
200 | return 0; |
201 | } | |
202 | ||
203 | return value; | |
204 | } | |
205 | ||
99965709 | 206 | static int sigma_read_pos(uint32_t *stoppos, uint32_t *triggerpos, |
0e1357e8 | 207 | struct dev_context *devc) |
28a35d8a HE |
208 | { |
209 | uint8_t buf[] = { | |
210 | REG_ADDR_LOW | READ_TRIGGER_POS_LOW, | |
211 | ||
212 | REG_READ_ADDR | NEXT_REG, | |
213 | REG_READ_ADDR | NEXT_REG, | |
214 | REG_READ_ADDR | NEXT_REG, | |
215 | REG_READ_ADDR | NEXT_REG, | |
216 | REG_READ_ADDR | NEXT_REG, | |
217 | REG_READ_ADDR | NEXT_REG, | |
218 | }; | |
28a35d8a HE |
219 | uint8_t result[6]; |
220 | ||
0e1357e8 | 221 | sigma_write(buf, sizeof(buf), devc); |
28a35d8a | 222 | |
0e1357e8 | 223 | sigma_read(result, sizeof(result), devc); |
28a35d8a HE |
224 | |
225 | *triggerpos = result[0] | (result[1] << 8) | (result[2] << 16); | |
226 | *stoppos = result[3] | (result[4] << 8) | (result[5] << 16); | |
227 | ||
57bbf56b HE |
228 | /* Not really sure why this must be done, but according to spec. */ |
229 | if ((--*stoppos & 0x1ff) == 0x1ff) | |
230 | stoppos -= 64; | |
231 | ||
232 | if ((*--triggerpos & 0x1ff) == 0x1ff) | |
233 | triggerpos -= 64; | |
234 | ||
28a35d8a HE |
235 | return 1; |
236 | } | |
237 | ||
99965709 | 238 | static int sigma_read_dram(uint16_t startchunk, size_t numchunks, |
0e1357e8 | 239 | uint8_t *data, struct dev_context *devc) |
28a35d8a HE |
240 | { |
241 | size_t i; | |
242 | uint8_t buf[4096]; | |
243 | int idx = 0; | |
244 | ||
fefa1800 | 245 | /* Send the startchunk. Index start with 1. */ |
28a35d8a HE |
246 | buf[0] = startchunk >> 8; |
247 | buf[1] = startchunk & 0xff; | |
0e1357e8 | 248 | sigma_write_register(WRITE_MEMROW, buf, 2, devc); |
28a35d8a | 249 | |
fefa1800 | 250 | /* Read the DRAM. */ |
28a35d8a HE |
251 | buf[idx++] = REG_DRAM_BLOCK; |
252 | buf[idx++] = REG_DRAM_WAIT_ACK; | |
253 | ||
254 | for (i = 0; i < numchunks; ++i) { | |
fefa1800 UH |
255 | /* Alternate bit to copy from DRAM to cache. */ |
256 | if (i != (numchunks - 1)) | |
257 | buf[idx++] = REG_DRAM_BLOCK | (((i + 1) % 2) << 4); | |
28a35d8a HE |
258 | |
259 | buf[idx++] = REG_DRAM_BLOCK_DATA | ((i % 2) << 4); | |
260 | ||
fefa1800 | 261 | if (i != (numchunks - 1)) |
28a35d8a HE |
262 | buf[idx++] = REG_DRAM_WAIT_ACK; |
263 | } | |
264 | ||
0e1357e8 | 265 | sigma_write(buf, idx, devc); |
28a35d8a | 266 | |
0e1357e8 | 267 | return sigma_read(data, numchunks * CHUNK_SIZE, devc); |
28a35d8a HE |
268 | } |
269 | ||
4ae1f451 | 270 | /* Upload trigger look-up tables to Sigma. */ |
0e1357e8 | 271 | static int sigma_write_trigger_lut(struct triggerlut *lut, struct dev_context *devc) |
ee492173 HE |
272 | { |
273 | int i; | |
274 | uint8_t tmp[2]; | |
275 | uint16_t bit; | |
276 | ||
277 | /* Transpose the table and send to Sigma. */ | |
278 | for (i = 0; i < 16; ++i) { | |
279 | bit = 1 << i; | |
280 | ||
281 | tmp[0] = tmp[1] = 0; | |
282 | ||
283 | if (lut->m2d[0] & bit) | |
284 | tmp[0] |= 0x01; | |
285 | if (lut->m2d[1] & bit) | |
286 | tmp[0] |= 0x02; | |
287 | if (lut->m2d[2] & bit) | |
288 | tmp[0] |= 0x04; | |
289 | if (lut->m2d[3] & bit) | |
290 | tmp[0] |= 0x08; | |
291 | ||
292 | if (lut->m3 & bit) | |
293 | tmp[0] |= 0x10; | |
294 | if (lut->m3s & bit) | |
295 | tmp[0] |= 0x20; | |
296 | if (lut->m4 & bit) | |
297 | tmp[0] |= 0x40; | |
298 | ||
299 | if (lut->m0d[0] & bit) | |
300 | tmp[1] |= 0x01; | |
301 | if (lut->m0d[1] & bit) | |
302 | tmp[1] |= 0x02; | |
303 | if (lut->m0d[2] & bit) | |
304 | tmp[1] |= 0x04; | |
305 | if (lut->m0d[3] & bit) | |
306 | tmp[1] |= 0x08; | |
307 | ||
308 | if (lut->m1d[0] & bit) | |
309 | tmp[1] |= 0x10; | |
310 | if (lut->m1d[1] & bit) | |
311 | tmp[1] |= 0x20; | |
312 | if (lut->m1d[2] & bit) | |
313 | tmp[1] |= 0x40; | |
314 | if (lut->m1d[3] & bit) | |
315 | tmp[1] |= 0x80; | |
316 | ||
99965709 | 317 | sigma_write_register(WRITE_TRIGGER_SELECT0, tmp, sizeof(tmp), |
0e1357e8 BV |
318 | devc); |
319 | sigma_set_register(WRITE_TRIGGER_SELECT1, 0x30 | i, devc); | |
ee492173 HE |
320 | } |
321 | ||
322 | /* Send the parameters */ | |
323 | sigma_write_register(WRITE_TRIGGER_SELECT0, (uint8_t *) &lut->params, | |
0e1357e8 | 324 | sizeof(lut->params), devc); |
ee492173 | 325 | |
e46b8fb1 | 326 | return SR_OK; |
ee492173 HE |
327 | } |
328 | ||
fefa1800 | 329 | /* Generate the bitbang stream for programming the FPGA. */ |
28a35d8a | 330 | static int bin2bitbang(const char *filename, |
fefa1800 | 331 | unsigned char **buf, size_t *buf_size) |
28a35d8a | 332 | { |
fefa1800 | 333 | FILE *f; |
e3fff420 | 334 | unsigned long file_size; |
28a35d8a HE |
335 | unsigned long offset = 0; |
336 | unsigned char *p; | |
e3fff420 HE |
337 | uint8_t *firmware; |
338 | unsigned long fwsize = 0; | |
28a35d8a HE |
339 | const int buffer_size = 65536; |
340 | size_t i; | |
e3fff420 | 341 | int c, bit, v; |
fefa1800 | 342 | uint32_t imm = 0x3f6df2ab; |
28a35d8a | 343 | |
868d8cef | 344 | f = g_fopen(filename, "rb"); |
28a35d8a | 345 | if (!f) { |
7b48d6e1 | 346 | sr_err("sigma: g_fopen(\"%s\", \"rb\")", filename); |
b53738ba | 347 | return SR_ERR; |
28a35d8a HE |
348 | } |
349 | ||
350 | if (-1 == fseek(f, 0, SEEK_END)) { | |
7b48d6e1 | 351 | sr_err("sigma: fseek on %s failed", filename); |
28a35d8a | 352 | fclose(f); |
b53738ba | 353 | return SR_ERR; |
28a35d8a HE |
354 | } |
355 | ||
356 | file_size = ftell(f); | |
357 | ||
358 | fseek(f, 0, SEEK_SET); | |
359 | ||
b53738ba | 360 | if (!(firmware = g_try_malloc(buffer_size))) { |
340cfac0 | 361 | sr_err("sigma: %s: firmware malloc failed", __func__); |
12ad53f5 | 362 | fclose(f); |
b53738ba | 363 | return SR_ERR_MALLOC; |
28a35d8a HE |
364 | } |
365 | ||
28a35d8a HE |
366 | while ((c = getc(f)) != EOF) { |
367 | imm = (imm + 0xa853753) % 177 + (imm * 0x8034052); | |
e3fff420 | 368 | firmware[fwsize++] = c ^ imm; |
28a35d8a HE |
369 | } |
370 | fclose(f); | |
371 | ||
e3fff420 HE |
372 | if(fwsize != file_size) { |
373 | sr_err("sigma: %s: Error reading firmware", filename); | |
374 | fclose(f); | |
375 | g_free(firmware); | |
376 | return SR_ERR; | |
28a35d8a HE |
377 | } |
378 | ||
28a35d8a HE |
379 | *buf_size = fwsize * 2 * 8; |
380 | ||
b53738ba | 381 | *buf = p = (unsigned char *)g_try_malloc(*buf_size); |
28a35d8a | 382 | if (!p) { |
340cfac0 | 383 | sr_err("sigma: %s: buf/p malloc failed", __func__); |
12ad53f5 | 384 | g_free(firmware); |
b53738ba | 385 | return SR_ERR_MALLOC; |
28a35d8a HE |
386 | } |
387 | ||
388 | for (i = 0; i < fwsize; ++i) { | |
28a35d8a | 389 | for (bit = 7; bit >= 0; --bit) { |
fefa1800 | 390 | v = firmware[i] & 1 << bit ? 0x40 : 0x00; |
28a35d8a HE |
391 | p[offset++] = v | 0x01; |
392 | p[offset++] = v; | |
393 | } | |
394 | } | |
395 | ||
396 | g_free(firmware); | |
397 | ||
398 | if (offset != *buf_size) { | |
399 | g_free(*buf); | |
7b48d6e1 | 400 | sr_err("sigma: Error reading firmware %s " |
0aeb0ccd | 401 | "offset=%ld, file_size=%ld, buf_size=%zd.", |
133a37bf | 402 | filename, offset, file_size, *buf_size); |
28a35d8a | 403 | |
b53738ba | 404 | return SR_ERR; |
28a35d8a HE |
405 | } |
406 | ||
b53738ba | 407 | return SR_OK; |
28a35d8a HE |
408 | } |
409 | ||
0448d110 BV |
410 | static void clear_instances(void) |
411 | { | |
412 | GSList *l; | |
413 | struct sr_dev_inst *sdi; | |
0e1357e8 BV |
414 | struct drv_context *drvc; |
415 | struct dev_context *devc; | |
416 | ||
417 | drvc = adi->priv; | |
0448d110 BV |
418 | |
419 | /* Properly close all devices. */ | |
0e1357e8 | 420 | for (l = drvc->instances; l; l = l->next) { |
0448d110 BV |
421 | if (!(sdi = l->data)) { |
422 | /* Log error, but continue cleaning up the rest. */ | |
423 | sr_err("sigma: %s: sdi was NULL, continuing", __func__); | |
424 | continue; | |
425 | } | |
426 | if (sdi->priv) { | |
0e1357e8 BV |
427 | devc = sdi->priv; |
428 | ftdi_free(&devc->ftdic); | |
429 | g_free(devc); | |
0448d110 BV |
430 | } |
431 | sr_dev_inst_free(sdi); | |
432 | } | |
0e1357e8 BV |
433 | g_slist_free(drvc->instances); |
434 | drvc->instances = NULL; | |
0448d110 BV |
435 | |
436 | } | |
437 | ||
40dda2c3 | 438 | static int hw_init(void) |
61136ea6 BV |
439 | { |
440 | ||
441 | /* Nothing to do. */ | |
442 | ||
443 | return SR_OK; | |
444 | } | |
445 | ||
0448d110 | 446 | static GSList *hw_scan(GSList *options) |
28a35d8a | 447 | { |
d68e2d1a | 448 | struct sr_dev_inst *sdi; |
87ca93c5 | 449 | struct sr_probe *probe; |
0e1357e8 BV |
450 | struct drv_context *drvc; |
451 | struct dev_context *devc; | |
0448d110 | 452 | GSList *devices; |
e3fff420 HE |
453 | struct ftdi_device_list *devlist; |
454 | char serial_txt[10]; | |
455 | uint32_t serial; | |
87ca93c5 | 456 | int ret, i; |
28a35d8a | 457 | |
0448d110 | 458 | (void)options; |
0e1357e8 | 459 | drvc = adi->priv; |
0448d110 BV |
460 | devices = NULL; |
461 | clear_instances(); | |
462 | ||
0e1357e8 BV |
463 | if (!(devc = g_try_malloc(sizeof(struct dev_context)))) { |
464 | sr_err("sigma: %s: devc malloc failed", __func__); | |
0448d110 | 465 | return NULL; |
b53738ba | 466 | } |
99965709 | 467 | |
0e1357e8 | 468 | ftdi_init(&devc->ftdic); |
28a35d8a | 469 | |
fefa1800 | 470 | /* Look for SIGMAs. */ |
e3fff420 | 471 | |
0e1357e8 | 472 | if ((ret = ftdi_usb_find_all(&devc->ftdic, &devlist, |
eec944c5 BV |
473 | USB_VENDOR, USB_PRODUCT)) <= 0) { |
474 | if (ret < 0) | |
475 | sr_err("ftdi_usb_find_all(): %d", ret); | |
99965709 | 476 | goto free; |
eec944c5 | 477 | } |
99965709 | 478 | |
e3fff420 | 479 | /* Make sure it's a version 1 or 2 SIGMA. */ |
0e1357e8 | 480 | ftdi_usb_get_strings(&devc->ftdic, devlist->dev, NULL, 0, NULL, 0, |
6352d030 | 481 | serial_txt, sizeof(serial_txt)); |
e3fff420 HE |
482 | sscanf(serial_txt, "%x", &serial); |
483 | ||
6352d030 | 484 | if (serial < 0xa6010000 || serial > 0xa602ffff) { |
e3fff420 | 485 | sr_err("sigma: Only SIGMA and SIGMA2 are supported " |
6352d030 | 486 | "in this version of sigrok."); |
e3fff420 HE |
487 | goto free; |
488 | } | |
489 | ||
490 | sr_info("Found ASIX SIGMA - Serial: %s", serial_txt); | |
491 | ||
0e1357e8 BV |
492 | devc->cur_samplerate = 0; |
493 | devc->period_ps = 0; | |
494 | devc->limit_msec = 0; | |
495 | devc->cur_firmware = -1; | |
496 | devc->num_probes = 0; | |
497 | devc->samples_per_event = 0; | |
498 | devc->capture_ratio = 50; | |
499 | devc->use_triggers = 0; | |
28a35d8a | 500 | |
fefa1800 | 501 | /* Register SIGMA device. */ |
d68e2d1a UH |
502 | if (!(sdi = sr_dev_inst_new(0, SR_ST_INITIALIZING, USB_VENDOR_NAME, |
503 | USB_MODEL_NAME, USB_MODEL_VERSION))) { | |
504 | sr_err("sigma: %s: sdi was NULL", __func__); | |
99965709 | 505 | goto free; |
d68e2d1a | 506 | } |
d7bbecfd | 507 | sdi->driver = adi; |
87ca93c5 BV |
508 | |
509 | for (i = 0; probe_names[i]; i++) { | |
510 | if (!(probe = sr_probe_new(i, SR_PROBE_ANALOG, TRUE, | |
511 | probe_names[i]))) | |
512 | return NULL; | |
513 | sdi->probes = g_slist_append(sdi->probes, probe); | |
514 | } | |
515 | ||
0448d110 | 516 | devices = g_slist_append(devices, sdi); |
0e1357e8 BV |
517 | drvc->instances = g_slist_append(drvc->instances, sdi); |
518 | sdi->priv = devc; | |
28a35d8a | 519 | |
fefa1800 | 520 | /* We will open the device again when we need it. */ |
e3fff420 | 521 | ftdi_list_free(&devlist); |
28a35d8a | 522 | |
0448d110 | 523 | return devices; |
ea9cfed7 | 524 | |
99965709 | 525 | free: |
0e1357e8 BV |
526 | ftdi_deinit(&devc->ftdic); |
527 | g_free(devc); | |
0448d110 | 528 | return NULL; |
28a35d8a HE |
529 | } |
530 | ||
0e1357e8 | 531 | static int upload_firmware(int firmware_idx, struct dev_context *devc) |
28a35d8a HE |
532 | { |
533 | int ret; | |
534 | unsigned char *buf; | |
535 | unsigned char pins; | |
536 | size_t buf_size; | |
28a35d8a | 537 | unsigned char result[32]; |
e8397563 | 538 | char firmware_path[128]; |
28a35d8a | 539 | |
fefa1800 | 540 | /* Make sure it's an ASIX SIGMA. */ |
0e1357e8 | 541 | if ((ret = ftdi_usb_open_desc(&devc->ftdic, |
28a35d8a | 542 | USB_VENDOR, USB_PRODUCT, USB_DESCRIPTION, NULL)) < 0) { |
7b48d6e1 | 543 | sr_err("sigma: ftdi_usb_open failed: %s", |
0e1357e8 | 544 | ftdi_get_error_string(&devc->ftdic)); |
28a35d8a HE |
545 | return 0; |
546 | } | |
547 | ||
0e1357e8 | 548 | if ((ret = ftdi_set_bitmode(&devc->ftdic, 0xdf, BITMODE_BITBANG)) < 0) { |
7b48d6e1 | 549 | sr_err("sigma: ftdi_set_bitmode failed: %s", |
0e1357e8 | 550 | ftdi_get_error_string(&devc->ftdic)); |
28a35d8a HE |
551 | return 0; |
552 | } | |
553 | ||
fefa1800 | 554 | /* Four times the speed of sigmalogan - Works well. */ |
0e1357e8 | 555 | if ((ret = ftdi_set_baudrate(&devc->ftdic, 750000)) < 0) { |
7b48d6e1 | 556 | sr_err("sigma: ftdi_set_baudrate failed: %s", |
0e1357e8 | 557 | ftdi_get_error_string(&devc->ftdic)); |
28a35d8a HE |
558 | return 0; |
559 | } | |
560 | ||
fefa1800 | 561 | /* Force the FPGA to reboot. */ |
0e1357e8 BV |
562 | sigma_write(suicide, sizeof(suicide), devc); |
563 | sigma_write(suicide, sizeof(suicide), devc); | |
564 | sigma_write(suicide, sizeof(suicide), devc); | |
565 | sigma_write(suicide, sizeof(suicide), devc); | |
28a35d8a | 566 | |
fefa1800 | 567 | /* Prepare to upload firmware (FPGA specific). */ |
0e1357e8 | 568 | sigma_write(init, sizeof(init), devc); |
28a35d8a | 569 | |
0e1357e8 | 570 | ftdi_usb_purge_buffers(&devc->ftdic); |
28a35d8a | 571 | |
fefa1800 | 572 | /* Wait until the FPGA asserts INIT_B. */ |
28a35d8a | 573 | while (1) { |
0e1357e8 | 574 | ret = sigma_read(result, 1, devc); |
28a35d8a HE |
575 | if (result[0] & 0x20) |
576 | break; | |
577 | } | |
578 | ||
9ddb2a12 | 579 | /* Prepare firmware. */ |
e8397563 | 580 | snprintf(firmware_path, sizeof(firmware_path), "%s/%s", FIRMWARE_DIR, |
f6564c8d HE |
581 | firmware_files[firmware_idx]); |
582 | ||
b53738ba | 583 | if ((ret = bin2bitbang(firmware_path, &buf, &buf_size)) != SR_OK) { |
7b48d6e1 | 584 | sr_err("sigma: An error occured while reading the firmware: %s", |
133a37bf | 585 | firmware_path); |
b53738ba | 586 | return ret; |
28a35d8a HE |
587 | } |
588 | ||
fefa1800 | 589 | /* Upload firmare. */ |
e3fff420 | 590 | sr_info("sigma: Uploading firmware %s", firmware_files[firmware_idx]); |
0e1357e8 | 591 | sigma_write(buf, buf_size, devc); |
28a35d8a HE |
592 | |
593 | g_free(buf); | |
594 | ||
0e1357e8 | 595 | if ((ret = ftdi_set_bitmode(&devc->ftdic, 0x00, BITMODE_RESET)) < 0) { |
7b48d6e1 | 596 | sr_err("sigma: ftdi_set_bitmode failed: %s", |
0e1357e8 | 597 | ftdi_get_error_string(&devc->ftdic)); |
e46b8fb1 | 598 | return SR_ERR; |
28a35d8a HE |
599 | } |
600 | ||
0e1357e8 | 601 | ftdi_usb_purge_buffers(&devc->ftdic); |
28a35d8a | 602 | |
fefa1800 | 603 | /* Discard garbage. */ |
0e1357e8 | 604 | while (1 == sigma_read(&pins, 1, devc)) |
28a35d8a HE |
605 | ; |
606 | ||
fefa1800 | 607 | /* Initialize the logic analyzer mode. */ |
0e1357e8 | 608 | sigma_write(logic_mode_start, sizeof(logic_mode_start), devc); |
28a35d8a | 609 | |
fefa1800 | 610 | /* Expect a 3 byte reply. */ |
0e1357e8 | 611 | ret = sigma_read(result, 3, devc); |
28a35d8a HE |
612 | if (ret != 3 || |
613 | result[0] != 0xa6 || result[1] != 0x55 || result[2] != 0xaa) { | |
7b48d6e1 | 614 | sr_err("sigma: Configuration failed. Invalid reply received."); |
e46b8fb1 | 615 | return SR_ERR; |
28a35d8a HE |
616 | } |
617 | ||
0e1357e8 | 618 | devc->cur_firmware = firmware_idx; |
f6564c8d | 619 | |
e3fff420 HE |
620 | sr_info("sigma: Firmware uploaded"); |
621 | ||
e46b8fb1 | 622 | return SR_OK; |
f6564c8d HE |
623 | } |
624 | ||
25a0f108 | 625 | static int hw_dev_open(struct sr_dev_inst *sdi) |
f6564c8d | 626 | { |
0e1357e8 | 627 | struct dev_context *devc; |
f6564c8d HE |
628 | int ret; |
629 | ||
0e1357e8 | 630 | devc = sdi->priv; |
99965709 | 631 | |
9ddb2a12 | 632 | /* Make sure it's an ASIX SIGMA. */ |
0e1357e8 | 633 | if ((ret = ftdi_usb_open_desc(&devc->ftdic, |
f6564c8d HE |
634 | USB_VENDOR, USB_PRODUCT, USB_DESCRIPTION, NULL)) < 0) { |
635 | ||
7b48d6e1 | 636 | sr_err("sigma: ftdi_usb_open failed: %s", |
0e1357e8 | 637 | ftdi_get_error_string(&devc->ftdic)); |
f6564c8d HE |
638 | |
639 | return 0; | |
640 | } | |
28a35d8a | 641 | |
5a2326a7 | 642 | sdi->status = SR_ST_ACTIVE; |
28a35d8a | 643 | |
e46b8fb1 | 644 | return SR_OK; |
f6564c8d HE |
645 | } |
646 | ||
6f4b1868 | 647 | static int set_samplerate(const struct sr_dev_inst *sdi, uint64_t samplerate) |
f6564c8d | 648 | { |
e8397563 | 649 | int i, ret; |
0e1357e8 | 650 | struct dev_context *devc = sdi->priv; |
f6564c8d HE |
651 | |
652 | for (i = 0; supported_samplerates[i]; i++) { | |
653 | if (supported_samplerates[i] == samplerate) | |
654 | break; | |
655 | } | |
656 | if (supported_samplerates[i] == 0) | |
e46b8fb1 | 657 | return SR_ERR_SAMPLERATE; |
f6564c8d | 658 | |
59df0c77 | 659 | if (samplerate <= SR_MHZ(50)) { |
0e1357e8 BV |
660 | ret = upload_firmware(0, devc); |
661 | devc->num_probes = 16; | |
e8397563 | 662 | } |
59df0c77 | 663 | if (samplerate == SR_MHZ(100)) { |
0e1357e8 BV |
664 | ret = upload_firmware(1, devc); |
665 | devc->num_probes = 8; | |
f78898e9 | 666 | } |
59df0c77 | 667 | else if (samplerate == SR_MHZ(200)) { |
0e1357e8 BV |
668 | ret = upload_firmware(2, devc); |
669 | devc->num_probes = 4; | |
f78898e9 | 670 | } |
f6564c8d | 671 | |
0e1357e8 BV |
672 | devc->cur_samplerate = samplerate; |
673 | devc->period_ps = 1000000000000 / samplerate; | |
674 | devc->samples_per_event = 16 / devc->num_probes; | |
675 | devc->state.state = SIGMA_IDLE; | |
f6564c8d | 676 | |
e8397563 | 677 | return ret; |
28a35d8a HE |
678 | } |
679 | ||
c53d793f HE |
680 | /* |
681 | * In 100 and 200 MHz mode, only a single pin rising/falling can be | |
682 | * set as trigger. In other modes, two rising/falling triggers can be set, | |
683 | * in addition to value/mask trigger for any number of probes. | |
684 | * | |
685 | * The Sigma supports complex triggers using boolean expressions, but this | |
686 | * has not been implemented yet. | |
687 | */ | |
6f4b1868 | 688 | static int configure_probes(const struct sr_dev_inst *sdi, const GSList *probes) |
57bbf56b | 689 | { |
0e1357e8 | 690 | struct dev_context *devc = sdi->priv; |
1b79df2f JH |
691 | const struct sr_probe *probe; |
692 | const GSList *l; | |
57bbf56b | 693 | int trigger_set = 0; |
a42aec7f | 694 | int probebit; |
57bbf56b | 695 | |
0e1357e8 | 696 | memset(&devc->trigger, 0, sizeof(struct sigma_trigger)); |
eec5275e | 697 | |
57bbf56b | 698 | for (l = probes; l; l = l->next) { |
1afe8989 | 699 | probe = (struct sr_probe *)l->data; |
b35c8293 | 700 | probebit = 1 << (probe->index); |
57bbf56b HE |
701 | |
702 | if (!probe->enabled || !probe->trigger) | |
703 | continue; | |
704 | ||
0e1357e8 | 705 | if (devc->cur_samplerate >= SR_MHZ(100)) { |
c53d793f | 706 | /* Fast trigger support. */ |
ee492173 | 707 | if (trigger_set) { |
7b48d6e1 | 708 | sr_err("sigma: ASIX SIGMA only supports a single " |
133a37bf | 709 | "pin trigger in 100 and 200MHz mode."); |
e46b8fb1 | 710 | return SR_ERR; |
ee492173 HE |
711 | } |
712 | if (probe->trigger[0] == 'f') | |
0e1357e8 | 713 | devc->trigger.fallingmask |= probebit; |
ee492173 | 714 | else if (probe->trigger[0] == 'r') |
0e1357e8 | 715 | devc->trigger.risingmask |= probebit; |
ee492173 | 716 | else { |
7b48d6e1 | 717 | sr_err("sigma: ASIX SIGMA only supports " |
133a37bf UH |
718 | "rising/falling trigger in 100 " |
719 | "and 200MHz mode."); | |
e46b8fb1 | 720 | return SR_ERR; |
ee492173 | 721 | } |
57bbf56b | 722 | |
c53d793f | 723 | ++trigger_set; |
ee492173 | 724 | } else { |
c53d793f HE |
725 | /* Simple trigger support (event). */ |
726 | if (probe->trigger[0] == '1') { | |
0e1357e8 BV |
727 | devc->trigger.simplevalue |= probebit; |
728 | devc->trigger.simplemask |= probebit; | |
c53d793f HE |
729 | } |
730 | else if (probe->trigger[0] == '0') { | |
0e1357e8 BV |
731 | devc->trigger.simplevalue &= ~probebit; |
732 | devc->trigger.simplemask |= probebit; | |
c53d793f HE |
733 | } |
734 | else if (probe->trigger[0] == 'f') { | |
0e1357e8 | 735 | devc->trigger.fallingmask |= probebit; |
c53d793f HE |
736 | ++trigger_set; |
737 | } | |
738 | else if (probe->trigger[0] == 'r') { | |
0e1357e8 | 739 | devc->trigger.risingmask |= probebit; |
c53d793f HE |
740 | ++trigger_set; |
741 | } | |
ee492173 | 742 | |
ea9cfed7 UH |
743 | /* |
744 | * Actually, Sigma supports 2 rising/falling triggers, | |
745 | * but they are ORed and the current trigger syntax | |
746 | * does not permit ORed triggers. | |
747 | */ | |
98b8cbc1 | 748 | if (trigger_set > 1) { |
7b48d6e1 UH |
749 | sr_err("sigma: ASIX SIGMA only supports 1 " |
750 | "rising/falling triggers."); | |
e46b8fb1 | 751 | return SR_ERR; |
ee492173 | 752 | } |
ee492173 | 753 | } |
5b5ea7c6 HE |
754 | |
755 | if (trigger_set) | |
0e1357e8 | 756 | devc->use_triggers = 1; |
57bbf56b HE |
757 | } |
758 | ||
e46b8fb1 | 759 | return SR_OK; |
57bbf56b HE |
760 | } |
761 | ||
25a0f108 | 762 | static int hw_dev_close(struct sr_dev_inst *sdi) |
28a35d8a | 763 | { |
0e1357e8 | 764 | struct dev_context *devc; |
28a35d8a | 765 | |
0e1357e8 | 766 | if (!(devc = sdi->priv)) { |
340cfac0 | 767 | sr_err("sigma: %s: sdi->priv was NULL", __func__); |
0abee507 | 768 | return SR_ERR_BUG; |
9be9893e | 769 | } |
697785d1 UH |
770 | |
771 | /* TODO */ | |
772 | if (sdi->status == SR_ST_ACTIVE) | |
0e1357e8 | 773 | ftdi_usb_close(&devc->ftdic); |
697785d1 UH |
774 | |
775 | sdi->status = SR_ST_INACTIVE; | |
776 | ||
777 | return SR_OK; | |
28a35d8a HE |
778 | } |
779 | ||
57ab7d9f | 780 | static int hw_cleanup(void) |
28a35d8a | 781 | { |
99965709 | 782 | |
0448d110 | 783 | clear_instances(); |
57ab7d9f | 784 | |
0448d110 | 785 | return SR_OK; |
28a35d8a HE |
786 | } |
787 | ||
41479605 BV |
788 | static int hw_info_get(int info_id, const void **data, |
789 | const struct sr_dev_inst *sdi) | |
28a35d8a | 790 | { |
0e1357e8 | 791 | struct dev_context *devc; |
99965709 | 792 | |
41479605 | 793 | switch (info_id) { |
b2b5445c BV |
794 | case SR_DI_HWCAPS: |
795 | *data = hwcaps; | |
796 | break; | |
5a2326a7 | 797 | case SR_DI_NUM_PROBES: |
41479605 | 798 | *data = GINT_TO_POINTER(NUM_PROBES); |
464d12c7 KS |
799 | break; |
800 | case SR_DI_PROBE_NAMES: | |
41479605 | 801 | *data = probe_names; |
28a35d8a | 802 | break; |
5a2326a7 | 803 | case SR_DI_SAMPLERATES: |
41479605 | 804 | *data = &samplerates; |
28a35d8a | 805 | break; |
5a2326a7 | 806 | case SR_DI_TRIGGER_TYPES: |
41479605 | 807 | *data = (char *)TRIGGER_TYPES; |
28a35d8a | 808 | break; |
5a2326a7 | 809 | case SR_DI_CUR_SAMPLERATE: |
41479605 | 810 | if (sdi) { |
0e1357e8 BV |
811 | devc = sdi->priv; |
812 | *data = &devc->cur_samplerate; | |
41479605 BV |
813 | } else |
814 | return SR_ERR; | |
28a35d8a | 815 | break; |
d7bbecfd BV |
816 | default: |
817 | return SR_ERR_ARG; | |
28a35d8a HE |
818 | } |
819 | ||
41479605 | 820 | return SR_OK; |
28a35d8a HE |
821 | } |
822 | ||
6f4b1868 BV |
823 | static int hw_dev_config_set(const struct sr_dev_inst *sdi, int hwcap, |
824 | const void *value) | |
28a35d8a | 825 | { |
0e1357e8 | 826 | struct dev_context *devc; |
28a35d8a | 827 | int ret; |
f6564c8d | 828 | |
0e1357e8 | 829 | devc = sdi->priv; |
99965709 | 830 | |
ffedd0bf | 831 | if (hwcap == SR_HWCAP_SAMPLERATE) { |
1b79df2f | 832 | ret = set_samplerate(sdi, *(const uint64_t *)value); |
ffedd0bf | 833 | } else if (hwcap == SR_HWCAP_PROBECONFIG) { |
99965709 | 834 | ret = configure_probes(sdi, value); |
ffedd0bf | 835 | } else if (hwcap == SR_HWCAP_LIMIT_MSEC) { |
0e1357e8 BV |
836 | devc->limit_msec = *(const uint64_t *)value; |
837 | if (devc->limit_msec > 0) | |
e46b8fb1 | 838 | ret = SR_OK; |
94ba4bd6 | 839 | else |
e46b8fb1 | 840 | ret = SR_ERR; |
ffedd0bf | 841 | } else if (hwcap == SR_HWCAP_CAPTURE_RATIO) { |
0e1357e8 BV |
842 | devc->capture_ratio = *(const uint64_t *)value; |
843 | if (devc->capture_ratio < 0 || devc->capture_ratio > 100) | |
e46b8fb1 | 844 | ret = SR_ERR; |
94ba4bd6 | 845 | else |
e46b8fb1 | 846 | ret = SR_OK; |
28a35d8a | 847 | } else { |
e46b8fb1 | 848 | ret = SR_ERR; |
28a35d8a HE |
849 | } |
850 | ||
851 | return ret; | |
852 | } | |
853 | ||
36b1c8e6 HE |
854 | /* Software trigger to determine exact trigger position. */ |
855 | static int get_trigger_offset(uint16_t *samples, uint16_t last_sample, | |
856 | struct sigma_trigger *t) | |
857 | { | |
858 | int i; | |
859 | ||
860 | for (i = 0; i < 8; ++i) { | |
861 | if (i > 0) | |
862 | last_sample = samples[i-1]; | |
863 | ||
864 | /* Simple triggers. */ | |
865 | if ((samples[i] & t->simplemask) != t->simplevalue) | |
866 | continue; | |
867 | ||
868 | /* Rising edge. */ | |
869 | if ((last_sample & t->risingmask) != 0 || (samples[i] & | |
870 | t->risingmask) != t->risingmask) | |
871 | continue; | |
872 | ||
873 | /* Falling edge. */ | |
bdfc7a89 HE |
874 | if ((last_sample & t->fallingmask) != t->fallingmask || |
875 | (samples[i] & t->fallingmask) != 0) | |
36b1c8e6 HE |
876 | continue; |
877 | ||
878 | break; | |
879 | } | |
880 | ||
881 | /* If we did not match, return original trigger pos. */ | |
882 | return i & 0x7; | |
883 | } | |
884 | ||
28a35d8a | 885 | /* |
fefa1800 UH |
886 | * Decode chunk of 1024 bytes, 64 clusters, 7 events per cluster. |
887 | * Each event is 20ns apart, and can contain multiple samples. | |
f78898e9 HE |
888 | * |
889 | * For 200 MHz, events contain 4 samples for each channel, spread 5 ns apart. | |
890 | * For 100 MHz, events contain 2 samples for each channel, spread 10 ns apart. | |
891 | * For 50 MHz and below, events contain one sample for each channel, | |
892 | * spread 20 ns apart. | |
28a35d8a HE |
893 | */ |
894 | static int decode_chunk_ts(uint8_t *buf, uint16_t *lastts, | |
88c51afe | 895 | uint16_t *lastsample, int triggerpos, |
3cd3a20b | 896 | uint16_t limit_chunk, void *cb_data) |
28a35d8a | 897 | { |
3cd3a20b | 898 | struct sr_dev_inst *sdi = cb_data; |
0e1357e8 | 899 | struct dev_context *devc = sdi->priv; |
fefa1800 | 900 | uint16_t tsdiff, ts; |
0e1357e8 | 901 | uint16_t samples[65536 * devc->samples_per_event]; |
b9c735a2 | 902 | struct sr_datafeed_packet packet; |
9c939c51 | 903 | struct sr_datafeed_logic logic; |
f78898e9 | 904 | int i, j, k, l, numpad, tosend; |
fefa1800 | 905 | size_t n = 0, sent = 0; |
0e1357e8 | 906 | int clustersize = EVENTS_PER_CLUSTER * devc->samples_per_event; |
fefa1800 | 907 | uint16_t *event; |
f78898e9 | 908 | uint16_t cur_sample; |
57bbf56b | 909 | int triggerts = -1; |
ee492173 | 910 | |
4ae1f451 | 911 | /* Check if trigger is in this chunk. */ |
ee492173 | 912 | if (triggerpos != -1) { |
0e1357e8 | 913 | if (devc->cur_samplerate <= SR_MHZ(50)) |
36b1c8e6 | 914 | triggerpos -= EVENTS_PER_CLUSTER - 1; |
ee492173 HE |
915 | |
916 | if (triggerpos < 0) | |
917 | triggerpos = 0; | |
57bbf56b | 918 | |
ee492173 HE |
919 | /* Find in which cluster the trigger occured. */ |
920 | triggerts = triggerpos / 7; | |
921 | } | |
28a35d8a | 922 | |
eec5275e | 923 | /* For each ts. */ |
28a35d8a | 924 | for (i = 0; i < 64; ++i) { |
fefa1800 | 925 | ts = *(uint16_t *) &buf[i * 16]; |
28a35d8a HE |
926 | tsdiff = ts - *lastts; |
927 | *lastts = ts; | |
928 | ||
88c51afe HE |
929 | /* Decode partial chunk. */ |
930 | if (limit_chunk && ts > limit_chunk) | |
e46b8fb1 | 931 | return SR_OK; |
88c51afe | 932 | |
fefa1800 | 933 | /* Pad last sample up to current point. */ |
0e1357e8 | 934 | numpad = tsdiff * devc->samples_per_event - clustersize; |
28a35d8a | 935 | if (numpad > 0) { |
f78898e9 HE |
936 | for (j = 0; j < numpad; ++j) |
937 | samples[j] = *lastsample; | |
938 | ||
939 | n = numpad; | |
28a35d8a HE |
940 | } |
941 | ||
57bbf56b HE |
942 | /* Send samples between previous and this timestamp to sigrok. */ |
943 | sent = 0; | |
944 | while (sent < n) { | |
945 | tosend = MIN(2048, n - sent); | |
946 | ||
5a2326a7 | 947 | packet.type = SR_DF_LOGIC; |
9c939c51 BV |
948 | packet.payload = &logic; |
949 | logic.length = tosend * sizeof(uint16_t); | |
950 | logic.unitsize = 2; | |
951 | logic.data = samples + sent; | |
0e1357e8 | 952 | sr_session_send(devc->session_dev_id, &packet); |
28a35d8a | 953 | |
57bbf56b HE |
954 | sent += tosend; |
955 | } | |
956 | n = 0; | |
957 | ||
958 | event = (uint16_t *) &buf[i * 16 + 2]; | |
f78898e9 HE |
959 | cur_sample = 0; |
960 | ||
961 | /* For each event in cluster. */ | |
28a35d8a | 962 | for (j = 0; j < 7; ++j) { |
f78898e9 HE |
963 | |
964 | /* For each sample in event. */ | |
0e1357e8 | 965 | for (k = 0; k < devc->samples_per_event; ++k) { |
f78898e9 HE |
966 | cur_sample = 0; |
967 | ||
968 | /* For each probe. */ | |
0e1357e8 | 969 | for (l = 0; l < devc->num_probes; ++l) |
edca2c5c | 970 | cur_sample |= (!!(event[j] & (1 << (l * |
0e1357e8 | 971 | devc->samples_per_event + k)))) << l; |
f78898e9 HE |
972 | |
973 | samples[n++] = cur_sample; | |
28a35d8a HE |
974 | } |
975 | } | |
976 | ||
eec5275e | 977 | /* Send data up to trigger point (if triggered). */ |
fefa1800 | 978 | sent = 0; |
57bbf56b HE |
979 | if (i == triggerts) { |
980 | /* | |
36b1c8e6 HE |
981 | * Trigger is not always accurate to sample because of |
982 | * pipeline delay. However, it always triggers before | |
983 | * the actual event. We therefore look at the next | |
984 | * samples to pinpoint the exact position of the trigger. | |
57bbf56b | 985 | */ |
bdfc7a89 | 986 | tosend = get_trigger_offset(samples, *lastsample, |
0e1357e8 | 987 | &devc->trigger); |
57bbf56b HE |
988 | |
989 | if (tosend > 0) { | |
5a2326a7 | 990 | packet.type = SR_DF_LOGIC; |
9c939c51 BV |
991 | packet.payload = &logic; |
992 | logic.length = tosend * sizeof(uint16_t); | |
993 | logic.unitsize = 2; | |
994 | logic.data = samples; | |
0e1357e8 | 995 | sr_session_send(devc->session_dev_id, &packet); |
57bbf56b HE |
996 | |
997 | sent += tosend; | |
998 | } | |
28a35d8a | 999 | |
5b5ea7c6 | 1000 | /* Only send trigger if explicitly enabled. */ |
0e1357e8 | 1001 | if (devc->use_triggers) { |
5a2326a7 | 1002 | packet.type = SR_DF_TRIGGER; |
0e1357e8 | 1003 | sr_session_send(devc->session_dev_id, &packet); |
5b5ea7c6 | 1004 | } |
28a35d8a | 1005 | } |
57bbf56b | 1006 | |
eec5275e | 1007 | /* Send rest of the chunk to sigrok. */ |
57bbf56b HE |
1008 | tosend = n - sent; |
1009 | ||
abda62ce | 1010 | if (tosend > 0) { |
5a2326a7 | 1011 | packet.type = SR_DF_LOGIC; |
9c939c51 BV |
1012 | packet.payload = &logic; |
1013 | logic.length = tosend * sizeof(uint16_t); | |
1014 | logic.unitsize = 2; | |
1015 | logic.data = samples + sent; | |
0e1357e8 | 1016 | sr_session_send(devc->session_dev_id, &packet); |
abda62ce | 1017 | } |
ee492173 HE |
1018 | |
1019 | *lastsample = samples[n - 1]; | |
28a35d8a HE |
1020 | } |
1021 | ||
e46b8fb1 | 1022 | return SR_OK; |
28a35d8a HE |
1023 | } |
1024 | ||
1f9813eb | 1025 | static int receive_data(int fd, int revents, void *cb_data) |
28a35d8a | 1026 | { |
1f9813eb | 1027 | struct sr_dev_inst *sdi = cb_data; |
0e1357e8 | 1028 | struct dev_context *devc = sdi->priv; |
b9c735a2 | 1029 | struct sr_datafeed_packet packet; |
28a35d8a HE |
1030 | const int chunks_per_read = 32; |
1031 | unsigned char buf[chunks_per_read * CHUNK_SIZE]; | |
6aac7737 | 1032 | int bufsz, numchunks, i, newchunks; |
94ba4bd6 | 1033 | uint64_t running_msec; |
28a35d8a | 1034 | struct timeval tv; |
28a35d8a | 1035 | |
cb93f8a9 UH |
1036 | /* Avoid compiler warnings. */ |
1037 | (void)fd; | |
1038 | (void)revents; | |
28a35d8a | 1039 | |
805919b0 | 1040 | /* Get the current position. */ |
0e1357e8 | 1041 | sigma_read_pos(&devc->state.stoppos, &devc->state.triggerpos, devc); |
805919b0 | 1042 | |
0e1357e8 | 1043 | numchunks = (devc->state.stoppos + 511) / 512; |
28a35d8a | 1044 | |
0e1357e8 | 1045 | if (devc->state.state == SIGMA_IDLE) |
805919b0 | 1046 | return TRUE; |
28a35d8a | 1047 | |
0e1357e8 | 1048 | if (devc->state.state == SIGMA_CAPTURE) { |
6aac7737 HE |
1049 | /* Check if the timer has expired, or memory is full. */ |
1050 | gettimeofday(&tv, 0); | |
0e1357e8 BV |
1051 | running_msec = (tv.tv_sec - devc->start_tv.tv_sec) * 1000 + |
1052 | (tv.tv_usec - devc->start_tv.tv_usec) / 1000; | |
28a35d8a | 1053 | |
0e1357e8 | 1054 | if (running_msec < devc->limit_msec && numchunks < 32767) |
805919b0 | 1055 | return TRUE; /* While capturing... */ |
e3fff420 | 1056 | else |
3ffb6964 | 1057 | hw_dev_acquisition_stop(sdi, sdi); |
6aac7737 | 1058 | |
0e1357e8 BV |
1059 | } else if (devc->state.state == SIGMA_DOWNLOAD) { |
1060 | if (devc->state.chunks_downloaded >= numchunks) { | |
6aac7737 | 1061 | /* End of samples. */ |
5a2326a7 | 1062 | packet.type = SR_DF_END; |
0e1357e8 | 1063 | sr_session_send(devc->session_dev_id, &packet); |
6aac7737 | 1064 | |
0e1357e8 | 1065 | devc->state.state = SIGMA_IDLE; |
f78898e9 | 1066 | |
6aac7737 HE |
1067 | return TRUE; |
1068 | } | |
1069 | ||
1070 | newchunks = MIN(chunks_per_read, | |
0e1357e8 | 1071 | numchunks - devc->state.chunks_downloaded); |
28a35d8a | 1072 | |
7b48d6e1 | 1073 | sr_info("sigma: Downloading sample data: %.0f %%", |
0e1357e8 | 1074 | 100.0 * devc->state.chunks_downloaded / numchunks); |
28a35d8a | 1075 | |
0e1357e8 BV |
1076 | bufsz = sigma_read_dram(devc->state.chunks_downloaded, |
1077 | newchunks, buf, devc); | |
719c5a93 UH |
1078 | /* TODO: Check bufsz. For now, just avoid compiler warnings. */ |
1079 | (void)bufsz; | |
28a35d8a | 1080 | |
fefa1800 | 1081 | /* Find first ts. */ |
0e1357e8 BV |
1082 | if (devc->state.chunks_downloaded == 0) { |
1083 | devc->state.lastts = *(uint16_t *) buf - 1; | |
1084 | devc->state.lastsample = 0; | |
6aac7737 | 1085 | } |
28a35d8a | 1086 | |
fefa1800 | 1087 | /* Decode chunks and send them to sigrok. */ |
28a35d8a | 1088 | for (i = 0; i < newchunks; ++i) { |
88c51afe HE |
1089 | int limit_chunk = 0; |
1090 | ||
1091 | /* The last chunk may potentially be only in part. */ | |
0e1357e8 | 1092 | if (devc->state.chunks_downloaded == numchunks - 1) { |
88c51afe | 1093 | /* Find the last valid timestamp */ |
0e1357e8 | 1094 | limit_chunk = devc->state.stoppos % 512 + devc->state.lastts; |
88c51afe HE |
1095 | } |
1096 | ||
0e1357e8 | 1097 | if (devc->state.chunks_downloaded + i == devc->state.triggerchunk) |
57bbf56b | 1098 | decode_chunk_ts(buf + (i * CHUNK_SIZE), |
0e1357e8 BV |
1099 | &devc->state.lastts, |
1100 | &devc->state.lastsample, | |
1101 | devc->state.triggerpos & 0x1ff, | |
1f9813eb | 1102 | limit_chunk, sdi); |
57bbf56b HE |
1103 | else |
1104 | decode_chunk_ts(buf + (i * CHUNK_SIZE), | |
0e1357e8 BV |
1105 | &devc->state.lastts, |
1106 | &devc->state.lastsample, | |
1f9813eb | 1107 | -1, limit_chunk, sdi); |
28a35d8a | 1108 | |
0e1357e8 | 1109 | ++devc->state.chunks_downloaded; |
88c51afe | 1110 | } |
28a35d8a HE |
1111 | } |
1112 | ||
28a35d8a HE |
1113 | return TRUE; |
1114 | } | |
1115 | ||
c53d793f HE |
1116 | /* Build a LUT entry used by the trigger functions. */ |
1117 | static void build_lut_entry(uint16_t value, uint16_t mask, uint16_t *entry) | |
ee492173 HE |
1118 | { |
1119 | int i, j, k, bit; | |
1120 | ||
f758d074 | 1121 | /* For each quad probe. */ |
ee492173 | 1122 | for (i = 0; i < 4; ++i) { |
c53d793f | 1123 | entry[i] = 0xffff; |
ee492173 | 1124 | |
f758d074 | 1125 | /* For each bit in LUT. */ |
ee492173 HE |
1126 | for (j = 0; j < 16; ++j) |
1127 | ||
f758d074 | 1128 | /* For each probe in quad. */ |
ee492173 HE |
1129 | for (k = 0; k < 4; ++k) { |
1130 | bit = 1 << (i * 4 + k); | |
1131 | ||
c53d793f HE |
1132 | /* Set bit in entry */ |
1133 | if ((mask & bit) && | |
1134 | ((!(value & bit)) != | |
4ae1f451 | 1135 | (!(j & (1 << k))))) |
c53d793f | 1136 | entry[i] &= ~(1 << j); |
ee492173 HE |
1137 | } |
1138 | } | |
c53d793f | 1139 | } |
ee492173 | 1140 | |
c53d793f HE |
1141 | /* Add a logical function to LUT mask. */ |
1142 | static void add_trigger_function(enum triggerop oper, enum triggerfunc func, | |
1143 | int index, int neg, uint16_t *mask) | |
1144 | { | |
1145 | int i, j; | |
1146 | int x[2][2], tmp, a, b, aset, bset, rset; | |
1147 | ||
1148 | memset(x, 0, 4 * sizeof(int)); | |
1149 | ||
1150 | /* Trigger detect condition. */ | |
1151 | switch (oper) { | |
1152 | case OP_LEVEL: | |
1153 | x[0][1] = 1; | |
1154 | x[1][1] = 1; | |
1155 | break; | |
1156 | case OP_NOT: | |
1157 | x[0][0] = 1; | |
1158 | x[1][0] = 1; | |
1159 | break; | |
1160 | case OP_RISE: | |
1161 | x[0][1] = 1; | |
1162 | break; | |
1163 | case OP_FALL: | |
1164 | x[1][0] = 1; | |
1165 | break; | |
1166 | case OP_RISEFALL: | |
1167 | x[0][1] = 1; | |
1168 | x[1][0] = 1; | |
1169 | break; | |
1170 | case OP_NOTRISE: | |
1171 | x[1][1] = 1; | |
1172 | x[0][0] = 1; | |
1173 | x[1][0] = 1; | |
1174 | break; | |
1175 | case OP_NOTFALL: | |
1176 | x[1][1] = 1; | |
1177 | x[0][0] = 1; | |
1178 | x[0][1] = 1; | |
1179 | break; | |
1180 | case OP_NOTRISEFALL: | |
1181 | x[1][1] = 1; | |
1182 | x[0][0] = 1; | |
1183 | break; | |
1184 | } | |
1185 | ||
1186 | /* Transpose if neg is set. */ | |
1187 | if (neg) { | |
ea9cfed7 | 1188 | for (i = 0; i < 2; ++i) { |
c53d793f HE |
1189 | for (j = 0; j < 2; ++j) { |
1190 | tmp = x[i][j]; | |
1191 | x[i][j] = x[1-i][1-j]; | |
1192 | x[1-i][1-j] = tmp; | |
1193 | } | |
ea9cfed7 | 1194 | } |
c53d793f HE |
1195 | } |
1196 | ||
1197 | /* Update mask with function. */ | |
1198 | for (i = 0; i < 16; ++i) { | |
1199 | a = (i >> (2 * index + 0)) & 1; | |
1200 | b = (i >> (2 * index + 1)) & 1; | |
1201 | ||
1202 | aset = (*mask >> i) & 1; | |
1203 | bset = x[b][a]; | |
1204 | ||
1205 | if (func == FUNC_AND || func == FUNC_NAND) | |
1206 | rset = aset & bset; | |
1207 | else if (func == FUNC_OR || func == FUNC_NOR) | |
1208 | rset = aset | bset; | |
1209 | else if (func == FUNC_XOR || func == FUNC_NXOR) | |
1210 | rset = aset ^ bset; | |
1211 | ||
1212 | if (func == FUNC_NAND || func == FUNC_NOR || func == FUNC_NXOR) | |
1213 | rset = !rset; | |
1214 | ||
1215 | *mask &= ~(1 << i); | |
1216 | ||
1217 | if (rset) | |
1218 | *mask |= 1 << i; | |
1219 | } | |
1220 | } | |
1221 | ||
1222 | /* | |
1223 | * Build trigger LUTs used by 50 MHz and lower sample rates for supporting | |
1224 | * simple pin change and state triggers. Only two transitions (rise/fall) can be | |
1225 | * set at any time, but a full mask and value can be set (0/1). | |
1226 | */ | |
0e1357e8 | 1227 | static int build_basic_trigger(struct triggerlut *lut, struct dev_context *devc) |
c53d793f HE |
1228 | { |
1229 | int i,j; | |
4ae1f451 | 1230 | uint16_t masks[2] = { 0, 0 }; |
c53d793f HE |
1231 | |
1232 | memset(lut, 0, sizeof(struct triggerlut)); | |
1233 | ||
1234 | /* Contant for simple triggers. */ | |
1235 | lut->m4 = 0xa000; | |
1236 | ||
1237 | /* Value/mask trigger support. */ | |
0e1357e8 | 1238 | build_lut_entry(devc->trigger.simplevalue, devc->trigger.simplemask, |
99965709 | 1239 | lut->m2d); |
c53d793f HE |
1240 | |
1241 | /* Rise/fall trigger support. */ | |
1242 | for (i = 0, j = 0; i < 16; ++i) { | |
0e1357e8 BV |
1243 | if (devc->trigger.risingmask & (1 << i) || |
1244 | devc->trigger.fallingmask & (1 << i)) | |
c53d793f HE |
1245 | masks[j++] = 1 << i; |
1246 | } | |
1247 | ||
1248 | build_lut_entry(masks[0], masks[0], lut->m0d); | |
1249 | build_lut_entry(masks[1], masks[1], lut->m1d); | |
1250 | ||
1251 | /* Add glue logic */ | |
1252 | if (masks[0] || masks[1]) { | |
1253 | /* Transition trigger. */ | |
0e1357e8 | 1254 | if (masks[0] & devc->trigger.risingmask) |
c53d793f | 1255 | add_trigger_function(OP_RISE, FUNC_OR, 0, 0, &lut->m3); |
0e1357e8 | 1256 | if (masks[0] & devc->trigger.fallingmask) |
c53d793f | 1257 | add_trigger_function(OP_FALL, FUNC_OR, 0, 0, &lut->m3); |
0e1357e8 | 1258 | if (masks[1] & devc->trigger.risingmask) |
c53d793f | 1259 | add_trigger_function(OP_RISE, FUNC_OR, 1, 0, &lut->m3); |
0e1357e8 | 1260 | if (masks[1] & devc->trigger.fallingmask) |
c53d793f HE |
1261 | add_trigger_function(OP_FALL, FUNC_OR, 1, 0, &lut->m3); |
1262 | } else { | |
1263 | /* Only value/mask trigger. */ | |
1264 | lut->m3 = 0xffff; | |
1265 | } | |
ee492173 | 1266 | |
c53d793f | 1267 | /* Triggertype: event. */ |
ee492173 HE |
1268 | lut->params.selres = 3; |
1269 | ||
e46b8fb1 | 1270 | return SR_OK; |
ee492173 HE |
1271 | } |
1272 | ||
3ffb6964 BV |
1273 | static int hw_dev_acquisition_start(const struct sr_dev_inst *sdi, |
1274 | void *cb_data) | |
28a35d8a | 1275 | { |
0e1357e8 | 1276 | struct dev_context *devc; |
3c36c403 HE |
1277 | struct sr_datafeed_packet *packet; |
1278 | struct sr_datafeed_header *header; | |
f366e86c | 1279 | struct sr_datafeed_meta_logic meta; |
9ddb2a12 | 1280 | struct clockselect_50 clockselect; |
82957b65 | 1281 | int frac, triggerpin, ret; |
57bbf56b HE |
1282 | uint8_t triggerselect; |
1283 | struct triggerinout triggerinout_conf; | |
ee492173 | 1284 | struct triggerlut lut; |
28a35d8a | 1285 | |
0e1357e8 | 1286 | devc = sdi->priv; |
28a35d8a | 1287 | |
ea9cfed7 | 1288 | /* If the samplerate has not been set, default to 200 kHz. */ |
0e1357e8 | 1289 | if (devc->cur_firmware == -1) { |
82957b65 UH |
1290 | if ((ret = set_samplerate(sdi, SR_KHZ(200))) != SR_OK) |
1291 | return ret; | |
1292 | } | |
e8397563 | 1293 | |
eec5275e | 1294 | /* Enter trigger programming mode. */ |
0e1357e8 | 1295 | sigma_set_register(WRITE_TRIGGER_SELECT1, 0x20, devc); |
28a35d8a | 1296 | |
eec5275e | 1297 | /* 100 and 200 MHz mode. */ |
0e1357e8 BV |
1298 | if (devc->cur_samplerate >= SR_MHZ(100)) { |
1299 | sigma_set_register(WRITE_TRIGGER_SELECT1, 0x81, devc); | |
57bbf56b | 1300 | |
a42aec7f HE |
1301 | /* Find which pin to trigger on from mask. */ |
1302 | for (triggerpin = 0; triggerpin < 8; ++triggerpin) | |
0e1357e8 | 1303 | if ((devc->trigger.risingmask | devc->trigger.fallingmask) & |
a42aec7f HE |
1304 | (1 << triggerpin)) |
1305 | break; | |
1306 | ||
1307 | /* Set trigger pin and light LED on trigger. */ | |
1308 | triggerselect = (1 << LEDSEL1) | (triggerpin & 0x7); | |
1309 | ||
1310 | /* Default rising edge. */ | |
0e1357e8 | 1311 | if (devc->trigger.fallingmask) |
a42aec7f | 1312 | triggerselect |= 1 << 3; |
57bbf56b | 1313 | |
eec5275e | 1314 | /* All other modes. */ |
0e1357e8 BV |
1315 | } else if (devc->cur_samplerate <= SR_MHZ(50)) { |
1316 | build_basic_trigger(&lut, devc); | |
ee492173 | 1317 | |
0e1357e8 | 1318 | sigma_write_trigger_lut(&lut, devc); |
57bbf56b HE |
1319 | |
1320 | triggerselect = (1 << LEDSEL1) | (1 << LEDSEL0); | |
1321 | } | |
1322 | ||
eec5275e | 1323 | /* Setup trigger in and out pins to default values. */ |
57bbf56b HE |
1324 | memset(&triggerinout_conf, 0, sizeof(struct triggerinout)); |
1325 | triggerinout_conf.trgout_bytrigger = 1; | |
1326 | triggerinout_conf.trgout_enable = 1; | |
1327 | ||
28a35d8a | 1328 | sigma_write_register(WRITE_TRIGGER_OPTION, |
57bbf56b | 1329 | (uint8_t *) &triggerinout_conf, |
0e1357e8 | 1330 | sizeof(struct triggerinout), devc); |
28a35d8a | 1331 | |
eec5275e | 1332 | /* Go back to normal mode. */ |
0e1357e8 | 1333 | sigma_set_register(WRITE_TRIGGER_SELECT1, triggerselect, devc); |
28a35d8a | 1334 | |
edca2c5c | 1335 | /* Set clock select register. */ |
0e1357e8 | 1336 | if (devc->cur_samplerate == SR_MHZ(200)) |
edca2c5c | 1337 | /* Enable 4 probes. */ |
0e1357e8 BV |
1338 | sigma_set_register(WRITE_CLOCK_SELECT, 0xf0, devc); |
1339 | else if (devc->cur_samplerate == SR_MHZ(100)) | |
edca2c5c | 1340 | /* Enable 8 probes. */ |
0e1357e8 | 1341 | sigma_set_register(WRITE_CLOCK_SELECT, 0x00, devc); |
edca2c5c HE |
1342 | else { |
1343 | /* | |
9ddb2a12 | 1344 | * 50 MHz mode (or fraction thereof). Any fraction down to |
eec5275e | 1345 | * 50 MHz / 256 can be used, but is not supported by sigrok API. |
edca2c5c | 1346 | */ |
0e1357e8 | 1347 | frac = SR_MHZ(50) / devc->cur_samplerate - 1; |
edca2c5c | 1348 | |
9ddb2a12 UH |
1349 | clockselect.async = 0; |
1350 | clockselect.fraction = frac; | |
1351 | clockselect.disabled_probes = 0; | |
edca2c5c HE |
1352 | |
1353 | sigma_write_register(WRITE_CLOCK_SELECT, | |
9ddb2a12 | 1354 | (uint8_t *) &clockselect, |
0e1357e8 | 1355 | sizeof(clockselect), devc); |
edca2c5c HE |
1356 | } |
1357 | ||
fefa1800 | 1358 | /* Setup maximum post trigger time. */ |
99965709 | 1359 | sigma_set_register(WRITE_POST_TRIGGER, |
0e1357e8 | 1360 | (devc->capture_ratio * 255) / 100, devc); |
28a35d8a | 1361 | |
eec5275e | 1362 | /* Start acqusition. */ |
0e1357e8 BV |
1363 | gettimeofday(&devc->start_tv, 0); |
1364 | sigma_set_register(WRITE_MODE, 0x0d, devc); | |
99965709 | 1365 | |
0e1357e8 | 1366 | devc->session_dev_id = cb_data; |
28a35d8a | 1367 | |
3c36c403 HE |
1368 | if (!(packet = g_try_malloc(sizeof(struct sr_datafeed_packet)))) { |
1369 | sr_err("sigma: %s: packet malloc failed.", __func__); | |
1370 | return SR_ERR_MALLOC; | |
1371 | } | |
1372 | ||
1373 | if (!(header = g_try_malloc(sizeof(struct sr_datafeed_header)))) { | |
1374 | sr_err("sigma: %s: header malloc failed.", __func__); | |
1375 | return SR_ERR_MALLOC; | |
1376 | } | |
28a35d8a | 1377 | |
3c36c403 HE |
1378 | /* Send header packet to the session bus. */ |
1379 | packet->type = SR_DF_HEADER; | |
1380 | packet->payload = header; | |
1381 | header->feed_version = 1; | |
1382 | gettimeofday(&header->starttime, NULL); | |
0e1357e8 | 1383 | sr_session_send(devc->session_dev_id, packet); |
f366e86c BV |
1384 | |
1385 | /* Send metadata about the SR_DF_LOGIC packets to come. */ | |
1386 | packet->type = SR_DF_META_LOGIC; | |
1387 | packet->payload = &meta; | |
0e1357e8 BV |
1388 | meta.samplerate = devc->cur_samplerate; |
1389 | meta.num_probes = devc->num_probes; | |
1390 | sr_session_send(devc->session_dev_id, packet); | |
f366e86c BV |
1391 | |
1392 | /* Add capture source. */ | |
3ffb6964 | 1393 | sr_source_add(0, G_IO_IN, 10, receive_data, (void *)sdi); |
f366e86c | 1394 | |
3c36c403 HE |
1395 | g_free(header); |
1396 | g_free(packet); | |
1397 | ||
0e1357e8 | 1398 | devc->state.state = SIGMA_CAPTURE; |
6aac7737 | 1399 | |
e46b8fb1 | 1400 | return SR_OK; |
28a35d8a HE |
1401 | } |
1402 | ||
3ffb6964 BV |
1403 | static int hw_dev_acquisition_stop(const struct sr_dev_inst *sdi, |
1404 | void *cb_data) | |
28a35d8a | 1405 | { |
0e1357e8 | 1406 | struct dev_context *devc; |
6aac7737 HE |
1407 | uint8_t modestatus; |
1408 | ||
cb93f8a9 | 1409 | /* Avoid compiler warnings. */ |
3cd3a20b | 1410 | (void)cb_data; |
28a35d8a | 1411 | |
0e1357e8 | 1412 | if (!(devc = sdi->priv)) { |
7b48d6e1 | 1413 | sr_err("sigma: %s: sdi->priv was NULL", __func__); |
3010f21c UH |
1414 | return SR_ERR_BUG; |
1415 | } | |
1416 | ||
fefa1800 | 1417 | /* Stop acquisition. */ |
0e1357e8 | 1418 | sigma_set_register(WRITE_MODE, 0x11, devc); |
28a35d8a | 1419 | |
6aac7737 | 1420 | /* Set SDRAM Read Enable. */ |
0e1357e8 | 1421 | sigma_set_register(WRITE_MODE, 0x02, devc); |
6aac7737 HE |
1422 | |
1423 | /* Get the current position. */ | |
0e1357e8 | 1424 | sigma_read_pos(&devc->state.stoppos, &devc->state.triggerpos, devc); |
6aac7737 HE |
1425 | |
1426 | /* Check if trigger has fired. */ | |
0e1357e8 | 1427 | modestatus = sigma_get_register(READ_MODE, devc); |
3010f21c | 1428 | if (modestatus & 0x20) |
0e1357e8 | 1429 | devc->state.triggerchunk = devc->state.triggerpos / 512; |
3010f21c | 1430 | else |
0e1357e8 | 1431 | devc->state.triggerchunk = -1; |
6aac7737 | 1432 | |
0e1357e8 | 1433 | devc->state.chunks_downloaded = 0; |
6aac7737 | 1434 | |
0e1357e8 | 1435 | devc->state.state = SIGMA_DOWNLOAD; |
3010f21c UH |
1436 | |
1437 | return SR_OK; | |
28a35d8a HE |
1438 | } |
1439 | ||
c09f0b57 | 1440 | SR_PRIV struct sr_dev_driver asix_sigma_driver_info = { |
e519ba86 | 1441 | .name = "asix-sigma", |
6352d030 | 1442 | .longname = "ASIX SIGMA/SIGMA2", |
e519ba86 UH |
1443 | .api_version = 1, |
1444 | .init = hw_init, | |
1445 | .cleanup = hw_cleanup, | |
61136ea6 | 1446 | .scan = hw_scan, |
e7eb703f UH |
1447 | .dev_open = hw_dev_open, |
1448 | .dev_close = hw_dev_close, | |
41479605 | 1449 | .info_get = hw_info_get, |
a9a245b4 | 1450 | .dev_config_set = hw_dev_config_set, |
6b3dfec8 UH |
1451 | .dev_acquisition_start = hw_dev_acquisition_start, |
1452 | .dev_acquisition_stop = hw_dev_acquisition_stop, | |
0e1357e8 | 1453 | .priv = NULL, |
28a35d8a | 1454 | }; |