]>
Commit | Line | Data |
---|---|---|
28a35d8a | 1 | /* |
50985c20 | 2 | * This file is part of the libsigrok project. |
28a35d8a | 3 | * |
868501fa | 4 | * Copyright (C) 2010-2012 Håvard Espeland <gus@ping.uio.no>, |
911f1834 UH |
5 | * Copyright (C) 2010 Martin Stensgård <mastensg@ping.uio.no> |
6 | * Copyright (C) 2010 Carl Henrik Lunde <chlunde@ping.uio.no> | |
28a35d8a HE |
7 | * |
8 | * This program is free software: you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation, either version 3 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
20 | */ | |
21 | ||
911f1834 | 22 | /* |
6352d030 | 23 | * ASIX SIGMA/SIGMA2 logic analyzer driver |
911f1834 UH |
24 | */ |
25 | ||
3bbd9849 UH |
26 | #include <glib.h> |
27 | #include <glib/gstdio.h> | |
28a35d8a HE |
28 | #include <ftdi.h> |
29 | #include <string.h> | |
e15e5873 | 30 | #include <unistd.h> |
45c59c8b BV |
31 | #include "libsigrok.h" |
32 | #include "libsigrok-internal.h" | |
28a35d8a HE |
33 | #include "asix-sigma.h" |
34 | ||
35 | #define USB_VENDOR 0xa600 | |
36 | #define USB_PRODUCT 0xa000 | |
37 | #define USB_DESCRIPTION "ASIX SIGMA" | |
38 | #define USB_VENDOR_NAME "ASIX" | |
39 | #define USB_MODEL_NAME "SIGMA" | |
28a35d8a | 40 | |
ed300b9f | 41 | SR_PRIV struct sr_dev_driver asix_sigma_driver_info; |
6078d2c9 | 42 | static int dev_acquisition_stop(struct sr_dev_inst *sdi, void *cb_data); |
28a35d8a | 43 | |
b1648dea MV |
44 | /* |
45 | * The ASIX Sigma supports arbitrary integer frequency divider in | |
46 | * the 50MHz mode. The divider is in range 1...256 , allowing for | |
47 | * very precise sampling rate selection. This driver supports only | |
48 | * a subset of the sampling rates. | |
49 | */ | |
2c9c0df8 | 50 | static const uint64_t samplerates[] = { |
b1648dea MV |
51 | SR_KHZ(200), /* div=250 */ |
52 | SR_KHZ(250), /* div=200 */ | |
53 | SR_KHZ(500), /* div=100 */ | |
54 | SR_MHZ(1), /* div=50 */ | |
55 | SR_MHZ(5), /* div=10 */ | |
56 | SR_MHZ(10), /* div=5 */ | |
57 | SR_MHZ(25), /* div=2 */ | |
58 | SR_MHZ(50), /* div=1 */ | |
59 | SR_MHZ(100), /* Special FW needed */ | |
60 | SR_MHZ(200), /* Special FW needed */ | |
28a35d8a HE |
61 | }; |
62 | ||
d261dbbf | 63 | /* |
ba7dd8bb | 64 | * Channel numbers seem to go from 1-16, according to this image: |
d261dbbf UH |
65 | * http://tools.asix.net/img/sigma_sigmacab_pins_720.jpg |
66 | * (the cable has two additional GND pins, and a TI and TO pin) | |
67 | */ | |
790c7ccc | 68 | static const char *channel_names[] = { |
78693401 UH |
69 | "1", "2", "3", "4", "5", "6", "7", "8", |
70 | "9", "10", "11", "12", "13", "14", "15", "16", | |
464d12c7 KS |
71 | }; |
72 | ||
2ff11e50 | 73 | static const uint32_t drvopts[] = { |
1953564a | 74 | SR_CONF_LOGIC_ANALYZER, |
e7ba5a99 BV |
75 | }; |
76 | ||
2ff11e50 BV |
77 | static const uint32_t devopts[] = { |
78 | SR_CONF_LIMIT_MSEC | SR_CONF_GET | SR_CONF_SET, | |
79 | SR_CONF_LIMIT_SAMPLES | SR_CONF_SET, | |
5827f61b BV |
80 | SR_CONF_SAMPLERATE | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST, |
81 | SR_CONF_TRIGGER_MATCH | SR_CONF_LIST, | |
82 | SR_CONF_CAPTURE_RATIO | SR_CONF_GET | SR_CONF_SET, | |
28a35d8a HE |
83 | }; |
84 | ||
39c64c6a BV |
85 | static const int32_t trigger_matches[] = { |
86 | SR_TRIGGER_ZERO, | |
87 | SR_TRIGGER_ONE, | |
88 | SR_TRIGGER_RISING, | |
89 | SR_TRIGGER_FALLING, | |
90 | }; | |
91 | ||
499b17e9 MV |
92 | static const char *sigma_firmware_files[] = { |
93 | /* 50 MHz, supports 8 bit fractions */ | |
94 | FIRMWARE_DIR "/asix-sigma-50.fw", | |
95 | /* 100 MHz */ | |
96 | FIRMWARE_DIR "/asix-sigma-100.fw", | |
97 | /* 200 MHz */ | |
98 | FIRMWARE_DIR "/asix-sigma-200.fw", | |
99 | /* Synchronous clock from pin */ | |
100 | FIRMWARE_DIR "/asix-sigma-50sync.fw", | |
101 | /* Frequency counter */ | |
102 | FIRMWARE_DIR "/asix-sigma-phasor.fw", | |
f6564c8d HE |
103 | }; |
104 | ||
0e1357e8 | 105 | static int sigma_read(void *buf, size_t size, struct dev_context *devc) |
28a35d8a HE |
106 | { |
107 | int ret; | |
fefa1800 | 108 | |
0e1357e8 | 109 | ret = ftdi_read_data(&devc->ftdic, (unsigned char *)buf, size); |
28a35d8a | 110 | if (ret < 0) { |
47f4f073 | 111 | sr_err("ftdi_read_data failed: %s", |
0e1357e8 | 112 | ftdi_get_error_string(&devc->ftdic)); |
28a35d8a HE |
113 | } |
114 | ||
115 | return ret; | |
116 | } | |
117 | ||
0e1357e8 | 118 | static int sigma_write(void *buf, size_t size, struct dev_context *devc) |
28a35d8a HE |
119 | { |
120 | int ret; | |
fefa1800 | 121 | |
0e1357e8 | 122 | ret = ftdi_write_data(&devc->ftdic, (unsigned char *)buf, size); |
28a35d8a | 123 | if (ret < 0) { |
47f4f073 | 124 | sr_err("ftdi_write_data failed: %s", |
0e1357e8 | 125 | ftdi_get_error_string(&devc->ftdic)); |
fefa1800 | 126 | } else if ((size_t) ret != size) { |
47f4f073 | 127 | sr_err("ftdi_write_data did not complete write."); |
28a35d8a HE |
128 | } |
129 | ||
130 | return ret; | |
131 | } | |
132 | ||
99965709 | 133 | static int sigma_write_register(uint8_t reg, uint8_t *data, size_t len, |
0e1357e8 | 134 | struct dev_context *devc) |
28a35d8a HE |
135 | { |
136 | size_t i; | |
137 | uint8_t buf[len + 2]; | |
138 | int idx = 0; | |
139 | ||
140 | buf[idx++] = REG_ADDR_LOW | (reg & 0xf); | |
141 | buf[idx++] = REG_ADDR_HIGH | (reg >> 4); | |
142 | ||
fefa1800 | 143 | for (i = 0; i < len; ++i) { |
28a35d8a HE |
144 | buf[idx++] = REG_DATA_LOW | (data[i] & 0xf); |
145 | buf[idx++] = REG_DATA_HIGH_WRITE | (data[i] >> 4); | |
146 | } | |
147 | ||
0e1357e8 | 148 | return sigma_write(buf, idx, devc); |
28a35d8a HE |
149 | } |
150 | ||
0e1357e8 | 151 | static int sigma_set_register(uint8_t reg, uint8_t value, struct dev_context *devc) |
28a35d8a | 152 | { |
0e1357e8 | 153 | return sigma_write_register(reg, &value, 1, devc); |
28a35d8a HE |
154 | } |
155 | ||
99965709 | 156 | static int sigma_read_register(uint8_t reg, uint8_t *data, size_t len, |
0e1357e8 | 157 | struct dev_context *devc) |
28a35d8a HE |
158 | { |
159 | uint8_t buf[3]; | |
fefa1800 | 160 | |
28a35d8a HE |
161 | buf[0] = REG_ADDR_LOW | (reg & 0xf); |
162 | buf[1] = REG_ADDR_HIGH | (reg >> 4); | |
28a35d8a HE |
163 | buf[2] = REG_READ_ADDR; |
164 | ||
0e1357e8 | 165 | sigma_write(buf, sizeof(buf), devc); |
28a35d8a | 166 | |
0e1357e8 | 167 | return sigma_read(data, len, devc); |
28a35d8a HE |
168 | } |
169 | ||
0e1357e8 | 170 | static uint8_t sigma_get_register(uint8_t reg, struct dev_context *devc) |
28a35d8a HE |
171 | { |
172 | uint8_t value; | |
fefa1800 | 173 | |
0e1357e8 | 174 | if (1 != sigma_read_register(reg, &value, 1, devc)) { |
47f4f073 | 175 | sr_err("sigma_get_register: 1 byte expected"); |
28a35d8a HE |
176 | return 0; |
177 | } | |
178 | ||
179 | return value; | |
180 | } | |
181 | ||
99965709 | 182 | static int sigma_read_pos(uint32_t *stoppos, uint32_t *triggerpos, |
0e1357e8 | 183 | struct dev_context *devc) |
28a35d8a HE |
184 | { |
185 | uint8_t buf[] = { | |
186 | REG_ADDR_LOW | READ_TRIGGER_POS_LOW, | |
187 | ||
188 | REG_READ_ADDR | NEXT_REG, | |
189 | REG_READ_ADDR | NEXT_REG, | |
190 | REG_READ_ADDR | NEXT_REG, | |
191 | REG_READ_ADDR | NEXT_REG, | |
192 | REG_READ_ADDR | NEXT_REG, | |
193 | REG_READ_ADDR | NEXT_REG, | |
194 | }; | |
28a35d8a HE |
195 | uint8_t result[6]; |
196 | ||
0e1357e8 | 197 | sigma_write(buf, sizeof(buf), devc); |
28a35d8a | 198 | |
0e1357e8 | 199 | sigma_read(result, sizeof(result), devc); |
28a35d8a HE |
200 | |
201 | *triggerpos = result[0] | (result[1] << 8) | (result[2] << 16); | |
202 | *stoppos = result[3] | (result[4] << 8) | (result[5] << 16); | |
203 | ||
57bbf56b HE |
204 | /* Not really sure why this must be done, but according to spec. */ |
205 | if ((--*stoppos & 0x1ff) == 0x1ff) | |
382cb19f | 206 | *stoppos -= 64; |
57bbf56b HE |
207 | |
208 | if ((*--triggerpos & 0x1ff) == 0x1ff) | |
382cb19f | 209 | *triggerpos -= 64; |
57bbf56b | 210 | |
28a35d8a HE |
211 | return 1; |
212 | } | |
213 | ||
99965709 | 214 | static int sigma_read_dram(uint16_t startchunk, size_t numchunks, |
0e1357e8 | 215 | uint8_t *data, struct dev_context *devc) |
28a35d8a HE |
216 | { |
217 | size_t i; | |
218 | uint8_t buf[4096]; | |
219 | int idx = 0; | |
220 | ||
fefa1800 | 221 | /* Send the startchunk. Index start with 1. */ |
28a35d8a HE |
222 | buf[0] = startchunk >> 8; |
223 | buf[1] = startchunk & 0xff; | |
0e1357e8 | 224 | sigma_write_register(WRITE_MEMROW, buf, 2, devc); |
28a35d8a | 225 | |
fefa1800 | 226 | /* Read the DRAM. */ |
28a35d8a HE |
227 | buf[idx++] = REG_DRAM_BLOCK; |
228 | buf[idx++] = REG_DRAM_WAIT_ACK; | |
229 | ||
230 | for (i = 0; i < numchunks; ++i) { | |
fefa1800 UH |
231 | /* Alternate bit to copy from DRAM to cache. */ |
232 | if (i != (numchunks - 1)) | |
233 | buf[idx++] = REG_DRAM_BLOCK | (((i + 1) % 2) << 4); | |
28a35d8a HE |
234 | |
235 | buf[idx++] = REG_DRAM_BLOCK_DATA | ((i % 2) << 4); | |
236 | ||
fefa1800 | 237 | if (i != (numchunks - 1)) |
28a35d8a HE |
238 | buf[idx++] = REG_DRAM_WAIT_ACK; |
239 | } | |
240 | ||
0e1357e8 | 241 | sigma_write(buf, idx, devc); |
28a35d8a | 242 | |
0e1357e8 | 243 | return sigma_read(data, numchunks * CHUNK_SIZE, devc); |
28a35d8a HE |
244 | } |
245 | ||
4ae1f451 | 246 | /* Upload trigger look-up tables to Sigma. */ |
0e1357e8 | 247 | static int sigma_write_trigger_lut(struct triggerlut *lut, struct dev_context *devc) |
ee492173 HE |
248 | { |
249 | int i; | |
250 | uint8_t tmp[2]; | |
251 | uint16_t bit; | |
252 | ||
253 | /* Transpose the table and send to Sigma. */ | |
254 | for (i = 0; i < 16; ++i) { | |
255 | bit = 1 << i; | |
256 | ||
257 | tmp[0] = tmp[1] = 0; | |
258 | ||
259 | if (lut->m2d[0] & bit) | |
260 | tmp[0] |= 0x01; | |
261 | if (lut->m2d[1] & bit) | |
262 | tmp[0] |= 0x02; | |
263 | if (lut->m2d[2] & bit) | |
264 | tmp[0] |= 0x04; | |
265 | if (lut->m2d[3] & bit) | |
266 | tmp[0] |= 0x08; | |
267 | ||
268 | if (lut->m3 & bit) | |
269 | tmp[0] |= 0x10; | |
270 | if (lut->m3s & bit) | |
271 | tmp[0] |= 0x20; | |
272 | if (lut->m4 & bit) | |
273 | tmp[0] |= 0x40; | |
274 | ||
275 | if (lut->m0d[0] & bit) | |
276 | tmp[1] |= 0x01; | |
277 | if (lut->m0d[1] & bit) | |
278 | tmp[1] |= 0x02; | |
279 | if (lut->m0d[2] & bit) | |
280 | tmp[1] |= 0x04; | |
281 | if (lut->m0d[3] & bit) | |
282 | tmp[1] |= 0x08; | |
283 | ||
284 | if (lut->m1d[0] & bit) | |
285 | tmp[1] |= 0x10; | |
286 | if (lut->m1d[1] & bit) | |
287 | tmp[1] |= 0x20; | |
288 | if (lut->m1d[2] & bit) | |
289 | tmp[1] |= 0x40; | |
290 | if (lut->m1d[3] & bit) | |
291 | tmp[1] |= 0x80; | |
292 | ||
99965709 | 293 | sigma_write_register(WRITE_TRIGGER_SELECT0, tmp, sizeof(tmp), |
0e1357e8 BV |
294 | devc); |
295 | sigma_set_register(WRITE_TRIGGER_SELECT1, 0x30 | i, devc); | |
ee492173 HE |
296 | } |
297 | ||
298 | /* Send the parameters */ | |
299 | sigma_write_register(WRITE_TRIGGER_SELECT0, (uint8_t *) &lut->params, | |
0e1357e8 | 300 | sizeof(lut->params), devc); |
ee492173 | 301 | |
e46b8fb1 | 302 | return SR_OK; |
ee492173 HE |
303 | } |
304 | ||
3678cf73 | 305 | static void clear_helper(void *priv) |
0448d110 | 306 | { |
0e1357e8 | 307 | struct dev_context *devc; |
ce4d26dd | 308 | |
3678cf73 | 309 | devc = priv; |
0e1357e8 | 310 | |
3678cf73 UH |
311 | ftdi_deinit(&devc->ftdic); |
312 | } | |
0448d110 | 313 | |
4f840ce9 | 314 | static int dev_clear(const struct sr_dev_driver *di) |
3678cf73 UH |
315 | { |
316 | return std_dev_clear(di, clear_helper); | |
0448d110 BV |
317 | } |
318 | ||
4f840ce9 | 319 | static int init(struct sr_dev_driver *di, struct sr_context *sr_ctx) |
61136ea6 | 320 | { |
f6beaac5 | 321 | return std_init(sr_ctx, di, LOG_PREFIX); |
61136ea6 BV |
322 | } |
323 | ||
4f840ce9 | 324 | static GSList *scan(struct sr_dev_driver *di, GSList *options) |
28a35d8a | 325 | { |
d68e2d1a | 326 | struct sr_dev_inst *sdi; |
0e1357e8 BV |
327 | struct drv_context *drvc; |
328 | struct dev_context *devc; | |
0448d110 | 329 | GSList *devices; |
e3fff420 HE |
330 | struct ftdi_device_list *devlist; |
331 | char serial_txt[10]; | |
332 | uint32_t serial; | |
790c7ccc MV |
333 | int ret; |
334 | unsigned int i; | |
28a35d8a | 335 | |
0448d110 | 336 | (void)options; |
64d33dc2 | 337 | |
a873c594 | 338 | drvc = di->priv; |
4b97c74e | 339 | |
0448d110 | 340 | devices = NULL; |
4b97c74e | 341 | |
f57d8ffe | 342 | devc = g_malloc0(sizeof(struct dev_context)); |
99965709 | 343 | |
0e1357e8 | 344 | ftdi_init(&devc->ftdic); |
28a35d8a | 345 | |
fefa1800 | 346 | /* Look for SIGMAs. */ |
e3fff420 | 347 | |
0e1357e8 | 348 | if ((ret = ftdi_usb_find_all(&devc->ftdic, &devlist, |
eec944c5 BV |
349 | USB_VENDOR, USB_PRODUCT)) <= 0) { |
350 | if (ret < 0) | |
351 | sr_err("ftdi_usb_find_all(): %d", ret); | |
99965709 | 352 | goto free; |
eec944c5 | 353 | } |
99965709 | 354 | |
e3fff420 | 355 | /* Make sure it's a version 1 or 2 SIGMA. */ |
0e1357e8 | 356 | ftdi_usb_get_strings(&devc->ftdic, devlist->dev, NULL, 0, NULL, 0, |
6352d030 | 357 | serial_txt, sizeof(serial_txt)); |
e3fff420 HE |
358 | sscanf(serial_txt, "%x", &serial); |
359 | ||
6352d030 | 360 | if (serial < 0xa6010000 || serial > 0xa602ffff) { |
47f4f073 UH |
361 | sr_err("Only SIGMA and SIGMA2 are supported " |
362 | "in this version of libsigrok."); | |
e3fff420 HE |
363 | goto free; |
364 | } | |
365 | ||
366 | sr_info("Found ASIX SIGMA - Serial: %s", serial_txt); | |
367 | ||
23b886bc | 368 | devc->cur_samplerate = samplerates[0]; |
0e1357e8 BV |
369 | devc->period_ps = 0; |
370 | devc->limit_msec = 0; | |
371 | devc->cur_firmware = -1; | |
ba7dd8bb | 372 | devc->num_channels = 0; |
0e1357e8 BV |
373 | devc->samples_per_event = 0; |
374 | devc->capture_ratio = 50; | |
375 | devc->use_triggers = 0; | |
28a35d8a | 376 | |
fefa1800 | 377 | /* Register SIGMA device. */ |
aac29cc1 | 378 | sdi = g_malloc0(sizeof(struct sr_dev_inst)); |
0af636be UH |
379 | sdi->status = SR_ST_INITIALIZING; |
380 | sdi->vendor = g_strdup(USB_VENDOR_NAME); | |
381 | sdi->model = g_strdup(USB_MODEL_NAME); | |
a873c594 | 382 | sdi->driver = di; |
87ca93c5 | 383 | |
5e23fcab ML |
384 | for (i = 0; i < ARRAY_SIZE(channel_names); i++) |
385 | sr_channel_new(sdi, i, SR_CHANNEL_LOGIC, TRUE, | |
790c7ccc | 386 | channel_names[i]); |
87ca93c5 | 387 | |
0448d110 | 388 | devices = g_slist_append(devices, sdi); |
0e1357e8 BV |
389 | drvc->instances = g_slist_append(drvc->instances, sdi); |
390 | sdi->priv = devc; | |
28a35d8a | 391 | |
fefa1800 | 392 | /* We will open the device again when we need it. */ |
e3fff420 | 393 | ftdi_list_free(&devlist); |
28a35d8a | 394 | |
0448d110 | 395 | return devices; |
ea9cfed7 | 396 | |
99965709 | 397 | free: |
0e1357e8 BV |
398 | ftdi_deinit(&devc->ftdic); |
399 | g_free(devc); | |
0448d110 | 400 | return NULL; |
28a35d8a HE |
401 | } |
402 | ||
4f840ce9 | 403 | static GSList *dev_list(const struct sr_dev_driver *di) |
811deee4 | 404 | { |
0e94d524 | 405 | return ((struct drv_context *)(di->priv))->instances; |
811deee4 BV |
406 | } |
407 | ||
d5fa188a MV |
408 | /* |
409 | * Configure the FPGA for bitbang mode. | |
410 | * This sequence is documented in section 2. of the ASIX Sigma programming | |
411 | * manual. This sequence is necessary to configure the FPGA in the Sigma | |
412 | * into Bitbang mode, in which it can be programmed with the firmware. | |
413 | */ | |
414 | static int sigma_fpga_init_bitbang(struct dev_context *devc) | |
415 | { | |
416 | uint8_t suicide[] = { | |
417 | 0x84, 0x84, 0x88, 0x84, 0x88, 0x84, 0x88, 0x84, | |
418 | }; | |
419 | uint8_t init_array[] = { | |
420 | 0x01, 0x03, 0x03, 0x01, 0x01, 0x01, 0x01, 0x01, | |
421 | 0x01, 0x01, | |
422 | }; | |
423 | int i, ret, timeout = 10000; | |
424 | uint8_t data; | |
425 | ||
426 | /* Section 2. part 1), do the FPGA suicide. */ | |
427 | sigma_write(suicide, sizeof(suicide), devc); | |
428 | sigma_write(suicide, sizeof(suicide), devc); | |
429 | sigma_write(suicide, sizeof(suicide), devc); | |
430 | sigma_write(suicide, sizeof(suicide), devc); | |
431 | ||
432 | /* Section 2. part 2), do pulse on D1. */ | |
433 | sigma_write(init_array, sizeof(init_array), devc); | |
434 | ftdi_usb_purge_buffers(&devc->ftdic); | |
435 | ||
436 | /* Wait until the FPGA asserts D6/INIT_B. */ | |
437 | for (i = 0; i < timeout; i++) { | |
438 | ret = sigma_read(&data, 1, devc); | |
439 | if (ret < 0) | |
440 | return ret; | |
441 | /* Test if pin D6 got asserted. */ | |
442 | if (data & (1 << 5)) | |
443 | return 0; | |
444 | /* The D6 was not asserted yet, wait a bit. */ | |
d9c3331d | 445 | g_usleep(10000); |
d5fa188a MV |
446 | } |
447 | ||
448 | return SR_ERR_TIMEOUT; | |
449 | } | |
450 | ||
64fe661b MV |
451 | /* |
452 | * Configure the FPGA for logic-analyzer mode. | |
453 | */ | |
454 | static int sigma_fpga_init_la(struct dev_context *devc) | |
455 | { | |
456 | /* Initialize the logic analyzer mode. */ | |
457 | uint8_t logic_mode_start[] = { | |
011f1091 MV |
458 | REG_ADDR_LOW | (READ_ID & 0xf), |
459 | REG_ADDR_HIGH | (READ_ID >> 8), | |
460 | REG_READ_ADDR, /* Read ID register. */ | |
461 | ||
462 | REG_ADDR_LOW | (WRITE_TEST & 0xf), | |
463 | REG_DATA_LOW | 0x5, | |
464 | REG_DATA_HIGH_WRITE | 0x5, | |
465 | REG_READ_ADDR, /* Read scratch register. */ | |
466 | ||
467 | REG_DATA_LOW | 0xa, | |
468 | REG_DATA_HIGH_WRITE | 0xa, | |
469 | REG_READ_ADDR, /* Read scratch register. */ | |
470 | ||
471 | REG_ADDR_LOW | (WRITE_MODE & 0xf), | |
472 | REG_DATA_LOW | 0x0, | |
473 | REG_DATA_HIGH_WRITE | 0x8, | |
64fe661b MV |
474 | }; |
475 | ||
476 | uint8_t result[3]; | |
477 | int ret; | |
478 | ||
479 | /* Initialize the logic analyzer mode. */ | |
480 | sigma_write(logic_mode_start, sizeof(logic_mode_start), devc); | |
481 | ||
011f1091 | 482 | /* Expect a 3 byte reply since we issued three READ requests. */ |
64fe661b MV |
483 | ret = sigma_read(result, 3, devc); |
484 | if (ret != 3) | |
485 | goto err; | |
486 | ||
487 | if (result[0] != 0xa6 || result[1] != 0x55 || result[2] != 0xaa) | |
488 | goto err; | |
489 | ||
490 | return SR_OK; | |
491 | err: | |
492 | sr_err("Configuration failed. Invalid reply received."); | |
493 | return SR_ERR; | |
494 | } | |
495 | ||
a80226bb MV |
496 | /* |
497 | * Read the firmware from a file and transform it into a series of bitbang | |
498 | * pulses used to program the FPGA. Note that the *bb_cmd must be free()'d | |
499 | * by the caller of this function. | |
500 | */ | |
501 | static int sigma_fw_2_bitbang(const char *filename, | |
502 | uint8_t **bb_cmd, gsize *bb_cmd_size) | |
503 | { | |
504 | GMappedFile *file; | |
505 | GError *error; | |
506 | gsize i, file_size, bb_size; | |
507 | gchar *firmware; | |
508 | uint8_t *bb_stream, *bbs; | |
509 | uint32_t imm; | |
510 | int bit, v; | |
511 | int ret = SR_OK; | |
512 | ||
513 | /* | |
514 | * Map the file and make the mapped buffer writable. | |
515 | * NOTE: Using writable=TRUE does _NOT_ mean that file that is mapped | |
516 | * will be modified. It will not be modified until someone uses | |
517 | * g_file_set_contents() on it. | |
518 | */ | |
519 | error = NULL; | |
520 | file = g_mapped_file_new(filename, TRUE, &error); | |
521 | g_assert_no_error(error); | |
522 | ||
523 | file_size = g_mapped_file_get_length(file); | |
524 | firmware = g_mapped_file_get_contents(file); | |
525 | g_assert(firmware); | |
526 | ||
527 | /* Weird magic transformation below, I have no idea what it does. */ | |
528 | imm = 0x3f6df2ab; | |
529 | for (i = 0; i < file_size; i++) { | |
530 | imm = (imm + 0xa853753) % 177 + (imm * 0x8034052); | |
531 | firmware[i] ^= imm & 0xff; | |
532 | } | |
533 | ||
534 | /* | |
535 | * Now that the firmware is "transformed", we will transcribe the | |
536 | * firmware blob into a sequence of toggles of the Dx wires. This | |
537 | * sequence will be fed directly into the Sigma, which must be in | |
538 | * the FPGA bitbang programming mode. | |
539 | */ | |
540 | ||
541 | /* Each bit of firmware is transcribed as two toggles of Dx wires. */ | |
542 | bb_size = file_size * 8 * 2; | |
543 | bb_stream = (uint8_t *)g_try_malloc(bb_size); | |
544 | if (!bb_stream) { | |
545 | sr_err("%s: Failed to allocate bitbang stream", __func__); | |
546 | ret = SR_ERR_MALLOC; | |
547 | goto exit; | |
548 | } | |
549 | ||
550 | bbs = bb_stream; | |
551 | for (i = 0; i < file_size; i++) { | |
552 | for (bit = 7; bit >= 0; bit--) { | |
553 | v = (firmware[i] & (1 << bit)) ? 0x40 : 0x00; | |
554 | *bbs++ = v | 0x01; | |
555 | *bbs++ = v; | |
556 | } | |
557 | } | |
558 | ||
559 | /* The transformation completed successfully, return the result. */ | |
560 | *bb_cmd = bb_stream; | |
561 | *bb_cmd_size = bb_size; | |
562 | ||
563 | exit: | |
564 | g_mapped_file_unref(file); | |
565 | return ret; | |
566 | } | |
567 | ||
0e1357e8 | 568 | static int upload_firmware(int firmware_idx, struct dev_context *devc) |
28a35d8a HE |
569 | { |
570 | int ret; | |
571 | unsigned char *buf; | |
572 | unsigned char pins; | |
573 | size_t buf_size; | |
499b17e9 | 574 | const char *firmware = sigma_firmware_files[firmware_idx]; |
8bbf7627 | 575 | struct ftdi_context *ftdic = &devc->ftdic; |
28a35d8a | 576 | |
fefa1800 | 577 | /* Make sure it's an ASIX SIGMA. */ |
8bbf7627 MV |
578 | ret = ftdi_usb_open_desc(ftdic, USB_VENDOR, USB_PRODUCT, |
579 | USB_DESCRIPTION, NULL); | |
580 | if (ret < 0) { | |
47f4f073 | 581 | sr_err("ftdi_usb_open failed: %s", |
8bbf7627 | 582 | ftdi_get_error_string(ftdic)); |
28a35d8a HE |
583 | return 0; |
584 | } | |
585 | ||
8bbf7627 MV |
586 | ret = ftdi_set_bitmode(ftdic, 0xdf, BITMODE_BITBANG); |
587 | if (ret < 0) { | |
47f4f073 | 588 | sr_err("ftdi_set_bitmode failed: %s", |
8bbf7627 | 589 | ftdi_get_error_string(ftdic)); |
28a35d8a HE |
590 | return 0; |
591 | } | |
592 | ||
fefa1800 | 593 | /* Four times the speed of sigmalogan - Works well. */ |
8bbf7627 MV |
594 | ret = ftdi_set_baudrate(ftdic, 750000); |
595 | if (ret < 0) { | |
47f4f073 | 596 | sr_err("ftdi_set_baudrate failed: %s", |
8bbf7627 | 597 | ftdi_get_error_string(ftdic)); |
28a35d8a HE |
598 | return 0; |
599 | } | |
600 | ||
d5fa188a MV |
601 | /* Initialize the FPGA for firmware upload. */ |
602 | ret = sigma_fpga_init_bitbang(devc); | |
603 | if (ret) | |
604 | return ret; | |
28a35d8a | 605 | |
9ddb2a12 | 606 | /* Prepare firmware. */ |
d485d443 | 607 | ret = sigma_fw_2_bitbang(firmware, &buf, &buf_size); |
8bbf7627 | 608 | if (ret != SR_OK) { |
47f4f073 | 609 | sr_err("An error occured while reading the firmware: %s", |
499b17e9 | 610 | firmware); |
b53738ba | 611 | return ret; |
28a35d8a HE |
612 | } |
613 | ||
fefa1800 | 614 | /* Upload firmare. */ |
499b17e9 | 615 | sr_info("Uploading firmware file '%s'.", firmware); |
0e1357e8 | 616 | sigma_write(buf, buf_size, devc); |
28a35d8a HE |
617 | |
618 | g_free(buf); | |
619 | ||
8bbf7627 MV |
620 | ret = ftdi_set_bitmode(ftdic, 0x00, BITMODE_RESET); |
621 | if (ret < 0) { | |
47f4f073 | 622 | sr_err("ftdi_set_bitmode failed: %s", |
8bbf7627 | 623 | ftdi_get_error_string(ftdic)); |
e46b8fb1 | 624 | return SR_ERR; |
28a35d8a HE |
625 | } |
626 | ||
8bbf7627 | 627 | ftdi_usb_purge_buffers(ftdic); |
28a35d8a | 628 | |
fefa1800 | 629 | /* Discard garbage. */ |
29b66a2e | 630 | while (sigma_read(&pins, 1, devc) == 1) |
28a35d8a HE |
631 | ; |
632 | ||
64fe661b MV |
633 | /* Initialize the FPGA for logic-analyzer mode. */ |
634 | ret = sigma_fpga_init_la(devc); | |
635 | if (ret != SR_OK) | |
636 | return ret; | |
28a35d8a | 637 | |
0e1357e8 | 638 | devc->cur_firmware = firmware_idx; |
f6564c8d | 639 | |
47f4f073 | 640 | sr_info("Firmware uploaded."); |
e3fff420 | 641 | |
e46b8fb1 | 642 | return SR_OK; |
f6564c8d HE |
643 | } |
644 | ||
6078d2c9 | 645 | static int dev_open(struct sr_dev_inst *sdi) |
f6564c8d | 646 | { |
0e1357e8 | 647 | struct dev_context *devc; |
f6564c8d HE |
648 | int ret; |
649 | ||
0e1357e8 | 650 | devc = sdi->priv; |
99965709 | 651 | |
9ddb2a12 | 652 | /* Make sure it's an ASIX SIGMA. */ |
0e1357e8 | 653 | if ((ret = ftdi_usb_open_desc(&devc->ftdic, |
f6564c8d HE |
654 | USB_VENDOR, USB_PRODUCT, USB_DESCRIPTION, NULL)) < 0) { |
655 | ||
47f4f073 | 656 | sr_err("ftdi_usb_open failed: %s", |
0e1357e8 | 657 | ftdi_get_error_string(&devc->ftdic)); |
f6564c8d HE |
658 | |
659 | return 0; | |
660 | } | |
28a35d8a | 661 | |
5a2326a7 | 662 | sdi->status = SR_ST_ACTIVE; |
28a35d8a | 663 | |
e46b8fb1 | 664 | return SR_OK; |
f6564c8d HE |
665 | } |
666 | ||
6f4b1868 | 667 | static int set_samplerate(const struct sr_dev_inst *sdi, uint64_t samplerate) |
f6564c8d | 668 | { |
2c9c0df8 BV |
669 | struct dev_context *devc; |
670 | unsigned int i; | |
671 | int ret; | |
f6564c8d | 672 | |
2c9c0df8 | 673 | devc = sdi->priv; |
f4abaa9f UH |
674 | ret = SR_OK; |
675 | ||
2c9c0df8 BV |
676 | for (i = 0; i < ARRAY_SIZE(samplerates); i++) { |
677 | if (samplerates[i] == samplerate) | |
f6564c8d HE |
678 | break; |
679 | } | |
2c9c0df8 | 680 | if (samplerates[i] == 0) |
e46b8fb1 | 681 | return SR_ERR_SAMPLERATE; |
f6564c8d | 682 | |
59df0c77 | 683 | if (samplerate <= SR_MHZ(50)) { |
0e1357e8 | 684 | ret = upload_firmware(0, devc); |
ba7dd8bb | 685 | devc->num_channels = 16; |
6b2d3385 | 686 | } else if (samplerate == SR_MHZ(100)) { |
0e1357e8 | 687 | ret = upload_firmware(1, devc); |
ba7dd8bb | 688 | devc->num_channels = 8; |
6b2d3385 | 689 | } else if (samplerate == SR_MHZ(200)) { |
0e1357e8 | 690 | ret = upload_firmware(2, devc); |
ba7dd8bb | 691 | devc->num_channels = 4; |
f78898e9 | 692 | } |
f6564c8d | 693 | |
6b2d3385 BV |
694 | if (ret == SR_OK) { |
695 | devc->cur_samplerate = samplerate; | |
696 | devc->period_ps = 1000000000000ULL / samplerate; | |
697 | devc->samples_per_event = 16 / devc->num_channels; | |
698 | devc->state.state = SIGMA_IDLE; | |
699 | } | |
f6564c8d | 700 | |
e8397563 | 701 | return ret; |
28a35d8a HE |
702 | } |
703 | ||
c53d793f HE |
704 | /* |
705 | * In 100 and 200 MHz mode, only a single pin rising/falling can be | |
706 | * set as trigger. In other modes, two rising/falling triggers can be set, | |
ba7dd8bb | 707 | * in addition to value/mask trigger for any number of channels. |
c53d793f HE |
708 | * |
709 | * The Sigma supports complex triggers using boolean expressions, but this | |
710 | * has not been implemented yet. | |
711 | */ | |
39c64c6a | 712 | static int convert_trigger(const struct sr_dev_inst *sdi) |
57bbf56b | 713 | { |
39c64c6a BV |
714 | struct dev_context *devc; |
715 | struct sr_trigger *trigger; | |
716 | struct sr_trigger_stage *stage; | |
717 | struct sr_trigger_match *match; | |
718 | const GSList *l, *m; | |
719 | int channelbit, trigger_set; | |
57bbf56b | 720 | |
39c64c6a | 721 | devc = sdi->priv; |
0e1357e8 | 722 | memset(&devc->trigger, 0, sizeof(struct sigma_trigger)); |
0812c40e | 723 | if (!(trigger = sr_session_trigger_get(sdi->session))) |
39c64c6a BV |
724 | return SR_OK; |
725 | ||
726 | trigger_set = 0; | |
727 | for (l = trigger->stages; l; l = l->next) { | |
728 | stage = l->data; | |
729 | for (m = stage->matches; m; m = m->next) { | |
730 | match = m->data; | |
731 | if (!match->channel->enabled) | |
732 | /* Ignore disabled channels with a trigger. */ | |
733 | continue; | |
734 | channelbit = 1 << (match->channel->index); | |
735 | if (devc->cur_samplerate >= SR_MHZ(100)) { | |
736 | /* Fast trigger support. */ | |
737 | if (trigger_set) { | |
738 | sr_err("Only a single pin trigger is " | |
739 | "supported in 100 and 200MHz mode."); | |
740 | return SR_ERR; | |
741 | } | |
742 | if (match->match == SR_TRIGGER_FALLING) | |
743 | devc->trigger.fallingmask |= channelbit; | |
744 | else if (match->match == SR_TRIGGER_RISING) | |
745 | devc->trigger.risingmask |= channelbit; | |
746 | else { | |
747 | sr_err("Only rising/falling trigger is " | |
748 | "supported in 100 and 200MHz mode."); | |
749 | return SR_ERR; | |
750 | } | |
eec5275e | 751 | |
c53d793f | 752 | ++trigger_set; |
39c64c6a BV |
753 | } else { |
754 | /* Simple trigger support (event). */ | |
755 | if (match->match == SR_TRIGGER_ONE) { | |
756 | devc->trigger.simplevalue |= channelbit; | |
757 | devc->trigger.simplemask |= channelbit; | |
758 | } | |
759 | else if (match->match == SR_TRIGGER_ZERO) { | |
760 | devc->trigger.simplevalue &= ~channelbit; | |
761 | devc->trigger.simplemask |= channelbit; | |
762 | } | |
763 | else if (match->match == SR_TRIGGER_FALLING) { | |
764 | devc->trigger.fallingmask |= channelbit; | |
765 | ++trigger_set; | |
766 | } | |
767 | else if (match->match == SR_TRIGGER_RISING) { | |
768 | devc->trigger.risingmask |= channelbit; | |
769 | ++trigger_set; | |
770 | } | |
771 | ||
772 | /* | |
773 | * Actually, Sigma supports 2 rising/falling triggers, | |
774 | * but they are ORed and the current trigger syntax | |
775 | * does not permit ORed triggers. | |
776 | */ | |
777 | if (trigger_set > 1) { | |
778 | sr_err("Only 1 rising/falling trigger " | |
779 | "is supported."); | |
780 | return SR_ERR; | |
781 | } | |
ee492173 | 782 | } |
ee492173 | 783 | } |
57bbf56b HE |
784 | } |
785 | ||
39c64c6a | 786 | |
e46b8fb1 | 787 | return SR_OK; |
57bbf56b HE |
788 | } |
789 | ||
6078d2c9 | 790 | static int dev_close(struct sr_dev_inst *sdi) |
28a35d8a | 791 | { |
0e1357e8 | 792 | struct dev_context *devc; |
28a35d8a | 793 | |
961009b0 | 794 | devc = sdi->priv; |
697785d1 UH |
795 | |
796 | /* TODO */ | |
797 | if (sdi->status == SR_ST_ACTIVE) | |
0e1357e8 | 798 | ftdi_usb_close(&devc->ftdic); |
697785d1 UH |
799 | |
800 | sdi->status = SR_ST_INACTIVE; | |
801 | ||
802 | return SR_OK; | |
28a35d8a HE |
803 | } |
804 | ||
4f840ce9 | 805 | static int cleanup(const struct sr_dev_driver *di) |
28a35d8a | 806 | { |
4f840ce9 | 807 | return dev_clear(di); |
28a35d8a HE |
808 | } |
809 | ||
584560f1 | 810 | static int config_get(uint32_t key, GVariant **data, const struct sr_dev_inst *sdi, |
53b4680f | 811 | const struct sr_channel_group *cg) |
28a35d8a | 812 | { |
0e1357e8 | 813 | struct dev_context *devc; |
99965709 | 814 | |
53b4680f | 815 | (void)cg; |
8f996b89 | 816 | |
fb2e6de7 BV |
817 | if (!sdi) |
818 | return SR_ERR; | |
819 | devc = sdi->priv; | |
820 | ||
584560f1 | 821 | switch (key) { |
123e1313 | 822 | case SR_CONF_SAMPLERATE: |
fb2e6de7 BV |
823 | *data = g_variant_new_uint64(devc->cur_samplerate); |
824 | break; | |
825 | case SR_CONF_LIMIT_MSEC: | |
826 | *data = g_variant_new_uint64(devc->limit_msec); | |
827 | break; | |
828 | case SR_CONF_CAPTURE_RATIO: | |
829 | *data = g_variant_new_uint64(devc->capture_ratio); | |
28a35d8a | 830 | break; |
d7bbecfd | 831 | default: |
bd6fbf62 | 832 | return SR_ERR_NA; |
28a35d8a HE |
833 | } |
834 | ||
41479605 | 835 | return SR_OK; |
28a35d8a HE |
836 | } |
837 | ||
584560f1 | 838 | static int config_set(uint32_t key, GVariant *data, const struct sr_dev_inst *sdi, |
53b4680f | 839 | const struct sr_channel_group *cg) |
28a35d8a | 840 | { |
0e1357e8 | 841 | struct dev_context *devc; |
6b2d3385 BV |
842 | uint64_t tmp; |
843 | int ret; | |
f6564c8d | 844 | |
53b4680f | 845 | (void)cg; |
8f996b89 | 846 | |
e73ffd42 BV |
847 | if (sdi->status != SR_ST_ACTIVE) |
848 | return SR_ERR_DEV_CLOSED; | |
849 | ||
0e1357e8 | 850 | devc = sdi->priv; |
99965709 | 851 | |
6b2d3385 | 852 | ret = SR_OK; |
584560f1 | 853 | switch (key) { |
6868626b | 854 | case SR_CONF_SAMPLERATE: |
2c9c0df8 | 855 | ret = set_samplerate(sdi, g_variant_get_uint64(data)); |
6868626b BV |
856 | break; |
857 | case SR_CONF_LIMIT_MSEC: | |
6b2d3385 BV |
858 | tmp = g_variant_get_uint64(data); |
859 | if (tmp > 0) | |
860 | devc->limit_msec = g_variant_get_uint64(data); | |
94ba4bd6 | 861 | else |
e46b8fb1 | 862 | ret = SR_ERR; |
6868626b BV |
863 | break; |
864 | case SR_CONF_LIMIT_SAMPLES: | |
6b2d3385 BV |
865 | tmp = g_variant_get_uint64(data); |
866 | devc->limit_msec = tmp * 1000 / devc->cur_samplerate; | |
6868626b BV |
867 | break; |
868 | case SR_CONF_CAPTURE_RATIO: | |
6b2d3385 BV |
869 | tmp = g_variant_get_uint64(data); |
870 | if (tmp <= 100) | |
871 | devc->capture_ratio = tmp; | |
94ba4bd6 | 872 | else |
6b2d3385 | 873 | ret = SR_ERR; |
6868626b BV |
874 | break; |
875 | default: | |
bd6fbf62 | 876 | ret = SR_ERR_NA; |
28a35d8a HE |
877 | } |
878 | ||
879 | return ret; | |
880 | } | |
881 | ||
584560f1 | 882 | static int config_list(uint32_t key, GVariant **data, const struct sr_dev_inst *sdi, |
53b4680f | 883 | const struct sr_channel_group *cg) |
a1c743fc | 884 | { |
2c9c0df8 BV |
885 | GVariant *gvar; |
886 | GVariantBuilder gvb; | |
a1c743fc BV |
887 | |
888 | (void)sdi; | |
53b4680f | 889 | (void)cg; |
a1c743fc BV |
890 | |
891 | switch (key) { | |
9a6517d1 | 892 | case SR_CONF_DEVICE_OPTIONS: |
e7ba5a99 BV |
893 | if (!sdi) |
894 | *data = g_variant_new_fixed_array(G_VARIANT_TYPE_UINT32, | |
2ff11e50 | 895 | drvopts, ARRAY_SIZE(drvopts), sizeof(uint32_t)); |
e7ba5a99 BV |
896 | else |
897 | *data = g_variant_new_fixed_array(G_VARIANT_TYPE_UINT32, | |
2ff11e50 | 898 | devopts, ARRAY_SIZE(devopts), sizeof(uint32_t)); |
9a6517d1 | 899 | break; |
a1c743fc | 900 | case SR_CONF_SAMPLERATE: |
2c9c0df8 BV |
901 | g_variant_builder_init(&gvb, G_VARIANT_TYPE("a{sv}")); |
902 | gvar = g_variant_new_fixed_array(G_VARIANT_TYPE("t"), samplerates, | |
903 | ARRAY_SIZE(samplerates), sizeof(uint64_t)); | |
904 | g_variant_builder_add(&gvb, "{sv}", "samplerates", gvar); | |
905 | *data = g_variant_builder_end(&gvb); | |
a1c743fc | 906 | break; |
39c64c6a | 907 | case SR_CONF_TRIGGER_MATCH: |
af945a66 | 908 | *data = g_variant_new_fixed_array(G_VARIANT_TYPE_INT32, |
39c64c6a BV |
909 | trigger_matches, ARRAY_SIZE(trigger_matches), |
910 | sizeof(int32_t)); | |
c50277a6 | 911 | break; |
a1c743fc | 912 | default: |
bd6fbf62 | 913 | return SR_ERR_NA; |
a1c743fc BV |
914 | } |
915 | ||
916 | return SR_OK; | |
917 | } | |
918 | ||
36b1c8e6 | 919 | /* Software trigger to determine exact trigger position. */ |
5fc01191 | 920 | static int get_trigger_offset(uint8_t *samples, uint16_t last_sample, |
36b1c8e6 HE |
921 | struct sigma_trigger *t) |
922 | { | |
923 | int i; | |
5fc01191 | 924 | uint16_t sample = 0; |
36b1c8e6 HE |
925 | |
926 | for (i = 0; i < 8; ++i) { | |
927 | if (i > 0) | |
5fc01191 MV |
928 | last_sample = sample; |
929 | sample = samples[2 * i] | (samples[2 * i + 1] << 8); | |
36b1c8e6 HE |
930 | |
931 | /* Simple triggers. */ | |
5fc01191 | 932 | if ((sample & t->simplemask) != t->simplevalue) |
36b1c8e6 HE |
933 | continue; |
934 | ||
935 | /* Rising edge. */ | |
5fc01191 MV |
936 | if (((last_sample & t->risingmask) != 0) || |
937 | ((sample & t->risingmask) != t->risingmask)) | |
36b1c8e6 HE |
938 | continue; |
939 | ||
940 | /* Falling edge. */ | |
bdfc7a89 | 941 | if ((last_sample & t->fallingmask) != t->fallingmask || |
5fc01191 | 942 | (sample & t->fallingmask) != 0) |
36b1c8e6 HE |
943 | continue; |
944 | ||
945 | break; | |
946 | } | |
947 | ||
948 | /* If we did not match, return original trigger pos. */ | |
949 | return i & 0x7; | |
950 | } | |
951 | ||
3513d965 MV |
952 | |
953 | /* | |
954 | * Return the timestamp of "DRAM cluster". | |
955 | */ | |
956 | static uint16_t sigma_dram_cluster_ts(struct sigma_dram_cluster *cluster) | |
957 | { | |
958 | return (cluster->timestamp_hi << 8) | cluster->timestamp_lo; | |
959 | } | |
960 | ||
23239b5c MV |
961 | static void sigma_decode_dram_cluster(struct sigma_dram_cluster *dram_cluster, |
962 | unsigned int events_in_cluster, | |
1e23158b | 963 | unsigned int triggered, |
23239b5c MV |
964 | struct sr_dev_inst *sdi) |
965 | { | |
966 | struct dev_context *devc = sdi->priv; | |
967 | struct sigma_state *ss = &devc->state; | |
968 | struct sr_datafeed_packet packet; | |
969 | struct sr_datafeed_logic logic; | |
970 | uint16_t tsdiff, ts; | |
971 | uint8_t samples[2048]; | |
972 | unsigned int i; | |
973 | ||
23239b5c MV |
974 | ts = sigma_dram_cluster_ts(dram_cluster); |
975 | tsdiff = ts - ss->lastts; | |
976 | ss->lastts = ts; | |
977 | ||
978 | packet.type = SR_DF_LOGIC; | |
979 | packet.payload = &logic; | |
980 | logic.unitsize = 2; | |
981 | logic.data = samples; | |
982 | ||
983 | /* | |
984 | * First of all, send Sigrok a copy of the last sample from | |
985 | * previous cluster as many times as needed to make up for | |
986 | * the differential characteristics of data we get from the | |
987 | * Sigma. Sigrok needs one sample of data per period. | |
988 | * | |
989 | * One DRAM cluster contains a timestamp and seven samples, | |
990 | * the units of timestamp are "devc->period_ps" , the first | |
991 | * sample in the cluster happens at the time of the timestamp | |
992 | * and the remaining samples happen at timestamp +1...+6 . | |
993 | */ | |
994 | for (ts = 0; ts < tsdiff - (EVENTS_PER_CLUSTER - 1); ts++) { | |
995 | i = ts % 1024; | |
996 | samples[2 * i + 0] = ss->lastsample & 0xff; | |
997 | samples[2 * i + 1] = ss->lastsample >> 8; | |
998 | ||
999 | /* | |
1000 | * If we have 1024 samples ready or we're at the | |
1001 | * end of submitting the padding samples, submit | |
1002 | * the packet to Sigrok. | |
1003 | */ | |
1004 | if ((i == 1023) || (ts == (tsdiff - EVENTS_PER_CLUSTER))) { | |
1005 | logic.length = (i + 1) * logic.unitsize; | |
102f1239 | 1006 | sr_session_send(sdi, &packet); |
23239b5c MV |
1007 | } |
1008 | } | |
1009 | ||
1010 | /* | |
1011 | * Parse the samples in current cluster and prepare them | |
1012 | * to be submitted to Sigrok. | |
1013 | */ | |
1014 | for (i = 0; i < events_in_cluster; i++) { | |
1015 | samples[2 * i + 1] = dram_cluster->samples[i].sample_lo; | |
1016 | samples[2 * i + 0] = dram_cluster->samples[i].sample_hi; | |
1017 | } | |
1018 | ||
1019 | /* Send data up to trigger point (if triggered). */ | |
1020 | int trigger_offset = 0; | |
1e23158b | 1021 | if (triggered) { |
23239b5c MV |
1022 | /* |
1023 | * Trigger is not always accurate to sample because of | |
1024 | * pipeline delay. However, it always triggers before | |
1025 | * the actual event. We therefore look at the next | |
1026 | * samples to pinpoint the exact position of the trigger. | |
1027 | */ | |
1028 | trigger_offset = get_trigger_offset(samples, | |
1029 | ss->lastsample, &devc->trigger); | |
1030 | ||
1031 | if (trigger_offset > 0) { | |
1032 | packet.type = SR_DF_LOGIC; | |
1033 | logic.length = trigger_offset * logic.unitsize; | |
102f1239 | 1034 | sr_session_send(sdi, &packet); |
23239b5c MV |
1035 | events_in_cluster -= trigger_offset; |
1036 | } | |
1037 | ||
1038 | /* Only send trigger if explicitly enabled. */ | |
1039 | if (devc->use_triggers) { | |
1040 | packet.type = SR_DF_TRIGGER; | |
102f1239 | 1041 | sr_session_send(sdi, &packet); |
23239b5c MV |
1042 | } |
1043 | } | |
1044 | ||
1045 | if (events_in_cluster > 0) { | |
1046 | packet.type = SR_DF_LOGIC; | |
1047 | logic.length = events_in_cluster * logic.unitsize; | |
1048 | logic.data = samples + (trigger_offset * logic.unitsize); | |
102f1239 | 1049 | sr_session_send(sdi, &packet); |
23239b5c MV |
1050 | } |
1051 | ||
1052 | ss->lastsample = | |
1053 | samples[2 * (events_in_cluster - 1) + 0] | | |
1054 | (samples[2 * (events_in_cluster - 1) + 1] << 8); | |
1055 | ||
1056 | } | |
1057 | ||
28a35d8a | 1058 | /* |
fefa1800 UH |
1059 | * Decode chunk of 1024 bytes, 64 clusters, 7 events per cluster. |
1060 | * Each event is 20ns apart, and can contain multiple samples. | |
f78898e9 HE |
1061 | * |
1062 | * For 200 MHz, events contain 4 samples for each channel, spread 5 ns apart. | |
1063 | * For 100 MHz, events contain 2 samples for each channel, spread 10 ns apart. | |
1064 | * For 50 MHz and below, events contain one sample for each channel, | |
1065 | * spread 20 ns apart. | |
28a35d8a | 1066 | */ |
1e23158b MV |
1067 | static int decode_chunk_ts(struct sigma_dram_line *dram_line, |
1068 | uint16_t events_in_line, | |
1069 | uint32_t trigger_event, | |
102f1239 | 1070 | struct sr_dev_inst *sdi) |
28a35d8a | 1071 | { |
3628074d | 1072 | struct sigma_dram_cluster *dram_cluster; |
0e1357e8 | 1073 | struct dev_context *devc = sdi->priv; |
5fc01191 MV |
1074 | unsigned int clusters_in_line = |
1075 | (events_in_line + (EVENTS_PER_CLUSTER - 1)) / EVENTS_PER_CLUSTER; | |
1076 | unsigned int events_in_cluster; | |
23239b5c | 1077 | unsigned int i; |
1e23158b | 1078 | uint32_t trigger_cluster = ~0, triggered = 0; |
ee492173 | 1079 | |
4ae1f451 | 1080 | /* Check if trigger is in this chunk. */ |
1e23158b MV |
1081 | if (trigger_event < (64 * 7)) { |
1082 | if (devc->cur_samplerate <= SR_MHZ(50)) { | |
1083 | trigger_event -= MIN(EVENTS_PER_CLUSTER - 1, | |
1084 | trigger_event); | |
1085 | } | |
57bbf56b | 1086 | |
ee492173 | 1087 | /* Find in which cluster the trigger occured. */ |
1e23158b | 1088 | trigger_cluster = trigger_event / EVENTS_PER_CLUSTER; |
ee492173 | 1089 | } |
28a35d8a | 1090 | |
5fc01191 MV |
1091 | /* For each full DRAM cluster. */ |
1092 | for (i = 0; i < clusters_in_line; i++) { | |
3628074d | 1093 | dram_cluster = &dram_line->cluster[i]; |
5fc01191 | 1094 | |
5fc01191 | 1095 | /* The last cluster might not be full. */ |
23239b5c MV |
1096 | if ((i == clusters_in_line - 1) && |
1097 | (events_in_line % EVENTS_PER_CLUSTER)) { | |
5fc01191 | 1098 | events_in_cluster = events_in_line % EVENTS_PER_CLUSTER; |
23239b5c | 1099 | } else { |
5fc01191 | 1100 | events_in_cluster = EVENTS_PER_CLUSTER; |
abda62ce | 1101 | } |
ee492173 | 1102 | |
1e23158b MV |
1103 | triggered = (i == trigger_cluster); |
1104 | sigma_decode_dram_cluster(dram_cluster, events_in_cluster, | |
1105 | triggered, sdi); | |
28a35d8a HE |
1106 | } |
1107 | ||
e46b8fb1 | 1108 | return SR_OK; |
28a35d8a HE |
1109 | } |
1110 | ||
6057d9fa | 1111 | static int download_capture(struct sr_dev_inst *sdi) |
28a35d8a | 1112 | { |
6057d9fa | 1113 | struct dev_context *devc = sdi->priv; |
e15e5873 | 1114 | const uint32_t chunks_per_read = 32; |
fd830beb | 1115 | struct sigma_dram_line *dram_line; |
c6648b66 | 1116 | int bufsz; |
462fe786 | 1117 | uint32_t stoppos, triggerpos; |
6057d9fa MV |
1118 | struct sr_datafeed_packet packet; |
1119 | uint8_t modestatus; | |
1120 | ||
c6648b66 MV |
1121 | uint32_t i; |
1122 | uint32_t dl_lines_total, dl_lines_curr, dl_lines_done; | |
46641fac | 1123 | uint32_t dl_events_in_line = 64 * 7; |
1e23158b | 1124 | uint32_t trg_line = ~0, trg_event = ~0; |
c6648b66 | 1125 | |
fd830beb MV |
1126 | dram_line = g_try_malloc0(chunks_per_read * sizeof(*dram_line)); |
1127 | if (!dram_line) | |
1128 | return FALSE; | |
1129 | ||
6868626b BV |
1130 | sr_info("Downloading sample data."); |
1131 | ||
6057d9fa MV |
1132 | /* Stop acquisition. */ |
1133 | sigma_set_register(WRITE_MODE, 0x11, devc); | |
1134 | ||
1135 | /* Set SDRAM Read Enable. */ | |
1136 | sigma_set_register(WRITE_MODE, 0x02, devc); | |
1137 | ||
1138 | /* Get the current position. */ | |
462fe786 | 1139 | sigma_read_pos(&stoppos, &triggerpos, devc); |
6057d9fa MV |
1140 | |
1141 | /* Check if trigger has fired. */ | |
1142 | modestatus = sigma_get_register(READ_MODE, devc); | |
1e23158b | 1143 | if (modestatus & 0x20) { |
c6648b66 | 1144 | trg_line = triggerpos >> 9; |
1e23158b MV |
1145 | trg_event = triggerpos & 0x1ff; |
1146 | } | |
6057d9fa | 1147 | |
c6648b66 MV |
1148 | /* |
1149 | * Determine how many 1024b "DRAM lines" do we need to read from the | |
1150 | * Sigma so we have a complete set of samples. Note that the last | |
1151 | * line can be only partial, containing less than 64 clusters. | |
1152 | */ | |
1153 | dl_lines_total = (stoppos >> 9) + 1; | |
6868626b | 1154 | |
c6648b66 | 1155 | dl_lines_done = 0; |
6868626b | 1156 | |
c6648b66 MV |
1157 | while (dl_lines_total > dl_lines_done) { |
1158 | /* We can download only up-to 32 DRAM lines in one go! */ | |
1159 | dl_lines_curr = MIN(chunks_per_read, dl_lines_total); | |
6868626b | 1160 | |
f41a4cae MV |
1161 | bufsz = sigma_read_dram(dl_lines_done, dl_lines_curr, |
1162 | (uint8_t *)dram_line, devc); | |
c6648b66 MV |
1163 | /* TODO: Check bufsz. For now, just avoid compiler warnings. */ |
1164 | (void)bufsz; | |
6868626b | 1165 | |
c6648b66 MV |
1166 | /* This is the first DRAM line, so find the initial timestamp. */ |
1167 | if (dl_lines_done == 0) { | |
3513d965 MV |
1168 | devc->state.lastts = |
1169 | sigma_dram_cluster_ts(&dram_line[0].cluster[0]); | |
c6648b66 | 1170 | devc->state.lastsample = 0; |
6868626b BV |
1171 | } |
1172 | ||
c6648b66 | 1173 | for (i = 0; i < dl_lines_curr; i++) { |
1e23158b | 1174 | uint32_t trigger_event = ~0; |
c6648b66 MV |
1175 | /* The last "DRAM line" can be only partially full. */ |
1176 | if (dl_lines_done + i == dl_lines_total - 1) | |
46641fac | 1177 | dl_events_in_line = stoppos & 0x1ff; |
c6648b66 | 1178 | |
e69ad48e | 1179 | /* Test if the trigger happened on this line. */ |
c6648b66 | 1180 | if (dl_lines_done + i == trg_line) |
1e23158b | 1181 | trigger_event = trg_event; |
e69ad48e | 1182 | |
1e23158b MV |
1183 | decode_chunk_ts(dram_line + i, dl_events_in_line, |
1184 | trigger_event, sdi); | |
c6648b66 | 1185 | } |
6868626b | 1186 | |
c6648b66 | 1187 | dl_lines_done += dl_lines_curr; |
6868626b BV |
1188 | } |
1189 | ||
6057d9fa MV |
1190 | /* All done. */ |
1191 | packet.type = SR_DF_END; | |
1192 | sr_session_send(sdi, &packet); | |
1193 | ||
1194 | dev_acquisition_stop(sdi, sdi); | |
1195 | ||
fd830beb MV |
1196 | g_free(dram_line); |
1197 | ||
6057d9fa | 1198 | return TRUE; |
6868626b BV |
1199 | } |
1200 | ||
d4051930 MV |
1201 | /* |
1202 | * Handle the Sigma when in CAPTURE mode. This function checks: | |
1203 | * - Sampling time ended | |
1204 | * - DRAM capacity overflow | |
1205 | * This function triggers download of the samples from Sigma | |
1206 | * in case either of the above conditions is true. | |
1207 | */ | |
1208 | static int sigma_capture_mode(struct sr_dev_inst *sdi) | |
6868626b | 1209 | { |
d4051930 MV |
1210 | struct dev_context *devc = sdi->priv; |
1211 | ||
94ba4bd6 | 1212 | uint64_t running_msec; |
28a35d8a | 1213 | struct timeval tv; |
28a35d8a | 1214 | |
00c86508 | 1215 | uint32_t stoppos, triggerpos; |
28a35d8a | 1216 | |
00c86508 | 1217 | /* Check if the selected sampling duration passed. */ |
d4051930 MV |
1218 | gettimeofday(&tv, 0); |
1219 | running_msec = (tv.tv_sec - devc->start_tv.tv_sec) * 1000 + | |
00c86508 MV |
1220 | (tv.tv_usec - devc->start_tv.tv_usec) / 1000; |
1221 | if (running_msec >= devc->limit_msec) | |
6057d9fa | 1222 | return download_capture(sdi); |
00c86508 MV |
1223 | |
1224 | /* Get the position in DRAM to which the FPGA is writing now. */ | |
1225 | sigma_read_pos(&stoppos, &triggerpos, devc); | |
1226 | /* Test if DRAM is full and if so, download the data. */ | |
1227 | if ((stoppos >> 9) == 32767) | |
6057d9fa | 1228 | return download_capture(sdi); |
28a35d8a | 1229 | |
d4051930 MV |
1230 | return TRUE; |
1231 | } | |
28a35d8a | 1232 | |
d4051930 MV |
1233 | static int receive_data(int fd, int revents, void *cb_data) |
1234 | { | |
1235 | struct sr_dev_inst *sdi; | |
1236 | struct dev_context *devc; | |
88c51afe | 1237 | |
d4051930 MV |
1238 | (void)fd; |
1239 | (void)revents; | |
88c51afe | 1240 | |
d4051930 MV |
1241 | sdi = cb_data; |
1242 | devc = sdi->priv; | |
1243 | ||
1244 | if (devc->state.state == SIGMA_IDLE) | |
1245 | return TRUE; | |
1246 | ||
1247 | if (devc->state.state == SIGMA_CAPTURE) | |
1248 | return sigma_capture_mode(sdi); | |
28a35d8a | 1249 | |
28a35d8a HE |
1250 | return TRUE; |
1251 | } | |
1252 | ||
c53d793f HE |
1253 | /* Build a LUT entry used by the trigger functions. */ |
1254 | static void build_lut_entry(uint16_t value, uint16_t mask, uint16_t *entry) | |
ee492173 HE |
1255 | { |
1256 | int i, j, k, bit; | |
1257 | ||
ba7dd8bb | 1258 | /* For each quad channel. */ |
ee492173 | 1259 | for (i = 0; i < 4; ++i) { |
c53d793f | 1260 | entry[i] = 0xffff; |
ee492173 | 1261 | |
f758d074 | 1262 | /* For each bit in LUT. */ |
ee492173 HE |
1263 | for (j = 0; j < 16; ++j) |
1264 | ||
ba7dd8bb | 1265 | /* For each channel in quad. */ |
ee492173 HE |
1266 | for (k = 0; k < 4; ++k) { |
1267 | bit = 1 << (i * 4 + k); | |
1268 | ||
c53d793f HE |
1269 | /* Set bit in entry */ |
1270 | if ((mask & bit) && | |
1271 | ((!(value & bit)) != | |
4ae1f451 | 1272 | (!(j & (1 << k))))) |
c53d793f | 1273 | entry[i] &= ~(1 << j); |
ee492173 HE |
1274 | } |
1275 | } | |
c53d793f | 1276 | } |
ee492173 | 1277 | |
c53d793f HE |
1278 | /* Add a logical function to LUT mask. */ |
1279 | static void add_trigger_function(enum triggerop oper, enum triggerfunc func, | |
1280 | int index, int neg, uint16_t *mask) | |
1281 | { | |
1282 | int i, j; | |
1283 | int x[2][2], tmp, a, b, aset, bset, rset; | |
1284 | ||
1285 | memset(x, 0, 4 * sizeof(int)); | |
1286 | ||
1287 | /* Trigger detect condition. */ | |
1288 | switch (oper) { | |
1289 | case OP_LEVEL: | |
1290 | x[0][1] = 1; | |
1291 | x[1][1] = 1; | |
1292 | break; | |
1293 | case OP_NOT: | |
1294 | x[0][0] = 1; | |
1295 | x[1][0] = 1; | |
1296 | break; | |
1297 | case OP_RISE: | |
1298 | x[0][1] = 1; | |
1299 | break; | |
1300 | case OP_FALL: | |
1301 | x[1][0] = 1; | |
1302 | break; | |
1303 | case OP_RISEFALL: | |
1304 | x[0][1] = 1; | |
1305 | x[1][0] = 1; | |
1306 | break; | |
1307 | case OP_NOTRISE: | |
1308 | x[1][1] = 1; | |
1309 | x[0][0] = 1; | |
1310 | x[1][0] = 1; | |
1311 | break; | |
1312 | case OP_NOTFALL: | |
1313 | x[1][1] = 1; | |
1314 | x[0][0] = 1; | |
1315 | x[0][1] = 1; | |
1316 | break; | |
1317 | case OP_NOTRISEFALL: | |
1318 | x[1][1] = 1; | |
1319 | x[0][0] = 1; | |
1320 | break; | |
1321 | } | |
1322 | ||
1323 | /* Transpose if neg is set. */ | |
1324 | if (neg) { | |
ea9cfed7 | 1325 | for (i = 0; i < 2; ++i) { |
c53d793f HE |
1326 | for (j = 0; j < 2; ++j) { |
1327 | tmp = x[i][j]; | |
1328 | x[i][j] = x[1-i][1-j]; | |
1329 | x[1-i][1-j] = tmp; | |
1330 | } | |
ea9cfed7 | 1331 | } |
c53d793f HE |
1332 | } |
1333 | ||
1334 | /* Update mask with function. */ | |
1335 | for (i = 0; i < 16; ++i) { | |
1336 | a = (i >> (2 * index + 0)) & 1; | |
1337 | b = (i >> (2 * index + 1)) & 1; | |
1338 | ||
1339 | aset = (*mask >> i) & 1; | |
1340 | bset = x[b][a]; | |
1341 | ||
382cb19f | 1342 | rset = 0; |
c53d793f HE |
1343 | if (func == FUNC_AND || func == FUNC_NAND) |
1344 | rset = aset & bset; | |
1345 | else if (func == FUNC_OR || func == FUNC_NOR) | |
1346 | rset = aset | bset; | |
1347 | else if (func == FUNC_XOR || func == FUNC_NXOR) | |
1348 | rset = aset ^ bset; | |
1349 | ||
1350 | if (func == FUNC_NAND || func == FUNC_NOR || func == FUNC_NXOR) | |
1351 | rset = !rset; | |
1352 | ||
1353 | *mask &= ~(1 << i); | |
1354 | ||
1355 | if (rset) | |
1356 | *mask |= 1 << i; | |
1357 | } | |
1358 | } | |
1359 | ||
1360 | /* | |
1361 | * Build trigger LUTs used by 50 MHz and lower sample rates for supporting | |
1362 | * simple pin change and state triggers. Only two transitions (rise/fall) can be | |
1363 | * set at any time, but a full mask and value can be set (0/1). | |
1364 | */ | |
0e1357e8 | 1365 | static int build_basic_trigger(struct triggerlut *lut, struct dev_context *devc) |
c53d793f HE |
1366 | { |
1367 | int i,j; | |
4ae1f451 | 1368 | uint16_t masks[2] = { 0, 0 }; |
c53d793f HE |
1369 | |
1370 | memset(lut, 0, sizeof(struct triggerlut)); | |
1371 | ||
1372 | /* Contant for simple triggers. */ | |
1373 | lut->m4 = 0xa000; | |
1374 | ||
1375 | /* Value/mask trigger support. */ | |
0e1357e8 | 1376 | build_lut_entry(devc->trigger.simplevalue, devc->trigger.simplemask, |
99965709 | 1377 | lut->m2d); |
c53d793f HE |
1378 | |
1379 | /* Rise/fall trigger support. */ | |
1380 | for (i = 0, j = 0; i < 16; ++i) { | |
0e1357e8 BV |
1381 | if (devc->trigger.risingmask & (1 << i) || |
1382 | devc->trigger.fallingmask & (1 << i)) | |
c53d793f HE |
1383 | masks[j++] = 1 << i; |
1384 | } | |
1385 | ||
1386 | build_lut_entry(masks[0], masks[0], lut->m0d); | |
1387 | build_lut_entry(masks[1], masks[1], lut->m1d); | |
1388 | ||
1389 | /* Add glue logic */ | |
1390 | if (masks[0] || masks[1]) { | |
1391 | /* Transition trigger. */ | |
0e1357e8 | 1392 | if (masks[0] & devc->trigger.risingmask) |
c53d793f | 1393 | add_trigger_function(OP_RISE, FUNC_OR, 0, 0, &lut->m3); |
0e1357e8 | 1394 | if (masks[0] & devc->trigger.fallingmask) |
c53d793f | 1395 | add_trigger_function(OP_FALL, FUNC_OR, 0, 0, &lut->m3); |
0e1357e8 | 1396 | if (masks[1] & devc->trigger.risingmask) |
c53d793f | 1397 | add_trigger_function(OP_RISE, FUNC_OR, 1, 0, &lut->m3); |
0e1357e8 | 1398 | if (masks[1] & devc->trigger.fallingmask) |
c53d793f HE |
1399 | add_trigger_function(OP_FALL, FUNC_OR, 1, 0, &lut->m3); |
1400 | } else { | |
1401 | /* Only value/mask trigger. */ | |
1402 | lut->m3 = 0xffff; | |
1403 | } | |
ee492173 | 1404 | |
c53d793f | 1405 | /* Triggertype: event. */ |
ee492173 HE |
1406 | lut->params.selres = 3; |
1407 | ||
e46b8fb1 | 1408 | return SR_OK; |
ee492173 HE |
1409 | } |
1410 | ||
6078d2c9 | 1411 | static int dev_acquisition_start(const struct sr_dev_inst *sdi, void *cb_data) |
28a35d8a | 1412 | { |
0e1357e8 | 1413 | struct dev_context *devc; |
9ddb2a12 | 1414 | struct clockselect_50 clockselect; |
82957b65 | 1415 | int frac, triggerpin, ret; |
f4abaa9f | 1416 | uint8_t triggerselect = 0; |
57bbf56b | 1417 | struct triggerinout triggerinout_conf; |
ee492173 | 1418 | struct triggerlut lut; |
28a35d8a | 1419 | |
e73ffd42 BV |
1420 | if (sdi->status != SR_ST_ACTIVE) |
1421 | return SR_ERR_DEV_CLOSED; | |
1422 | ||
0e1357e8 | 1423 | devc = sdi->priv; |
28a35d8a | 1424 | |
39c64c6a BV |
1425 | if (convert_trigger(sdi) != SR_OK) { |
1426 | sr_err("Failed to configure triggers."); | |
014359e3 BV |
1427 | return SR_ERR; |
1428 | } | |
1429 | ||
ea9cfed7 | 1430 | /* If the samplerate has not been set, default to 200 kHz. */ |
0e1357e8 | 1431 | if (devc->cur_firmware == -1) { |
82957b65 UH |
1432 | if ((ret = set_samplerate(sdi, SR_KHZ(200))) != SR_OK) |
1433 | return ret; | |
1434 | } | |
e8397563 | 1435 | |
eec5275e | 1436 | /* Enter trigger programming mode. */ |
0e1357e8 | 1437 | sigma_set_register(WRITE_TRIGGER_SELECT1, 0x20, devc); |
28a35d8a | 1438 | |
eec5275e | 1439 | /* 100 and 200 MHz mode. */ |
0e1357e8 BV |
1440 | if (devc->cur_samplerate >= SR_MHZ(100)) { |
1441 | sigma_set_register(WRITE_TRIGGER_SELECT1, 0x81, devc); | |
57bbf56b | 1442 | |
a42aec7f HE |
1443 | /* Find which pin to trigger on from mask. */ |
1444 | for (triggerpin = 0; triggerpin < 8; ++triggerpin) | |
0e1357e8 | 1445 | if ((devc->trigger.risingmask | devc->trigger.fallingmask) & |
a42aec7f HE |
1446 | (1 << triggerpin)) |
1447 | break; | |
1448 | ||
1449 | /* Set trigger pin and light LED on trigger. */ | |
1450 | triggerselect = (1 << LEDSEL1) | (triggerpin & 0x7); | |
1451 | ||
1452 | /* Default rising edge. */ | |
0e1357e8 | 1453 | if (devc->trigger.fallingmask) |
a42aec7f | 1454 | triggerselect |= 1 << 3; |
57bbf56b | 1455 | |
eec5275e | 1456 | /* All other modes. */ |
0e1357e8 BV |
1457 | } else if (devc->cur_samplerate <= SR_MHZ(50)) { |
1458 | build_basic_trigger(&lut, devc); | |
ee492173 | 1459 | |
0e1357e8 | 1460 | sigma_write_trigger_lut(&lut, devc); |
57bbf56b HE |
1461 | |
1462 | triggerselect = (1 << LEDSEL1) | (1 << LEDSEL0); | |
1463 | } | |
1464 | ||
eec5275e | 1465 | /* Setup trigger in and out pins to default values. */ |
57bbf56b HE |
1466 | memset(&triggerinout_conf, 0, sizeof(struct triggerinout)); |
1467 | triggerinout_conf.trgout_bytrigger = 1; | |
1468 | triggerinout_conf.trgout_enable = 1; | |
1469 | ||
28a35d8a | 1470 | sigma_write_register(WRITE_TRIGGER_OPTION, |
57bbf56b | 1471 | (uint8_t *) &triggerinout_conf, |
0e1357e8 | 1472 | sizeof(struct triggerinout), devc); |
28a35d8a | 1473 | |
eec5275e | 1474 | /* Go back to normal mode. */ |
0e1357e8 | 1475 | sigma_set_register(WRITE_TRIGGER_SELECT1, triggerselect, devc); |
28a35d8a | 1476 | |
edca2c5c | 1477 | /* Set clock select register. */ |
0e1357e8 | 1478 | if (devc->cur_samplerate == SR_MHZ(200)) |
ba7dd8bb | 1479 | /* Enable 4 channels. */ |
0e1357e8 BV |
1480 | sigma_set_register(WRITE_CLOCK_SELECT, 0xf0, devc); |
1481 | else if (devc->cur_samplerate == SR_MHZ(100)) | |
ba7dd8bb | 1482 | /* Enable 8 channels. */ |
0e1357e8 | 1483 | sigma_set_register(WRITE_CLOCK_SELECT, 0x00, devc); |
edca2c5c HE |
1484 | else { |
1485 | /* | |
9ddb2a12 | 1486 | * 50 MHz mode (or fraction thereof). Any fraction down to |
eec5275e | 1487 | * 50 MHz / 256 can be used, but is not supported by sigrok API. |
edca2c5c | 1488 | */ |
0e1357e8 | 1489 | frac = SR_MHZ(50) / devc->cur_samplerate - 1; |
edca2c5c | 1490 | |
9ddb2a12 UH |
1491 | clockselect.async = 0; |
1492 | clockselect.fraction = frac; | |
ba7dd8bb | 1493 | clockselect.disabled_channels = 0; |
edca2c5c HE |
1494 | |
1495 | sigma_write_register(WRITE_CLOCK_SELECT, | |
9ddb2a12 | 1496 | (uint8_t *) &clockselect, |
0e1357e8 | 1497 | sizeof(clockselect), devc); |
edca2c5c HE |
1498 | } |
1499 | ||
fefa1800 | 1500 | /* Setup maximum post trigger time. */ |
99965709 | 1501 | sigma_set_register(WRITE_POST_TRIGGER, |
0e1357e8 | 1502 | (devc->capture_ratio * 255) / 100, devc); |
28a35d8a | 1503 | |
eec5275e | 1504 | /* Start acqusition. */ |
0e1357e8 BV |
1505 | gettimeofday(&devc->start_tv, 0); |
1506 | sigma_set_register(WRITE_MODE, 0x0d, devc); | |
99965709 | 1507 | |
3e9b7f9c | 1508 | devc->cb_data = cb_data; |
28a35d8a | 1509 | |
3c36c403 | 1510 | /* Send header packet to the session bus. */ |
102f1239 | 1511 | std_session_send_df_header(sdi, LOG_PREFIX); |
f366e86c | 1512 | |
f366e86c | 1513 | /* Add capture source. */ |
102f1239 | 1514 | sr_session_source_add(sdi->session, 0, G_IO_IN, 10, receive_data, (void *)sdi); |
f366e86c | 1515 | |
0e1357e8 | 1516 | devc->state.state = SIGMA_CAPTURE; |
6aac7737 | 1517 | |
e46b8fb1 | 1518 | return SR_OK; |
28a35d8a HE |
1519 | } |
1520 | ||
6078d2c9 | 1521 | static int dev_acquisition_stop(struct sr_dev_inst *sdi, void *cb_data) |
28a35d8a | 1522 | { |
0e1357e8 | 1523 | struct dev_context *devc; |
6aac7737 | 1524 | |
3cd3a20b | 1525 | (void)cb_data; |
28a35d8a | 1526 | |
6868626b BV |
1527 | devc = sdi->priv; |
1528 | devc->state.state = SIGMA_IDLE; | |
6aac7737 | 1529 | |
102f1239 | 1530 | sr_session_source_remove(sdi->session, 0); |
3010f21c UH |
1531 | |
1532 | return SR_OK; | |
28a35d8a HE |
1533 | } |
1534 | ||
c09f0b57 | 1535 | SR_PRIV struct sr_dev_driver asix_sigma_driver_info = { |
e519ba86 | 1536 | .name = "asix-sigma", |
6352d030 | 1537 | .longname = "ASIX SIGMA/SIGMA2", |
e519ba86 | 1538 | .api_version = 1, |
6078d2c9 UH |
1539 | .init = init, |
1540 | .cleanup = cleanup, | |
1541 | .scan = scan, | |
1542 | .dev_list = dev_list, | |
3b412e3a | 1543 | .dev_clear = dev_clear, |
035a1078 BV |
1544 | .config_get = config_get, |
1545 | .config_set = config_set, | |
a1c743fc | 1546 | .config_list = config_list, |
6078d2c9 UH |
1547 | .dev_open = dev_open, |
1548 | .dev_close = dev_close, | |
1549 | .dev_acquisition_start = dev_acquisition_start, | |
1550 | .dev_acquisition_stop = dev_acquisition_stop, | |
0e1357e8 | 1551 | .priv = NULL, |
28a35d8a | 1552 | }; |