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Commit | Line | Data |
---|---|---|
28a35d8a | 1 | /* |
50985c20 | 2 | * This file is part of the libsigrok project. |
28a35d8a | 3 | * |
868501fa | 4 | * Copyright (C) 2010-2012 Håvard Espeland <gus@ping.uio.no>, |
911f1834 UH |
5 | * Copyright (C) 2010 Martin Stensgård <mastensg@ping.uio.no> |
6 | * Copyright (C) 2010 Carl Henrik Lunde <chlunde@ping.uio.no> | |
28a35d8a HE |
7 | * |
8 | * This program is free software: you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation, either version 3 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
20 | */ | |
21 | ||
911f1834 | 22 | /* |
6352d030 | 23 | * ASIX SIGMA/SIGMA2 logic analyzer driver |
911f1834 UH |
24 | */ |
25 | ||
3bbd9849 UH |
26 | #include <glib.h> |
27 | #include <glib/gstdio.h> | |
28a35d8a HE |
28 | #include <ftdi.h> |
29 | #include <string.h> | |
45c59c8b BV |
30 | #include "libsigrok.h" |
31 | #include "libsigrok-internal.h" | |
28a35d8a HE |
32 | #include "asix-sigma.h" |
33 | ||
34 | #define USB_VENDOR 0xa600 | |
35 | #define USB_PRODUCT 0xa000 | |
36 | #define USB_DESCRIPTION "ASIX SIGMA" | |
37 | #define USB_VENDOR_NAME "ASIX" | |
38 | #define USB_MODEL_NAME "SIGMA" | |
39 | #define USB_MODEL_VERSION "" | |
c50277a6 | 40 | #define TRIGGER_TYPE "rf10" |
464d12c7 | 41 | #define NUM_PROBES 16 |
28a35d8a | 42 | |
ed300b9f | 43 | SR_PRIV struct sr_dev_driver asix_sigma_driver_info; |
a873c594 | 44 | static struct sr_dev_driver *di = &asix_sigma_driver_info; |
6078d2c9 | 45 | static int dev_acquisition_stop(struct sr_dev_inst *sdi, void *cb_data); |
28a35d8a | 46 | |
2c9c0df8 | 47 | static const uint64_t samplerates[] = { |
59df0c77 UH |
48 | SR_KHZ(200), |
49 | SR_KHZ(250), | |
50 | SR_KHZ(500), | |
51 | SR_MHZ(1), | |
52 | SR_MHZ(5), | |
53 | SR_MHZ(10), | |
54 | SR_MHZ(25), | |
55 | SR_MHZ(50), | |
56 | SR_MHZ(100), | |
57 | SR_MHZ(200), | |
28a35d8a HE |
58 | }; |
59 | ||
d261dbbf UH |
60 | /* |
61 | * Probe numbers seem to go from 1-16, according to this image: | |
62 | * http://tools.asix.net/img/sigma_sigmacab_pins_720.jpg | |
63 | * (the cable has two additional GND pins, and a TI and TO pin) | |
64 | */ | |
c37d2b1b | 65 | static const char *probe_names[NUM_PROBES + 1] = { |
78693401 UH |
66 | "1", "2", "3", "4", "5", "6", "7", "8", |
67 | "9", "10", "11", "12", "13", "14", "15", "16", | |
464d12c7 KS |
68 | NULL, |
69 | }; | |
70 | ||
2c9c0df8 | 71 | static const int32_t hwcaps[] = { |
1953564a BV |
72 | SR_CONF_LOGIC_ANALYZER, |
73 | SR_CONF_SAMPLERATE, | |
74 | SR_CONF_CAPTURE_RATIO, | |
1953564a | 75 | SR_CONF_LIMIT_MSEC, |
28a35d8a HE |
76 | }; |
77 | ||
fefa1800 UH |
78 | /* Force the FPGA to reboot. */ |
79 | static uint8_t suicide[] = { | |
80 | 0x84, 0x84, 0x88, 0x84, 0x88, 0x84, 0x88, 0x84, | |
81 | }; | |
82 | ||
83 | /* Prepare to upload firmware (FPGA specific). */ | |
6078d2c9 | 84 | static uint8_t init_array[] = { |
fefa1800 UH |
85 | 0x03, 0x03, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, |
86 | }; | |
87 | ||
88 | /* Initialize the logic analyzer mode. */ | |
89 | static uint8_t logic_mode_start[] = { | |
90 | 0x00, 0x40, 0x0f, 0x25, 0x35, 0x40, | |
91 | 0x2a, 0x3a, 0x40, 0x03, 0x20, 0x38, | |
92 | }; | |
93 | ||
eec5275e | 94 | static const char *firmware_files[] = { |
a8116d76 HE |
95 | "asix-sigma-50.fw", /* 50 MHz, supports 8 bit fractions */ |
96 | "asix-sigma-100.fw", /* 100 MHz */ | |
97 | "asix-sigma-200.fw", /* 200 MHz */ | |
ed09fd07 | 98 | "asix-sigma-50sync.fw", /* Synchronous clock from pin */ |
a8116d76 | 99 | "asix-sigma-phasor.fw", /* Frequency counter */ |
f6564c8d HE |
100 | }; |
101 | ||
0e1357e8 | 102 | static int sigma_read(void *buf, size_t size, struct dev_context *devc) |
28a35d8a HE |
103 | { |
104 | int ret; | |
fefa1800 | 105 | |
0e1357e8 | 106 | ret = ftdi_read_data(&devc->ftdic, (unsigned char *)buf, size); |
28a35d8a | 107 | if (ret < 0) { |
47f4f073 | 108 | sr_err("ftdi_read_data failed: %s", |
0e1357e8 | 109 | ftdi_get_error_string(&devc->ftdic)); |
28a35d8a HE |
110 | } |
111 | ||
112 | return ret; | |
113 | } | |
114 | ||
0e1357e8 | 115 | static int sigma_write(void *buf, size_t size, struct dev_context *devc) |
28a35d8a HE |
116 | { |
117 | int ret; | |
fefa1800 | 118 | |
0e1357e8 | 119 | ret = ftdi_write_data(&devc->ftdic, (unsigned char *)buf, size); |
28a35d8a | 120 | if (ret < 0) { |
47f4f073 | 121 | sr_err("ftdi_write_data failed: %s", |
0e1357e8 | 122 | ftdi_get_error_string(&devc->ftdic)); |
fefa1800 | 123 | } else if ((size_t) ret != size) { |
47f4f073 | 124 | sr_err("ftdi_write_data did not complete write."); |
28a35d8a HE |
125 | } |
126 | ||
127 | return ret; | |
128 | } | |
129 | ||
99965709 | 130 | static int sigma_write_register(uint8_t reg, uint8_t *data, size_t len, |
0e1357e8 | 131 | struct dev_context *devc) |
28a35d8a HE |
132 | { |
133 | size_t i; | |
134 | uint8_t buf[len + 2]; | |
135 | int idx = 0; | |
136 | ||
137 | buf[idx++] = REG_ADDR_LOW | (reg & 0xf); | |
138 | buf[idx++] = REG_ADDR_HIGH | (reg >> 4); | |
139 | ||
fefa1800 | 140 | for (i = 0; i < len; ++i) { |
28a35d8a HE |
141 | buf[idx++] = REG_DATA_LOW | (data[i] & 0xf); |
142 | buf[idx++] = REG_DATA_HIGH_WRITE | (data[i] >> 4); | |
143 | } | |
144 | ||
0e1357e8 | 145 | return sigma_write(buf, idx, devc); |
28a35d8a HE |
146 | } |
147 | ||
0e1357e8 | 148 | static int sigma_set_register(uint8_t reg, uint8_t value, struct dev_context *devc) |
28a35d8a | 149 | { |
0e1357e8 | 150 | return sigma_write_register(reg, &value, 1, devc); |
28a35d8a HE |
151 | } |
152 | ||
99965709 | 153 | static int sigma_read_register(uint8_t reg, uint8_t *data, size_t len, |
0e1357e8 | 154 | struct dev_context *devc) |
28a35d8a HE |
155 | { |
156 | uint8_t buf[3]; | |
fefa1800 | 157 | |
28a35d8a HE |
158 | buf[0] = REG_ADDR_LOW | (reg & 0xf); |
159 | buf[1] = REG_ADDR_HIGH | (reg >> 4); | |
28a35d8a HE |
160 | buf[2] = REG_READ_ADDR; |
161 | ||
0e1357e8 | 162 | sigma_write(buf, sizeof(buf), devc); |
28a35d8a | 163 | |
0e1357e8 | 164 | return sigma_read(data, len, devc); |
28a35d8a HE |
165 | } |
166 | ||
0e1357e8 | 167 | static uint8_t sigma_get_register(uint8_t reg, struct dev_context *devc) |
28a35d8a HE |
168 | { |
169 | uint8_t value; | |
fefa1800 | 170 | |
0e1357e8 | 171 | if (1 != sigma_read_register(reg, &value, 1, devc)) { |
47f4f073 | 172 | sr_err("sigma_get_register: 1 byte expected"); |
28a35d8a HE |
173 | return 0; |
174 | } | |
175 | ||
176 | return value; | |
177 | } | |
178 | ||
99965709 | 179 | static int sigma_read_pos(uint32_t *stoppos, uint32_t *triggerpos, |
0e1357e8 | 180 | struct dev_context *devc) |
28a35d8a HE |
181 | { |
182 | uint8_t buf[] = { | |
183 | REG_ADDR_LOW | READ_TRIGGER_POS_LOW, | |
184 | ||
185 | REG_READ_ADDR | NEXT_REG, | |
186 | REG_READ_ADDR | NEXT_REG, | |
187 | REG_READ_ADDR | NEXT_REG, | |
188 | REG_READ_ADDR | NEXT_REG, | |
189 | REG_READ_ADDR | NEXT_REG, | |
190 | REG_READ_ADDR | NEXT_REG, | |
191 | }; | |
28a35d8a HE |
192 | uint8_t result[6]; |
193 | ||
0e1357e8 | 194 | sigma_write(buf, sizeof(buf), devc); |
28a35d8a | 195 | |
0e1357e8 | 196 | sigma_read(result, sizeof(result), devc); |
28a35d8a HE |
197 | |
198 | *triggerpos = result[0] | (result[1] << 8) | (result[2] << 16); | |
199 | *stoppos = result[3] | (result[4] << 8) | (result[5] << 16); | |
200 | ||
57bbf56b HE |
201 | /* Not really sure why this must be done, but according to spec. */ |
202 | if ((--*stoppos & 0x1ff) == 0x1ff) | |
203 | stoppos -= 64; | |
204 | ||
205 | if ((*--triggerpos & 0x1ff) == 0x1ff) | |
206 | triggerpos -= 64; | |
207 | ||
28a35d8a HE |
208 | return 1; |
209 | } | |
210 | ||
99965709 | 211 | static int sigma_read_dram(uint16_t startchunk, size_t numchunks, |
0e1357e8 | 212 | uint8_t *data, struct dev_context *devc) |
28a35d8a HE |
213 | { |
214 | size_t i; | |
215 | uint8_t buf[4096]; | |
216 | int idx = 0; | |
217 | ||
fefa1800 | 218 | /* Send the startchunk. Index start with 1. */ |
28a35d8a HE |
219 | buf[0] = startchunk >> 8; |
220 | buf[1] = startchunk & 0xff; | |
0e1357e8 | 221 | sigma_write_register(WRITE_MEMROW, buf, 2, devc); |
28a35d8a | 222 | |
fefa1800 | 223 | /* Read the DRAM. */ |
28a35d8a HE |
224 | buf[idx++] = REG_DRAM_BLOCK; |
225 | buf[idx++] = REG_DRAM_WAIT_ACK; | |
226 | ||
227 | for (i = 0; i < numchunks; ++i) { | |
fefa1800 UH |
228 | /* Alternate bit to copy from DRAM to cache. */ |
229 | if (i != (numchunks - 1)) | |
230 | buf[idx++] = REG_DRAM_BLOCK | (((i + 1) % 2) << 4); | |
28a35d8a HE |
231 | |
232 | buf[idx++] = REG_DRAM_BLOCK_DATA | ((i % 2) << 4); | |
233 | ||
fefa1800 | 234 | if (i != (numchunks - 1)) |
28a35d8a HE |
235 | buf[idx++] = REG_DRAM_WAIT_ACK; |
236 | } | |
237 | ||
0e1357e8 | 238 | sigma_write(buf, idx, devc); |
28a35d8a | 239 | |
0e1357e8 | 240 | return sigma_read(data, numchunks * CHUNK_SIZE, devc); |
28a35d8a HE |
241 | } |
242 | ||
4ae1f451 | 243 | /* Upload trigger look-up tables to Sigma. */ |
0e1357e8 | 244 | static int sigma_write_trigger_lut(struct triggerlut *lut, struct dev_context *devc) |
ee492173 HE |
245 | { |
246 | int i; | |
247 | uint8_t tmp[2]; | |
248 | uint16_t bit; | |
249 | ||
250 | /* Transpose the table and send to Sigma. */ | |
251 | for (i = 0; i < 16; ++i) { | |
252 | bit = 1 << i; | |
253 | ||
254 | tmp[0] = tmp[1] = 0; | |
255 | ||
256 | if (lut->m2d[0] & bit) | |
257 | tmp[0] |= 0x01; | |
258 | if (lut->m2d[1] & bit) | |
259 | tmp[0] |= 0x02; | |
260 | if (lut->m2d[2] & bit) | |
261 | tmp[0] |= 0x04; | |
262 | if (lut->m2d[3] & bit) | |
263 | tmp[0] |= 0x08; | |
264 | ||
265 | if (lut->m3 & bit) | |
266 | tmp[0] |= 0x10; | |
267 | if (lut->m3s & bit) | |
268 | tmp[0] |= 0x20; | |
269 | if (lut->m4 & bit) | |
270 | tmp[0] |= 0x40; | |
271 | ||
272 | if (lut->m0d[0] & bit) | |
273 | tmp[1] |= 0x01; | |
274 | if (lut->m0d[1] & bit) | |
275 | tmp[1] |= 0x02; | |
276 | if (lut->m0d[2] & bit) | |
277 | tmp[1] |= 0x04; | |
278 | if (lut->m0d[3] & bit) | |
279 | tmp[1] |= 0x08; | |
280 | ||
281 | if (lut->m1d[0] & bit) | |
282 | tmp[1] |= 0x10; | |
283 | if (lut->m1d[1] & bit) | |
284 | tmp[1] |= 0x20; | |
285 | if (lut->m1d[2] & bit) | |
286 | tmp[1] |= 0x40; | |
287 | if (lut->m1d[3] & bit) | |
288 | tmp[1] |= 0x80; | |
289 | ||
99965709 | 290 | sigma_write_register(WRITE_TRIGGER_SELECT0, tmp, sizeof(tmp), |
0e1357e8 BV |
291 | devc); |
292 | sigma_set_register(WRITE_TRIGGER_SELECT1, 0x30 | i, devc); | |
ee492173 HE |
293 | } |
294 | ||
295 | /* Send the parameters */ | |
296 | sigma_write_register(WRITE_TRIGGER_SELECT0, (uint8_t *) &lut->params, | |
0e1357e8 | 297 | sizeof(lut->params), devc); |
ee492173 | 298 | |
e46b8fb1 | 299 | return SR_OK; |
ee492173 HE |
300 | } |
301 | ||
fefa1800 | 302 | /* Generate the bitbang stream for programming the FPGA. */ |
28a35d8a | 303 | static int bin2bitbang(const char *filename, |
fefa1800 | 304 | unsigned char **buf, size_t *buf_size) |
28a35d8a | 305 | { |
fefa1800 | 306 | FILE *f; |
e3fff420 | 307 | unsigned long file_size; |
28a35d8a HE |
308 | unsigned long offset = 0; |
309 | unsigned char *p; | |
e3fff420 HE |
310 | uint8_t *firmware; |
311 | unsigned long fwsize = 0; | |
28a35d8a HE |
312 | const int buffer_size = 65536; |
313 | size_t i; | |
e3fff420 | 314 | int c, bit, v; |
fefa1800 | 315 | uint32_t imm = 0x3f6df2ab; |
28a35d8a | 316 | |
868d8cef | 317 | f = g_fopen(filename, "rb"); |
28a35d8a | 318 | if (!f) { |
47f4f073 | 319 | sr_err("g_fopen(\"%s\", \"rb\")", filename); |
b53738ba | 320 | return SR_ERR; |
28a35d8a HE |
321 | } |
322 | ||
323 | if (-1 == fseek(f, 0, SEEK_END)) { | |
47f4f073 | 324 | sr_err("fseek on %s failed", filename); |
28a35d8a | 325 | fclose(f); |
b53738ba | 326 | return SR_ERR; |
28a35d8a HE |
327 | } |
328 | ||
329 | file_size = ftell(f); | |
330 | ||
331 | fseek(f, 0, SEEK_SET); | |
332 | ||
b53738ba | 333 | if (!(firmware = g_try_malloc(buffer_size))) { |
47f4f073 | 334 | sr_err("%s: firmware malloc failed", __func__); |
12ad53f5 | 335 | fclose(f); |
b53738ba | 336 | return SR_ERR_MALLOC; |
28a35d8a HE |
337 | } |
338 | ||
28a35d8a HE |
339 | while ((c = getc(f)) != EOF) { |
340 | imm = (imm + 0xa853753) % 177 + (imm * 0x8034052); | |
e3fff420 | 341 | firmware[fwsize++] = c ^ imm; |
28a35d8a HE |
342 | } |
343 | fclose(f); | |
344 | ||
e3fff420 | 345 | if(fwsize != file_size) { |
47f4f073 | 346 | sr_err("%s: Error reading firmware", filename); |
e3fff420 HE |
347 | fclose(f); |
348 | g_free(firmware); | |
349 | return SR_ERR; | |
28a35d8a HE |
350 | } |
351 | ||
28a35d8a HE |
352 | *buf_size = fwsize * 2 * 8; |
353 | ||
b53738ba | 354 | *buf = p = (unsigned char *)g_try_malloc(*buf_size); |
28a35d8a | 355 | if (!p) { |
47f4f073 | 356 | sr_err("%s: buf/p malloc failed", __func__); |
12ad53f5 | 357 | g_free(firmware); |
b53738ba | 358 | return SR_ERR_MALLOC; |
28a35d8a HE |
359 | } |
360 | ||
361 | for (i = 0; i < fwsize; ++i) { | |
28a35d8a | 362 | for (bit = 7; bit >= 0; --bit) { |
fefa1800 | 363 | v = firmware[i] & 1 << bit ? 0x40 : 0x00; |
28a35d8a HE |
364 | p[offset++] = v | 0x01; |
365 | p[offset++] = v; | |
366 | } | |
367 | } | |
368 | ||
369 | g_free(firmware); | |
370 | ||
371 | if (offset != *buf_size) { | |
372 | g_free(*buf); | |
47f4f073 | 373 | sr_err("Error reading firmware %s " |
0aeb0ccd | 374 | "offset=%ld, file_size=%ld, buf_size=%zd.", |
133a37bf | 375 | filename, offset, file_size, *buf_size); |
28a35d8a | 376 | |
b53738ba | 377 | return SR_ERR; |
28a35d8a HE |
378 | } |
379 | ||
b53738ba | 380 | return SR_OK; |
28a35d8a HE |
381 | } |
382 | ||
3678cf73 | 383 | static void clear_helper(void *priv) |
0448d110 | 384 | { |
0e1357e8 | 385 | struct dev_context *devc; |
ce4d26dd | 386 | |
3678cf73 | 387 | devc = priv; |
0e1357e8 | 388 | |
3678cf73 UH |
389 | ftdi_deinit(&devc->ftdic); |
390 | } | |
0448d110 | 391 | |
3b412e3a | 392 | static int dev_clear(void) |
3678cf73 UH |
393 | { |
394 | return std_dev_clear(di, clear_helper); | |
0448d110 BV |
395 | } |
396 | ||
6078d2c9 | 397 | static int init(struct sr_context *sr_ctx) |
61136ea6 | 398 | { |
f6beaac5 | 399 | return std_init(sr_ctx, di, LOG_PREFIX); |
61136ea6 BV |
400 | } |
401 | ||
6078d2c9 | 402 | static GSList *scan(GSList *options) |
28a35d8a | 403 | { |
d68e2d1a | 404 | struct sr_dev_inst *sdi; |
87ca93c5 | 405 | struct sr_probe *probe; |
0e1357e8 BV |
406 | struct drv_context *drvc; |
407 | struct dev_context *devc; | |
0448d110 | 408 | GSList *devices; |
e3fff420 HE |
409 | struct ftdi_device_list *devlist; |
410 | char serial_txt[10]; | |
411 | uint32_t serial; | |
87ca93c5 | 412 | int ret, i; |
28a35d8a | 413 | |
0448d110 | 414 | (void)options; |
64d33dc2 | 415 | |
a873c594 | 416 | drvc = di->priv; |
4b97c74e | 417 | |
0448d110 | 418 | devices = NULL; |
4b97c74e | 419 | |
0e1357e8 | 420 | if (!(devc = g_try_malloc(sizeof(struct dev_context)))) { |
47f4f073 | 421 | sr_err("%s: devc malloc failed", __func__); |
0448d110 | 422 | return NULL; |
b53738ba | 423 | } |
99965709 | 424 | |
0e1357e8 | 425 | ftdi_init(&devc->ftdic); |
28a35d8a | 426 | |
fefa1800 | 427 | /* Look for SIGMAs. */ |
e3fff420 | 428 | |
0e1357e8 | 429 | if ((ret = ftdi_usb_find_all(&devc->ftdic, &devlist, |
eec944c5 BV |
430 | USB_VENDOR, USB_PRODUCT)) <= 0) { |
431 | if (ret < 0) | |
432 | sr_err("ftdi_usb_find_all(): %d", ret); | |
99965709 | 433 | goto free; |
eec944c5 | 434 | } |
99965709 | 435 | |
e3fff420 | 436 | /* Make sure it's a version 1 or 2 SIGMA. */ |
0e1357e8 | 437 | ftdi_usb_get_strings(&devc->ftdic, devlist->dev, NULL, 0, NULL, 0, |
6352d030 | 438 | serial_txt, sizeof(serial_txt)); |
e3fff420 HE |
439 | sscanf(serial_txt, "%x", &serial); |
440 | ||
6352d030 | 441 | if (serial < 0xa6010000 || serial > 0xa602ffff) { |
47f4f073 UH |
442 | sr_err("Only SIGMA and SIGMA2 are supported " |
443 | "in this version of libsigrok."); | |
e3fff420 HE |
444 | goto free; |
445 | } | |
446 | ||
447 | sr_info("Found ASIX SIGMA - Serial: %s", serial_txt); | |
448 | ||
0e1357e8 BV |
449 | devc->cur_samplerate = 0; |
450 | devc->period_ps = 0; | |
451 | devc->limit_msec = 0; | |
452 | devc->cur_firmware = -1; | |
453 | devc->num_probes = 0; | |
454 | devc->samples_per_event = 0; | |
455 | devc->capture_ratio = 50; | |
456 | devc->use_triggers = 0; | |
28a35d8a | 457 | |
fefa1800 | 458 | /* Register SIGMA device. */ |
d68e2d1a UH |
459 | if (!(sdi = sr_dev_inst_new(0, SR_ST_INITIALIZING, USB_VENDOR_NAME, |
460 | USB_MODEL_NAME, USB_MODEL_VERSION))) { | |
47f4f073 | 461 | sr_err("%s: sdi was NULL", __func__); |
99965709 | 462 | goto free; |
d68e2d1a | 463 | } |
a873c594 | 464 | sdi->driver = di; |
87ca93c5 BV |
465 | |
466 | for (i = 0; probe_names[i]; i++) { | |
de6e0eca | 467 | if (!(probe = sr_probe_new(i, SR_PROBE_LOGIC, TRUE, |
87ca93c5 BV |
468 | probe_names[i]))) |
469 | return NULL; | |
470 | sdi->probes = g_slist_append(sdi->probes, probe); | |
471 | } | |
472 | ||
0448d110 | 473 | devices = g_slist_append(devices, sdi); |
0e1357e8 BV |
474 | drvc->instances = g_slist_append(drvc->instances, sdi); |
475 | sdi->priv = devc; | |
28a35d8a | 476 | |
fefa1800 | 477 | /* We will open the device again when we need it. */ |
e3fff420 | 478 | ftdi_list_free(&devlist); |
28a35d8a | 479 | |
0448d110 | 480 | return devices; |
ea9cfed7 | 481 | |
99965709 | 482 | free: |
0e1357e8 BV |
483 | ftdi_deinit(&devc->ftdic); |
484 | g_free(devc); | |
0448d110 | 485 | return NULL; |
28a35d8a HE |
486 | } |
487 | ||
6078d2c9 | 488 | static GSList *dev_list(void) |
811deee4 | 489 | { |
0e94d524 | 490 | return ((struct drv_context *)(di->priv))->instances; |
811deee4 BV |
491 | } |
492 | ||
0e1357e8 | 493 | static int upload_firmware(int firmware_idx, struct dev_context *devc) |
28a35d8a HE |
494 | { |
495 | int ret; | |
496 | unsigned char *buf; | |
497 | unsigned char pins; | |
498 | size_t buf_size; | |
28a35d8a | 499 | unsigned char result[32]; |
e8397563 | 500 | char firmware_path[128]; |
28a35d8a | 501 | |
fefa1800 | 502 | /* Make sure it's an ASIX SIGMA. */ |
0e1357e8 | 503 | if ((ret = ftdi_usb_open_desc(&devc->ftdic, |
28a35d8a | 504 | USB_VENDOR, USB_PRODUCT, USB_DESCRIPTION, NULL)) < 0) { |
47f4f073 | 505 | sr_err("ftdi_usb_open failed: %s", |
0e1357e8 | 506 | ftdi_get_error_string(&devc->ftdic)); |
28a35d8a HE |
507 | return 0; |
508 | } | |
509 | ||
0e1357e8 | 510 | if ((ret = ftdi_set_bitmode(&devc->ftdic, 0xdf, BITMODE_BITBANG)) < 0) { |
47f4f073 | 511 | sr_err("ftdi_set_bitmode failed: %s", |
0e1357e8 | 512 | ftdi_get_error_string(&devc->ftdic)); |
28a35d8a HE |
513 | return 0; |
514 | } | |
515 | ||
fefa1800 | 516 | /* Four times the speed of sigmalogan - Works well. */ |
0e1357e8 | 517 | if ((ret = ftdi_set_baudrate(&devc->ftdic, 750000)) < 0) { |
47f4f073 | 518 | sr_err("ftdi_set_baudrate failed: %s", |
0e1357e8 | 519 | ftdi_get_error_string(&devc->ftdic)); |
28a35d8a HE |
520 | return 0; |
521 | } | |
522 | ||
fefa1800 | 523 | /* Force the FPGA to reboot. */ |
0e1357e8 BV |
524 | sigma_write(suicide, sizeof(suicide), devc); |
525 | sigma_write(suicide, sizeof(suicide), devc); | |
526 | sigma_write(suicide, sizeof(suicide), devc); | |
527 | sigma_write(suicide, sizeof(suicide), devc); | |
28a35d8a | 528 | |
fefa1800 | 529 | /* Prepare to upload firmware (FPGA specific). */ |
6078d2c9 | 530 | sigma_write(init_array, sizeof(init_array), devc); |
28a35d8a | 531 | |
0e1357e8 | 532 | ftdi_usb_purge_buffers(&devc->ftdic); |
28a35d8a | 533 | |
fefa1800 | 534 | /* Wait until the FPGA asserts INIT_B. */ |
28a35d8a | 535 | while (1) { |
0e1357e8 | 536 | ret = sigma_read(result, 1, devc); |
28a35d8a HE |
537 | if (result[0] & 0x20) |
538 | break; | |
539 | } | |
540 | ||
9ddb2a12 | 541 | /* Prepare firmware. */ |
e8397563 | 542 | snprintf(firmware_path, sizeof(firmware_path), "%s/%s", FIRMWARE_DIR, |
f6564c8d HE |
543 | firmware_files[firmware_idx]); |
544 | ||
b53738ba | 545 | if ((ret = bin2bitbang(firmware_path, &buf, &buf_size)) != SR_OK) { |
47f4f073 | 546 | sr_err("An error occured while reading the firmware: %s", |
133a37bf | 547 | firmware_path); |
b53738ba | 548 | return ret; |
28a35d8a HE |
549 | } |
550 | ||
fefa1800 | 551 | /* Upload firmare. */ |
47f4f073 | 552 | sr_info("Uploading firmware file '%s'.", firmware_files[firmware_idx]); |
0e1357e8 | 553 | sigma_write(buf, buf_size, devc); |
28a35d8a HE |
554 | |
555 | g_free(buf); | |
556 | ||
0e1357e8 | 557 | if ((ret = ftdi_set_bitmode(&devc->ftdic, 0x00, BITMODE_RESET)) < 0) { |
47f4f073 | 558 | sr_err("ftdi_set_bitmode failed: %s", |
0e1357e8 | 559 | ftdi_get_error_string(&devc->ftdic)); |
e46b8fb1 | 560 | return SR_ERR; |
28a35d8a HE |
561 | } |
562 | ||
0e1357e8 | 563 | ftdi_usb_purge_buffers(&devc->ftdic); |
28a35d8a | 564 | |
fefa1800 | 565 | /* Discard garbage. */ |
0e1357e8 | 566 | while (1 == sigma_read(&pins, 1, devc)) |
28a35d8a HE |
567 | ; |
568 | ||
fefa1800 | 569 | /* Initialize the logic analyzer mode. */ |
0e1357e8 | 570 | sigma_write(logic_mode_start, sizeof(logic_mode_start), devc); |
28a35d8a | 571 | |
fefa1800 | 572 | /* Expect a 3 byte reply. */ |
0e1357e8 | 573 | ret = sigma_read(result, 3, devc); |
28a35d8a HE |
574 | if (ret != 3 || |
575 | result[0] != 0xa6 || result[1] != 0x55 || result[2] != 0xaa) { | |
47f4f073 | 576 | sr_err("Configuration failed. Invalid reply received."); |
e46b8fb1 | 577 | return SR_ERR; |
28a35d8a HE |
578 | } |
579 | ||
0e1357e8 | 580 | devc->cur_firmware = firmware_idx; |
f6564c8d | 581 | |
47f4f073 | 582 | sr_info("Firmware uploaded."); |
e3fff420 | 583 | |
e46b8fb1 | 584 | return SR_OK; |
f6564c8d HE |
585 | } |
586 | ||
6078d2c9 | 587 | static int dev_open(struct sr_dev_inst *sdi) |
f6564c8d | 588 | { |
0e1357e8 | 589 | struct dev_context *devc; |
f6564c8d HE |
590 | int ret; |
591 | ||
0e1357e8 | 592 | devc = sdi->priv; |
99965709 | 593 | |
9ddb2a12 | 594 | /* Make sure it's an ASIX SIGMA. */ |
0e1357e8 | 595 | if ((ret = ftdi_usb_open_desc(&devc->ftdic, |
f6564c8d HE |
596 | USB_VENDOR, USB_PRODUCT, USB_DESCRIPTION, NULL)) < 0) { |
597 | ||
47f4f073 | 598 | sr_err("ftdi_usb_open failed: %s", |
0e1357e8 | 599 | ftdi_get_error_string(&devc->ftdic)); |
f6564c8d HE |
600 | |
601 | return 0; | |
602 | } | |
28a35d8a | 603 | |
5a2326a7 | 604 | sdi->status = SR_ST_ACTIVE; |
28a35d8a | 605 | |
e46b8fb1 | 606 | return SR_OK; |
f6564c8d HE |
607 | } |
608 | ||
6f4b1868 | 609 | static int set_samplerate(const struct sr_dev_inst *sdi, uint64_t samplerate) |
f6564c8d | 610 | { |
2c9c0df8 BV |
611 | struct dev_context *devc; |
612 | unsigned int i; | |
613 | int ret; | |
f6564c8d | 614 | |
2c9c0df8 | 615 | devc = sdi->priv; |
f4abaa9f UH |
616 | ret = SR_OK; |
617 | ||
2c9c0df8 BV |
618 | for (i = 0; i < ARRAY_SIZE(samplerates); i++) { |
619 | if (samplerates[i] == samplerate) | |
f6564c8d HE |
620 | break; |
621 | } | |
2c9c0df8 | 622 | if (samplerates[i] == 0) |
e46b8fb1 | 623 | return SR_ERR_SAMPLERATE; |
f6564c8d | 624 | |
59df0c77 | 625 | if (samplerate <= SR_MHZ(50)) { |
0e1357e8 BV |
626 | ret = upload_firmware(0, devc); |
627 | devc->num_probes = 16; | |
e8397563 | 628 | } |
59df0c77 | 629 | if (samplerate == SR_MHZ(100)) { |
0e1357e8 BV |
630 | ret = upload_firmware(1, devc); |
631 | devc->num_probes = 8; | |
f78898e9 | 632 | } |
59df0c77 | 633 | else if (samplerate == SR_MHZ(200)) { |
0e1357e8 BV |
634 | ret = upload_firmware(2, devc); |
635 | devc->num_probes = 4; | |
f78898e9 | 636 | } |
f6564c8d | 637 | |
0e1357e8 | 638 | devc->cur_samplerate = samplerate; |
5edc02c7 | 639 | devc->period_ps = 1000000000000ULL / samplerate; |
0e1357e8 BV |
640 | devc->samples_per_event = 16 / devc->num_probes; |
641 | devc->state.state = SIGMA_IDLE; | |
f6564c8d | 642 | |
e8397563 | 643 | return ret; |
28a35d8a HE |
644 | } |
645 | ||
c53d793f HE |
646 | /* |
647 | * In 100 and 200 MHz mode, only a single pin rising/falling can be | |
648 | * set as trigger. In other modes, two rising/falling triggers can be set, | |
649 | * in addition to value/mask trigger for any number of probes. | |
650 | * | |
651 | * The Sigma supports complex triggers using boolean expressions, but this | |
652 | * has not been implemented yet. | |
653 | */ | |
014359e3 | 654 | static int configure_probes(const struct sr_dev_inst *sdi) |
57bbf56b | 655 | { |
0e1357e8 | 656 | struct dev_context *devc = sdi->priv; |
1b79df2f JH |
657 | const struct sr_probe *probe; |
658 | const GSList *l; | |
57bbf56b | 659 | int trigger_set = 0; |
a42aec7f | 660 | int probebit; |
57bbf56b | 661 | |
0e1357e8 | 662 | memset(&devc->trigger, 0, sizeof(struct sigma_trigger)); |
eec5275e | 663 | |
014359e3 | 664 | for (l = sdi->probes; l; l = l->next) { |
1afe8989 | 665 | probe = (struct sr_probe *)l->data; |
b35c8293 | 666 | probebit = 1 << (probe->index); |
57bbf56b HE |
667 | |
668 | if (!probe->enabled || !probe->trigger) | |
669 | continue; | |
670 | ||
0e1357e8 | 671 | if (devc->cur_samplerate >= SR_MHZ(100)) { |
c53d793f | 672 | /* Fast trigger support. */ |
ee492173 | 673 | if (trigger_set) { |
47f4f073 UH |
674 | sr_err("Only a single pin trigger in 100 and " |
675 | "200MHz mode is supported."); | |
e46b8fb1 | 676 | return SR_ERR; |
ee492173 HE |
677 | } |
678 | if (probe->trigger[0] == 'f') | |
0e1357e8 | 679 | devc->trigger.fallingmask |= probebit; |
ee492173 | 680 | else if (probe->trigger[0] == 'r') |
0e1357e8 | 681 | devc->trigger.risingmask |= probebit; |
ee492173 | 682 | else { |
47f4f073 UH |
683 | sr_err("Only rising/falling trigger in 100 " |
684 | "and 200MHz mode is supported."); | |
e46b8fb1 | 685 | return SR_ERR; |
ee492173 | 686 | } |
57bbf56b | 687 | |
c53d793f | 688 | ++trigger_set; |
ee492173 | 689 | } else { |
c53d793f HE |
690 | /* Simple trigger support (event). */ |
691 | if (probe->trigger[0] == '1') { | |
0e1357e8 BV |
692 | devc->trigger.simplevalue |= probebit; |
693 | devc->trigger.simplemask |= probebit; | |
c53d793f HE |
694 | } |
695 | else if (probe->trigger[0] == '0') { | |
0e1357e8 BV |
696 | devc->trigger.simplevalue &= ~probebit; |
697 | devc->trigger.simplemask |= probebit; | |
c53d793f HE |
698 | } |
699 | else if (probe->trigger[0] == 'f') { | |
0e1357e8 | 700 | devc->trigger.fallingmask |= probebit; |
c53d793f HE |
701 | ++trigger_set; |
702 | } | |
703 | else if (probe->trigger[0] == 'r') { | |
0e1357e8 | 704 | devc->trigger.risingmask |= probebit; |
c53d793f HE |
705 | ++trigger_set; |
706 | } | |
ee492173 | 707 | |
ea9cfed7 UH |
708 | /* |
709 | * Actually, Sigma supports 2 rising/falling triggers, | |
710 | * but they are ORed and the current trigger syntax | |
711 | * does not permit ORed triggers. | |
712 | */ | |
98b8cbc1 | 713 | if (trigger_set > 1) { |
47f4f073 UH |
714 | sr_err("Only 1 rising/falling trigger " |
715 | "is supported."); | |
e46b8fb1 | 716 | return SR_ERR; |
ee492173 | 717 | } |
ee492173 | 718 | } |
5b5ea7c6 HE |
719 | |
720 | if (trigger_set) | |
0e1357e8 | 721 | devc->use_triggers = 1; |
57bbf56b HE |
722 | } |
723 | ||
e46b8fb1 | 724 | return SR_OK; |
57bbf56b HE |
725 | } |
726 | ||
6078d2c9 | 727 | static int dev_close(struct sr_dev_inst *sdi) |
28a35d8a | 728 | { |
0e1357e8 | 729 | struct dev_context *devc; |
28a35d8a | 730 | |
961009b0 | 731 | devc = sdi->priv; |
697785d1 UH |
732 | |
733 | /* TODO */ | |
734 | if (sdi->status == SR_ST_ACTIVE) | |
0e1357e8 | 735 | ftdi_usb_close(&devc->ftdic); |
697785d1 UH |
736 | |
737 | sdi->status = SR_ST_INACTIVE; | |
738 | ||
739 | return SR_OK; | |
28a35d8a HE |
740 | } |
741 | ||
6078d2c9 | 742 | static int cleanup(void) |
28a35d8a | 743 | { |
3b412e3a | 744 | return dev_clear(); |
28a35d8a HE |
745 | } |
746 | ||
8f996b89 ML |
747 | static int config_get(int id, GVariant **data, const struct sr_dev_inst *sdi, |
748 | const struct sr_probe_group *probe_group) | |
28a35d8a | 749 | { |
0e1357e8 | 750 | struct dev_context *devc; |
99965709 | 751 | |
8f996b89 ML |
752 | (void)probe_group; |
753 | ||
035a1078 | 754 | switch (id) { |
123e1313 | 755 | case SR_CONF_SAMPLERATE: |
41479605 | 756 | if (sdi) { |
0e1357e8 | 757 | devc = sdi->priv; |
2c9c0df8 | 758 | *data = g_variant_new_uint64(devc->cur_samplerate); |
41479605 BV |
759 | } else |
760 | return SR_ERR; | |
28a35d8a | 761 | break; |
d7bbecfd | 762 | default: |
bd6fbf62 | 763 | return SR_ERR_NA; |
28a35d8a HE |
764 | } |
765 | ||
41479605 | 766 | return SR_OK; |
28a35d8a HE |
767 | } |
768 | ||
8f996b89 ML |
769 | static int config_set(int id, GVariant *data, const struct sr_dev_inst *sdi, |
770 | const struct sr_probe_group *probe_group) | |
28a35d8a | 771 | { |
0e1357e8 | 772 | struct dev_context *devc; |
28a35d8a | 773 | int ret; |
f6564c8d | 774 | |
8f996b89 ML |
775 | (void)probe_group; |
776 | ||
e73ffd42 BV |
777 | if (sdi->status != SR_ST_ACTIVE) |
778 | return SR_ERR_DEV_CLOSED; | |
779 | ||
0e1357e8 | 780 | devc = sdi->priv; |
99965709 | 781 | |
035a1078 | 782 | if (id == SR_CONF_SAMPLERATE) { |
2c9c0df8 | 783 | ret = set_samplerate(sdi, g_variant_get_uint64(data)); |
035a1078 | 784 | } else if (id == SR_CONF_LIMIT_MSEC) { |
2c9c0df8 | 785 | devc->limit_msec = g_variant_get_uint64(data); |
0e1357e8 | 786 | if (devc->limit_msec > 0) |
e46b8fb1 | 787 | ret = SR_OK; |
94ba4bd6 | 788 | else |
e46b8fb1 | 789 | ret = SR_ERR; |
035a1078 | 790 | } else if (id == SR_CONF_CAPTURE_RATIO) { |
2c9c0df8 | 791 | devc->capture_ratio = g_variant_get_uint64(data); |
0e1357e8 | 792 | if (devc->capture_ratio < 0 || devc->capture_ratio > 100) |
e46b8fb1 | 793 | ret = SR_ERR; |
94ba4bd6 | 794 | else |
e46b8fb1 | 795 | ret = SR_OK; |
28a35d8a | 796 | } else { |
bd6fbf62 | 797 | ret = SR_ERR_NA; |
28a35d8a HE |
798 | } |
799 | ||
800 | return ret; | |
801 | } | |
802 | ||
8f996b89 ML |
803 | static int config_list(int key, GVariant **data, const struct sr_dev_inst *sdi, |
804 | const struct sr_probe_group *probe_group) | |
a1c743fc | 805 | { |
2c9c0df8 BV |
806 | GVariant *gvar; |
807 | GVariantBuilder gvb; | |
a1c743fc BV |
808 | |
809 | (void)sdi; | |
8f996b89 | 810 | (void)probe_group; |
a1c743fc BV |
811 | |
812 | switch (key) { | |
9a6517d1 | 813 | case SR_CONF_DEVICE_OPTIONS: |
2c9c0df8 BV |
814 | *data = g_variant_new_fixed_array(G_VARIANT_TYPE_INT32, |
815 | hwcaps, ARRAY_SIZE(hwcaps), sizeof(int32_t)); | |
9a6517d1 | 816 | break; |
a1c743fc | 817 | case SR_CONF_SAMPLERATE: |
2c9c0df8 BV |
818 | g_variant_builder_init(&gvb, G_VARIANT_TYPE("a{sv}")); |
819 | gvar = g_variant_new_fixed_array(G_VARIANT_TYPE("t"), samplerates, | |
820 | ARRAY_SIZE(samplerates), sizeof(uint64_t)); | |
821 | g_variant_builder_add(&gvb, "{sv}", "samplerates", gvar); | |
822 | *data = g_variant_builder_end(&gvb); | |
a1c743fc | 823 | break; |
c50277a6 | 824 | case SR_CONF_TRIGGER_TYPE: |
2c9c0df8 | 825 | *data = g_variant_new_string(TRIGGER_TYPE); |
c50277a6 | 826 | break; |
a1c743fc | 827 | default: |
bd6fbf62 | 828 | return SR_ERR_NA; |
a1c743fc BV |
829 | } |
830 | ||
831 | return SR_OK; | |
832 | } | |
833 | ||
36b1c8e6 HE |
834 | /* Software trigger to determine exact trigger position. */ |
835 | static int get_trigger_offset(uint16_t *samples, uint16_t last_sample, | |
836 | struct sigma_trigger *t) | |
837 | { | |
838 | int i; | |
839 | ||
840 | for (i = 0; i < 8; ++i) { | |
841 | if (i > 0) | |
842 | last_sample = samples[i-1]; | |
843 | ||
844 | /* Simple triggers. */ | |
845 | if ((samples[i] & t->simplemask) != t->simplevalue) | |
846 | continue; | |
847 | ||
848 | /* Rising edge. */ | |
849 | if ((last_sample & t->risingmask) != 0 || (samples[i] & | |
850 | t->risingmask) != t->risingmask) | |
851 | continue; | |
852 | ||
853 | /* Falling edge. */ | |
bdfc7a89 HE |
854 | if ((last_sample & t->fallingmask) != t->fallingmask || |
855 | (samples[i] & t->fallingmask) != 0) | |
36b1c8e6 HE |
856 | continue; |
857 | ||
858 | break; | |
859 | } | |
860 | ||
861 | /* If we did not match, return original trigger pos. */ | |
862 | return i & 0x7; | |
863 | } | |
864 | ||
28a35d8a | 865 | /* |
fefa1800 UH |
866 | * Decode chunk of 1024 bytes, 64 clusters, 7 events per cluster. |
867 | * Each event is 20ns apart, and can contain multiple samples. | |
f78898e9 HE |
868 | * |
869 | * For 200 MHz, events contain 4 samples for each channel, spread 5 ns apart. | |
870 | * For 100 MHz, events contain 2 samples for each channel, spread 10 ns apart. | |
871 | * For 50 MHz and below, events contain one sample for each channel, | |
872 | * spread 20 ns apart. | |
28a35d8a HE |
873 | */ |
874 | static int decode_chunk_ts(uint8_t *buf, uint16_t *lastts, | |
88c51afe | 875 | uint16_t *lastsample, int triggerpos, |
3cd3a20b | 876 | uint16_t limit_chunk, void *cb_data) |
28a35d8a | 877 | { |
3cd3a20b | 878 | struct sr_dev_inst *sdi = cb_data; |
0e1357e8 | 879 | struct dev_context *devc = sdi->priv; |
fefa1800 | 880 | uint16_t tsdiff, ts; |
0e1357e8 | 881 | uint16_t samples[65536 * devc->samples_per_event]; |
b9c735a2 | 882 | struct sr_datafeed_packet packet; |
9c939c51 | 883 | struct sr_datafeed_logic logic; |
f78898e9 | 884 | int i, j, k, l, numpad, tosend; |
fefa1800 | 885 | size_t n = 0, sent = 0; |
0e1357e8 | 886 | int clustersize = EVENTS_PER_CLUSTER * devc->samples_per_event; |
fefa1800 | 887 | uint16_t *event; |
f78898e9 | 888 | uint16_t cur_sample; |
57bbf56b | 889 | int triggerts = -1; |
ee492173 | 890 | |
4ae1f451 | 891 | /* Check if trigger is in this chunk. */ |
ee492173 | 892 | if (triggerpos != -1) { |
0e1357e8 | 893 | if (devc->cur_samplerate <= SR_MHZ(50)) |
36b1c8e6 | 894 | triggerpos -= EVENTS_PER_CLUSTER - 1; |
ee492173 HE |
895 | |
896 | if (triggerpos < 0) | |
897 | triggerpos = 0; | |
57bbf56b | 898 | |
ee492173 HE |
899 | /* Find in which cluster the trigger occured. */ |
900 | triggerts = triggerpos / 7; | |
901 | } | |
28a35d8a | 902 | |
eec5275e | 903 | /* For each ts. */ |
28a35d8a | 904 | for (i = 0; i < 64; ++i) { |
fefa1800 | 905 | ts = *(uint16_t *) &buf[i * 16]; |
28a35d8a HE |
906 | tsdiff = ts - *lastts; |
907 | *lastts = ts; | |
908 | ||
88c51afe HE |
909 | /* Decode partial chunk. */ |
910 | if (limit_chunk && ts > limit_chunk) | |
e46b8fb1 | 911 | return SR_OK; |
88c51afe | 912 | |
fefa1800 | 913 | /* Pad last sample up to current point. */ |
0e1357e8 | 914 | numpad = tsdiff * devc->samples_per_event - clustersize; |
28a35d8a | 915 | if (numpad > 0) { |
f78898e9 HE |
916 | for (j = 0; j < numpad; ++j) |
917 | samples[j] = *lastsample; | |
918 | ||
919 | n = numpad; | |
28a35d8a HE |
920 | } |
921 | ||
57bbf56b HE |
922 | /* Send samples between previous and this timestamp to sigrok. */ |
923 | sent = 0; | |
924 | while (sent < n) { | |
925 | tosend = MIN(2048, n - sent); | |
926 | ||
5a2326a7 | 927 | packet.type = SR_DF_LOGIC; |
9c939c51 BV |
928 | packet.payload = &logic; |
929 | logic.length = tosend * sizeof(uint16_t); | |
930 | logic.unitsize = 2; | |
931 | logic.data = samples + sent; | |
3e9b7f9c | 932 | sr_session_send(devc->cb_data, &packet); |
28a35d8a | 933 | |
57bbf56b HE |
934 | sent += tosend; |
935 | } | |
936 | n = 0; | |
937 | ||
938 | event = (uint16_t *) &buf[i * 16 + 2]; | |
f78898e9 HE |
939 | cur_sample = 0; |
940 | ||
941 | /* For each event in cluster. */ | |
28a35d8a | 942 | for (j = 0; j < 7; ++j) { |
f78898e9 HE |
943 | |
944 | /* For each sample in event. */ | |
0e1357e8 | 945 | for (k = 0; k < devc->samples_per_event; ++k) { |
f78898e9 HE |
946 | cur_sample = 0; |
947 | ||
948 | /* For each probe. */ | |
0e1357e8 | 949 | for (l = 0; l < devc->num_probes; ++l) |
edca2c5c | 950 | cur_sample |= (!!(event[j] & (1 << (l * |
0e1357e8 | 951 | devc->samples_per_event + k)))) << l; |
f78898e9 HE |
952 | |
953 | samples[n++] = cur_sample; | |
28a35d8a HE |
954 | } |
955 | } | |
956 | ||
eec5275e | 957 | /* Send data up to trigger point (if triggered). */ |
fefa1800 | 958 | sent = 0; |
57bbf56b HE |
959 | if (i == triggerts) { |
960 | /* | |
36b1c8e6 HE |
961 | * Trigger is not always accurate to sample because of |
962 | * pipeline delay. However, it always triggers before | |
963 | * the actual event. We therefore look at the next | |
964 | * samples to pinpoint the exact position of the trigger. | |
57bbf56b | 965 | */ |
bdfc7a89 | 966 | tosend = get_trigger_offset(samples, *lastsample, |
0e1357e8 | 967 | &devc->trigger); |
57bbf56b HE |
968 | |
969 | if (tosend > 0) { | |
5a2326a7 | 970 | packet.type = SR_DF_LOGIC; |
9c939c51 BV |
971 | packet.payload = &logic; |
972 | logic.length = tosend * sizeof(uint16_t); | |
973 | logic.unitsize = 2; | |
974 | logic.data = samples; | |
3e9b7f9c | 975 | sr_session_send(devc->cb_data, &packet); |
57bbf56b HE |
976 | |
977 | sent += tosend; | |
978 | } | |
28a35d8a | 979 | |
5b5ea7c6 | 980 | /* Only send trigger if explicitly enabled. */ |
0e1357e8 | 981 | if (devc->use_triggers) { |
5a2326a7 | 982 | packet.type = SR_DF_TRIGGER; |
3e9b7f9c | 983 | sr_session_send(devc->cb_data, &packet); |
5b5ea7c6 | 984 | } |
28a35d8a | 985 | } |
57bbf56b | 986 | |
eec5275e | 987 | /* Send rest of the chunk to sigrok. */ |
57bbf56b HE |
988 | tosend = n - sent; |
989 | ||
abda62ce | 990 | if (tosend > 0) { |
5a2326a7 | 991 | packet.type = SR_DF_LOGIC; |
9c939c51 BV |
992 | packet.payload = &logic; |
993 | logic.length = tosend * sizeof(uint16_t); | |
994 | logic.unitsize = 2; | |
995 | logic.data = samples + sent; | |
3e9b7f9c | 996 | sr_session_send(devc->cb_data, &packet); |
abda62ce | 997 | } |
ee492173 HE |
998 | |
999 | *lastsample = samples[n - 1]; | |
28a35d8a HE |
1000 | } |
1001 | ||
e46b8fb1 | 1002 | return SR_OK; |
28a35d8a HE |
1003 | } |
1004 | ||
1f9813eb | 1005 | static int receive_data(int fd, int revents, void *cb_data) |
28a35d8a | 1006 | { |
1f9813eb | 1007 | struct sr_dev_inst *sdi = cb_data; |
0e1357e8 | 1008 | struct dev_context *devc = sdi->priv; |
b9c735a2 | 1009 | struct sr_datafeed_packet packet; |
28a35d8a HE |
1010 | const int chunks_per_read = 32; |
1011 | unsigned char buf[chunks_per_read * CHUNK_SIZE]; | |
6aac7737 | 1012 | int bufsz, numchunks, i, newchunks; |
94ba4bd6 | 1013 | uint64_t running_msec; |
28a35d8a | 1014 | struct timeval tv; |
28a35d8a | 1015 | |
cb93f8a9 UH |
1016 | (void)fd; |
1017 | (void)revents; | |
28a35d8a | 1018 | |
805919b0 | 1019 | /* Get the current position. */ |
0e1357e8 | 1020 | sigma_read_pos(&devc->state.stoppos, &devc->state.triggerpos, devc); |
805919b0 | 1021 | |
0e1357e8 | 1022 | numchunks = (devc->state.stoppos + 511) / 512; |
28a35d8a | 1023 | |
0e1357e8 | 1024 | if (devc->state.state == SIGMA_IDLE) |
805919b0 | 1025 | return TRUE; |
28a35d8a | 1026 | |
0e1357e8 | 1027 | if (devc->state.state == SIGMA_CAPTURE) { |
6aac7737 HE |
1028 | /* Check if the timer has expired, or memory is full. */ |
1029 | gettimeofday(&tv, 0); | |
0e1357e8 BV |
1030 | running_msec = (tv.tv_sec - devc->start_tv.tv_sec) * 1000 + |
1031 | (tv.tv_usec - devc->start_tv.tv_usec) / 1000; | |
28a35d8a | 1032 | |
0e1357e8 | 1033 | if (running_msec < devc->limit_msec && numchunks < 32767) |
805919b0 | 1034 | return TRUE; /* While capturing... */ |
e3fff420 | 1035 | else |
6078d2c9 | 1036 | dev_acquisition_stop(sdi, sdi); |
6aac7737 | 1037 | |
dc890b8f UH |
1038 | } |
1039 | ||
1040 | if (devc->state.state == SIGMA_DOWNLOAD) { | |
0e1357e8 | 1041 | if (devc->state.chunks_downloaded >= numchunks) { |
6aac7737 | 1042 | /* End of samples. */ |
5a2326a7 | 1043 | packet.type = SR_DF_END; |
3e9b7f9c | 1044 | sr_session_send(devc->cb_data, &packet); |
6aac7737 | 1045 | |
0e1357e8 | 1046 | devc->state.state = SIGMA_IDLE; |
f78898e9 | 1047 | |
6aac7737 HE |
1048 | return TRUE; |
1049 | } | |
1050 | ||
1051 | newchunks = MIN(chunks_per_read, | |
0e1357e8 | 1052 | numchunks - devc->state.chunks_downloaded); |
28a35d8a | 1053 | |
47f4f073 | 1054 | sr_info("Downloading sample data: %.0f %%.", |
0e1357e8 | 1055 | 100.0 * devc->state.chunks_downloaded / numchunks); |
28a35d8a | 1056 | |
0e1357e8 BV |
1057 | bufsz = sigma_read_dram(devc->state.chunks_downloaded, |
1058 | newchunks, buf, devc); | |
719c5a93 UH |
1059 | /* TODO: Check bufsz. For now, just avoid compiler warnings. */ |
1060 | (void)bufsz; | |
28a35d8a | 1061 | |
fefa1800 | 1062 | /* Find first ts. */ |
0e1357e8 | 1063 | if (devc->state.chunks_downloaded == 0) { |
c36923b0 | 1064 | devc->state.lastts = RL16(buf) - 1; |
0e1357e8 | 1065 | devc->state.lastsample = 0; |
6aac7737 | 1066 | } |
28a35d8a | 1067 | |
fefa1800 | 1068 | /* Decode chunks and send them to sigrok. */ |
28a35d8a | 1069 | for (i = 0; i < newchunks; ++i) { |
88c51afe HE |
1070 | int limit_chunk = 0; |
1071 | ||
1072 | /* The last chunk may potentially be only in part. */ | |
0e1357e8 | 1073 | if (devc->state.chunks_downloaded == numchunks - 1) { |
88c51afe | 1074 | /* Find the last valid timestamp */ |
0e1357e8 | 1075 | limit_chunk = devc->state.stoppos % 512 + devc->state.lastts; |
88c51afe HE |
1076 | } |
1077 | ||
0e1357e8 | 1078 | if (devc->state.chunks_downloaded + i == devc->state.triggerchunk) |
57bbf56b | 1079 | decode_chunk_ts(buf + (i * CHUNK_SIZE), |
0e1357e8 BV |
1080 | &devc->state.lastts, |
1081 | &devc->state.lastsample, | |
1082 | devc->state.triggerpos & 0x1ff, | |
1f9813eb | 1083 | limit_chunk, sdi); |
57bbf56b HE |
1084 | else |
1085 | decode_chunk_ts(buf + (i * CHUNK_SIZE), | |
0e1357e8 BV |
1086 | &devc->state.lastts, |
1087 | &devc->state.lastsample, | |
1f9813eb | 1088 | -1, limit_chunk, sdi); |
28a35d8a | 1089 | |
0e1357e8 | 1090 | ++devc->state.chunks_downloaded; |
88c51afe | 1091 | } |
28a35d8a HE |
1092 | } |
1093 | ||
28a35d8a HE |
1094 | return TRUE; |
1095 | } | |
1096 | ||
c53d793f HE |
1097 | /* Build a LUT entry used by the trigger functions. */ |
1098 | static void build_lut_entry(uint16_t value, uint16_t mask, uint16_t *entry) | |
ee492173 HE |
1099 | { |
1100 | int i, j, k, bit; | |
1101 | ||
f758d074 | 1102 | /* For each quad probe. */ |
ee492173 | 1103 | for (i = 0; i < 4; ++i) { |
c53d793f | 1104 | entry[i] = 0xffff; |
ee492173 | 1105 | |
f758d074 | 1106 | /* For each bit in LUT. */ |
ee492173 HE |
1107 | for (j = 0; j < 16; ++j) |
1108 | ||
f758d074 | 1109 | /* For each probe in quad. */ |
ee492173 HE |
1110 | for (k = 0; k < 4; ++k) { |
1111 | bit = 1 << (i * 4 + k); | |
1112 | ||
c53d793f HE |
1113 | /* Set bit in entry */ |
1114 | if ((mask & bit) && | |
1115 | ((!(value & bit)) != | |
4ae1f451 | 1116 | (!(j & (1 << k))))) |
c53d793f | 1117 | entry[i] &= ~(1 << j); |
ee492173 HE |
1118 | } |
1119 | } | |
c53d793f | 1120 | } |
ee492173 | 1121 | |
c53d793f HE |
1122 | /* Add a logical function to LUT mask. */ |
1123 | static void add_trigger_function(enum triggerop oper, enum triggerfunc func, | |
1124 | int index, int neg, uint16_t *mask) | |
1125 | { | |
1126 | int i, j; | |
1127 | int x[2][2], tmp, a, b, aset, bset, rset; | |
1128 | ||
1129 | memset(x, 0, 4 * sizeof(int)); | |
1130 | ||
1131 | /* Trigger detect condition. */ | |
1132 | switch (oper) { | |
1133 | case OP_LEVEL: | |
1134 | x[0][1] = 1; | |
1135 | x[1][1] = 1; | |
1136 | break; | |
1137 | case OP_NOT: | |
1138 | x[0][0] = 1; | |
1139 | x[1][0] = 1; | |
1140 | break; | |
1141 | case OP_RISE: | |
1142 | x[0][1] = 1; | |
1143 | break; | |
1144 | case OP_FALL: | |
1145 | x[1][0] = 1; | |
1146 | break; | |
1147 | case OP_RISEFALL: | |
1148 | x[0][1] = 1; | |
1149 | x[1][0] = 1; | |
1150 | break; | |
1151 | case OP_NOTRISE: | |
1152 | x[1][1] = 1; | |
1153 | x[0][0] = 1; | |
1154 | x[1][0] = 1; | |
1155 | break; | |
1156 | case OP_NOTFALL: | |
1157 | x[1][1] = 1; | |
1158 | x[0][0] = 1; | |
1159 | x[0][1] = 1; | |
1160 | break; | |
1161 | case OP_NOTRISEFALL: | |
1162 | x[1][1] = 1; | |
1163 | x[0][0] = 1; | |
1164 | break; | |
1165 | } | |
1166 | ||
1167 | /* Transpose if neg is set. */ | |
1168 | if (neg) { | |
ea9cfed7 | 1169 | for (i = 0; i < 2; ++i) { |
c53d793f HE |
1170 | for (j = 0; j < 2; ++j) { |
1171 | tmp = x[i][j]; | |
1172 | x[i][j] = x[1-i][1-j]; | |
1173 | x[1-i][1-j] = tmp; | |
1174 | } | |
ea9cfed7 | 1175 | } |
c53d793f HE |
1176 | } |
1177 | ||
1178 | /* Update mask with function. */ | |
1179 | for (i = 0; i < 16; ++i) { | |
1180 | a = (i >> (2 * index + 0)) & 1; | |
1181 | b = (i >> (2 * index + 1)) & 1; | |
1182 | ||
1183 | aset = (*mask >> i) & 1; | |
1184 | bset = x[b][a]; | |
1185 | ||
1186 | if (func == FUNC_AND || func == FUNC_NAND) | |
1187 | rset = aset & bset; | |
1188 | else if (func == FUNC_OR || func == FUNC_NOR) | |
1189 | rset = aset | bset; | |
1190 | else if (func == FUNC_XOR || func == FUNC_NXOR) | |
1191 | rset = aset ^ bset; | |
1192 | ||
1193 | if (func == FUNC_NAND || func == FUNC_NOR || func == FUNC_NXOR) | |
1194 | rset = !rset; | |
1195 | ||
1196 | *mask &= ~(1 << i); | |
1197 | ||
1198 | if (rset) | |
1199 | *mask |= 1 << i; | |
1200 | } | |
1201 | } | |
1202 | ||
1203 | /* | |
1204 | * Build trigger LUTs used by 50 MHz and lower sample rates for supporting | |
1205 | * simple pin change and state triggers. Only two transitions (rise/fall) can be | |
1206 | * set at any time, but a full mask and value can be set (0/1). | |
1207 | */ | |
0e1357e8 | 1208 | static int build_basic_trigger(struct triggerlut *lut, struct dev_context *devc) |
c53d793f HE |
1209 | { |
1210 | int i,j; | |
4ae1f451 | 1211 | uint16_t masks[2] = { 0, 0 }; |
c53d793f HE |
1212 | |
1213 | memset(lut, 0, sizeof(struct triggerlut)); | |
1214 | ||
1215 | /* Contant for simple triggers. */ | |
1216 | lut->m4 = 0xa000; | |
1217 | ||
1218 | /* Value/mask trigger support. */ | |
0e1357e8 | 1219 | build_lut_entry(devc->trigger.simplevalue, devc->trigger.simplemask, |
99965709 | 1220 | lut->m2d); |
c53d793f HE |
1221 | |
1222 | /* Rise/fall trigger support. */ | |
1223 | for (i = 0, j = 0; i < 16; ++i) { | |
0e1357e8 BV |
1224 | if (devc->trigger.risingmask & (1 << i) || |
1225 | devc->trigger.fallingmask & (1 << i)) | |
c53d793f HE |
1226 | masks[j++] = 1 << i; |
1227 | } | |
1228 | ||
1229 | build_lut_entry(masks[0], masks[0], lut->m0d); | |
1230 | build_lut_entry(masks[1], masks[1], lut->m1d); | |
1231 | ||
1232 | /* Add glue logic */ | |
1233 | if (masks[0] || masks[1]) { | |
1234 | /* Transition trigger. */ | |
0e1357e8 | 1235 | if (masks[0] & devc->trigger.risingmask) |
c53d793f | 1236 | add_trigger_function(OP_RISE, FUNC_OR, 0, 0, &lut->m3); |
0e1357e8 | 1237 | if (masks[0] & devc->trigger.fallingmask) |
c53d793f | 1238 | add_trigger_function(OP_FALL, FUNC_OR, 0, 0, &lut->m3); |
0e1357e8 | 1239 | if (masks[1] & devc->trigger.risingmask) |
c53d793f | 1240 | add_trigger_function(OP_RISE, FUNC_OR, 1, 0, &lut->m3); |
0e1357e8 | 1241 | if (masks[1] & devc->trigger.fallingmask) |
c53d793f HE |
1242 | add_trigger_function(OP_FALL, FUNC_OR, 1, 0, &lut->m3); |
1243 | } else { | |
1244 | /* Only value/mask trigger. */ | |
1245 | lut->m3 = 0xffff; | |
1246 | } | |
ee492173 | 1247 | |
c53d793f | 1248 | /* Triggertype: event. */ |
ee492173 HE |
1249 | lut->params.selres = 3; |
1250 | ||
e46b8fb1 | 1251 | return SR_OK; |
ee492173 HE |
1252 | } |
1253 | ||
6078d2c9 | 1254 | static int dev_acquisition_start(const struct sr_dev_inst *sdi, void *cb_data) |
28a35d8a | 1255 | { |
0e1357e8 | 1256 | struct dev_context *devc; |
9ddb2a12 | 1257 | struct clockselect_50 clockselect; |
82957b65 | 1258 | int frac, triggerpin, ret; |
f4abaa9f | 1259 | uint8_t triggerselect = 0; |
57bbf56b | 1260 | struct triggerinout triggerinout_conf; |
ee492173 | 1261 | struct triggerlut lut; |
28a35d8a | 1262 | |
e73ffd42 BV |
1263 | if (sdi->status != SR_ST_ACTIVE) |
1264 | return SR_ERR_DEV_CLOSED; | |
1265 | ||
0e1357e8 | 1266 | devc = sdi->priv; |
28a35d8a | 1267 | |
014359e3 | 1268 | if (configure_probes(sdi) != SR_OK) { |
47f4f073 | 1269 | sr_err("Failed to configure probes."); |
014359e3 BV |
1270 | return SR_ERR; |
1271 | } | |
1272 | ||
ea9cfed7 | 1273 | /* If the samplerate has not been set, default to 200 kHz. */ |
0e1357e8 | 1274 | if (devc->cur_firmware == -1) { |
82957b65 UH |
1275 | if ((ret = set_samplerate(sdi, SR_KHZ(200))) != SR_OK) |
1276 | return ret; | |
1277 | } | |
e8397563 | 1278 | |
eec5275e | 1279 | /* Enter trigger programming mode. */ |
0e1357e8 | 1280 | sigma_set_register(WRITE_TRIGGER_SELECT1, 0x20, devc); |
28a35d8a | 1281 | |
eec5275e | 1282 | /* 100 and 200 MHz mode. */ |
0e1357e8 BV |
1283 | if (devc->cur_samplerate >= SR_MHZ(100)) { |
1284 | sigma_set_register(WRITE_TRIGGER_SELECT1, 0x81, devc); | |
57bbf56b | 1285 | |
a42aec7f HE |
1286 | /* Find which pin to trigger on from mask. */ |
1287 | for (triggerpin = 0; triggerpin < 8; ++triggerpin) | |
0e1357e8 | 1288 | if ((devc->trigger.risingmask | devc->trigger.fallingmask) & |
a42aec7f HE |
1289 | (1 << triggerpin)) |
1290 | break; | |
1291 | ||
1292 | /* Set trigger pin and light LED on trigger. */ | |
1293 | triggerselect = (1 << LEDSEL1) | (triggerpin & 0x7); | |
1294 | ||
1295 | /* Default rising edge. */ | |
0e1357e8 | 1296 | if (devc->trigger.fallingmask) |
a42aec7f | 1297 | triggerselect |= 1 << 3; |
57bbf56b | 1298 | |
eec5275e | 1299 | /* All other modes. */ |
0e1357e8 BV |
1300 | } else if (devc->cur_samplerate <= SR_MHZ(50)) { |
1301 | build_basic_trigger(&lut, devc); | |
ee492173 | 1302 | |
0e1357e8 | 1303 | sigma_write_trigger_lut(&lut, devc); |
57bbf56b HE |
1304 | |
1305 | triggerselect = (1 << LEDSEL1) | (1 << LEDSEL0); | |
1306 | } | |
1307 | ||
eec5275e | 1308 | /* Setup trigger in and out pins to default values. */ |
57bbf56b HE |
1309 | memset(&triggerinout_conf, 0, sizeof(struct triggerinout)); |
1310 | triggerinout_conf.trgout_bytrigger = 1; | |
1311 | triggerinout_conf.trgout_enable = 1; | |
1312 | ||
28a35d8a | 1313 | sigma_write_register(WRITE_TRIGGER_OPTION, |
57bbf56b | 1314 | (uint8_t *) &triggerinout_conf, |
0e1357e8 | 1315 | sizeof(struct triggerinout), devc); |
28a35d8a | 1316 | |
eec5275e | 1317 | /* Go back to normal mode. */ |
0e1357e8 | 1318 | sigma_set_register(WRITE_TRIGGER_SELECT1, triggerselect, devc); |
28a35d8a | 1319 | |
edca2c5c | 1320 | /* Set clock select register. */ |
0e1357e8 | 1321 | if (devc->cur_samplerate == SR_MHZ(200)) |
edca2c5c | 1322 | /* Enable 4 probes. */ |
0e1357e8 BV |
1323 | sigma_set_register(WRITE_CLOCK_SELECT, 0xf0, devc); |
1324 | else if (devc->cur_samplerate == SR_MHZ(100)) | |
edca2c5c | 1325 | /* Enable 8 probes. */ |
0e1357e8 | 1326 | sigma_set_register(WRITE_CLOCK_SELECT, 0x00, devc); |
edca2c5c HE |
1327 | else { |
1328 | /* | |
9ddb2a12 | 1329 | * 50 MHz mode (or fraction thereof). Any fraction down to |
eec5275e | 1330 | * 50 MHz / 256 can be used, but is not supported by sigrok API. |
edca2c5c | 1331 | */ |
0e1357e8 | 1332 | frac = SR_MHZ(50) / devc->cur_samplerate - 1; |
edca2c5c | 1333 | |
9ddb2a12 UH |
1334 | clockselect.async = 0; |
1335 | clockselect.fraction = frac; | |
1336 | clockselect.disabled_probes = 0; | |
edca2c5c HE |
1337 | |
1338 | sigma_write_register(WRITE_CLOCK_SELECT, | |
9ddb2a12 | 1339 | (uint8_t *) &clockselect, |
0e1357e8 | 1340 | sizeof(clockselect), devc); |
edca2c5c HE |
1341 | } |
1342 | ||
fefa1800 | 1343 | /* Setup maximum post trigger time. */ |
99965709 | 1344 | sigma_set_register(WRITE_POST_TRIGGER, |
0e1357e8 | 1345 | (devc->capture_ratio * 255) / 100, devc); |
28a35d8a | 1346 | |
eec5275e | 1347 | /* Start acqusition. */ |
0e1357e8 BV |
1348 | gettimeofday(&devc->start_tv, 0); |
1349 | sigma_set_register(WRITE_MODE, 0x0d, devc); | |
99965709 | 1350 | |
3e9b7f9c | 1351 | devc->cb_data = cb_data; |
28a35d8a | 1352 | |
3c36c403 | 1353 | /* Send header packet to the session bus. */ |
29a27196 | 1354 | std_session_send_df_header(cb_data, LOG_PREFIX); |
f366e86c | 1355 | |
f366e86c | 1356 | /* Add capture source. */ |
3ffb6964 | 1357 | sr_source_add(0, G_IO_IN, 10, receive_data, (void *)sdi); |
f366e86c | 1358 | |
0e1357e8 | 1359 | devc->state.state = SIGMA_CAPTURE; |
6aac7737 | 1360 | |
e46b8fb1 | 1361 | return SR_OK; |
28a35d8a HE |
1362 | } |
1363 | ||
6078d2c9 | 1364 | static int dev_acquisition_stop(struct sr_dev_inst *sdi, void *cb_data) |
28a35d8a | 1365 | { |
0e1357e8 | 1366 | struct dev_context *devc; |
6aac7737 HE |
1367 | uint8_t modestatus; |
1368 | ||
3cd3a20b | 1369 | (void)cb_data; |
28a35d8a | 1370 | |
503c4afb BV |
1371 | sr_source_remove(0); |
1372 | ||
0e1357e8 | 1373 | if (!(devc = sdi->priv)) { |
47f4f073 | 1374 | sr_err("%s: sdi->priv was NULL", __func__); |
3010f21c UH |
1375 | return SR_ERR_BUG; |
1376 | } | |
1377 | ||
fefa1800 | 1378 | /* Stop acquisition. */ |
0e1357e8 | 1379 | sigma_set_register(WRITE_MODE, 0x11, devc); |
28a35d8a | 1380 | |
6aac7737 | 1381 | /* Set SDRAM Read Enable. */ |
0e1357e8 | 1382 | sigma_set_register(WRITE_MODE, 0x02, devc); |
6aac7737 HE |
1383 | |
1384 | /* Get the current position. */ | |
0e1357e8 | 1385 | sigma_read_pos(&devc->state.stoppos, &devc->state.triggerpos, devc); |
6aac7737 HE |
1386 | |
1387 | /* Check if trigger has fired. */ | |
0e1357e8 | 1388 | modestatus = sigma_get_register(READ_MODE, devc); |
3010f21c | 1389 | if (modestatus & 0x20) |
0e1357e8 | 1390 | devc->state.triggerchunk = devc->state.triggerpos / 512; |
3010f21c | 1391 | else |
0e1357e8 | 1392 | devc->state.triggerchunk = -1; |
6aac7737 | 1393 | |
0e1357e8 | 1394 | devc->state.chunks_downloaded = 0; |
6aac7737 | 1395 | |
0e1357e8 | 1396 | devc->state.state = SIGMA_DOWNLOAD; |
3010f21c UH |
1397 | |
1398 | return SR_OK; | |
28a35d8a HE |
1399 | } |
1400 | ||
c09f0b57 | 1401 | SR_PRIV struct sr_dev_driver asix_sigma_driver_info = { |
e519ba86 | 1402 | .name = "asix-sigma", |
6352d030 | 1403 | .longname = "ASIX SIGMA/SIGMA2", |
e519ba86 | 1404 | .api_version = 1, |
6078d2c9 UH |
1405 | .init = init, |
1406 | .cleanup = cleanup, | |
1407 | .scan = scan, | |
1408 | .dev_list = dev_list, | |
3b412e3a | 1409 | .dev_clear = dev_clear, |
035a1078 BV |
1410 | .config_get = config_get, |
1411 | .config_set = config_set, | |
a1c743fc | 1412 | .config_list = config_list, |
6078d2c9 UH |
1413 | .dev_open = dev_open, |
1414 | .dev_close = dev_close, | |
1415 | .dev_acquisition_start = dev_acquisition_start, | |
1416 | .dev_acquisition_stop = dev_acquisition_stop, | |
0e1357e8 | 1417 | .priv = NULL, |
28a35d8a | 1418 | }; |