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Commit | Line | Data |
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28a35d8a | 1 | /* |
50985c20 | 2 | * This file is part of the libsigrok project. |
28a35d8a | 3 | * |
868501fa | 4 | * Copyright (C) 2010-2012 Håvard Espeland <gus@ping.uio.no>, |
911f1834 UH |
5 | * Copyright (C) 2010 Martin Stensgård <mastensg@ping.uio.no> |
6 | * Copyright (C) 2010 Carl Henrik Lunde <chlunde@ping.uio.no> | |
28a35d8a HE |
7 | * |
8 | * This program is free software: you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation, either version 3 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
20 | */ | |
21 | ||
911f1834 | 22 | /* |
6352d030 | 23 | * ASIX SIGMA/SIGMA2 logic analyzer driver |
911f1834 UH |
24 | */ |
25 | ||
6ec6c43b | 26 | #include <config.h> |
3ba56876 | 27 | #include "protocol.h" |
28a35d8a | 28 | |
b1648dea MV |
29 | /* |
30 | * The ASIX Sigma supports arbitrary integer frequency divider in | |
31 | * the 50MHz mode. The divider is in range 1...256 , allowing for | |
32 | * very precise sampling rate selection. This driver supports only | |
33 | * a subset of the sampling rates. | |
34 | */ | |
3ba56876 | 35 | SR_PRIV const uint64_t samplerates[] = { |
b1648dea MV |
36 | SR_KHZ(200), /* div=250 */ |
37 | SR_KHZ(250), /* div=200 */ | |
38 | SR_KHZ(500), /* div=100 */ | |
39 | SR_MHZ(1), /* div=50 */ | |
40 | SR_MHZ(5), /* div=10 */ | |
41 | SR_MHZ(10), /* div=5 */ | |
42 | SR_MHZ(25), /* div=2 */ | |
43 | SR_MHZ(50), /* div=1 */ | |
44 | SR_MHZ(100), /* Special FW needed */ | |
45 | SR_MHZ(200), /* Special FW needed */ | |
28a35d8a HE |
46 | }; |
47 | ||
4154a516 | 48 | SR_PRIV const size_t samplerates_count = ARRAY_SIZE(samplerates); |
39c64c6a | 49 | |
8e2d6c9d | 50 | static const char sigma_firmware_files[][24] = { |
499b17e9 | 51 | /* 50 MHz, supports 8 bit fractions */ |
8e2d6c9d | 52 | "asix-sigma-50.fw", |
499b17e9 | 53 | /* 100 MHz */ |
8e2d6c9d | 54 | "asix-sigma-100.fw", |
499b17e9 | 55 | /* 200 MHz */ |
8e2d6c9d | 56 | "asix-sigma-200.fw", |
499b17e9 | 57 | /* Synchronous clock from pin */ |
8e2d6c9d | 58 | "asix-sigma-50sync.fw", |
499b17e9 | 59 | /* Frequency counter */ |
8e2d6c9d | 60 | "asix-sigma-phasor.fw", |
f6564c8d HE |
61 | }; |
62 | ||
0e1357e8 | 63 | static int sigma_read(void *buf, size_t size, struct dev_context *devc) |
28a35d8a HE |
64 | { |
65 | int ret; | |
fefa1800 | 66 | |
0e1357e8 | 67 | ret = ftdi_read_data(&devc->ftdic, (unsigned char *)buf, size); |
28a35d8a | 68 | if (ret < 0) { |
47f4f073 | 69 | sr_err("ftdi_read_data failed: %s", |
0e1357e8 | 70 | ftdi_get_error_string(&devc->ftdic)); |
28a35d8a HE |
71 | } |
72 | ||
73 | return ret; | |
74 | } | |
75 | ||
0e1357e8 | 76 | static int sigma_write(void *buf, size_t size, struct dev_context *devc) |
28a35d8a HE |
77 | { |
78 | int ret; | |
fefa1800 | 79 | |
0e1357e8 | 80 | ret = ftdi_write_data(&devc->ftdic, (unsigned char *)buf, size); |
28a35d8a | 81 | if (ret < 0) { |
47f4f073 | 82 | sr_err("ftdi_write_data failed: %s", |
0e1357e8 | 83 | ftdi_get_error_string(&devc->ftdic)); |
fefa1800 | 84 | } else if ((size_t) ret != size) { |
47f4f073 | 85 | sr_err("ftdi_write_data did not complete write."); |
28a35d8a HE |
86 | } |
87 | ||
88 | return ret; | |
89 | } | |
90 | ||
e8686e3a AG |
91 | /* |
92 | * NOTE: We chose the buffer size to be large enough to hold any write to the | |
93 | * device. We still print a message just in case. | |
94 | */ | |
3ba56876 | 95 | SR_PRIV int sigma_write_register(uint8_t reg, uint8_t *data, size_t len, |
96 | struct dev_context *devc) | |
28a35d8a HE |
97 | { |
98 | size_t i; | |
e8686e3a | 99 | uint8_t buf[80]; |
28a35d8a HE |
100 | int idx = 0; |
101 | ||
7c86d853 | 102 | if ((2 * len + 2) > sizeof(buf)) { |
e8686e3a | 103 | sr_err("Attempted to write %zu bytes, but buffer is too small.", |
7c86d853 | 104 | len); |
e8686e3a AG |
105 | return SR_ERR_BUG; |
106 | } | |
107 | ||
28a35d8a HE |
108 | buf[idx++] = REG_ADDR_LOW | (reg & 0xf); |
109 | buf[idx++] = REG_ADDR_HIGH | (reg >> 4); | |
110 | ||
0a1f7b09 | 111 | for (i = 0; i < len; i++) { |
28a35d8a HE |
112 | buf[idx++] = REG_DATA_LOW | (data[i] & 0xf); |
113 | buf[idx++] = REG_DATA_HIGH_WRITE | (data[i] >> 4); | |
114 | } | |
115 | ||
0e1357e8 | 116 | return sigma_write(buf, idx, devc); |
28a35d8a HE |
117 | } |
118 | ||
3ba56876 | 119 | SR_PRIV int sigma_set_register(uint8_t reg, uint8_t value, struct dev_context *devc) |
28a35d8a | 120 | { |
0e1357e8 | 121 | return sigma_write_register(reg, &value, 1, devc); |
28a35d8a HE |
122 | } |
123 | ||
99965709 | 124 | static int sigma_read_register(uint8_t reg, uint8_t *data, size_t len, |
0e1357e8 | 125 | struct dev_context *devc) |
28a35d8a HE |
126 | { |
127 | uint8_t buf[3]; | |
fefa1800 | 128 | |
28a35d8a HE |
129 | buf[0] = REG_ADDR_LOW | (reg & 0xf); |
130 | buf[1] = REG_ADDR_HIGH | (reg >> 4); | |
28a35d8a HE |
131 | buf[2] = REG_READ_ADDR; |
132 | ||
0e1357e8 | 133 | sigma_write(buf, sizeof(buf), devc); |
28a35d8a | 134 | |
0e1357e8 | 135 | return sigma_read(data, len, devc); |
28a35d8a HE |
136 | } |
137 | ||
0e1357e8 | 138 | static uint8_t sigma_get_register(uint8_t reg, struct dev_context *devc) |
28a35d8a HE |
139 | { |
140 | uint8_t value; | |
fefa1800 | 141 | |
0e1357e8 | 142 | if (1 != sigma_read_register(reg, &value, 1, devc)) { |
47f4f073 | 143 | sr_err("sigma_get_register: 1 byte expected"); |
28a35d8a HE |
144 | return 0; |
145 | } | |
146 | ||
147 | return value; | |
148 | } | |
149 | ||
99965709 | 150 | static int sigma_read_pos(uint32_t *stoppos, uint32_t *triggerpos, |
0e1357e8 | 151 | struct dev_context *devc) |
28a35d8a HE |
152 | { |
153 | uint8_t buf[] = { | |
154 | REG_ADDR_LOW | READ_TRIGGER_POS_LOW, | |
155 | ||
156 | REG_READ_ADDR | NEXT_REG, | |
157 | REG_READ_ADDR | NEXT_REG, | |
158 | REG_READ_ADDR | NEXT_REG, | |
159 | REG_READ_ADDR | NEXT_REG, | |
160 | REG_READ_ADDR | NEXT_REG, | |
161 | REG_READ_ADDR | NEXT_REG, | |
162 | }; | |
28a35d8a HE |
163 | uint8_t result[6]; |
164 | ||
0e1357e8 | 165 | sigma_write(buf, sizeof(buf), devc); |
28a35d8a | 166 | |
0e1357e8 | 167 | sigma_read(result, sizeof(result), devc); |
28a35d8a HE |
168 | |
169 | *triggerpos = result[0] | (result[1] << 8) | (result[2] << 16); | |
170 | *stoppos = result[3] | (result[4] << 8) | (result[5] << 16); | |
171 | ||
57bbf56b HE |
172 | /* Not really sure why this must be done, but according to spec. */ |
173 | if ((--*stoppos & 0x1ff) == 0x1ff) | |
382cb19f | 174 | *stoppos -= 64; |
57bbf56b HE |
175 | |
176 | if ((*--triggerpos & 0x1ff) == 0x1ff) | |
382cb19f | 177 | *triggerpos -= 64; |
57bbf56b | 178 | |
28a35d8a HE |
179 | return 1; |
180 | } | |
181 | ||
99965709 | 182 | static int sigma_read_dram(uint16_t startchunk, size_t numchunks, |
0e1357e8 | 183 | uint8_t *data, struct dev_context *devc) |
28a35d8a HE |
184 | { |
185 | size_t i; | |
186 | uint8_t buf[4096]; | |
f06fb3e9 | 187 | int idx; |
28a35d8a | 188 | |
fefa1800 | 189 | /* Send the startchunk. Index start with 1. */ |
f06fb3e9 GS |
190 | idx = 0; |
191 | buf[idx++] = startchunk >> 8; | |
192 | buf[idx++] = startchunk & 0xff; | |
193 | sigma_write_register(WRITE_MEMROW, buf, idx, devc); | |
28a35d8a | 194 | |
fefa1800 | 195 | /* Read the DRAM. */ |
f06fb3e9 | 196 | idx = 0; |
28a35d8a HE |
197 | buf[idx++] = REG_DRAM_BLOCK; |
198 | buf[idx++] = REG_DRAM_WAIT_ACK; | |
199 | ||
0a1f7b09 | 200 | for (i = 0; i < numchunks; i++) { |
fefa1800 UH |
201 | /* Alternate bit to copy from DRAM to cache. */ |
202 | if (i != (numchunks - 1)) | |
203 | buf[idx++] = REG_DRAM_BLOCK | (((i + 1) % 2) << 4); | |
28a35d8a HE |
204 | |
205 | buf[idx++] = REG_DRAM_BLOCK_DATA | ((i % 2) << 4); | |
206 | ||
fefa1800 | 207 | if (i != (numchunks - 1)) |
28a35d8a HE |
208 | buf[idx++] = REG_DRAM_WAIT_ACK; |
209 | } | |
210 | ||
0e1357e8 | 211 | sigma_write(buf, idx, devc); |
28a35d8a | 212 | |
0e1357e8 | 213 | return sigma_read(data, numchunks * CHUNK_SIZE, devc); |
28a35d8a HE |
214 | } |
215 | ||
4ae1f451 | 216 | /* Upload trigger look-up tables to Sigma. */ |
3ba56876 | 217 | SR_PRIV int sigma_write_trigger_lut(struct triggerlut *lut, struct dev_context *devc) |
ee492173 HE |
218 | { |
219 | int i; | |
220 | uint8_t tmp[2]; | |
221 | uint16_t bit; | |
222 | ||
223 | /* Transpose the table and send to Sigma. */ | |
0a1f7b09 | 224 | for (i = 0; i < 16; i++) { |
ee492173 HE |
225 | bit = 1 << i; |
226 | ||
227 | tmp[0] = tmp[1] = 0; | |
228 | ||
229 | if (lut->m2d[0] & bit) | |
230 | tmp[0] |= 0x01; | |
231 | if (lut->m2d[1] & bit) | |
232 | tmp[0] |= 0x02; | |
233 | if (lut->m2d[2] & bit) | |
234 | tmp[0] |= 0x04; | |
235 | if (lut->m2d[3] & bit) | |
236 | tmp[0] |= 0x08; | |
237 | ||
238 | if (lut->m3 & bit) | |
239 | tmp[0] |= 0x10; | |
240 | if (lut->m3s & bit) | |
241 | tmp[0] |= 0x20; | |
242 | if (lut->m4 & bit) | |
243 | tmp[0] |= 0x40; | |
244 | ||
245 | if (lut->m0d[0] & bit) | |
246 | tmp[1] |= 0x01; | |
247 | if (lut->m0d[1] & bit) | |
248 | tmp[1] |= 0x02; | |
249 | if (lut->m0d[2] & bit) | |
250 | tmp[1] |= 0x04; | |
251 | if (lut->m0d[3] & bit) | |
252 | tmp[1] |= 0x08; | |
253 | ||
254 | if (lut->m1d[0] & bit) | |
255 | tmp[1] |= 0x10; | |
256 | if (lut->m1d[1] & bit) | |
257 | tmp[1] |= 0x20; | |
258 | if (lut->m1d[2] & bit) | |
259 | tmp[1] |= 0x40; | |
260 | if (lut->m1d[3] & bit) | |
261 | tmp[1] |= 0x80; | |
262 | ||
99965709 | 263 | sigma_write_register(WRITE_TRIGGER_SELECT0, tmp, sizeof(tmp), |
0e1357e8 BV |
264 | devc); |
265 | sigma_set_register(WRITE_TRIGGER_SELECT1, 0x30 | i, devc); | |
ee492173 HE |
266 | } |
267 | ||
268 | /* Send the parameters */ | |
269 | sigma_write_register(WRITE_TRIGGER_SELECT0, (uint8_t *) &lut->params, | |
0e1357e8 | 270 | sizeof(lut->params), devc); |
ee492173 | 271 | |
e46b8fb1 | 272 | return SR_OK; |
ee492173 HE |
273 | } |
274 | ||
3ba56876 | 275 | SR_PRIV void sigma_clear_helper(void *priv) |
0448d110 | 276 | { |
0e1357e8 | 277 | struct dev_context *devc; |
ce4d26dd | 278 | |
3678cf73 | 279 | devc = priv; |
0e1357e8 | 280 | |
3678cf73 UH |
281 | ftdi_deinit(&devc->ftdic); |
282 | } | |
0448d110 | 283 | |
d5fa188a MV |
284 | /* |
285 | * Configure the FPGA for bitbang mode. | |
286 | * This sequence is documented in section 2. of the ASIX Sigma programming | |
287 | * manual. This sequence is necessary to configure the FPGA in the Sigma | |
288 | * into Bitbang mode, in which it can be programmed with the firmware. | |
289 | */ | |
290 | static int sigma_fpga_init_bitbang(struct dev_context *devc) | |
291 | { | |
292 | uint8_t suicide[] = { | |
293 | 0x84, 0x84, 0x88, 0x84, 0x88, 0x84, 0x88, 0x84, | |
294 | }; | |
295 | uint8_t init_array[] = { | |
296 | 0x01, 0x03, 0x03, 0x01, 0x01, 0x01, 0x01, 0x01, | |
297 | 0x01, 0x01, | |
298 | }; | |
1a46cc62 | 299 | int i, ret, timeout = (10 * 1000); |
d5fa188a MV |
300 | uint8_t data; |
301 | ||
302 | /* Section 2. part 1), do the FPGA suicide. */ | |
303 | sigma_write(suicide, sizeof(suicide), devc); | |
304 | sigma_write(suicide, sizeof(suicide), devc); | |
305 | sigma_write(suicide, sizeof(suicide), devc); | |
306 | sigma_write(suicide, sizeof(suicide), devc); | |
307 | ||
308 | /* Section 2. part 2), do pulse on D1. */ | |
309 | sigma_write(init_array, sizeof(init_array), devc); | |
310 | ftdi_usb_purge_buffers(&devc->ftdic); | |
311 | ||
312 | /* Wait until the FPGA asserts D6/INIT_B. */ | |
313 | for (i = 0; i < timeout; i++) { | |
314 | ret = sigma_read(&data, 1, devc); | |
315 | if (ret < 0) | |
316 | return ret; | |
317 | /* Test if pin D6 got asserted. */ | |
318 | if (data & (1 << 5)) | |
319 | return 0; | |
320 | /* The D6 was not asserted yet, wait a bit. */ | |
1a46cc62 | 321 | g_usleep(10 * 1000); |
d5fa188a MV |
322 | } |
323 | ||
324 | return SR_ERR_TIMEOUT; | |
325 | } | |
326 | ||
64fe661b MV |
327 | /* |
328 | * Configure the FPGA for logic-analyzer mode. | |
329 | */ | |
330 | static int sigma_fpga_init_la(struct dev_context *devc) | |
331 | { | |
332 | /* Initialize the logic analyzer mode. */ | |
333 | uint8_t logic_mode_start[] = { | |
011f1091 | 334 | REG_ADDR_LOW | (READ_ID & 0xf), |
84a6ed1a | 335 | REG_ADDR_HIGH | (READ_ID >> 4), |
011f1091 MV |
336 | REG_READ_ADDR, /* Read ID register. */ |
337 | ||
338 | REG_ADDR_LOW | (WRITE_TEST & 0xf), | |
339 | REG_DATA_LOW | 0x5, | |
340 | REG_DATA_HIGH_WRITE | 0x5, | |
341 | REG_READ_ADDR, /* Read scratch register. */ | |
342 | ||
343 | REG_DATA_LOW | 0xa, | |
344 | REG_DATA_HIGH_WRITE | 0xa, | |
345 | REG_READ_ADDR, /* Read scratch register. */ | |
346 | ||
347 | REG_ADDR_LOW | (WRITE_MODE & 0xf), | |
348 | REG_DATA_LOW | 0x0, | |
349 | REG_DATA_HIGH_WRITE | 0x8, | |
64fe661b MV |
350 | }; |
351 | ||
352 | uint8_t result[3]; | |
353 | int ret; | |
354 | ||
355 | /* Initialize the logic analyzer mode. */ | |
356 | sigma_write(logic_mode_start, sizeof(logic_mode_start), devc); | |
357 | ||
011f1091 | 358 | /* Expect a 3 byte reply since we issued three READ requests. */ |
64fe661b MV |
359 | ret = sigma_read(result, 3, devc); |
360 | if (ret != 3) | |
361 | goto err; | |
362 | ||
363 | if (result[0] != 0xa6 || result[1] != 0x55 || result[2] != 0xaa) | |
364 | goto err; | |
365 | ||
366 | return SR_OK; | |
367 | err: | |
368 | sr_err("Configuration failed. Invalid reply received."); | |
369 | return SR_ERR; | |
370 | } | |
371 | ||
a80226bb MV |
372 | /* |
373 | * Read the firmware from a file and transform it into a series of bitbang | |
374 | * pulses used to program the FPGA. Note that the *bb_cmd must be free()'d | |
375 | * by the caller of this function. | |
376 | */ | |
8e2d6c9d | 377 | static int sigma_fw_2_bitbang(struct sr_context *ctx, const char *name, |
a80226bb MV |
378 | uint8_t **bb_cmd, gsize *bb_cmd_size) |
379 | { | |
8e2d6c9d DE |
380 | size_t i, file_size, bb_size; |
381 | char *firmware; | |
a80226bb MV |
382 | uint8_t *bb_stream, *bbs; |
383 | uint32_t imm; | |
384 | int bit, v; | |
385 | int ret = SR_OK; | |
386 | ||
387825dc | 387 | /* Retrieve the on-disk firmware file content. */ |
8e2d6c9d DE |
388 | firmware = sr_resource_load(ctx, SR_RESOURCE_FIRMWARE, |
389 | name, &file_size, 256 * 1024); | |
390 | if (!firmware) | |
391 | return SR_ERR; | |
a80226bb | 392 | |
387825dc | 393 | /* Unscramble the file content (XOR with "random" sequence). */ |
a80226bb MV |
394 | imm = 0x3f6df2ab; |
395 | for (i = 0; i < file_size; i++) { | |
396 | imm = (imm + 0xa853753) % 177 + (imm * 0x8034052); | |
397 | firmware[i] ^= imm & 0xff; | |
398 | } | |
399 | ||
400 | /* | |
387825dc GS |
401 | * Generate a sequence of bitbang samples. With two samples per |
402 | * FPGA configuration bit, providing the level for the DIN signal | |
403 | * as well as two edges for CCLK. See Xilinx UG332 for details | |
404 | * ("slave serial" mode). | |
405 | * | |
406 | * Note that CCLK is inverted in hardware. That's why the | |
407 | * respective bit is first set and then cleared in the bitbang | |
408 | * sample sets. So that the DIN level will be stable when the | |
409 | * data gets sampled at the rising CCLK edge, and the signals' | |
410 | * setup time constraint will be met. | |
411 | * | |
412 | * The caller will put the FPGA into download mode, will send | |
413 | * the bitbang samples, and release the allocated memory. | |
a80226bb | 414 | */ |
a80226bb MV |
415 | bb_size = file_size * 8 * 2; |
416 | bb_stream = (uint8_t *)g_try_malloc(bb_size); | |
417 | if (!bb_stream) { | |
418 | sr_err("%s: Failed to allocate bitbang stream", __func__); | |
419 | ret = SR_ERR_MALLOC; | |
420 | goto exit; | |
421 | } | |
a80226bb MV |
422 | bbs = bb_stream; |
423 | for (i = 0; i < file_size; i++) { | |
424 | for (bit = 7; bit >= 0; bit--) { | |
425 | v = (firmware[i] & (1 << bit)) ? 0x40 : 0x00; | |
426 | *bbs++ = v | 0x01; | |
427 | *bbs++ = v; | |
428 | } | |
429 | } | |
430 | ||
431 | /* The transformation completed successfully, return the result. */ | |
432 | *bb_cmd = bb_stream; | |
433 | *bb_cmd_size = bb_size; | |
434 | ||
435 | exit: | |
8e2d6c9d | 436 | g_free(firmware); |
a80226bb MV |
437 | return ret; |
438 | } | |
439 | ||
8e2d6c9d DE |
440 | static int upload_firmware(struct sr_context *ctx, |
441 | int firmware_idx, struct dev_context *devc) | |
28a35d8a HE |
442 | { |
443 | int ret; | |
444 | unsigned char *buf; | |
445 | unsigned char pins; | |
446 | size_t buf_size; | |
a9016883 GS |
447 | const char *firmware; |
448 | struct ftdi_context *ftdic; | |
449 | ||
450 | /* Avoid downloading the same firmware multiple times. */ | |
451 | firmware = sigma_firmware_files[firmware_idx]; | |
452 | if (devc->cur_firmware == firmware_idx) { | |
453 | sr_info("Not uploading firmware file '%s' again.", firmware); | |
454 | return SR_OK; | |
455 | } | |
28a35d8a | 456 | |
fefa1800 | 457 | /* Make sure it's an ASIX SIGMA. */ |
a9016883 | 458 | ftdic = &devc->ftdic; |
8bbf7627 MV |
459 | ret = ftdi_usb_open_desc(ftdic, USB_VENDOR, USB_PRODUCT, |
460 | USB_DESCRIPTION, NULL); | |
461 | if (ret < 0) { | |
47f4f073 | 462 | sr_err("ftdi_usb_open failed: %s", |
8bbf7627 | 463 | ftdi_get_error_string(ftdic)); |
28a35d8a HE |
464 | return 0; |
465 | } | |
466 | ||
8bbf7627 MV |
467 | ret = ftdi_set_bitmode(ftdic, 0xdf, BITMODE_BITBANG); |
468 | if (ret < 0) { | |
47f4f073 | 469 | sr_err("ftdi_set_bitmode failed: %s", |
8bbf7627 | 470 | ftdi_get_error_string(ftdic)); |
28a35d8a HE |
471 | return 0; |
472 | } | |
473 | ||
fefa1800 | 474 | /* Four times the speed of sigmalogan - Works well. */ |
1a46cc62 | 475 | ret = ftdi_set_baudrate(ftdic, 750 * 1000); |
8bbf7627 | 476 | if (ret < 0) { |
47f4f073 | 477 | sr_err("ftdi_set_baudrate failed: %s", |
8bbf7627 | 478 | ftdi_get_error_string(ftdic)); |
28a35d8a HE |
479 | return 0; |
480 | } | |
481 | ||
d5fa188a MV |
482 | /* Initialize the FPGA for firmware upload. */ |
483 | ret = sigma_fpga_init_bitbang(devc); | |
484 | if (ret) | |
485 | return ret; | |
28a35d8a | 486 | |
9ddb2a12 | 487 | /* Prepare firmware. */ |
8e2d6c9d | 488 | ret = sigma_fw_2_bitbang(ctx, firmware, &buf, &buf_size); |
8bbf7627 | 489 | if (ret != SR_OK) { |
f3f19d11 | 490 | sr_err("An error occurred while reading the firmware: %s", |
499b17e9 | 491 | firmware); |
b53738ba | 492 | return ret; |
28a35d8a HE |
493 | } |
494 | ||
f3f19d11 | 495 | /* Upload firmware. */ |
499b17e9 | 496 | sr_info("Uploading firmware file '%s'.", firmware); |
0e1357e8 | 497 | sigma_write(buf, buf_size, devc); |
28a35d8a HE |
498 | |
499 | g_free(buf); | |
500 | ||
8bbf7627 MV |
501 | ret = ftdi_set_bitmode(ftdic, 0x00, BITMODE_RESET); |
502 | if (ret < 0) { | |
47f4f073 | 503 | sr_err("ftdi_set_bitmode failed: %s", |
8bbf7627 | 504 | ftdi_get_error_string(ftdic)); |
e46b8fb1 | 505 | return SR_ERR; |
28a35d8a HE |
506 | } |
507 | ||
8bbf7627 | 508 | ftdi_usb_purge_buffers(ftdic); |
28a35d8a | 509 | |
fefa1800 | 510 | /* Discard garbage. */ |
29b66a2e | 511 | while (sigma_read(&pins, 1, devc) == 1) |
28a35d8a HE |
512 | ; |
513 | ||
64fe661b MV |
514 | /* Initialize the FPGA for logic-analyzer mode. */ |
515 | ret = sigma_fpga_init_la(devc); | |
516 | if (ret != SR_OK) | |
517 | return ret; | |
28a35d8a | 518 | |
0e1357e8 | 519 | devc->cur_firmware = firmware_idx; |
f6564c8d | 520 | |
47f4f073 | 521 | sr_info("Firmware uploaded."); |
e3fff420 | 522 | |
e46b8fb1 | 523 | return SR_OK; |
f6564c8d HE |
524 | } |
525 | ||
9a0a606a GS |
526 | /* |
527 | * Sigma doesn't support limiting the number of samples, so we have to | |
528 | * translate the number and the samplerate to an elapsed time. | |
529 | * | |
530 | * In addition we need to ensure that the last data cluster has passed | |
531 | * the hardware pipeline, and became available to the PC side. With RLE | |
532 | * compression up to 327ms could pass before another cluster accumulates | |
533 | * at 200kHz samplerate when input pins don't change. | |
534 | */ | |
535 | SR_PRIV uint64_t sigma_limit_samples_to_msec(const struct dev_context *devc, | |
536 | uint64_t limit_samples) | |
537 | { | |
538 | uint64_t limit_msec; | |
539 | uint64_t worst_cluster_time_ms; | |
540 | ||
541 | limit_msec = limit_samples * 1000 / devc->cur_samplerate; | |
542 | worst_cluster_time_ms = 65536 * 1000 / devc->cur_samplerate; | |
543 | /* | |
544 | * One cluster time is not enough to flush pipeline when sampling | |
545 | * grounded pins with 1 sample limit at 200kHz. Hence the 2* fix. | |
546 | */ | |
547 | return limit_msec + 2 * worst_cluster_time_ms; | |
548 | } | |
549 | ||
3ba56876 | 550 | SR_PRIV int sigma_set_samplerate(const struct sr_dev_inst *sdi, uint64_t samplerate) |
f6564c8d | 551 | { |
2c9c0df8 | 552 | struct dev_context *devc; |
8e2d6c9d | 553 | struct drv_context *drvc; |
4154a516 | 554 | size_t i; |
2c9c0df8 | 555 | int ret; |
f6564c8d | 556 | |
2c9c0df8 | 557 | devc = sdi->priv; |
8e2d6c9d | 558 | drvc = sdi->driver->context; |
f4abaa9f UH |
559 | ret = SR_OK; |
560 | ||
2f7e529c | 561 | /* Reject rates that are not in the list of supported rates. */ |
4154a516 | 562 | for (i = 0; i < samplerates_count; i++) { |
2c9c0df8 | 563 | if (samplerates[i] == samplerate) |
f6564c8d HE |
564 | break; |
565 | } | |
4154a516 | 566 | if (i >= samplerates_count || samplerates[i] == 0) |
e46b8fb1 | 567 | return SR_ERR_SAMPLERATE; |
f6564c8d | 568 | |
2f7e529c GS |
569 | /* |
570 | * Depending on the samplerates of 200/100/50- MHz, specific | |
571 | * firmware is required and higher rates might limit the set | |
572 | * of available channels. | |
573 | */ | |
59df0c77 | 574 | if (samplerate <= SR_MHZ(50)) { |
8e2d6c9d | 575 | ret = upload_firmware(drvc->sr_ctx, 0, devc); |
ba7dd8bb | 576 | devc->num_channels = 16; |
6b2d3385 | 577 | } else if (samplerate == SR_MHZ(100)) { |
8e2d6c9d | 578 | ret = upload_firmware(drvc->sr_ctx, 1, devc); |
ba7dd8bb | 579 | devc->num_channels = 8; |
6b2d3385 | 580 | } else if (samplerate == SR_MHZ(200)) { |
8e2d6c9d | 581 | ret = upload_firmware(drvc->sr_ctx, 2, devc); |
ba7dd8bb | 582 | devc->num_channels = 4; |
f78898e9 | 583 | } |
f6564c8d | 584 | |
2f7e529c GS |
585 | /* |
586 | * Derive the sample period from the sample rate as well as the | |
587 | * number of samples that the device will communicate within | |
588 | * an "event" (memory organization internal to the device). | |
589 | */ | |
6b2d3385 BV |
590 | if (ret == SR_OK) { |
591 | devc->cur_samplerate = samplerate; | |
592 | devc->period_ps = 1000000000000ULL / samplerate; | |
593 | devc->samples_per_event = 16 / devc->num_channels; | |
594 | devc->state.state = SIGMA_IDLE; | |
595 | } | |
f6564c8d | 596 | |
2f7e529c GS |
597 | /* |
598 | * Support for "limit_samples" is implemented by stopping | |
599 | * acquisition after a corresponding period of time. | |
600 | * Re-calculate that period of time, in case the limit is | |
601 | * set first and the samplerate gets (re-)configured later. | |
602 | */ | |
603 | if (ret == SR_OK && devc->limit_samples) { | |
604 | uint64_t msecs; | |
9a0a606a | 605 | msecs = sigma_limit_samples_to_msec(devc, devc->limit_samples); |
2f7e529c GS |
606 | devc->limit_msec = msecs; |
607 | } | |
608 | ||
e8397563 | 609 | return ret; |
28a35d8a HE |
610 | } |
611 | ||
c53d793f HE |
612 | /* |
613 | * In 100 and 200 MHz mode, only a single pin rising/falling can be | |
614 | * set as trigger. In other modes, two rising/falling triggers can be set, | |
ba7dd8bb | 615 | * in addition to value/mask trigger for any number of channels. |
c53d793f HE |
616 | * |
617 | * The Sigma supports complex triggers using boolean expressions, but this | |
618 | * has not been implemented yet. | |
619 | */ | |
3ba56876 | 620 | SR_PRIV int sigma_convert_trigger(const struct sr_dev_inst *sdi) |
57bbf56b | 621 | { |
39c64c6a BV |
622 | struct dev_context *devc; |
623 | struct sr_trigger *trigger; | |
624 | struct sr_trigger_stage *stage; | |
625 | struct sr_trigger_match *match; | |
626 | const GSList *l, *m; | |
627 | int channelbit, trigger_set; | |
57bbf56b | 628 | |
39c64c6a | 629 | devc = sdi->priv; |
0e1357e8 | 630 | memset(&devc->trigger, 0, sizeof(struct sigma_trigger)); |
0812c40e | 631 | if (!(trigger = sr_session_trigger_get(sdi->session))) |
39c64c6a BV |
632 | return SR_OK; |
633 | ||
634 | trigger_set = 0; | |
635 | for (l = trigger->stages; l; l = l->next) { | |
636 | stage = l->data; | |
637 | for (m = stage->matches; m; m = m->next) { | |
638 | match = m->data; | |
639 | if (!match->channel->enabled) | |
640 | /* Ignore disabled channels with a trigger. */ | |
641 | continue; | |
642 | channelbit = 1 << (match->channel->index); | |
643 | if (devc->cur_samplerate >= SR_MHZ(100)) { | |
644 | /* Fast trigger support. */ | |
645 | if (trigger_set) { | |
646 | sr_err("Only a single pin trigger is " | |
647 | "supported in 100 and 200MHz mode."); | |
648 | return SR_ERR; | |
649 | } | |
650 | if (match->match == SR_TRIGGER_FALLING) | |
651 | devc->trigger.fallingmask |= channelbit; | |
652 | else if (match->match == SR_TRIGGER_RISING) | |
653 | devc->trigger.risingmask |= channelbit; | |
654 | else { | |
655 | sr_err("Only rising/falling trigger is " | |
656 | "supported in 100 and 200MHz mode."); | |
657 | return SR_ERR; | |
658 | } | |
eec5275e | 659 | |
0a1f7b09 | 660 | trigger_set++; |
39c64c6a BV |
661 | } else { |
662 | /* Simple trigger support (event). */ | |
663 | if (match->match == SR_TRIGGER_ONE) { | |
664 | devc->trigger.simplevalue |= channelbit; | |
665 | devc->trigger.simplemask |= channelbit; | |
666 | } | |
667 | else if (match->match == SR_TRIGGER_ZERO) { | |
668 | devc->trigger.simplevalue &= ~channelbit; | |
669 | devc->trigger.simplemask |= channelbit; | |
670 | } | |
671 | else if (match->match == SR_TRIGGER_FALLING) { | |
672 | devc->trigger.fallingmask |= channelbit; | |
0a1f7b09 | 673 | trigger_set++; |
39c64c6a BV |
674 | } |
675 | else if (match->match == SR_TRIGGER_RISING) { | |
676 | devc->trigger.risingmask |= channelbit; | |
0a1f7b09 | 677 | trigger_set++; |
39c64c6a BV |
678 | } |
679 | ||
680 | /* | |
681 | * Actually, Sigma supports 2 rising/falling triggers, | |
682 | * but they are ORed and the current trigger syntax | |
683 | * does not permit ORed triggers. | |
684 | */ | |
685 | if (trigger_set > 1) { | |
686 | sr_err("Only 1 rising/falling trigger " | |
687 | "is supported."); | |
688 | return SR_ERR; | |
689 | } | |
ee492173 | 690 | } |
ee492173 | 691 | } |
57bbf56b HE |
692 | } |
693 | ||
e46b8fb1 | 694 | return SR_OK; |
57bbf56b HE |
695 | } |
696 | ||
a1c743fc | 697 | |
36b1c8e6 | 698 | /* Software trigger to determine exact trigger position. */ |
5fc01191 | 699 | static int get_trigger_offset(uint8_t *samples, uint16_t last_sample, |
36b1c8e6 HE |
700 | struct sigma_trigger *t) |
701 | { | |
702 | int i; | |
5fc01191 | 703 | uint16_t sample = 0; |
36b1c8e6 | 704 | |
0a1f7b09 | 705 | for (i = 0; i < 8; i++) { |
36b1c8e6 | 706 | if (i > 0) |
5fc01191 MV |
707 | last_sample = sample; |
708 | sample = samples[2 * i] | (samples[2 * i + 1] << 8); | |
36b1c8e6 HE |
709 | |
710 | /* Simple triggers. */ | |
5fc01191 | 711 | if ((sample & t->simplemask) != t->simplevalue) |
36b1c8e6 HE |
712 | continue; |
713 | ||
714 | /* Rising edge. */ | |
5fc01191 MV |
715 | if (((last_sample & t->risingmask) != 0) || |
716 | ((sample & t->risingmask) != t->risingmask)) | |
36b1c8e6 HE |
717 | continue; |
718 | ||
719 | /* Falling edge. */ | |
bdfc7a89 | 720 | if ((last_sample & t->fallingmask) != t->fallingmask || |
5fc01191 | 721 | (sample & t->fallingmask) != 0) |
36b1c8e6 HE |
722 | continue; |
723 | ||
724 | break; | |
725 | } | |
726 | ||
727 | /* If we did not match, return original trigger pos. */ | |
728 | return i & 0x7; | |
729 | } | |
730 | ||
3513d965 MV |
731 | /* |
732 | * Return the timestamp of "DRAM cluster". | |
733 | */ | |
734 | static uint16_t sigma_dram_cluster_ts(struct sigma_dram_cluster *cluster) | |
735 | { | |
736 | return (cluster->timestamp_hi << 8) | cluster->timestamp_lo; | |
737 | } | |
738 | ||
0498f743 GS |
739 | /* |
740 | * Return one 16bit data entity of a DRAM cluster at the specified index. | |
741 | */ | |
742 | static uint16_t sigma_dram_cluster_data(struct sigma_dram_cluster *cl, int idx) | |
743 | { | |
744 | uint16_t sample; | |
745 | ||
746 | sample = 0; | |
747 | sample |= cl->samples[idx].sample_lo << 0; | |
748 | sample |= cl->samples[idx].sample_hi << 8; | |
3281cf59 | 749 | sample = (sample >> 8) | (sample << 8); |
0498f743 GS |
750 | return sample; |
751 | } | |
752 | ||
85c032e4 GS |
753 | /* |
754 | * Deinterlace sample data that was retrieved at 100MHz samplerate. | |
755 | * One 16bit item contains two samples of 8bits each. The bits of | |
756 | * multiple samples are interleaved. | |
757 | */ | |
758 | static uint16_t sigma_deinterlace_100mhz_data(uint16_t indata, int idx) | |
759 | { | |
760 | uint16_t outdata; | |
761 | ||
762 | indata >>= idx; | |
763 | outdata = 0; | |
764 | outdata |= (indata >> (0 * 2 - 0)) & (1 << 0); | |
765 | outdata |= (indata >> (1 * 2 - 1)) & (1 << 1); | |
766 | outdata |= (indata >> (2 * 2 - 2)) & (1 << 2); | |
767 | outdata |= (indata >> (3 * 2 - 3)) & (1 << 3); | |
768 | outdata |= (indata >> (4 * 2 - 4)) & (1 << 4); | |
769 | outdata |= (indata >> (5 * 2 - 5)) & (1 << 5); | |
770 | outdata |= (indata >> (6 * 2 - 6)) & (1 << 6); | |
771 | outdata |= (indata >> (7 * 2 - 7)) & (1 << 7); | |
772 | return outdata; | |
773 | } | |
774 | ||
775 | /* | |
776 | * Deinterlace sample data that was retrieved at 200MHz samplerate. | |
777 | * One 16bit item contains four samples of 4bits each. The bits of | |
778 | * multiple samples are interleaved. | |
779 | */ | |
780 | static uint16_t sigma_deinterlace_200mhz_data(uint16_t indata, int idx) | |
781 | { | |
782 | uint16_t outdata; | |
783 | ||
784 | indata >>= idx; | |
785 | outdata = 0; | |
786 | outdata |= (indata >> (0 * 4 - 0)) & (1 << 0); | |
787 | outdata |= (indata >> (1 * 4 - 1)) & (1 << 1); | |
788 | outdata |= (indata >> (2 * 4 - 2)) & (1 << 2); | |
789 | outdata |= (indata >> (3 * 4 - 3)) & (1 << 3); | |
790 | return outdata; | |
791 | } | |
792 | ||
0498f743 GS |
793 | static void store_sr_sample(uint8_t *samples, int idx, uint16_t data) |
794 | { | |
795 | samples[2 * idx + 0] = (data >> 0) & 0xff; | |
796 | samples[2 * idx + 1] = (data >> 8) & 0xff; | |
797 | } | |
798 | ||
85c032e4 GS |
799 | /* |
800 | * This size translates to: event count (1K events per cluster), times | |
801 | * the sample width (unitsize, 16bits per event), times the maximum | |
802 | * number of samples per event. | |
803 | */ | |
804 | #define SAMPLES_BUFFER_SIZE (1024 * 2 * 4) | |
805 | ||
23239b5c MV |
806 | static void sigma_decode_dram_cluster(struct sigma_dram_cluster *dram_cluster, |
807 | unsigned int events_in_cluster, | |
1e23158b | 808 | unsigned int triggered, |
23239b5c MV |
809 | struct sr_dev_inst *sdi) |
810 | { | |
811 | struct dev_context *devc = sdi->priv; | |
812 | struct sigma_state *ss = &devc->state; | |
813 | struct sr_datafeed_packet packet; | |
814 | struct sr_datafeed_logic logic; | |
85c032e4 GS |
815 | uint16_t tsdiff, ts, sample, item16; |
816 | uint8_t samples[SAMPLES_BUFFER_SIZE]; | |
817 | uint8_t *send_ptr; | |
818 | size_t send_count, trig_count; | |
23239b5c | 819 | unsigned int i; |
85c032e4 | 820 | int j; |
23239b5c | 821 | |
23239b5c MV |
822 | ts = sigma_dram_cluster_ts(dram_cluster); |
823 | tsdiff = ts - ss->lastts; | |
a44b3b3f | 824 | ss->lastts = ts + EVENTS_PER_CLUSTER; |
23239b5c MV |
825 | |
826 | packet.type = SR_DF_LOGIC; | |
827 | packet.payload = &logic; | |
828 | logic.unitsize = 2; | |
829 | logic.data = samples; | |
830 | ||
831 | /* | |
832 | * First of all, send Sigrok a copy of the last sample from | |
833 | * previous cluster as many times as needed to make up for | |
834 | * the differential characteristics of data we get from the | |
835 | * Sigma. Sigrok needs one sample of data per period. | |
836 | * | |
837 | * One DRAM cluster contains a timestamp and seven samples, | |
838 | * the units of timestamp are "devc->period_ps" , the first | |
839 | * sample in the cluster happens at the time of the timestamp | |
840 | * and the remaining samples happen at timestamp +1...+6 . | |
841 | */ | |
a44b3b3f | 842 | for (ts = 0; ts < tsdiff; ts++) { |
23239b5c | 843 | i = ts % 1024; |
0498f743 | 844 | store_sr_sample(samples, i, ss->lastsample); |
23239b5c MV |
845 | |
846 | /* | |
847 | * If we have 1024 samples ready or we're at the | |
848 | * end of submitting the padding samples, submit | |
85c032e4 GS |
849 | * the packet to Sigrok. Since constant data is |
850 | * sent, duplication of data for rates above 50MHz | |
851 | * is simple. | |
23239b5c | 852 | */ |
a44b3b3f | 853 | if ((i == 1023) || (ts == tsdiff - 1)) { |
23239b5c | 854 | logic.length = (i + 1) * logic.unitsize; |
85c032e4 GS |
855 | for (j = 0; j < devc->samples_per_event; j++) |
856 | sr_session_send(sdi, &packet); | |
23239b5c MV |
857 | } |
858 | } | |
859 | ||
860 | /* | |
861 | * Parse the samples in current cluster and prepare them | |
85c032e4 GS |
862 | * to be submitted to Sigrok. Cope with memory layouts that |
863 | * vary with the samplerate. | |
23239b5c | 864 | */ |
85c032e4 GS |
865 | send_ptr = &samples[0]; |
866 | send_count = 0; | |
0498f743 | 867 | sample = 0; |
23239b5c | 868 | for (i = 0; i < events_in_cluster; i++) { |
85c032e4 GS |
869 | item16 = sigma_dram_cluster_data(dram_cluster, i); |
870 | if (devc->cur_samplerate == SR_MHZ(200)) { | |
871 | sample = sigma_deinterlace_200mhz_data(item16, 0); | |
872 | store_sr_sample(samples, send_count++, sample); | |
873 | sample = sigma_deinterlace_200mhz_data(item16, 1); | |
874 | store_sr_sample(samples, send_count++, sample); | |
875 | sample = sigma_deinterlace_200mhz_data(item16, 2); | |
876 | store_sr_sample(samples, send_count++, sample); | |
877 | sample = sigma_deinterlace_200mhz_data(item16, 3); | |
878 | store_sr_sample(samples, send_count++, sample); | |
879 | } else if (devc->cur_samplerate == SR_MHZ(100)) { | |
880 | sample = sigma_deinterlace_100mhz_data(item16, 0); | |
881 | store_sr_sample(samples, send_count++, sample); | |
882 | sample = sigma_deinterlace_100mhz_data(item16, 1); | |
883 | store_sr_sample(samples, send_count++, sample); | |
884 | } else { | |
885 | sample = item16; | |
886 | store_sr_sample(samples, send_count++, sample); | |
887 | } | |
23239b5c MV |
888 | } |
889 | ||
de3f7acb GS |
890 | /* |
891 | * If a trigger position applies, then provide the datafeed with | |
892 | * the first part of data up to that position, then send the | |
893 | * trigger marker. | |
894 | */ | |
23239b5c | 895 | int trigger_offset = 0; |
1e23158b | 896 | if (triggered) { |
23239b5c MV |
897 | /* |
898 | * Trigger is not always accurate to sample because of | |
899 | * pipeline delay. However, it always triggers before | |
900 | * the actual event. We therefore look at the next | |
901 | * samples to pinpoint the exact position of the trigger. | |
902 | */ | |
903 | trigger_offset = get_trigger_offset(samples, | |
904 | ss->lastsample, &devc->trigger); | |
905 | ||
906 | if (trigger_offset > 0) { | |
85c032e4 | 907 | trig_count = trigger_offset * devc->samples_per_event; |
23239b5c | 908 | packet.type = SR_DF_LOGIC; |
85c032e4 | 909 | logic.length = trig_count * logic.unitsize; |
102f1239 | 910 | sr_session_send(sdi, &packet); |
85c032e4 GS |
911 | send_ptr += trig_count * logic.unitsize; |
912 | send_count -= trig_count; | |
23239b5c MV |
913 | } |
914 | ||
915 | /* Only send trigger if explicitly enabled. */ | |
916 | if (devc->use_triggers) { | |
917 | packet.type = SR_DF_TRIGGER; | |
102f1239 | 918 | sr_session_send(sdi, &packet); |
23239b5c MV |
919 | } |
920 | } | |
921 | ||
de3f7acb GS |
922 | /* |
923 | * Send the data after the trigger, or all of the received data | |
924 | * if no trigger position applies. | |
925 | */ | |
85c032e4 | 926 | if (send_count) { |
23239b5c | 927 | packet.type = SR_DF_LOGIC; |
85c032e4 GS |
928 | logic.length = send_count * logic.unitsize; |
929 | logic.data = send_ptr; | |
102f1239 | 930 | sr_session_send(sdi, &packet); |
23239b5c MV |
931 | } |
932 | ||
0498f743 | 933 | ss->lastsample = sample; |
23239b5c MV |
934 | } |
935 | ||
28a35d8a | 936 | /* |
fefa1800 UH |
937 | * Decode chunk of 1024 bytes, 64 clusters, 7 events per cluster. |
938 | * Each event is 20ns apart, and can contain multiple samples. | |
f78898e9 HE |
939 | * |
940 | * For 200 MHz, events contain 4 samples for each channel, spread 5 ns apart. | |
941 | * For 100 MHz, events contain 2 samples for each channel, spread 10 ns apart. | |
942 | * For 50 MHz and below, events contain one sample for each channel, | |
943 | * spread 20 ns apart. | |
28a35d8a | 944 | */ |
1e23158b MV |
945 | static int decode_chunk_ts(struct sigma_dram_line *dram_line, |
946 | uint16_t events_in_line, | |
947 | uint32_t trigger_event, | |
102f1239 | 948 | struct sr_dev_inst *sdi) |
28a35d8a | 949 | { |
3628074d | 950 | struct sigma_dram_cluster *dram_cluster; |
f06fb3e9 GS |
951 | struct dev_context *devc; |
952 | unsigned int clusters_in_line; | |
5fc01191 | 953 | unsigned int events_in_cluster; |
23239b5c | 954 | unsigned int i; |
f06fb3e9 GS |
955 | uint32_t trigger_cluster, triggered; |
956 | ||
957 | devc = sdi->priv; | |
958 | clusters_in_line = events_in_line; | |
959 | clusters_in_line += EVENTS_PER_CLUSTER - 1; | |
960 | clusters_in_line /= EVENTS_PER_CLUSTER; | |
961 | trigger_cluster = ~0; | |
962 | triggered = 0; | |
ee492173 | 963 | |
4ae1f451 | 964 | /* Check if trigger is in this chunk. */ |
1e23158b MV |
965 | if (trigger_event < (64 * 7)) { |
966 | if (devc->cur_samplerate <= SR_MHZ(50)) { | |
967 | trigger_event -= MIN(EVENTS_PER_CLUSTER - 1, | |
968 | trigger_event); | |
969 | } | |
57bbf56b | 970 | |
f3f19d11 | 971 | /* Find in which cluster the trigger occurred. */ |
1e23158b | 972 | trigger_cluster = trigger_event / EVENTS_PER_CLUSTER; |
ee492173 | 973 | } |
28a35d8a | 974 | |
5fc01191 MV |
975 | /* For each full DRAM cluster. */ |
976 | for (i = 0; i < clusters_in_line; i++) { | |
3628074d | 977 | dram_cluster = &dram_line->cluster[i]; |
5fc01191 | 978 | |
5fc01191 | 979 | /* The last cluster might not be full. */ |
23239b5c MV |
980 | if ((i == clusters_in_line - 1) && |
981 | (events_in_line % EVENTS_PER_CLUSTER)) { | |
5fc01191 | 982 | events_in_cluster = events_in_line % EVENTS_PER_CLUSTER; |
23239b5c | 983 | } else { |
5fc01191 | 984 | events_in_cluster = EVENTS_PER_CLUSTER; |
abda62ce | 985 | } |
ee492173 | 986 | |
1e23158b MV |
987 | triggered = (i == trigger_cluster); |
988 | sigma_decode_dram_cluster(dram_cluster, events_in_cluster, | |
989 | triggered, sdi); | |
28a35d8a HE |
990 | } |
991 | ||
e46b8fb1 | 992 | return SR_OK; |
28a35d8a HE |
993 | } |
994 | ||
6057d9fa | 995 | static int download_capture(struct sr_dev_inst *sdi) |
28a35d8a | 996 | { |
e15e5873 | 997 | const uint32_t chunks_per_read = 32; |
f06fb3e9 GS |
998 | |
999 | struct dev_context *devc; | |
fd830beb | 1000 | struct sigma_dram_line *dram_line; |
c6648b66 | 1001 | int bufsz; |
462fe786 | 1002 | uint32_t stoppos, triggerpos; |
6057d9fa | 1003 | uint8_t modestatus; |
c6648b66 MV |
1004 | uint32_t i; |
1005 | uint32_t dl_lines_total, dl_lines_curr, dl_lines_done; | |
f06fb3e9 GS |
1006 | uint32_t dl_events_in_line; |
1007 | uint32_t trg_line, trg_event; | |
1008 | ||
1009 | devc = sdi->priv; | |
1010 | dl_events_in_line = 64 * 7; | |
1011 | trg_line = ~0; | |
1012 | trg_event = ~0; | |
c6648b66 | 1013 | |
fd830beb MV |
1014 | dram_line = g_try_malloc0(chunks_per_read * sizeof(*dram_line)); |
1015 | if (!dram_line) | |
1016 | return FALSE; | |
1017 | ||
6868626b BV |
1018 | sr_info("Downloading sample data."); |
1019 | ||
6057d9fa MV |
1020 | /* Stop acquisition. */ |
1021 | sigma_set_register(WRITE_MODE, 0x11, devc); | |
1022 | ||
1023 | /* Set SDRAM Read Enable. */ | |
1024 | sigma_set_register(WRITE_MODE, 0x02, devc); | |
1025 | ||
1026 | /* Get the current position. */ | |
462fe786 | 1027 | sigma_read_pos(&stoppos, &triggerpos, devc); |
6057d9fa MV |
1028 | |
1029 | /* Check if trigger has fired. */ | |
1030 | modestatus = sigma_get_register(READ_MODE, devc); | |
1e23158b | 1031 | if (modestatus & 0x20) { |
c6648b66 | 1032 | trg_line = triggerpos >> 9; |
1e23158b MV |
1033 | trg_event = triggerpos & 0x1ff; |
1034 | } | |
6057d9fa | 1035 | |
c6648b66 MV |
1036 | /* |
1037 | * Determine how many 1024b "DRAM lines" do we need to read from the | |
1038 | * Sigma so we have a complete set of samples. Note that the last | |
1039 | * line can be only partial, containing less than 64 clusters. | |
1040 | */ | |
1041 | dl_lines_total = (stoppos >> 9) + 1; | |
6868626b | 1042 | |
c6648b66 | 1043 | dl_lines_done = 0; |
6868626b | 1044 | |
c6648b66 MV |
1045 | while (dl_lines_total > dl_lines_done) { |
1046 | /* We can download only up-to 32 DRAM lines in one go! */ | |
1047 | dl_lines_curr = MIN(chunks_per_read, dl_lines_total); | |
6868626b | 1048 | |
f41a4cae MV |
1049 | bufsz = sigma_read_dram(dl_lines_done, dl_lines_curr, |
1050 | (uint8_t *)dram_line, devc); | |
c6648b66 MV |
1051 | /* TODO: Check bufsz. For now, just avoid compiler warnings. */ |
1052 | (void)bufsz; | |
6868626b | 1053 | |
c6648b66 MV |
1054 | /* This is the first DRAM line, so find the initial timestamp. */ |
1055 | if (dl_lines_done == 0) { | |
3513d965 MV |
1056 | devc->state.lastts = |
1057 | sigma_dram_cluster_ts(&dram_line[0].cluster[0]); | |
c6648b66 | 1058 | devc->state.lastsample = 0; |
6868626b BV |
1059 | } |
1060 | ||
c6648b66 | 1061 | for (i = 0; i < dl_lines_curr; i++) { |
1e23158b | 1062 | uint32_t trigger_event = ~0; |
c6648b66 MV |
1063 | /* The last "DRAM line" can be only partially full. */ |
1064 | if (dl_lines_done + i == dl_lines_total - 1) | |
46641fac | 1065 | dl_events_in_line = stoppos & 0x1ff; |
c6648b66 | 1066 | |
e69ad48e | 1067 | /* Test if the trigger happened on this line. */ |
c6648b66 | 1068 | if (dl_lines_done + i == trg_line) |
1e23158b | 1069 | trigger_event = trg_event; |
e69ad48e | 1070 | |
1e23158b MV |
1071 | decode_chunk_ts(dram_line + i, dl_events_in_line, |
1072 | trigger_event, sdi); | |
c6648b66 | 1073 | } |
6868626b | 1074 | |
c6648b66 | 1075 | dl_lines_done += dl_lines_curr; |
6868626b BV |
1076 | } |
1077 | ||
bee2b016 | 1078 | std_session_send_df_end(sdi); |
6057d9fa | 1079 | |
695dc859 | 1080 | sdi->driver->dev_acquisition_stop(sdi); |
6057d9fa | 1081 | |
fd830beb MV |
1082 | g_free(dram_line); |
1083 | ||
6057d9fa | 1084 | return TRUE; |
6868626b BV |
1085 | } |
1086 | ||
d4051930 MV |
1087 | /* |
1088 | * Handle the Sigma when in CAPTURE mode. This function checks: | |
1089 | * - Sampling time ended | |
1090 | * - DRAM capacity overflow | |
1091 | * This function triggers download of the samples from Sigma | |
1092 | * in case either of the above conditions is true. | |
1093 | */ | |
1094 | static int sigma_capture_mode(struct sr_dev_inst *sdi) | |
6868626b | 1095 | { |
f06fb3e9 | 1096 | struct dev_context *devc; |
94ba4bd6 | 1097 | uint64_t running_msec; |
28a35d8a | 1098 | struct timeval tv; |
00c86508 | 1099 | uint32_t stoppos, triggerpos; |
28a35d8a | 1100 | |
f06fb3e9 GS |
1101 | devc = sdi->priv; |
1102 | ||
00c86508 | 1103 | /* Check if the selected sampling duration passed. */ |
d4051930 MV |
1104 | gettimeofday(&tv, 0); |
1105 | running_msec = (tv.tv_sec - devc->start_tv.tv_sec) * 1000 + | |
00c86508 MV |
1106 | (tv.tv_usec - devc->start_tv.tv_usec) / 1000; |
1107 | if (running_msec >= devc->limit_msec) | |
6057d9fa | 1108 | return download_capture(sdi); |
00c86508 MV |
1109 | |
1110 | /* Get the position in DRAM to which the FPGA is writing now. */ | |
1111 | sigma_read_pos(&stoppos, &triggerpos, devc); | |
1112 | /* Test if DRAM is full and if so, download the data. */ | |
1113 | if ((stoppos >> 9) == 32767) | |
6057d9fa | 1114 | return download_capture(sdi); |
28a35d8a | 1115 | |
d4051930 MV |
1116 | return TRUE; |
1117 | } | |
28a35d8a | 1118 | |
3ba56876 | 1119 | SR_PRIV int sigma_receive_data(int fd, int revents, void *cb_data) |
d4051930 MV |
1120 | { |
1121 | struct sr_dev_inst *sdi; | |
1122 | struct dev_context *devc; | |
88c51afe | 1123 | |
d4051930 MV |
1124 | (void)fd; |
1125 | (void)revents; | |
88c51afe | 1126 | |
d4051930 MV |
1127 | sdi = cb_data; |
1128 | devc = sdi->priv; | |
1129 | ||
1130 | if (devc->state.state == SIGMA_IDLE) | |
1131 | return TRUE; | |
1132 | ||
1133 | if (devc->state.state == SIGMA_CAPTURE) | |
1134 | return sigma_capture_mode(sdi); | |
28a35d8a | 1135 | |
28a35d8a HE |
1136 | return TRUE; |
1137 | } | |
1138 | ||
c53d793f HE |
1139 | /* Build a LUT entry used by the trigger functions. */ |
1140 | static void build_lut_entry(uint16_t value, uint16_t mask, uint16_t *entry) | |
ee492173 HE |
1141 | { |
1142 | int i, j, k, bit; | |
1143 | ||
ba7dd8bb | 1144 | /* For each quad channel. */ |
0a1f7b09 | 1145 | for (i = 0; i < 4; i++) { |
c53d793f | 1146 | entry[i] = 0xffff; |
ee492173 | 1147 | |
f758d074 | 1148 | /* For each bit in LUT. */ |
0a1f7b09 | 1149 | for (j = 0; j < 16; j++) |
ee492173 | 1150 | |
ba7dd8bb | 1151 | /* For each channel in quad. */ |
0a1f7b09 | 1152 | for (k = 0; k < 4; k++) { |
ee492173 HE |
1153 | bit = 1 << (i * 4 + k); |
1154 | ||
c53d793f | 1155 | /* Set bit in entry */ |
0a1f7b09 UH |
1156 | if ((mask & bit) && ((!(value & bit)) != |
1157 | (!(j & (1 << k))))) | |
c53d793f | 1158 | entry[i] &= ~(1 << j); |
ee492173 HE |
1159 | } |
1160 | } | |
c53d793f | 1161 | } |
ee492173 | 1162 | |
c53d793f HE |
1163 | /* Add a logical function to LUT mask. */ |
1164 | static void add_trigger_function(enum triggerop oper, enum triggerfunc func, | |
1165 | int index, int neg, uint16_t *mask) | |
1166 | { | |
1167 | int i, j; | |
1168 | int x[2][2], tmp, a, b, aset, bset, rset; | |
1169 | ||
1170 | memset(x, 0, 4 * sizeof(int)); | |
1171 | ||
1172 | /* Trigger detect condition. */ | |
1173 | switch (oper) { | |
1174 | case OP_LEVEL: | |
1175 | x[0][1] = 1; | |
1176 | x[1][1] = 1; | |
1177 | break; | |
1178 | case OP_NOT: | |
1179 | x[0][0] = 1; | |
1180 | x[1][0] = 1; | |
1181 | break; | |
1182 | case OP_RISE: | |
1183 | x[0][1] = 1; | |
1184 | break; | |
1185 | case OP_FALL: | |
1186 | x[1][0] = 1; | |
1187 | break; | |
1188 | case OP_RISEFALL: | |
1189 | x[0][1] = 1; | |
1190 | x[1][0] = 1; | |
1191 | break; | |
1192 | case OP_NOTRISE: | |
1193 | x[1][1] = 1; | |
1194 | x[0][0] = 1; | |
1195 | x[1][0] = 1; | |
1196 | break; | |
1197 | case OP_NOTFALL: | |
1198 | x[1][1] = 1; | |
1199 | x[0][0] = 1; | |
1200 | x[0][1] = 1; | |
1201 | break; | |
1202 | case OP_NOTRISEFALL: | |
1203 | x[1][1] = 1; | |
1204 | x[0][0] = 1; | |
1205 | break; | |
1206 | } | |
1207 | ||
1208 | /* Transpose if neg is set. */ | |
1209 | if (neg) { | |
0a1f7b09 UH |
1210 | for (i = 0; i < 2; i++) { |
1211 | for (j = 0; j < 2; j++) { | |
c53d793f | 1212 | tmp = x[i][j]; |
0a1f7b09 UH |
1213 | x[i][j] = x[1 - i][1 - j]; |
1214 | x[1 - i][1 - j] = tmp; | |
c53d793f | 1215 | } |
ea9cfed7 | 1216 | } |
c53d793f HE |
1217 | } |
1218 | ||
1219 | /* Update mask with function. */ | |
0a1f7b09 | 1220 | for (i = 0; i < 16; i++) { |
c53d793f HE |
1221 | a = (i >> (2 * index + 0)) & 1; |
1222 | b = (i >> (2 * index + 1)) & 1; | |
1223 | ||
1224 | aset = (*mask >> i) & 1; | |
1225 | bset = x[b][a]; | |
1226 | ||
382cb19f | 1227 | rset = 0; |
c53d793f HE |
1228 | if (func == FUNC_AND || func == FUNC_NAND) |
1229 | rset = aset & bset; | |
1230 | else if (func == FUNC_OR || func == FUNC_NOR) | |
1231 | rset = aset | bset; | |
1232 | else if (func == FUNC_XOR || func == FUNC_NXOR) | |
1233 | rset = aset ^ bset; | |
1234 | ||
1235 | if (func == FUNC_NAND || func == FUNC_NOR || func == FUNC_NXOR) | |
1236 | rset = !rset; | |
1237 | ||
1238 | *mask &= ~(1 << i); | |
1239 | ||
1240 | if (rset) | |
1241 | *mask |= 1 << i; | |
1242 | } | |
1243 | } | |
1244 | ||
1245 | /* | |
1246 | * Build trigger LUTs used by 50 MHz and lower sample rates for supporting | |
1247 | * simple pin change and state triggers. Only two transitions (rise/fall) can be | |
1248 | * set at any time, but a full mask and value can be set (0/1). | |
1249 | */ | |
3ba56876 | 1250 | SR_PRIV int sigma_build_basic_trigger(struct triggerlut *lut, struct dev_context *devc) |
c53d793f HE |
1251 | { |
1252 | int i,j; | |
4ae1f451 | 1253 | uint16_t masks[2] = { 0, 0 }; |
c53d793f HE |
1254 | |
1255 | memset(lut, 0, sizeof(struct triggerlut)); | |
1256 | ||
f3f19d11 | 1257 | /* Constant for simple triggers. */ |
c53d793f HE |
1258 | lut->m4 = 0xa000; |
1259 | ||
1260 | /* Value/mask trigger support. */ | |
0e1357e8 | 1261 | build_lut_entry(devc->trigger.simplevalue, devc->trigger.simplemask, |
99965709 | 1262 | lut->m2d); |
c53d793f HE |
1263 | |
1264 | /* Rise/fall trigger support. */ | |
0a1f7b09 | 1265 | for (i = 0, j = 0; i < 16; i++) { |
0e1357e8 BV |
1266 | if (devc->trigger.risingmask & (1 << i) || |
1267 | devc->trigger.fallingmask & (1 << i)) | |
c53d793f HE |
1268 | masks[j++] = 1 << i; |
1269 | } | |
1270 | ||
1271 | build_lut_entry(masks[0], masks[0], lut->m0d); | |
1272 | build_lut_entry(masks[1], masks[1], lut->m1d); | |
1273 | ||
1274 | /* Add glue logic */ | |
1275 | if (masks[0] || masks[1]) { | |
1276 | /* Transition trigger. */ | |
0e1357e8 | 1277 | if (masks[0] & devc->trigger.risingmask) |
c53d793f | 1278 | add_trigger_function(OP_RISE, FUNC_OR, 0, 0, &lut->m3); |
0e1357e8 | 1279 | if (masks[0] & devc->trigger.fallingmask) |
c53d793f | 1280 | add_trigger_function(OP_FALL, FUNC_OR, 0, 0, &lut->m3); |
0e1357e8 | 1281 | if (masks[1] & devc->trigger.risingmask) |
c53d793f | 1282 | add_trigger_function(OP_RISE, FUNC_OR, 1, 0, &lut->m3); |
0e1357e8 | 1283 | if (masks[1] & devc->trigger.fallingmask) |
c53d793f HE |
1284 | add_trigger_function(OP_FALL, FUNC_OR, 1, 0, &lut->m3); |
1285 | } else { | |
1286 | /* Only value/mask trigger. */ | |
1287 | lut->m3 = 0xffff; | |
1288 | } | |
ee492173 | 1289 | |
c53d793f | 1290 | /* Triggertype: event. */ |
ee492173 HE |
1291 | lut->params.selres = 3; |
1292 | ||
e46b8fb1 | 1293 | return SR_OK; |
ee492173 | 1294 | } |