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Commit | Line | Data |
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28a35d8a | 1 | /* |
50985c20 | 2 | * This file is part of the libsigrok project. |
28a35d8a | 3 | * |
868501fa | 4 | * Copyright (C) 2010-2012 Håvard Espeland <gus@ping.uio.no>, |
911f1834 UH |
5 | * Copyright (C) 2010 Martin Stensgård <mastensg@ping.uio.no> |
6 | * Copyright (C) 2010 Carl Henrik Lunde <chlunde@ping.uio.no> | |
28a35d8a HE |
7 | * |
8 | * This program is free software: you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation, either version 3 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
20 | */ | |
21 | ||
911f1834 | 22 | /* |
6352d030 | 23 | * ASIX SIGMA/SIGMA2 logic analyzer driver |
911f1834 UH |
24 | */ |
25 | ||
6ec6c43b | 26 | #include <config.h> |
3ba56876 | 27 | #include "protocol.h" |
28a35d8a | 28 | |
b1648dea MV |
29 | /* |
30 | * The ASIX Sigma supports arbitrary integer frequency divider in | |
31 | * the 50MHz mode. The divider is in range 1...256 , allowing for | |
32 | * very precise sampling rate selection. This driver supports only | |
33 | * a subset of the sampling rates. | |
34 | */ | |
3ba56876 | 35 | SR_PRIV const uint64_t samplerates[] = { |
b1648dea MV |
36 | SR_KHZ(200), /* div=250 */ |
37 | SR_KHZ(250), /* div=200 */ | |
38 | SR_KHZ(500), /* div=100 */ | |
39 | SR_MHZ(1), /* div=50 */ | |
40 | SR_MHZ(5), /* div=10 */ | |
41 | SR_MHZ(10), /* div=5 */ | |
42 | SR_MHZ(25), /* div=2 */ | |
43 | SR_MHZ(50), /* div=1 */ | |
44 | SR_MHZ(100), /* Special FW needed */ | |
45 | SR_MHZ(200), /* Special FW needed */ | |
28a35d8a HE |
46 | }; |
47 | ||
4154a516 | 48 | SR_PRIV const size_t samplerates_count = ARRAY_SIZE(samplerates); |
39c64c6a | 49 | |
8e2d6c9d | 50 | static const char sigma_firmware_files[][24] = { |
499b17e9 | 51 | /* 50 MHz, supports 8 bit fractions */ |
8e2d6c9d | 52 | "asix-sigma-50.fw", |
499b17e9 | 53 | /* 100 MHz */ |
8e2d6c9d | 54 | "asix-sigma-100.fw", |
499b17e9 | 55 | /* 200 MHz */ |
8e2d6c9d | 56 | "asix-sigma-200.fw", |
499b17e9 | 57 | /* Synchronous clock from pin */ |
8e2d6c9d | 58 | "asix-sigma-50sync.fw", |
499b17e9 | 59 | /* Frequency counter */ |
8e2d6c9d | 60 | "asix-sigma-phasor.fw", |
f6564c8d HE |
61 | }; |
62 | ||
0e1357e8 | 63 | static int sigma_read(void *buf, size_t size, struct dev_context *devc) |
28a35d8a HE |
64 | { |
65 | int ret; | |
fefa1800 | 66 | |
0e1357e8 | 67 | ret = ftdi_read_data(&devc->ftdic, (unsigned char *)buf, size); |
28a35d8a | 68 | if (ret < 0) { |
47f4f073 | 69 | sr_err("ftdi_read_data failed: %s", |
0e1357e8 | 70 | ftdi_get_error_string(&devc->ftdic)); |
28a35d8a HE |
71 | } |
72 | ||
73 | return ret; | |
74 | } | |
75 | ||
0e1357e8 | 76 | static int sigma_write(void *buf, size_t size, struct dev_context *devc) |
28a35d8a HE |
77 | { |
78 | int ret; | |
fefa1800 | 79 | |
0e1357e8 | 80 | ret = ftdi_write_data(&devc->ftdic, (unsigned char *)buf, size); |
28a35d8a | 81 | if (ret < 0) { |
47f4f073 | 82 | sr_err("ftdi_write_data failed: %s", |
0e1357e8 | 83 | ftdi_get_error_string(&devc->ftdic)); |
fefa1800 | 84 | } else if ((size_t) ret != size) { |
47f4f073 | 85 | sr_err("ftdi_write_data did not complete write."); |
28a35d8a HE |
86 | } |
87 | ||
88 | return ret; | |
89 | } | |
90 | ||
e8686e3a AG |
91 | /* |
92 | * NOTE: We chose the buffer size to be large enough to hold any write to the | |
93 | * device. We still print a message just in case. | |
94 | */ | |
3ba56876 | 95 | SR_PRIV int sigma_write_register(uint8_t reg, uint8_t *data, size_t len, |
96 | struct dev_context *devc) | |
28a35d8a HE |
97 | { |
98 | size_t i; | |
e8686e3a | 99 | uint8_t buf[80]; |
28a35d8a HE |
100 | int idx = 0; |
101 | ||
7c86d853 | 102 | if ((2 * len + 2) > sizeof(buf)) { |
e8686e3a | 103 | sr_err("Attempted to write %zu bytes, but buffer is too small.", |
7c86d853 | 104 | len); |
e8686e3a AG |
105 | return SR_ERR_BUG; |
106 | } | |
107 | ||
28a35d8a HE |
108 | buf[idx++] = REG_ADDR_LOW | (reg & 0xf); |
109 | buf[idx++] = REG_ADDR_HIGH | (reg >> 4); | |
110 | ||
0a1f7b09 | 111 | for (i = 0; i < len; i++) { |
28a35d8a HE |
112 | buf[idx++] = REG_DATA_LOW | (data[i] & 0xf); |
113 | buf[idx++] = REG_DATA_HIGH_WRITE | (data[i] >> 4); | |
114 | } | |
115 | ||
0e1357e8 | 116 | return sigma_write(buf, idx, devc); |
28a35d8a HE |
117 | } |
118 | ||
3ba56876 | 119 | SR_PRIV int sigma_set_register(uint8_t reg, uint8_t value, struct dev_context *devc) |
28a35d8a | 120 | { |
0e1357e8 | 121 | return sigma_write_register(reg, &value, 1, devc); |
28a35d8a HE |
122 | } |
123 | ||
99965709 | 124 | static int sigma_read_register(uint8_t reg, uint8_t *data, size_t len, |
0e1357e8 | 125 | struct dev_context *devc) |
28a35d8a HE |
126 | { |
127 | uint8_t buf[3]; | |
fefa1800 | 128 | |
28a35d8a HE |
129 | buf[0] = REG_ADDR_LOW | (reg & 0xf); |
130 | buf[1] = REG_ADDR_HIGH | (reg >> 4); | |
28a35d8a HE |
131 | buf[2] = REG_READ_ADDR; |
132 | ||
0e1357e8 | 133 | sigma_write(buf, sizeof(buf), devc); |
28a35d8a | 134 | |
0e1357e8 | 135 | return sigma_read(data, len, devc); |
28a35d8a HE |
136 | } |
137 | ||
0e1357e8 | 138 | static uint8_t sigma_get_register(uint8_t reg, struct dev_context *devc) |
28a35d8a HE |
139 | { |
140 | uint8_t value; | |
fefa1800 | 141 | |
0e1357e8 | 142 | if (1 != sigma_read_register(reg, &value, 1, devc)) { |
47f4f073 | 143 | sr_err("sigma_get_register: 1 byte expected"); |
28a35d8a HE |
144 | return 0; |
145 | } | |
146 | ||
147 | return value; | |
148 | } | |
149 | ||
99965709 | 150 | static int sigma_read_pos(uint32_t *stoppos, uint32_t *triggerpos, |
0e1357e8 | 151 | struct dev_context *devc) |
28a35d8a HE |
152 | { |
153 | uint8_t buf[] = { | |
154 | REG_ADDR_LOW | READ_TRIGGER_POS_LOW, | |
155 | ||
156 | REG_READ_ADDR | NEXT_REG, | |
157 | REG_READ_ADDR | NEXT_REG, | |
158 | REG_READ_ADDR | NEXT_REG, | |
159 | REG_READ_ADDR | NEXT_REG, | |
160 | REG_READ_ADDR | NEXT_REG, | |
161 | REG_READ_ADDR | NEXT_REG, | |
162 | }; | |
28a35d8a HE |
163 | uint8_t result[6]; |
164 | ||
0e1357e8 | 165 | sigma_write(buf, sizeof(buf), devc); |
28a35d8a | 166 | |
0e1357e8 | 167 | sigma_read(result, sizeof(result), devc); |
28a35d8a HE |
168 | |
169 | *triggerpos = result[0] | (result[1] << 8) | (result[2] << 16); | |
170 | *stoppos = result[3] | (result[4] << 8) | (result[5] << 16); | |
171 | ||
57bbf56b HE |
172 | /* Not really sure why this must be done, but according to spec. */ |
173 | if ((--*stoppos & 0x1ff) == 0x1ff) | |
382cb19f | 174 | *stoppos -= 64; |
57bbf56b HE |
175 | |
176 | if ((*--triggerpos & 0x1ff) == 0x1ff) | |
382cb19f | 177 | *triggerpos -= 64; |
57bbf56b | 178 | |
28a35d8a HE |
179 | return 1; |
180 | } | |
181 | ||
99965709 | 182 | static int sigma_read_dram(uint16_t startchunk, size_t numchunks, |
0e1357e8 | 183 | uint8_t *data, struct dev_context *devc) |
28a35d8a HE |
184 | { |
185 | size_t i; | |
186 | uint8_t buf[4096]; | |
f06fb3e9 | 187 | int idx; |
28a35d8a | 188 | |
fefa1800 | 189 | /* Send the startchunk. Index start with 1. */ |
f06fb3e9 GS |
190 | idx = 0; |
191 | buf[idx++] = startchunk >> 8; | |
192 | buf[idx++] = startchunk & 0xff; | |
193 | sigma_write_register(WRITE_MEMROW, buf, idx, devc); | |
28a35d8a | 194 | |
fefa1800 | 195 | /* Read the DRAM. */ |
f06fb3e9 | 196 | idx = 0; |
28a35d8a HE |
197 | buf[idx++] = REG_DRAM_BLOCK; |
198 | buf[idx++] = REG_DRAM_WAIT_ACK; | |
199 | ||
0a1f7b09 | 200 | for (i = 0; i < numchunks; i++) { |
fefa1800 UH |
201 | /* Alternate bit to copy from DRAM to cache. */ |
202 | if (i != (numchunks - 1)) | |
203 | buf[idx++] = REG_DRAM_BLOCK | (((i + 1) % 2) << 4); | |
28a35d8a HE |
204 | |
205 | buf[idx++] = REG_DRAM_BLOCK_DATA | ((i % 2) << 4); | |
206 | ||
fefa1800 | 207 | if (i != (numchunks - 1)) |
28a35d8a HE |
208 | buf[idx++] = REG_DRAM_WAIT_ACK; |
209 | } | |
210 | ||
0e1357e8 | 211 | sigma_write(buf, idx, devc); |
28a35d8a | 212 | |
0e1357e8 | 213 | return sigma_read(data, numchunks * CHUNK_SIZE, devc); |
28a35d8a HE |
214 | } |
215 | ||
4ae1f451 | 216 | /* Upload trigger look-up tables to Sigma. */ |
3ba56876 | 217 | SR_PRIV int sigma_write_trigger_lut(struct triggerlut *lut, struct dev_context *devc) |
ee492173 HE |
218 | { |
219 | int i; | |
220 | uint8_t tmp[2]; | |
221 | uint16_t bit; | |
222 | ||
223 | /* Transpose the table and send to Sigma. */ | |
0a1f7b09 | 224 | for (i = 0; i < 16; i++) { |
ee492173 HE |
225 | bit = 1 << i; |
226 | ||
227 | tmp[0] = tmp[1] = 0; | |
228 | ||
229 | if (lut->m2d[0] & bit) | |
230 | tmp[0] |= 0x01; | |
231 | if (lut->m2d[1] & bit) | |
232 | tmp[0] |= 0x02; | |
233 | if (lut->m2d[2] & bit) | |
234 | tmp[0] |= 0x04; | |
235 | if (lut->m2d[3] & bit) | |
236 | tmp[0] |= 0x08; | |
237 | ||
238 | if (lut->m3 & bit) | |
239 | tmp[0] |= 0x10; | |
240 | if (lut->m3s & bit) | |
241 | tmp[0] |= 0x20; | |
242 | if (lut->m4 & bit) | |
243 | tmp[0] |= 0x40; | |
244 | ||
245 | if (lut->m0d[0] & bit) | |
246 | tmp[1] |= 0x01; | |
247 | if (lut->m0d[1] & bit) | |
248 | tmp[1] |= 0x02; | |
249 | if (lut->m0d[2] & bit) | |
250 | tmp[1] |= 0x04; | |
251 | if (lut->m0d[3] & bit) | |
252 | tmp[1] |= 0x08; | |
253 | ||
254 | if (lut->m1d[0] & bit) | |
255 | tmp[1] |= 0x10; | |
256 | if (lut->m1d[1] & bit) | |
257 | tmp[1] |= 0x20; | |
258 | if (lut->m1d[2] & bit) | |
259 | tmp[1] |= 0x40; | |
260 | if (lut->m1d[3] & bit) | |
261 | tmp[1] |= 0x80; | |
262 | ||
99965709 | 263 | sigma_write_register(WRITE_TRIGGER_SELECT0, tmp, sizeof(tmp), |
0e1357e8 BV |
264 | devc); |
265 | sigma_set_register(WRITE_TRIGGER_SELECT1, 0x30 | i, devc); | |
ee492173 HE |
266 | } |
267 | ||
268 | /* Send the parameters */ | |
269 | sigma_write_register(WRITE_TRIGGER_SELECT0, (uint8_t *) &lut->params, | |
0e1357e8 | 270 | sizeof(lut->params), devc); |
ee492173 | 271 | |
e46b8fb1 | 272 | return SR_OK; |
ee492173 HE |
273 | } |
274 | ||
3ba56876 | 275 | SR_PRIV void sigma_clear_helper(void *priv) |
0448d110 | 276 | { |
0e1357e8 | 277 | struct dev_context *devc; |
ce4d26dd | 278 | |
3678cf73 | 279 | devc = priv; |
0e1357e8 | 280 | |
3678cf73 UH |
281 | ftdi_deinit(&devc->ftdic); |
282 | } | |
0448d110 | 283 | |
d5fa188a MV |
284 | /* |
285 | * Configure the FPGA for bitbang mode. | |
286 | * This sequence is documented in section 2. of the ASIX Sigma programming | |
287 | * manual. This sequence is necessary to configure the FPGA in the Sigma | |
288 | * into Bitbang mode, in which it can be programmed with the firmware. | |
289 | */ | |
290 | static int sigma_fpga_init_bitbang(struct dev_context *devc) | |
291 | { | |
292 | uint8_t suicide[] = { | |
293 | 0x84, 0x84, 0x88, 0x84, 0x88, 0x84, 0x88, 0x84, | |
294 | }; | |
295 | uint8_t init_array[] = { | |
296 | 0x01, 0x03, 0x03, 0x01, 0x01, 0x01, 0x01, 0x01, | |
297 | 0x01, 0x01, | |
298 | }; | |
1a46cc62 | 299 | int i, ret, timeout = (10 * 1000); |
d5fa188a MV |
300 | uint8_t data; |
301 | ||
302 | /* Section 2. part 1), do the FPGA suicide. */ | |
303 | sigma_write(suicide, sizeof(suicide), devc); | |
304 | sigma_write(suicide, sizeof(suicide), devc); | |
305 | sigma_write(suicide, sizeof(suicide), devc); | |
306 | sigma_write(suicide, sizeof(suicide), devc); | |
307 | ||
308 | /* Section 2. part 2), do pulse on D1. */ | |
309 | sigma_write(init_array, sizeof(init_array), devc); | |
310 | ftdi_usb_purge_buffers(&devc->ftdic); | |
311 | ||
312 | /* Wait until the FPGA asserts D6/INIT_B. */ | |
313 | for (i = 0; i < timeout; i++) { | |
314 | ret = sigma_read(&data, 1, devc); | |
315 | if (ret < 0) | |
316 | return ret; | |
317 | /* Test if pin D6 got asserted. */ | |
318 | if (data & (1 << 5)) | |
319 | return 0; | |
320 | /* The D6 was not asserted yet, wait a bit. */ | |
1a46cc62 | 321 | g_usleep(10 * 1000); |
d5fa188a MV |
322 | } |
323 | ||
324 | return SR_ERR_TIMEOUT; | |
325 | } | |
326 | ||
64fe661b MV |
327 | /* |
328 | * Configure the FPGA for logic-analyzer mode. | |
329 | */ | |
330 | static int sigma_fpga_init_la(struct dev_context *devc) | |
331 | { | |
332 | /* Initialize the logic analyzer mode. */ | |
22f64ed8 | 333 | uint8_t mode_regval = WMR_SDRAMINIT; |
64fe661b | 334 | uint8_t logic_mode_start[] = { |
011f1091 | 335 | REG_ADDR_LOW | (READ_ID & 0xf), |
84a6ed1a | 336 | REG_ADDR_HIGH | (READ_ID >> 4), |
011f1091 MV |
337 | REG_READ_ADDR, /* Read ID register. */ |
338 | ||
339 | REG_ADDR_LOW | (WRITE_TEST & 0xf), | |
340 | REG_DATA_LOW | 0x5, | |
341 | REG_DATA_HIGH_WRITE | 0x5, | |
342 | REG_READ_ADDR, /* Read scratch register. */ | |
343 | ||
344 | REG_DATA_LOW | 0xa, | |
345 | REG_DATA_HIGH_WRITE | 0xa, | |
346 | REG_READ_ADDR, /* Read scratch register. */ | |
347 | ||
348 | REG_ADDR_LOW | (WRITE_MODE & 0xf), | |
22f64ed8 GS |
349 | REG_DATA_LOW | (mode_regval & 0xf), |
350 | REG_DATA_HIGH_WRITE | (mode_regval >> 4), | |
64fe661b MV |
351 | }; |
352 | ||
353 | uint8_t result[3]; | |
354 | int ret; | |
355 | ||
356 | /* Initialize the logic analyzer mode. */ | |
357 | sigma_write(logic_mode_start, sizeof(logic_mode_start), devc); | |
358 | ||
011f1091 | 359 | /* Expect a 3 byte reply since we issued three READ requests. */ |
64fe661b MV |
360 | ret = sigma_read(result, 3, devc); |
361 | if (ret != 3) | |
362 | goto err; | |
363 | ||
364 | if (result[0] != 0xa6 || result[1] != 0x55 || result[2] != 0xaa) | |
365 | goto err; | |
366 | ||
367 | return SR_OK; | |
368 | err: | |
369 | sr_err("Configuration failed. Invalid reply received."); | |
370 | return SR_ERR; | |
371 | } | |
372 | ||
a80226bb MV |
373 | /* |
374 | * Read the firmware from a file and transform it into a series of bitbang | |
375 | * pulses used to program the FPGA. Note that the *bb_cmd must be free()'d | |
376 | * by the caller of this function. | |
377 | */ | |
8e2d6c9d | 378 | static int sigma_fw_2_bitbang(struct sr_context *ctx, const char *name, |
a80226bb MV |
379 | uint8_t **bb_cmd, gsize *bb_cmd_size) |
380 | { | |
8e2d6c9d DE |
381 | size_t i, file_size, bb_size; |
382 | char *firmware; | |
a80226bb MV |
383 | uint8_t *bb_stream, *bbs; |
384 | uint32_t imm; | |
385 | int bit, v; | |
386 | int ret = SR_OK; | |
387 | ||
387825dc | 388 | /* Retrieve the on-disk firmware file content. */ |
8e2d6c9d DE |
389 | firmware = sr_resource_load(ctx, SR_RESOURCE_FIRMWARE, |
390 | name, &file_size, 256 * 1024); | |
391 | if (!firmware) | |
392 | return SR_ERR; | |
a80226bb | 393 | |
387825dc | 394 | /* Unscramble the file content (XOR with "random" sequence). */ |
a80226bb MV |
395 | imm = 0x3f6df2ab; |
396 | for (i = 0; i < file_size; i++) { | |
397 | imm = (imm + 0xa853753) % 177 + (imm * 0x8034052); | |
398 | firmware[i] ^= imm & 0xff; | |
399 | } | |
400 | ||
401 | /* | |
387825dc GS |
402 | * Generate a sequence of bitbang samples. With two samples per |
403 | * FPGA configuration bit, providing the level for the DIN signal | |
404 | * as well as two edges for CCLK. See Xilinx UG332 for details | |
405 | * ("slave serial" mode). | |
406 | * | |
407 | * Note that CCLK is inverted in hardware. That's why the | |
408 | * respective bit is first set and then cleared in the bitbang | |
409 | * sample sets. So that the DIN level will be stable when the | |
410 | * data gets sampled at the rising CCLK edge, and the signals' | |
411 | * setup time constraint will be met. | |
412 | * | |
413 | * The caller will put the FPGA into download mode, will send | |
414 | * the bitbang samples, and release the allocated memory. | |
a80226bb | 415 | */ |
a80226bb MV |
416 | bb_size = file_size * 8 * 2; |
417 | bb_stream = (uint8_t *)g_try_malloc(bb_size); | |
418 | if (!bb_stream) { | |
419 | sr_err("%s: Failed to allocate bitbang stream", __func__); | |
420 | ret = SR_ERR_MALLOC; | |
421 | goto exit; | |
422 | } | |
a80226bb MV |
423 | bbs = bb_stream; |
424 | for (i = 0; i < file_size; i++) { | |
425 | for (bit = 7; bit >= 0; bit--) { | |
426 | v = (firmware[i] & (1 << bit)) ? 0x40 : 0x00; | |
427 | *bbs++ = v | 0x01; | |
428 | *bbs++ = v; | |
429 | } | |
430 | } | |
431 | ||
432 | /* The transformation completed successfully, return the result. */ | |
433 | *bb_cmd = bb_stream; | |
434 | *bb_cmd_size = bb_size; | |
435 | ||
436 | exit: | |
8e2d6c9d | 437 | g_free(firmware); |
a80226bb MV |
438 | return ret; |
439 | } | |
440 | ||
8e2d6c9d DE |
441 | static int upload_firmware(struct sr_context *ctx, |
442 | int firmware_idx, struct dev_context *devc) | |
28a35d8a HE |
443 | { |
444 | int ret; | |
445 | unsigned char *buf; | |
446 | unsigned char pins; | |
447 | size_t buf_size; | |
a9016883 GS |
448 | const char *firmware; |
449 | struct ftdi_context *ftdic; | |
450 | ||
451 | /* Avoid downloading the same firmware multiple times. */ | |
452 | firmware = sigma_firmware_files[firmware_idx]; | |
453 | if (devc->cur_firmware == firmware_idx) { | |
454 | sr_info("Not uploading firmware file '%s' again.", firmware); | |
455 | return SR_OK; | |
456 | } | |
28a35d8a | 457 | |
fefa1800 | 458 | /* Make sure it's an ASIX SIGMA. */ |
a9016883 | 459 | ftdic = &devc->ftdic; |
8bbf7627 MV |
460 | ret = ftdi_usb_open_desc(ftdic, USB_VENDOR, USB_PRODUCT, |
461 | USB_DESCRIPTION, NULL); | |
462 | if (ret < 0) { | |
47f4f073 | 463 | sr_err("ftdi_usb_open failed: %s", |
8bbf7627 | 464 | ftdi_get_error_string(ftdic)); |
28a35d8a HE |
465 | return 0; |
466 | } | |
467 | ||
8bbf7627 MV |
468 | ret = ftdi_set_bitmode(ftdic, 0xdf, BITMODE_BITBANG); |
469 | if (ret < 0) { | |
47f4f073 | 470 | sr_err("ftdi_set_bitmode failed: %s", |
8bbf7627 | 471 | ftdi_get_error_string(ftdic)); |
28a35d8a HE |
472 | return 0; |
473 | } | |
474 | ||
fefa1800 | 475 | /* Four times the speed of sigmalogan - Works well. */ |
1a46cc62 | 476 | ret = ftdi_set_baudrate(ftdic, 750 * 1000); |
8bbf7627 | 477 | if (ret < 0) { |
47f4f073 | 478 | sr_err("ftdi_set_baudrate failed: %s", |
8bbf7627 | 479 | ftdi_get_error_string(ftdic)); |
28a35d8a HE |
480 | return 0; |
481 | } | |
482 | ||
d5fa188a MV |
483 | /* Initialize the FPGA for firmware upload. */ |
484 | ret = sigma_fpga_init_bitbang(devc); | |
485 | if (ret) | |
486 | return ret; | |
28a35d8a | 487 | |
9ddb2a12 | 488 | /* Prepare firmware. */ |
8e2d6c9d | 489 | ret = sigma_fw_2_bitbang(ctx, firmware, &buf, &buf_size); |
8bbf7627 | 490 | if (ret != SR_OK) { |
f3f19d11 | 491 | sr_err("An error occurred while reading the firmware: %s", |
499b17e9 | 492 | firmware); |
b53738ba | 493 | return ret; |
28a35d8a HE |
494 | } |
495 | ||
f3f19d11 | 496 | /* Upload firmware. */ |
499b17e9 | 497 | sr_info("Uploading firmware file '%s'.", firmware); |
0e1357e8 | 498 | sigma_write(buf, buf_size, devc); |
28a35d8a HE |
499 | |
500 | g_free(buf); | |
501 | ||
8bbf7627 MV |
502 | ret = ftdi_set_bitmode(ftdic, 0x00, BITMODE_RESET); |
503 | if (ret < 0) { | |
47f4f073 | 504 | sr_err("ftdi_set_bitmode failed: %s", |
8bbf7627 | 505 | ftdi_get_error_string(ftdic)); |
e46b8fb1 | 506 | return SR_ERR; |
28a35d8a HE |
507 | } |
508 | ||
8bbf7627 | 509 | ftdi_usb_purge_buffers(ftdic); |
28a35d8a | 510 | |
fefa1800 | 511 | /* Discard garbage. */ |
29b66a2e | 512 | while (sigma_read(&pins, 1, devc) == 1) |
28a35d8a HE |
513 | ; |
514 | ||
64fe661b MV |
515 | /* Initialize the FPGA for logic-analyzer mode. */ |
516 | ret = sigma_fpga_init_la(devc); | |
517 | if (ret != SR_OK) | |
518 | return ret; | |
28a35d8a | 519 | |
0e1357e8 | 520 | devc->cur_firmware = firmware_idx; |
f6564c8d | 521 | |
47f4f073 | 522 | sr_info("Firmware uploaded."); |
e3fff420 | 523 | |
e46b8fb1 | 524 | return SR_OK; |
f6564c8d HE |
525 | } |
526 | ||
9a0a606a GS |
527 | /* |
528 | * Sigma doesn't support limiting the number of samples, so we have to | |
529 | * translate the number and the samplerate to an elapsed time. | |
530 | * | |
531 | * In addition we need to ensure that the last data cluster has passed | |
532 | * the hardware pipeline, and became available to the PC side. With RLE | |
533 | * compression up to 327ms could pass before another cluster accumulates | |
534 | * at 200kHz samplerate when input pins don't change. | |
535 | */ | |
536 | SR_PRIV uint64_t sigma_limit_samples_to_msec(const struct dev_context *devc, | |
537 | uint64_t limit_samples) | |
538 | { | |
539 | uint64_t limit_msec; | |
540 | uint64_t worst_cluster_time_ms; | |
541 | ||
542 | limit_msec = limit_samples * 1000 / devc->cur_samplerate; | |
543 | worst_cluster_time_ms = 65536 * 1000 / devc->cur_samplerate; | |
544 | /* | |
545 | * One cluster time is not enough to flush pipeline when sampling | |
546 | * grounded pins with 1 sample limit at 200kHz. Hence the 2* fix. | |
547 | */ | |
548 | return limit_msec + 2 * worst_cluster_time_ms; | |
549 | } | |
550 | ||
3ba56876 | 551 | SR_PRIV int sigma_set_samplerate(const struct sr_dev_inst *sdi, uint64_t samplerate) |
f6564c8d | 552 | { |
2c9c0df8 | 553 | struct dev_context *devc; |
8e2d6c9d | 554 | struct drv_context *drvc; |
4154a516 | 555 | size_t i; |
2c9c0df8 | 556 | int ret; |
f6564c8d | 557 | |
2c9c0df8 | 558 | devc = sdi->priv; |
8e2d6c9d | 559 | drvc = sdi->driver->context; |
f4abaa9f UH |
560 | ret = SR_OK; |
561 | ||
2f7e529c | 562 | /* Reject rates that are not in the list of supported rates. */ |
4154a516 | 563 | for (i = 0; i < samplerates_count; i++) { |
2c9c0df8 | 564 | if (samplerates[i] == samplerate) |
f6564c8d HE |
565 | break; |
566 | } | |
4154a516 | 567 | if (i >= samplerates_count || samplerates[i] == 0) |
e46b8fb1 | 568 | return SR_ERR_SAMPLERATE; |
f6564c8d | 569 | |
2f7e529c GS |
570 | /* |
571 | * Depending on the samplerates of 200/100/50- MHz, specific | |
572 | * firmware is required and higher rates might limit the set | |
573 | * of available channels. | |
574 | */ | |
59df0c77 | 575 | if (samplerate <= SR_MHZ(50)) { |
8e2d6c9d | 576 | ret = upload_firmware(drvc->sr_ctx, 0, devc); |
ba7dd8bb | 577 | devc->num_channels = 16; |
6b2d3385 | 578 | } else if (samplerate == SR_MHZ(100)) { |
8e2d6c9d | 579 | ret = upload_firmware(drvc->sr_ctx, 1, devc); |
ba7dd8bb | 580 | devc->num_channels = 8; |
6b2d3385 | 581 | } else if (samplerate == SR_MHZ(200)) { |
8e2d6c9d | 582 | ret = upload_firmware(drvc->sr_ctx, 2, devc); |
ba7dd8bb | 583 | devc->num_channels = 4; |
f78898e9 | 584 | } |
f6564c8d | 585 | |
2f7e529c GS |
586 | /* |
587 | * Derive the sample period from the sample rate as well as the | |
588 | * number of samples that the device will communicate within | |
589 | * an "event" (memory organization internal to the device). | |
590 | */ | |
6b2d3385 BV |
591 | if (ret == SR_OK) { |
592 | devc->cur_samplerate = samplerate; | |
593 | devc->period_ps = 1000000000000ULL / samplerate; | |
594 | devc->samples_per_event = 16 / devc->num_channels; | |
595 | devc->state.state = SIGMA_IDLE; | |
596 | } | |
f6564c8d | 597 | |
2f7e529c GS |
598 | /* |
599 | * Support for "limit_samples" is implemented by stopping | |
600 | * acquisition after a corresponding period of time. | |
601 | * Re-calculate that period of time, in case the limit is | |
602 | * set first and the samplerate gets (re-)configured later. | |
603 | */ | |
604 | if (ret == SR_OK && devc->limit_samples) { | |
605 | uint64_t msecs; | |
9a0a606a | 606 | msecs = sigma_limit_samples_to_msec(devc, devc->limit_samples); |
2f7e529c GS |
607 | devc->limit_msec = msecs; |
608 | } | |
609 | ||
e8397563 | 610 | return ret; |
28a35d8a HE |
611 | } |
612 | ||
c53d793f HE |
613 | /* |
614 | * In 100 and 200 MHz mode, only a single pin rising/falling can be | |
615 | * set as trigger. In other modes, two rising/falling triggers can be set, | |
ba7dd8bb | 616 | * in addition to value/mask trigger for any number of channels. |
c53d793f HE |
617 | * |
618 | * The Sigma supports complex triggers using boolean expressions, but this | |
619 | * has not been implemented yet. | |
620 | */ | |
3ba56876 | 621 | SR_PRIV int sigma_convert_trigger(const struct sr_dev_inst *sdi) |
57bbf56b | 622 | { |
39c64c6a BV |
623 | struct dev_context *devc; |
624 | struct sr_trigger *trigger; | |
625 | struct sr_trigger_stage *stage; | |
626 | struct sr_trigger_match *match; | |
627 | const GSList *l, *m; | |
628 | int channelbit, trigger_set; | |
57bbf56b | 629 | |
39c64c6a | 630 | devc = sdi->priv; |
0e1357e8 | 631 | memset(&devc->trigger, 0, sizeof(struct sigma_trigger)); |
0812c40e | 632 | if (!(trigger = sr_session_trigger_get(sdi->session))) |
39c64c6a BV |
633 | return SR_OK; |
634 | ||
635 | trigger_set = 0; | |
636 | for (l = trigger->stages; l; l = l->next) { | |
637 | stage = l->data; | |
638 | for (m = stage->matches; m; m = m->next) { | |
639 | match = m->data; | |
640 | if (!match->channel->enabled) | |
641 | /* Ignore disabled channels with a trigger. */ | |
642 | continue; | |
643 | channelbit = 1 << (match->channel->index); | |
644 | if (devc->cur_samplerate >= SR_MHZ(100)) { | |
645 | /* Fast trigger support. */ | |
646 | if (trigger_set) { | |
647 | sr_err("Only a single pin trigger is " | |
648 | "supported in 100 and 200MHz mode."); | |
649 | return SR_ERR; | |
650 | } | |
651 | if (match->match == SR_TRIGGER_FALLING) | |
652 | devc->trigger.fallingmask |= channelbit; | |
653 | else if (match->match == SR_TRIGGER_RISING) | |
654 | devc->trigger.risingmask |= channelbit; | |
655 | else { | |
656 | sr_err("Only rising/falling trigger is " | |
657 | "supported in 100 and 200MHz mode."); | |
658 | return SR_ERR; | |
659 | } | |
eec5275e | 660 | |
0a1f7b09 | 661 | trigger_set++; |
39c64c6a BV |
662 | } else { |
663 | /* Simple trigger support (event). */ | |
664 | if (match->match == SR_TRIGGER_ONE) { | |
665 | devc->trigger.simplevalue |= channelbit; | |
666 | devc->trigger.simplemask |= channelbit; | |
667 | } | |
668 | else if (match->match == SR_TRIGGER_ZERO) { | |
669 | devc->trigger.simplevalue &= ~channelbit; | |
670 | devc->trigger.simplemask |= channelbit; | |
671 | } | |
672 | else if (match->match == SR_TRIGGER_FALLING) { | |
673 | devc->trigger.fallingmask |= channelbit; | |
0a1f7b09 | 674 | trigger_set++; |
39c64c6a BV |
675 | } |
676 | else if (match->match == SR_TRIGGER_RISING) { | |
677 | devc->trigger.risingmask |= channelbit; | |
0a1f7b09 | 678 | trigger_set++; |
39c64c6a BV |
679 | } |
680 | ||
681 | /* | |
682 | * Actually, Sigma supports 2 rising/falling triggers, | |
683 | * but they are ORed and the current trigger syntax | |
684 | * does not permit ORed triggers. | |
685 | */ | |
686 | if (trigger_set > 1) { | |
687 | sr_err("Only 1 rising/falling trigger " | |
688 | "is supported."); | |
689 | return SR_ERR; | |
690 | } | |
ee492173 | 691 | } |
ee492173 | 692 | } |
57bbf56b HE |
693 | } |
694 | ||
e46b8fb1 | 695 | return SR_OK; |
57bbf56b HE |
696 | } |
697 | ||
a1c743fc | 698 | |
36b1c8e6 | 699 | /* Software trigger to determine exact trigger position. */ |
5fc01191 | 700 | static int get_trigger_offset(uint8_t *samples, uint16_t last_sample, |
36b1c8e6 HE |
701 | struct sigma_trigger *t) |
702 | { | |
703 | int i; | |
5fc01191 | 704 | uint16_t sample = 0; |
36b1c8e6 | 705 | |
0a1f7b09 | 706 | for (i = 0; i < 8; i++) { |
36b1c8e6 | 707 | if (i > 0) |
5fc01191 MV |
708 | last_sample = sample; |
709 | sample = samples[2 * i] | (samples[2 * i + 1] << 8); | |
36b1c8e6 HE |
710 | |
711 | /* Simple triggers. */ | |
5fc01191 | 712 | if ((sample & t->simplemask) != t->simplevalue) |
36b1c8e6 HE |
713 | continue; |
714 | ||
715 | /* Rising edge. */ | |
5fc01191 MV |
716 | if (((last_sample & t->risingmask) != 0) || |
717 | ((sample & t->risingmask) != t->risingmask)) | |
36b1c8e6 HE |
718 | continue; |
719 | ||
720 | /* Falling edge. */ | |
bdfc7a89 | 721 | if ((last_sample & t->fallingmask) != t->fallingmask || |
5fc01191 | 722 | (sample & t->fallingmask) != 0) |
36b1c8e6 HE |
723 | continue; |
724 | ||
725 | break; | |
726 | } | |
727 | ||
728 | /* If we did not match, return original trigger pos. */ | |
729 | return i & 0x7; | |
730 | } | |
731 | ||
3513d965 MV |
732 | /* |
733 | * Return the timestamp of "DRAM cluster". | |
734 | */ | |
735 | static uint16_t sigma_dram_cluster_ts(struct sigma_dram_cluster *cluster) | |
736 | { | |
737 | return (cluster->timestamp_hi << 8) | cluster->timestamp_lo; | |
738 | } | |
739 | ||
0498f743 GS |
740 | /* |
741 | * Return one 16bit data entity of a DRAM cluster at the specified index. | |
742 | */ | |
743 | static uint16_t sigma_dram_cluster_data(struct sigma_dram_cluster *cl, int idx) | |
744 | { | |
745 | uint16_t sample; | |
746 | ||
747 | sample = 0; | |
748 | sample |= cl->samples[idx].sample_lo << 0; | |
749 | sample |= cl->samples[idx].sample_hi << 8; | |
3281cf59 | 750 | sample = (sample >> 8) | (sample << 8); |
0498f743 GS |
751 | return sample; |
752 | } | |
753 | ||
85c032e4 GS |
754 | /* |
755 | * Deinterlace sample data that was retrieved at 100MHz samplerate. | |
756 | * One 16bit item contains two samples of 8bits each. The bits of | |
757 | * multiple samples are interleaved. | |
758 | */ | |
759 | static uint16_t sigma_deinterlace_100mhz_data(uint16_t indata, int idx) | |
760 | { | |
761 | uint16_t outdata; | |
762 | ||
763 | indata >>= idx; | |
764 | outdata = 0; | |
765 | outdata |= (indata >> (0 * 2 - 0)) & (1 << 0); | |
766 | outdata |= (indata >> (1 * 2 - 1)) & (1 << 1); | |
767 | outdata |= (indata >> (2 * 2 - 2)) & (1 << 2); | |
768 | outdata |= (indata >> (3 * 2 - 3)) & (1 << 3); | |
769 | outdata |= (indata >> (4 * 2 - 4)) & (1 << 4); | |
770 | outdata |= (indata >> (5 * 2 - 5)) & (1 << 5); | |
771 | outdata |= (indata >> (6 * 2 - 6)) & (1 << 6); | |
772 | outdata |= (indata >> (7 * 2 - 7)) & (1 << 7); | |
773 | return outdata; | |
774 | } | |
775 | ||
776 | /* | |
777 | * Deinterlace sample data that was retrieved at 200MHz samplerate. | |
778 | * One 16bit item contains four samples of 4bits each. The bits of | |
779 | * multiple samples are interleaved. | |
780 | */ | |
781 | static uint16_t sigma_deinterlace_200mhz_data(uint16_t indata, int idx) | |
782 | { | |
783 | uint16_t outdata; | |
784 | ||
785 | indata >>= idx; | |
786 | outdata = 0; | |
787 | outdata |= (indata >> (0 * 4 - 0)) & (1 << 0); | |
788 | outdata |= (indata >> (1 * 4 - 1)) & (1 << 1); | |
789 | outdata |= (indata >> (2 * 4 - 2)) & (1 << 2); | |
790 | outdata |= (indata >> (3 * 4 - 3)) & (1 << 3); | |
791 | return outdata; | |
792 | } | |
793 | ||
0498f743 GS |
794 | static void store_sr_sample(uint8_t *samples, int idx, uint16_t data) |
795 | { | |
796 | samples[2 * idx + 0] = (data >> 0) & 0xff; | |
797 | samples[2 * idx + 1] = (data >> 8) & 0xff; | |
798 | } | |
799 | ||
735ed8a1 GS |
800 | /* |
801 | * Local wrapper around sr_session_send() calls. Make sure to not send | |
802 | * more samples to the session's datafeed than what was requested by a | |
803 | * previously configured (optional) sample count. | |
804 | */ | |
805 | static void sigma_session_send(struct sr_dev_inst *sdi, | |
806 | struct sr_datafeed_packet *packet) | |
807 | { | |
808 | struct dev_context *devc; | |
809 | struct sr_datafeed_logic *logic; | |
810 | uint64_t send_now; | |
811 | ||
812 | devc = sdi->priv; | |
813 | if (devc->limit_samples) { | |
814 | logic = (void *)packet->payload; | |
815 | send_now = logic->length / logic->unitsize; | |
816 | if (devc->sent_samples + send_now > devc->limit_samples) { | |
817 | send_now = devc->limit_samples - devc->sent_samples; | |
818 | logic->length = send_now * logic->unitsize; | |
819 | } | |
820 | if (!send_now) | |
821 | return; | |
822 | devc->sent_samples += send_now; | |
823 | } | |
824 | ||
825 | sr_session_send(sdi, packet); | |
826 | } | |
827 | ||
85c032e4 GS |
828 | /* |
829 | * This size translates to: event count (1K events per cluster), times | |
830 | * the sample width (unitsize, 16bits per event), times the maximum | |
831 | * number of samples per event. | |
832 | */ | |
833 | #define SAMPLES_BUFFER_SIZE (1024 * 2 * 4) | |
834 | ||
23239b5c MV |
835 | static void sigma_decode_dram_cluster(struct sigma_dram_cluster *dram_cluster, |
836 | unsigned int events_in_cluster, | |
1e23158b | 837 | unsigned int triggered, |
23239b5c MV |
838 | struct sr_dev_inst *sdi) |
839 | { | |
840 | struct dev_context *devc = sdi->priv; | |
841 | struct sigma_state *ss = &devc->state; | |
842 | struct sr_datafeed_packet packet; | |
843 | struct sr_datafeed_logic logic; | |
85c032e4 GS |
844 | uint16_t tsdiff, ts, sample, item16; |
845 | uint8_t samples[SAMPLES_BUFFER_SIZE]; | |
846 | uint8_t *send_ptr; | |
847 | size_t send_count, trig_count; | |
23239b5c | 848 | unsigned int i; |
85c032e4 | 849 | int j; |
23239b5c | 850 | |
23239b5c MV |
851 | ts = sigma_dram_cluster_ts(dram_cluster); |
852 | tsdiff = ts - ss->lastts; | |
a44b3b3f | 853 | ss->lastts = ts + EVENTS_PER_CLUSTER; |
23239b5c MV |
854 | |
855 | packet.type = SR_DF_LOGIC; | |
856 | packet.payload = &logic; | |
857 | logic.unitsize = 2; | |
858 | logic.data = samples; | |
859 | ||
860 | /* | |
861 | * First of all, send Sigrok a copy of the last sample from | |
862 | * previous cluster as many times as needed to make up for | |
863 | * the differential characteristics of data we get from the | |
864 | * Sigma. Sigrok needs one sample of data per period. | |
865 | * | |
866 | * One DRAM cluster contains a timestamp and seven samples, | |
867 | * the units of timestamp are "devc->period_ps" , the first | |
868 | * sample in the cluster happens at the time of the timestamp | |
869 | * and the remaining samples happen at timestamp +1...+6 . | |
870 | */ | |
a44b3b3f | 871 | for (ts = 0; ts < tsdiff; ts++) { |
23239b5c | 872 | i = ts % 1024; |
0498f743 | 873 | store_sr_sample(samples, i, ss->lastsample); |
23239b5c MV |
874 | |
875 | /* | |
876 | * If we have 1024 samples ready or we're at the | |
877 | * end of submitting the padding samples, submit | |
85c032e4 GS |
878 | * the packet to Sigrok. Since constant data is |
879 | * sent, duplication of data for rates above 50MHz | |
880 | * is simple. | |
23239b5c | 881 | */ |
a44b3b3f | 882 | if ((i == 1023) || (ts == tsdiff - 1)) { |
23239b5c | 883 | logic.length = (i + 1) * logic.unitsize; |
85c032e4 | 884 | for (j = 0; j < devc->samples_per_event; j++) |
735ed8a1 | 885 | sigma_session_send(sdi, &packet); |
23239b5c MV |
886 | } |
887 | } | |
888 | ||
889 | /* | |
890 | * Parse the samples in current cluster and prepare them | |
85c032e4 GS |
891 | * to be submitted to Sigrok. Cope with memory layouts that |
892 | * vary with the samplerate. | |
23239b5c | 893 | */ |
85c032e4 GS |
894 | send_ptr = &samples[0]; |
895 | send_count = 0; | |
0498f743 | 896 | sample = 0; |
23239b5c | 897 | for (i = 0; i < events_in_cluster; i++) { |
85c032e4 GS |
898 | item16 = sigma_dram_cluster_data(dram_cluster, i); |
899 | if (devc->cur_samplerate == SR_MHZ(200)) { | |
900 | sample = sigma_deinterlace_200mhz_data(item16, 0); | |
901 | store_sr_sample(samples, send_count++, sample); | |
902 | sample = sigma_deinterlace_200mhz_data(item16, 1); | |
903 | store_sr_sample(samples, send_count++, sample); | |
904 | sample = sigma_deinterlace_200mhz_data(item16, 2); | |
905 | store_sr_sample(samples, send_count++, sample); | |
906 | sample = sigma_deinterlace_200mhz_data(item16, 3); | |
907 | store_sr_sample(samples, send_count++, sample); | |
908 | } else if (devc->cur_samplerate == SR_MHZ(100)) { | |
909 | sample = sigma_deinterlace_100mhz_data(item16, 0); | |
910 | store_sr_sample(samples, send_count++, sample); | |
911 | sample = sigma_deinterlace_100mhz_data(item16, 1); | |
912 | store_sr_sample(samples, send_count++, sample); | |
913 | } else { | |
914 | sample = item16; | |
915 | store_sr_sample(samples, send_count++, sample); | |
916 | } | |
23239b5c MV |
917 | } |
918 | ||
de3f7acb GS |
919 | /* |
920 | * If a trigger position applies, then provide the datafeed with | |
921 | * the first part of data up to that position, then send the | |
922 | * trigger marker. | |
923 | */ | |
23239b5c | 924 | int trigger_offset = 0; |
1e23158b | 925 | if (triggered) { |
23239b5c MV |
926 | /* |
927 | * Trigger is not always accurate to sample because of | |
928 | * pipeline delay. However, it always triggers before | |
929 | * the actual event. We therefore look at the next | |
930 | * samples to pinpoint the exact position of the trigger. | |
931 | */ | |
932 | trigger_offset = get_trigger_offset(samples, | |
933 | ss->lastsample, &devc->trigger); | |
934 | ||
935 | if (trigger_offset > 0) { | |
85c032e4 | 936 | trig_count = trigger_offset * devc->samples_per_event; |
23239b5c | 937 | packet.type = SR_DF_LOGIC; |
85c032e4 | 938 | logic.length = trig_count * logic.unitsize; |
735ed8a1 | 939 | sigma_session_send(sdi, &packet); |
85c032e4 GS |
940 | send_ptr += trig_count * logic.unitsize; |
941 | send_count -= trig_count; | |
23239b5c MV |
942 | } |
943 | ||
944 | /* Only send trigger if explicitly enabled. */ | |
945 | if (devc->use_triggers) { | |
946 | packet.type = SR_DF_TRIGGER; | |
102f1239 | 947 | sr_session_send(sdi, &packet); |
23239b5c MV |
948 | } |
949 | } | |
950 | ||
de3f7acb GS |
951 | /* |
952 | * Send the data after the trigger, or all of the received data | |
953 | * if no trigger position applies. | |
954 | */ | |
85c032e4 | 955 | if (send_count) { |
23239b5c | 956 | packet.type = SR_DF_LOGIC; |
85c032e4 GS |
957 | logic.length = send_count * logic.unitsize; |
958 | logic.data = send_ptr; | |
735ed8a1 | 959 | sigma_session_send(sdi, &packet); |
23239b5c MV |
960 | } |
961 | ||
0498f743 | 962 | ss->lastsample = sample; |
23239b5c MV |
963 | } |
964 | ||
28a35d8a | 965 | /* |
fefa1800 UH |
966 | * Decode chunk of 1024 bytes, 64 clusters, 7 events per cluster. |
967 | * Each event is 20ns apart, and can contain multiple samples. | |
f78898e9 HE |
968 | * |
969 | * For 200 MHz, events contain 4 samples for each channel, spread 5 ns apart. | |
970 | * For 100 MHz, events contain 2 samples for each channel, spread 10 ns apart. | |
971 | * For 50 MHz and below, events contain one sample for each channel, | |
972 | * spread 20 ns apart. | |
28a35d8a | 973 | */ |
1e23158b MV |
974 | static int decode_chunk_ts(struct sigma_dram_line *dram_line, |
975 | uint16_t events_in_line, | |
976 | uint32_t trigger_event, | |
102f1239 | 977 | struct sr_dev_inst *sdi) |
28a35d8a | 978 | { |
3628074d | 979 | struct sigma_dram_cluster *dram_cluster; |
f06fb3e9 GS |
980 | struct dev_context *devc; |
981 | unsigned int clusters_in_line; | |
5fc01191 | 982 | unsigned int events_in_cluster; |
23239b5c | 983 | unsigned int i; |
f06fb3e9 GS |
984 | uint32_t trigger_cluster, triggered; |
985 | ||
986 | devc = sdi->priv; | |
987 | clusters_in_line = events_in_line; | |
988 | clusters_in_line += EVENTS_PER_CLUSTER - 1; | |
989 | clusters_in_line /= EVENTS_PER_CLUSTER; | |
990 | trigger_cluster = ~0; | |
991 | triggered = 0; | |
ee492173 | 992 | |
4ae1f451 | 993 | /* Check if trigger is in this chunk. */ |
1e23158b MV |
994 | if (trigger_event < (64 * 7)) { |
995 | if (devc->cur_samplerate <= SR_MHZ(50)) { | |
996 | trigger_event -= MIN(EVENTS_PER_CLUSTER - 1, | |
997 | trigger_event); | |
998 | } | |
57bbf56b | 999 | |
f3f19d11 | 1000 | /* Find in which cluster the trigger occurred. */ |
1e23158b | 1001 | trigger_cluster = trigger_event / EVENTS_PER_CLUSTER; |
ee492173 | 1002 | } |
28a35d8a | 1003 | |
5fc01191 MV |
1004 | /* For each full DRAM cluster. */ |
1005 | for (i = 0; i < clusters_in_line; i++) { | |
3628074d | 1006 | dram_cluster = &dram_line->cluster[i]; |
5fc01191 | 1007 | |
5fc01191 | 1008 | /* The last cluster might not be full. */ |
23239b5c MV |
1009 | if ((i == clusters_in_line - 1) && |
1010 | (events_in_line % EVENTS_PER_CLUSTER)) { | |
5fc01191 | 1011 | events_in_cluster = events_in_line % EVENTS_PER_CLUSTER; |
23239b5c | 1012 | } else { |
5fc01191 | 1013 | events_in_cluster = EVENTS_PER_CLUSTER; |
abda62ce | 1014 | } |
ee492173 | 1015 | |
1e23158b MV |
1016 | triggered = (i == trigger_cluster); |
1017 | sigma_decode_dram_cluster(dram_cluster, events_in_cluster, | |
1018 | triggered, sdi); | |
28a35d8a HE |
1019 | } |
1020 | ||
e46b8fb1 | 1021 | return SR_OK; |
28a35d8a HE |
1022 | } |
1023 | ||
6057d9fa | 1024 | static int download_capture(struct sr_dev_inst *sdi) |
28a35d8a | 1025 | { |
e15e5873 | 1026 | const uint32_t chunks_per_read = 32; |
f06fb3e9 GS |
1027 | |
1028 | struct dev_context *devc; | |
fd830beb | 1029 | struct sigma_dram_line *dram_line; |
c6648b66 | 1030 | int bufsz; |
462fe786 | 1031 | uint32_t stoppos, triggerpos; |
6057d9fa | 1032 | uint8_t modestatus; |
c6648b66 MV |
1033 | uint32_t i; |
1034 | uint32_t dl_lines_total, dl_lines_curr, dl_lines_done; | |
f06fb3e9 GS |
1035 | uint32_t dl_events_in_line; |
1036 | uint32_t trg_line, trg_event; | |
1037 | ||
1038 | devc = sdi->priv; | |
1039 | dl_events_in_line = 64 * 7; | |
1040 | trg_line = ~0; | |
1041 | trg_event = ~0; | |
c6648b66 | 1042 | |
fd830beb MV |
1043 | dram_line = g_try_malloc0(chunks_per_read * sizeof(*dram_line)); |
1044 | if (!dram_line) | |
1045 | return FALSE; | |
1046 | ||
6868626b BV |
1047 | sr_info("Downloading sample data."); |
1048 | ||
22f64ed8 GS |
1049 | /* |
1050 | * Ask the hardware to stop data acquisition. Reception of the | |
1051 | * FORCESTOP request makes the hardware "disable RLE" (store | |
1052 | * clusters to DRAM regardless of whether pin state changes) and | |
1053 | * raise the POSTTRIGGERED flag. | |
1054 | */ | |
1055 | sigma_set_register(WRITE_MODE, WMR_FORCESTOP | WMR_SDRAMWRITEEN, devc); | |
1056 | do { | |
1057 | modestatus = sigma_get_register(READ_MODE, devc); | |
1058 | } while (!(modestatus & RMR_POSTTRIGGERED)); | |
6057d9fa MV |
1059 | |
1060 | /* Set SDRAM Read Enable. */ | |
22f64ed8 | 1061 | sigma_set_register(WRITE_MODE, WMR_SDRAMREADEN, devc); |
6057d9fa MV |
1062 | |
1063 | /* Get the current position. */ | |
462fe786 | 1064 | sigma_read_pos(&stoppos, &triggerpos, devc); |
6057d9fa MV |
1065 | |
1066 | /* Check if trigger has fired. */ | |
1067 | modestatus = sigma_get_register(READ_MODE, devc); | |
22f64ed8 | 1068 | if (modestatus & RMR_TRIGGERED) { |
c6648b66 | 1069 | trg_line = triggerpos >> 9; |
1e23158b MV |
1070 | trg_event = triggerpos & 0x1ff; |
1071 | } | |
6057d9fa | 1072 | |
735ed8a1 GS |
1073 | devc->sent_samples = 0; |
1074 | ||
c6648b66 MV |
1075 | /* |
1076 | * Determine how many 1024b "DRAM lines" do we need to read from the | |
1077 | * Sigma so we have a complete set of samples. Note that the last | |
1078 | * line can be only partial, containing less than 64 clusters. | |
1079 | */ | |
1080 | dl_lines_total = (stoppos >> 9) + 1; | |
6868626b | 1081 | |
c6648b66 | 1082 | dl_lines_done = 0; |
6868626b | 1083 | |
c6648b66 MV |
1084 | while (dl_lines_total > dl_lines_done) { |
1085 | /* We can download only up-to 32 DRAM lines in one go! */ | |
1086 | dl_lines_curr = MIN(chunks_per_read, dl_lines_total); | |
6868626b | 1087 | |
f41a4cae MV |
1088 | bufsz = sigma_read_dram(dl_lines_done, dl_lines_curr, |
1089 | (uint8_t *)dram_line, devc); | |
c6648b66 MV |
1090 | /* TODO: Check bufsz. For now, just avoid compiler warnings. */ |
1091 | (void)bufsz; | |
6868626b | 1092 | |
c6648b66 MV |
1093 | /* This is the first DRAM line, so find the initial timestamp. */ |
1094 | if (dl_lines_done == 0) { | |
3513d965 MV |
1095 | devc->state.lastts = |
1096 | sigma_dram_cluster_ts(&dram_line[0].cluster[0]); | |
c6648b66 | 1097 | devc->state.lastsample = 0; |
6868626b BV |
1098 | } |
1099 | ||
c6648b66 | 1100 | for (i = 0; i < dl_lines_curr; i++) { |
1e23158b | 1101 | uint32_t trigger_event = ~0; |
c6648b66 MV |
1102 | /* The last "DRAM line" can be only partially full. */ |
1103 | if (dl_lines_done + i == dl_lines_total - 1) | |
46641fac | 1104 | dl_events_in_line = stoppos & 0x1ff; |
c6648b66 | 1105 | |
e69ad48e | 1106 | /* Test if the trigger happened on this line. */ |
c6648b66 | 1107 | if (dl_lines_done + i == trg_line) |
1e23158b | 1108 | trigger_event = trg_event; |
e69ad48e | 1109 | |
1e23158b MV |
1110 | decode_chunk_ts(dram_line + i, dl_events_in_line, |
1111 | trigger_event, sdi); | |
c6648b66 | 1112 | } |
6868626b | 1113 | |
c6648b66 | 1114 | dl_lines_done += dl_lines_curr; |
6868626b BV |
1115 | } |
1116 | ||
bee2b016 | 1117 | std_session_send_df_end(sdi); |
6057d9fa | 1118 | |
695dc859 | 1119 | sdi->driver->dev_acquisition_stop(sdi); |
6057d9fa | 1120 | |
fd830beb MV |
1121 | g_free(dram_line); |
1122 | ||
6057d9fa | 1123 | return TRUE; |
6868626b BV |
1124 | } |
1125 | ||
d4051930 MV |
1126 | /* |
1127 | * Handle the Sigma when in CAPTURE mode. This function checks: | |
1128 | * - Sampling time ended | |
1129 | * - DRAM capacity overflow | |
1130 | * This function triggers download of the samples from Sigma | |
1131 | * in case either of the above conditions is true. | |
1132 | */ | |
1133 | static int sigma_capture_mode(struct sr_dev_inst *sdi) | |
6868626b | 1134 | { |
f06fb3e9 | 1135 | struct dev_context *devc; |
94ba4bd6 | 1136 | uint64_t running_msec; |
28a35d8a | 1137 | struct timeval tv; |
00c86508 | 1138 | uint32_t stoppos, triggerpos; |
28a35d8a | 1139 | |
f06fb3e9 GS |
1140 | devc = sdi->priv; |
1141 | ||
00c86508 | 1142 | /* Check if the selected sampling duration passed. */ |
d4051930 MV |
1143 | gettimeofday(&tv, 0); |
1144 | running_msec = (tv.tv_sec - devc->start_tv.tv_sec) * 1000 + | |
00c86508 MV |
1145 | (tv.tv_usec - devc->start_tv.tv_usec) / 1000; |
1146 | if (running_msec >= devc->limit_msec) | |
6057d9fa | 1147 | return download_capture(sdi); |
00c86508 MV |
1148 | |
1149 | /* Get the position in DRAM to which the FPGA is writing now. */ | |
1150 | sigma_read_pos(&stoppos, &triggerpos, devc); | |
1151 | /* Test if DRAM is full and if so, download the data. */ | |
1152 | if ((stoppos >> 9) == 32767) | |
6057d9fa | 1153 | return download_capture(sdi); |
28a35d8a | 1154 | |
d4051930 MV |
1155 | return TRUE; |
1156 | } | |
28a35d8a | 1157 | |
3ba56876 | 1158 | SR_PRIV int sigma_receive_data(int fd, int revents, void *cb_data) |
d4051930 MV |
1159 | { |
1160 | struct sr_dev_inst *sdi; | |
1161 | struct dev_context *devc; | |
88c51afe | 1162 | |
d4051930 MV |
1163 | (void)fd; |
1164 | (void)revents; | |
88c51afe | 1165 | |
d4051930 MV |
1166 | sdi = cb_data; |
1167 | devc = sdi->priv; | |
1168 | ||
1169 | if (devc->state.state == SIGMA_IDLE) | |
1170 | return TRUE; | |
1171 | ||
1172 | if (devc->state.state == SIGMA_CAPTURE) | |
1173 | return sigma_capture_mode(sdi); | |
28a35d8a | 1174 | |
28a35d8a HE |
1175 | return TRUE; |
1176 | } | |
1177 | ||
c53d793f HE |
1178 | /* Build a LUT entry used by the trigger functions. */ |
1179 | static void build_lut_entry(uint16_t value, uint16_t mask, uint16_t *entry) | |
ee492173 HE |
1180 | { |
1181 | int i, j, k, bit; | |
1182 | ||
ba7dd8bb | 1183 | /* For each quad channel. */ |
0a1f7b09 | 1184 | for (i = 0; i < 4; i++) { |
c53d793f | 1185 | entry[i] = 0xffff; |
ee492173 | 1186 | |
f758d074 | 1187 | /* For each bit in LUT. */ |
0a1f7b09 | 1188 | for (j = 0; j < 16; j++) |
ee492173 | 1189 | |
ba7dd8bb | 1190 | /* For each channel in quad. */ |
0a1f7b09 | 1191 | for (k = 0; k < 4; k++) { |
ee492173 HE |
1192 | bit = 1 << (i * 4 + k); |
1193 | ||
c53d793f | 1194 | /* Set bit in entry */ |
0a1f7b09 UH |
1195 | if ((mask & bit) && ((!(value & bit)) != |
1196 | (!(j & (1 << k))))) | |
c53d793f | 1197 | entry[i] &= ~(1 << j); |
ee492173 HE |
1198 | } |
1199 | } | |
c53d793f | 1200 | } |
ee492173 | 1201 | |
c53d793f HE |
1202 | /* Add a logical function to LUT mask. */ |
1203 | static void add_trigger_function(enum triggerop oper, enum triggerfunc func, | |
1204 | int index, int neg, uint16_t *mask) | |
1205 | { | |
1206 | int i, j; | |
1207 | int x[2][2], tmp, a, b, aset, bset, rset; | |
1208 | ||
1209 | memset(x, 0, 4 * sizeof(int)); | |
1210 | ||
1211 | /* Trigger detect condition. */ | |
1212 | switch (oper) { | |
1213 | case OP_LEVEL: | |
1214 | x[0][1] = 1; | |
1215 | x[1][1] = 1; | |
1216 | break; | |
1217 | case OP_NOT: | |
1218 | x[0][0] = 1; | |
1219 | x[1][0] = 1; | |
1220 | break; | |
1221 | case OP_RISE: | |
1222 | x[0][1] = 1; | |
1223 | break; | |
1224 | case OP_FALL: | |
1225 | x[1][0] = 1; | |
1226 | break; | |
1227 | case OP_RISEFALL: | |
1228 | x[0][1] = 1; | |
1229 | x[1][0] = 1; | |
1230 | break; | |
1231 | case OP_NOTRISE: | |
1232 | x[1][1] = 1; | |
1233 | x[0][0] = 1; | |
1234 | x[1][0] = 1; | |
1235 | break; | |
1236 | case OP_NOTFALL: | |
1237 | x[1][1] = 1; | |
1238 | x[0][0] = 1; | |
1239 | x[0][1] = 1; | |
1240 | break; | |
1241 | case OP_NOTRISEFALL: | |
1242 | x[1][1] = 1; | |
1243 | x[0][0] = 1; | |
1244 | break; | |
1245 | } | |
1246 | ||
1247 | /* Transpose if neg is set. */ | |
1248 | if (neg) { | |
0a1f7b09 UH |
1249 | for (i = 0; i < 2; i++) { |
1250 | for (j = 0; j < 2; j++) { | |
c53d793f | 1251 | tmp = x[i][j]; |
0a1f7b09 UH |
1252 | x[i][j] = x[1 - i][1 - j]; |
1253 | x[1 - i][1 - j] = tmp; | |
c53d793f | 1254 | } |
ea9cfed7 | 1255 | } |
c53d793f HE |
1256 | } |
1257 | ||
1258 | /* Update mask with function. */ | |
0a1f7b09 | 1259 | for (i = 0; i < 16; i++) { |
c53d793f HE |
1260 | a = (i >> (2 * index + 0)) & 1; |
1261 | b = (i >> (2 * index + 1)) & 1; | |
1262 | ||
1263 | aset = (*mask >> i) & 1; | |
1264 | bset = x[b][a]; | |
1265 | ||
382cb19f | 1266 | rset = 0; |
c53d793f HE |
1267 | if (func == FUNC_AND || func == FUNC_NAND) |
1268 | rset = aset & bset; | |
1269 | else if (func == FUNC_OR || func == FUNC_NOR) | |
1270 | rset = aset | bset; | |
1271 | else if (func == FUNC_XOR || func == FUNC_NXOR) | |
1272 | rset = aset ^ bset; | |
1273 | ||
1274 | if (func == FUNC_NAND || func == FUNC_NOR || func == FUNC_NXOR) | |
1275 | rset = !rset; | |
1276 | ||
1277 | *mask &= ~(1 << i); | |
1278 | ||
1279 | if (rset) | |
1280 | *mask |= 1 << i; | |
1281 | } | |
1282 | } | |
1283 | ||
1284 | /* | |
1285 | * Build trigger LUTs used by 50 MHz and lower sample rates for supporting | |
1286 | * simple pin change and state triggers. Only two transitions (rise/fall) can be | |
1287 | * set at any time, but a full mask and value can be set (0/1). | |
1288 | */ | |
3ba56876 | 1289 | SR_PRIV int sigma_build_basic_trigger(struct triggerlut *lut, struct dev_context *devc) |
c53d793f HE |
1290 | { |
1291 | int i,j; | |
4ae1f451 | 1292 | uint16_t masks[2] = { 0, 0 }; |
c53d793f HE |
1293 | |
1294 | memset(lut, 0, sizeof(struct triggerlut)); | |
1295 | ||
f3f19d11 | 1296 | /* Constant for simple triggers. */ |
c53d793f HE |
1297 | lut->m4 = 0xa000; |
1298 | ||
1299 | /* Value/mask trigger support. */ | |
0e1357e8 | 1300 | build_lut_entry(devc->trigger.simplevalue, devc->trigger.simplemask, |
99965709 | 1301 | lut->m2d); |
c53d793f HE |
1302 | |
1303 | /* Rise/fall trigger support. */ | |
0a1f7b09 | 1304 | for (i = 0, j = 0; i < 16; i++) { |
0e1357e8 BV |
1305 | if (devc->trigger.risingmask & (1 << i) || |
1306 | devc->trigger.fallingmask & (1 << i)) | |
c53d793f HE |
1307 | masks[j++] = 1 << i; |
1308 | } | |
1309 | ||
1310 | build_lut_entry(masks[0], masks[0], lut->m0d); | |
1311 | build_lut_entry(masks[1], masks[1], lut->m1d); | |
1312 | ||
1313 | /* Add glue logic */ | |
1314 | if (masks[0] || masks[1]) { | |
1315 | /* Transition trigger. */ | |
0e1357e8 | 1316 | if (masks[0] & devc->trigger.risingmask) |
c53d793f | 1317 | add_trigger_function(OP_RISE, FUNC_OR, 0, 0, &lut->m3); |
0e1357e8 | 1318 | if (masks[0] & devc->trigger.fallingmask) |
c53d793f | 1319 | add_trigger_function(OP_FALL, FUNC_OR, 0, 0, &lut->m3); |
0e1357e8 | 1320 | if (masks[1] & devc->trigger.risingmask) |
c53d793f | 1321 | add_trigger_function(OP_RISE, FUNC_OR, 1, 0, &lut->m3); |
0e1357e8 | 1322 | if (masks[1] & devc->trigger.fallingmask) |
c53d793f HE |
1323 | add_trigger_function(OP_FALL, FUNC_OR, 1, 0, &lut->m3); |
1324 | } else { | |
1325 | /* Only value/mask trigger. */ | |
1326 | lut->m3 = 0xffff; | |
1327 | } | |
ee492173 | 1328 | |
c53d793f | 1329 | /* Triggertype: event. */ |
ee492173 HE |
1330 | lut->params.selres = 3; |
1331 | ||
e46b8fb1 | 1332 | return SR_OK; |
ee492173 | 1333 | } |