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Commit | Line | Data |
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28a35d8a | 1 | /* |
50985c20 | 2 | * This file is part of the libsigrok project. |
28a35d8a | 3 | * |
868501fa | 4 | * Copyright (C) 2010-2012 Håvard Espeland <gus@ping.uio.no>, |
911f1834 UH |
5 | * Copyright (C) 2010 Martin Stensgård <mastensg@ping.uio.no> |
6 | * Copyright (C) 2010 Carl Henrik Lunde <chlunde@ping.uio.no> | |
28a35d8a HE |
7 | * |
8 | * This program is free software: you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation, either version 3 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
20 | */ | |
21 | ||
911f1834 | 22 | /* |
6352d030 | 23 | * ASIX SIGMA/SIGMA2 logic analyzer driver |
911f1834 UH |
24 | */ |
25 | ||
6ec6c43b | 26 | #include <config.h> |
3ba56876 | 27 | #include "protocol.h" |
28a35d8a | 28 | |
b1648dea MV |
29 | /* |
30 | * The ASIX Sigma supports arbitrary integer frequency divider in | |
31 | * the 50MHz mode. The divider is in range 1...256 , allowing for | |
32 | * very precise sampling rate selection. This driver supports only | |
33 | * a subset of the sampling rates. | |
34 | */ | |
3ba56876 | 35 | SR_PRIV const uint64_t samplerates[] = { |
b1648dea MV |
36 | SR_KHZ(200), /* div=250 */ |
37 | SR_KHZ(250), /* div=200 */ | |
38 | SR_KHZ(500), /* div=100 */ | |
39 | SR_MHZ(1), /* div=50 */ | |
40 | SR_MHZ(5), /* div=10 */ | |
41 | SR_MHZ(10), /* div=5 */ | |
42 | SR_MHZ(25), /* div=2 */ | |
43 | SR_MHZ(50), /* div=1 */ | |
44 | SR_MHZ(100), /* Special FW needed */ | |
45 | SR_MHZ(200), /* Special FW needed */ | |
28a35d8a HE |
46 | }; |
47 | ||
4154a516 | 48 | SR_PRIV const size_t samplerates_count = ARRAY_SIZE(samplerates); |
39c64c6a | 49 | |
742368a2 GS |
50 | static const char *firmware_files[] = { |
51 | "asix-sigma-50.fw", /* Up to 50MHz sample rate, 8bit divider. */ | |
52 | "asix-sigma-100.fw", /* 100MHz sample rate, fixed. */ | |
53 | "asix-sigma-200.fw", /* 200MHz sample rate, fixed. */ | |
54 | "asix-sigma-50sync.fw", /* Synchronous clock from external pin. */ | |
55 | "asix-sigma-phasor.fw", /* Frequency counter. */ | |
f6564c8d HE |
56 | }; |
57 | ||
742368a2 GS |
58 | #define SIGMA_FIRMWARE_SIZE_LIMIT (256 * 1024) |
59 | ||
0e1357e8 | 60 | static int sigma_read(void *buf, size_t size, struct dev_context *devc) |
28a35d8a HE |
61 | { |
62 | int ret; | |
fefa1800 | 63 | |
0e1357e8 | 64 | ret = ftdi_read_data(&devc->ftdic, (unsigned char *)buf, size); |
28a35d8a | 65 | if (ret < 0) { |
47f4f073 | 66 | sr_err("ftdi_read_data failed: %s", |
0e1357e8 | 67 | ftdi_get_error_string(&devc->ftdic)); |
28a35d8a HE |
68 | } |
69 | ||
70 | return ret; | |
71 | } | |
72 | ||
0e1357e8 | 73 | static int sigma_write(void *buf, size_t size, struct dev_context *devc) |
28a35d8a HE |
74 | { |
75 | int ret; | |
fefa1800 | 76 | |
0e1357e8 | 77 | ret = ftdi_write_data(&devc->ftdic, (unsigned char *)buf, size); |
8ebad343 | 78 | if (ret < 0) |
47f4f073 | 79 | sr_err("ftdi_write_data failed: %s", |
0e1357e8 | 80 | ftdi_get_error_string(&devc->ftdic)); |
8ebad343 | 81 | else if ((size_t) ret != size) |
47f4f073 | 82 | sr_err("ftdi_write_data did not complete write."); |
28a35d8a HE |
83 | |
84 | return ret; | |
85 | } | |
86 | ||
e8686e3a AG |
87 | /* |
88 | * NOTE: We chose the buffer size to be large enough to hold any write to the | |
89 | * device. We still print a message just in case. | |
90 | */ | |
3ba56876 | 91 | SR_PRIV int sigma_write_register(uint8_t reg, uint8_t *data, size_t len, |
92 | struct dev_context *devc) | |
28a35d8a HE |
93 | { |
94 | size_t i; | |
e8686e3a | 95 | uint8_t buf[80]; |
28a35d8a HE |
96 | int idx = 0; |
97 | ||
7c86d853 | 98 | if ((2 * len + 2) > sizeof(buf)) { |
e8686e3a | 99 | sr_err("Attempted to write %zu bytes, but buffer is too small.", |
7c86d853 | 100 | len); |
e8686e3a AG |
101 | return SR_ERR_BUG; |
102 | } | |
103 | ||
28a35d8a HE |
104 | buf[idx++] = REG_ADDR_LOW | (reg & 0xf); |
105 | buf[idx++] = REG_ADDR_HIGH | (reg >> 4); | |
106 | ||
0a1f7b09 | 107 | for (i = 0; i < len; i++) { |
28a35d8a HE |
108 | buf[idx++] = REG_DATA_LOW | (data[i] & 0xf); |
109 | buf[idx++] = REG_DATA_HIGH_WRITE | (data[i] >> 4); | |
110 | } | |
111 | ||
0e1357e8 | 112 | return sigma_write(buf, idx, devc); |
28a35d8a HE |
113 | } |
114 | ||
3ba56876 | 115 | SR_PRIV int sigma_set_register(uint8_t reg, uint8_t value, struct dev_context *devc) |
28a35d8a | 116 | { |
0e1357e8 | 117 | return sigma_write_register(reg, &value, 1, devc); |
28a35d8a HE |
118 | } |
119 | ||
99965709 | 120 | static int sigma_read_register(uint8_t reg, uint8_t *data, size_t len, |
0e1357e8 | 121 | struct dev_context *devc) |
28a35d8a HE |
122 | { |
123 | uint8_t buf[3]; | |
fefa1800 | 124 | |
28a35d8a HE |
125 | buf[0] = REG_ADDR_LOW | (reg & 0xf); |
126 | buf[1] = REG_ADDR_HIGH | (reg >> 4); | |
28a35d8a HE |
127 | buf[2] = REG_READ_ADDR; |
128 | ||
0e1357e8 | 129 | sigma_write(buf, sizeof(buf), devc); |
28a35d8a | 130 | |
0e1357e8 | 131 | return sigma_read(data, len, devc); |
28a35d8a HE |
132 | } |
133 | ||
99965709 | 134 | static int sigma_read_pos(uint32_t *stoppos, uint32_t *triggerpos, |
0e1357e8 | 135 | struct dev_context *devc) |
28a35d8a | 136 | { |
07411a60 GS |
137 | /* |
138 | * Read 6 registers starting at trigger position LSB. | |
139 | * Which yields two 24bit counter values. | |
140 | */ | |
28a35d8a HE |
141 | uint8_t buf[] = { |
142 | REG_ADDR_LOW | READ_TRIGGER_POS_LOW, | |
07411a60 GS |
143 | REG_READ_ADDR | REG_ADDR_INC, |
144 | REG_READ_ADDR | REG_ADDR_INC, | |
145 | REG_READ_ADDR | REG_ADDR_INC, | |
146 | REG_READ_ADDR | REG_ADDR_INC, | |
147 | REG_READ_ADDR | REG_ADDR_INC, | |
148 | REG_READ_ADDR | REG_ADDR_INC, | |
28a35d8a | 149 | }; |
28a35d8a HE |
150 | uint8_t result[6]; |
151 | ||
0e1357e8 | 152 | sigma_write(buf, sizeof(buf), devc); |
28a35d8a | 153 | |
0e1357e8 | 154 | sigma_read(result, sizeof(result), devc); |
28a35d8a HE |
155 | |
156 | *triggerpos = result[0] | (result[1] << 8) | (result[2] << 16); | |
157 | *stoppos = result[3] | (result[4] << 8) | (result[5] << 16); | |
158 | ||
dc400817 GS |
159 | /* |
160 | * These "position" values point to after the event (end of | |
161 | * capture data, trigger condition matched). This is why they | |
162 | * get decremented here. Sample memory consists of 512-byte | |
163 | * chunks with meta data in the upper 64 bytes. Thus when the | |
164 | * decrements takes us into this upper part of the chunk, then | |
165 | * further move backwards to the end of the chunk's data part. | |
2c33b092 GS |
166 | * |
167 | * TODO Re-consider the above comment's validity. It's true | |
168 | * that a 1024byte row contains 512 u16 entities, of which 64 | |
169 | * are timestamps and 448 are events with sample data. It's not | |
170 | * true that 64bytes of metadata reside at the top of a 512byte | |
171 | * block in a row. | |
172 | * | |
173 | * TODO Use ROW_MASK and CLUSTERS_PER_ROW here? | |
dc400817 | 174 | */ |
57bbf56b | 175 | if ((--*stoppos & 0x1ff) == 0x1ff) |
382cb19f | 176 | *stoppos -= 64; |
dc400817 | 177 | if ((--*triggerpos & 0x1ff) == 0x1ff) |
382cb19f | 178 | *triggerpos -= 64; |
57bbf56b | 179 | |
28a35d8a HE |
180 | return 1; |
181 | } | |
182 | ||
99965709 | 183 | static int sigma_read_dram(uint16_t startchunk, size_t numchunks, |
0e1357e8 | 184 | uint8_t *data, struct dev_context *devc) |
28a35d8a | 185 | { |
28a35d8a | 186 | uint8_t buf[4096]; |
f06fb3e9 | 187 | int idx; |
07411a60 GS |
188 | size_t chunk; |
189 | int sel; | |
190 | gboolean is_last; | |
28a35d8a | 191 | |
07411a60 | 192 | /* Communicate DRAM start address (memory row, aka samples line). */ |
f06fb3e9 GS |
193 | idx = 0; |
194 | buf[idx++] = startchunk >> 8; | |
195 | buf[idx++] = startchunk & 0xff; | |
196 | sigma_write_register(WRITE_MEMROW, buf, idx, devc); | |
28a35d8a | 197 | |
07411a60 GS |
198 | /* |
199 | * Access DRAM content. Fetch from DRAM to FPGA's internal RAM, | |
200 | * then transfer via USB. Interleave the FPGA's DRAM access and | |
201 | * USB transfer, use alternating buffers (0/1) in the process. | |
202 | */ | |
f06fb3e9 | 203 | idx = 0; |
28a35d8a HE |
204 | buf[idx++] = REG_DRAM_BLOCK; |
205 | buf[idx++] = REG_DRAM_WAIT_ACK; | |
07411a60 GS |
206 | for (chunk = 0; chunk < numchunks; chunk++) { |
207 | sel = chunk % 2; | |
208 | is_last = chunk == numchunks - 1; | |
209 | if (!is_last) | |
210 | buf[idx++] = REG_DRAM_BLOCK | REG_DRAM_SEL_BOOL(!sel); | |
211 | buf[idx++] = REG_DRAM_BLOCK_DATA | REG_DRAM_SEL_BOOL(sel); | |
212 | if (!is_last) | |
28a35d8a HE |
213 | buf[idx++] = REG_DRAM_WAIT_ACK; |
214 | } | |
0e1357e8 | 215 | sigma_write(buf, idx, devc); |
28a35d8a | 216 | |
2c33b092 | 217 | return sigma_read(data, numchunks * ROW_LENGTH_BYTES, devc); |
28a35d8a HE |
218 | } |
219 | ||
4ae1f451 | 220 | /* Upload trigger look-up tables to Sigma. */ |
3ba56876 | 221 | SR_PRIV int sigma_write_trigger_lut(struct triggerlut *lut, struct dev_context *devc) |
ee492173 HE |
222 | { |
223 | int i; | |
224 | uint8_t tmp[2]; | |
225 | uint16_t bit; | |
226 | ||
227 | /* Transpose the table and send to Sigma. */ | |
0a1f7b09 | 228 | for (i = 0; i < 16; i++) { |
ee492173 HE |
229 | bit = 1 << i; |
230 | ||
231 | tmp[0] = tmp[1] = 0; | |
232 | ||
233 | if (lut->m2d[0] & bit) | |
234 | tmp[0] |= 0x01; | |
235 | if (lut->m2d[1] & bit) | |
236 | tmp[0] |= 0x02; | |
237 | if (lut->m2d[2] & bit) | |
238 | tmp[0] |= 0x04; | |
239 | if (lut->m2d[3] & bit) | |
240 | tmp[0] |= 0x08; | |
241 | ||
242 | if (lut->m3 & bit) | |
243 | tmp[0] |= 0x10; | |
244 | if (lut->m3s & bit) | |
245 | tmp[0] |= 0x20; | |
246 | if (lut->m4 & bit) | |
247 | tmp[0] |= 0x40; | |
248 | ||
249 | if (lut->m0d[0] & bit) | |
250 | tmp[1] |= 0x01; | |
251 | if (lut->m0d[1] & bit) | |
252 | tmp[1] |= 0x02; | |
253 | if (lut->m0d[2] & bit) | |
254 | tmp[1] |= 0x04; | |
255 | if (lut->m0d[3] & bit) | |
256 | tmp[1] |= 0x08; | |
257 | ||
258 | if (lut->m1d[0] & bit) | |
259 | tmp[1] |= 0x10; | |
260 | if (lut->m1d[1] & bit) | |
261 | tmp[1] |= 0x20; | |
262 | if (lut->m1d[2] & bit) | |
263 | tmp[1] |= 0x40; | |
264 | if (lut->m1d[3] & bit) | |
265 | tmp[1] |= 0x80; | |
266 | ||
9fb4c632 | 267 | sigma_write_register(WRITE_TRIGGER_SELECT, tmp, sizeof(tmp), |
0e1357e8 | 268 | devc); |
9fb4c632 | 269 | sigma_set_register(WRITE_TRIGGER_SELECT2, 0x30 | i, devc); |
ee492173 HE |
270 | } |
271 | ||
272 | /* Send the parameters */ | |
9fb4c632 | 273 | sigma_write_register(WRITE_TRIGGER_SELECT, (uint8_t *) &lut->params, |
0e1357e8 | 274 | sizeof(lut->params), devc); |
ee492173 | 275 | |
e46b8fb1 | 276 | return SR_OK; |
ee492173 HE |
277 | } |
278 | ||
d5fa188a | 279 | /* |
dc0906e2 GS |
280 | * See Xilinx UG332 for Spartan-3 FPGA configuration. The SIGMA device |
281 | * uses FTDI bitbang mode for netlist download in slave serial mode. | |
282 | * (LATER: The OMEGA device's cable contains a more capable FTDI chip | |
283 | * and uses MPSSE mode for bitbang. -- Can we also use FT232H in FT245 | |
284 | * compatible bitbang mode? For maximum code re-use and reduced libftdi | |
285 | * dependency? See section 3.5.5 of FT232H: D0 clk, D1 data (out), D2 | |
286 | * data (in), D3 select, D4-7 GPIOL. See section 3.5.7 for MCU FIFO.) | |
287 | * | |
288 | * 750kbps rate (four times the speed of sigmalogan) works well for | |
289 | * netlist download. All pins except INIT_B are output pins during | |
290 | * configuration download. | |
291 | * | |
292 | * Some pins are inverted as a byproduct of level shifting circuitry. | |
293 | * That's why high CCLK level (from the cable's point of view) is idle | |
294 | * from the FPGA's perspective. | |
295 | * | |
296 | * The vendor's literature discusses a "suicide sequence" which ends | |
297 | * regular FPGA execution and should be sent before entering bitbang | |
298 | * mode and sending configuration data. Set D7 and toggle D2, D3, D4 | |
299 | * a few times. | |
300 | */ | |
301 | #define BB_PIN_CCLK (1 << 0) /* D0, CCLK */ | |
302 | #define BB_PIN_PROG (1 << 1) /* D1, PROG */ | |
303 | #define BB_PIN_D2 (1 << 2) /* D2, (part of) SUICIDE */ | |
304 | #define BB_PIN_D3 (1 << 3) /* D3, (part of) SUICIDE */ | |
305 | #define BB_PIN_D4 (1 << 4) /* D4, (part of) SUICIDE (unused?) */ | |
306 | #define BB_PIN_INIT (1 << 5) /* D5, INIT, input pin */ | |
307 | #define BB_PIN_DIN (1 << 6) /* D6, DIN */ | |
308 | #define BB_PIN_D7 (1 << 7) /* D7, (part of) SUICIDE */ | |
309 | ||
310 | #define BB_BITRATE (750 * 1000) | |
311 | #define BB_PINMASK (0xff & ~BB_PIN_INIT) | |
312 | ||
313 | /* | |
314 | * Initiate slave serial mode for configuration download. Which is done | |
315 | * by pulsing PROG_B and sensing INIT_B. Make sure CCLK is idle before | |
316 | * initiating the configuration download. Run a "suicide sequence" first | |
317 | * to terminate the regular FPGA operation before reconfiguration. | |
d5fa188a MV |
318 | */ |
319 | static int sigma_fpga_init_bitbang(struct dev_context *devc) | |
320 | { | |
321 | uint8_t suicide[] = { | |
dc0906e2 GS |
322 | BB_PIN_D7 | BB_PIN_D2, |
323 | BB_PIN_D7 | BB_PIN_D2, | |
324 | BB_PIN_D7 | BB_PIN_D3, | |
325 | BB_PIN_D7 | BB_PIN_D2, | |
326 | BB_PIN_D7 | BB_PIN_D3, | |
327 | BB_PIN_D7 | BB_PIN_D2, | |
328 | BB_PIN_D7 | BB_PIN_D3, | |
329 | BB_PIN_D7 | BB_PIN_D2, | |
d5fa188a MV |
330 | }; |
331 | uint8_t init_array[] = { | |
dc0906e2 GS |
332 | BB_PIN_CCLK, |
333 | BB_PIN_CCLK | BB_PIN_PROG, | |
334 | BB_PIN_CCLK | BB_PIN_PROG, | |
335 | BB_PIN_CCLK, | |
336 | BB_PIN_CCLK, | |
337 | BB_PIN_CCLK, | |
338 | BB_PIN_CCLK, | |
339 | BB_PIN_CCLK, | |
340 | BB_PIN_CCLK, | |
341 | BB_PIN_CCLK, | |
d5fa188a | 342 | }; |
dc0906e2 | 343 | int retries, ret; |
d5fa188a MV |
344 | uint8_t data; |
345 | ||
346 | /* Section 2. part 1), do the FPGA suicide. */ | |
347 | sigma_write(suicide, sizeof(suicide), devc); | |
348 | sigma_write(suicide, sizeof(suicide), devc); | |
349 | sigma_write(suicide, sizeof(suicide), devc); | |
350 | sigma_write(suicide, sizeof(suicide), devc); | |
351 | ||
dc0906e2 | 352 | /* Section 2. part 2), pulse PROG. */ |
d5fa188a MV |
353 | sigma_write(init_array, sizeof(init_array), devc); |
354 | ftdi_usb_purge_buffers(&devc->ftdic); | |
355 | ||
dc0906e2 GS |
356 | /* Wait until the FPGA asserts INIT_B. */ |
357 | retries = 10; | |
358 | while (retries--) { | |
d5fa188a MV |
359 | ret = sigma_read(&data, 1, devc); |
360 | if (ret < 0) | |
361 | return ret; | |
dc0906e2 GS |
362 | if (data & BB_PIN_INIT) |
363 | return SR_OK; | |
1a46cc62 | 364 | g_usleep(10 * 1000); |
d5fa188a MV |
365 | } |
366 | ||
367 | return SR_ERR_TIMEOUT; | |
368 | } | |
369 | ||
64fe661b MV |
370 | /* |
371 | * Configure the FPGA for logic-analyzer mode. | |
372 | */ | |
373 | static int sigma_fpga_init_la(struct dev_context *devc) | |
374 | { | |
dc0906e2 GS |
375 | /* |
376 | * TODO Construct the sequence at runtime? Such that request data | |
377 | * and response check values will match more apparently? | |
378 | */ | |
22f64ed8 | 379 | uint8_t mode_regval = WMR_SDRAMINIT; |
64fe661b | 380 | uint8_t logic_mode_start[] = { |
dc0906e2 | 381 | /* Read ID register. */ |
011f1091 | 382 | REG_ADDR_LOW | (READ_ID & 0xf), |
84a6ed1a | 383 | REG_ADDR_HIGH | (READ_ID >> 4), |
dc0906e2 | 384 | REG_READ_ADDR, |
011f1091 | 385 | |
dc0906e2 | 386 | /* Write 0x55 to scratch register, read back. */ |
011f1091 MV |
387 | REG_ADDR_LOW | (WRITE_TEST & 0xf), |
388 | REG_DATA_LOW | 0x5, | |
389 | REG_DATA_HIGH_WRITE | 0x5, | |
dc0906e2 | 390 | REG_READ_ADDR, |
011f1091 | 391 | |
dc0906e2 | 392 | /* Write 0xaa to scratch register, read back. */ |
011f1091 MV |
393 | REG_DATA_LOW | 0xa, |
394 | REG_DATA_HIGH_WRITE | 0xa, | |
dc0906e2 | 395 | REG_READ_ADDR, |
011f1091 | 396 | |
dc0906e2 | 397 | /* Initiate SDRAM initialization in mode register. */ |
011f1091 | 398 | REG_ADDR_LOW | (WRITE_MODE & 0xf), |
22f64ed8 GS |
399 | REG_DATA_LOW | (mode_regval & 0xf), |
400 | REG_DATA_HIGH_WRITE | (mode_regval >> 4), | |
64fe661b | 401 | }; |
64fe661b MV |
402 | uint8_t result[3]; |
403 | int ret; | |
404 | ||
dc0906e2 GS |
405 | /* |
406 | * Send the command sequence which contains 3 READ requests. | |
407 | * Expect to see the corresponding 3 response bytes. | |
408 | */ | |
64fe661b | 409 | sigma_write(logic_mode_start, sizeof(logic_mode_start), devc); |
dc0906e2 GS |
410 | ret = sigma_read(result, ARRAY_SIZE(result), devc); |
411 | if (ret != ARRAY_SIZE(result)) | |
64fe661b | 412 | goto err; |
64fe661b MV |
413 | if (result[0] != 0xa6 || result[1] != 0x55 || result[2] != 0xaa) |
414 | goto err; | |
415 | ||
416 | return SR_OK; | |
dc0906e2 | 417 | |
64fe661b MV |
418 | err: |
419 | sr_err("Configuration failed. Invalid reply received."); | |
420 | return SR_ERR; | |
421 | } | |
422 | ||
a80226bb MV |
423 | /* |
424 | * Read the firmware from a file and transform it into a series of bitbang | |
425 | * pulses used to program the FPGA. Note that the *bb_cmd must be free()'d | |
426 | * by the caller of this function. | |
427 | */ | |
8e2d6c9d | 428 | static int sigma_fw_2_bitbang(struct sr_context *ctx, const char *name, |
a80226bb MV |
429 | uint8_t **bb_cmd, gsize *bb_cmd_size) |
430 | { | |
dc0906e2 GS |
431 | uint8_t *firmware; |
432 | size_t file_size; | |
433 | uint8_t *p; | |
434 | size_t l; | |
a80226bb | 435 | uint32_t imm; |
dc0906e2 GS |
436 | size_t bb_size; |
437 | uint8_t *bb_stream, *bbs, byte, mask, v; | |
a80226bb | 438 | |
387825dc | 439 | /* Retrieve the on-disk firmware file content. */ |
742368a2 GS |
440 | firmware = sr_resource_load(ctx, SR_RESOURCE_FIRMWARE, name, |
441 | &file_size, SIGMA_FIRMWARE_SIZE_LIMIT); | |
8e2d6c9d | 442 | if (!firmware) |
dc0906e2 | 443 | return SR_ERR_IO; |
a80226bb | 444 | |
387825dc | 445 | /* Unscramble the file content (XOR with "random" sequence). */ |
dc0906e2 GS |
446 | p = firmware; |
447 | l = file_size; | |
a80226bb | 448 | imm = 0x3f6df2ab; |
dc0906e2 | 449 | while (l--) { |
a80226bb | 450 | imm = (imm + 0xa853753) % 177 + (imm * 0x8034052); |
dc0906e2 | 451 | *p++ ^= imm & 0xff; |
a80226bb MV |
452 | } |
453 | ||
454 | /* | |
387825dc GS |
455 | * Generate a sequence of bitbang samples. With two samples per |
456 | * FPGA configuration bit, providing the level for the DIN signal | |
457 | * as well as two edges for CCLK. See Xilinx UG332 for details | |
458 | * ("slave serial" mode). | |
459 | * | |
460 | * Note that CCLK is inverted in hardware. That's why the | |
461 | * respective bit is first set and then cleared in the bitbang | |
462 | * sample sets. So that the DIN level will be stable when the | |
463 | * data gets sampled at the rising CCLK edge, and the signals' | |
464 | * setup time constraint will be met. | |
465 | * | |
466 | * The caller will put the FPGA into download mode, will send | |
467 | * the bitbang samples, and release the allocated memory. | |
a80226bb | 468 | */ |
a80226bb | 469 | bb_size = file_size * 8 * 2; |
dc0906e2 | 470 | bb_stream = g_try_malloc(bb_size); |
a80226bb MV |
471 | if (!bb_stream) { |
472 | sr_err("%s: Failed to allocate bitbang stream", __func__); | |
dc0906e2 GS |
473 | g_free(firmware); |
474 | return SR_ERR_MALLOC; | |
a80226bb | 475 | } |
a80226bb | 476 | bbs = bb_stream; |
dc0906e2 GS |
477 | p = firmware; |
478 | l = file_size; | |
479 | while (l--) { | |
480 | byte = *p++; | |
481 | mask = 0x80; | |
482 | while (mask) { | |
483 | v = (byte & mask) ? BB_PIN_DIN : 0; | |
484 | mask >>= 1; | |
485 | *bbs++ = v | BB_PIN_CCLK; | |
a80226bb MV |
486 | *bbs++ = v; |
487 | } | |
488 | } | |
dc0906e2 | 489 | g_free(firmware); |
a80226bb MV |
490 | |
491 | /* The transformation completed successfully, return the result. */ | |
492 | *bb_cmd = bb_stream; | |
493 | *bb_cmd_size = bb_size; | |
494 | ||
dc0906e2 | 495 | return SR_OK; |
a80226bb MV |
496 | } |
497 | ||
8e2d6c9d DE |
498 | static int upload_firmware(struct sr_context *ctx, |
499 | int firmware_idx, struct dev_context *devc) | |
28a35d8a HE |
500 | { |
501 | int ret; | |
502 | unsigned char *buf; | |
503 | unsigned char pins; | |
504 | size_t buf_size; | |
a9016883 | 505 | const char *firmware; |
a9016883 GS |
506 | |
507 | /* Avoid downloading the same firmware multiple times. */ | |
4b25cbff | 508 | firmware = firmware_files[firmware_idx]; |
a9016883 GS |
509 | if (devc->cur_firmware == firmware_idx) { |
510 | sr_info("Not uploading firmware file '%s' again.", firmware); | |
511 | return SR_OK; | |
512 | } | |
28a35d8a | 513 | |
dc0906e2 GS |
514 | /* Set the cable to bitbang mode. */ |
515 | ret = ftdi_set_bitmode(&devc->ftdic, BB_PINMASK, BITMODE_BITBANG); | |
8bbf7627 | 516 | if (ret < 0) { |
47f4f073 | 517 | sr_err("ftdi_set_bitmode failed: %s", |
1f4f98e0 | 518 | ftdi_get_error_string(&devc->ftdic)); |
7bcf2168 | 519 | return SR_ERR; |
28a35d8a | 520 | } |
dc0906e2 | 521 | ret = ftdi_set_baudrate(&devc->ftdic, BB_BITRATE); |
8bbf7627 | 522 | if (ret < 0) { |
47f4f073 | 523 | sr_err("ftdi_set_baudrate failed: %s", |
1f4f98e0 | 524 | ftdi_get_error_string(&devc->ftdic)); |
7bcf2168 | 525 | return SR_ERR; |
28a35d8a HE |
526 | } |
527 | ||
dc0906e2 | 528 | /* Initiate FPGA configuration mode. */ |
d5fa188a MV |
529 | ret = sigma_fpga_init_bitbang(devc); |
530 | if (ret) | |
531 | return ret; | |
28a35d8a | 532 | |
dc0906e2 | 533 | /* Prepare wire format of the firmware image. */ |
8e2d6c9d | 534 | ret = sigma_fw_2_bitbang(ctx, firmware, &buf, &buf_size); |
8bbf7627 | 535 | if (ret != SR_OK) { |
f3f19d11 | 536 | sr_err("An error occurred while reading the firmware: %s", |
499b17e9 | 537 | firmware); |
b53738ba | 538 | return ret; |
28a35d8a HE |
539 | } |
540 | ||
dc0906e2 | 541 | /* Write the FPGA netlist to the cable. */ |
499b17e9 | 542 | sr_info("Uploading firmware file '%s'.", firmware); |
0e1357e8 | 543 | sigma_write(buf, buf_size, devc); |
28a35d8a HE |
544 | |
545 | g_free(buf); | |
546 | ||
dc0906e2 GS |
547 | /* Leave bitbang mode and discard pending input data. */ |
548 | ret = ftdi_set_bitmode(&devc->ftdic, 0, BITMODE_RESET); | |
8bbf7627 | 549 | if (ret < 0) { |
47f4f073 | 550 | sr_err("ftdi_set_bitmode failed: %s", |
1f4f98e0 | 551 | ftdi_get_error_string(&devc->ftdic)); |
e46b8fb1 | 552 | return SR_ERR; |
28a35d8a | 553 | } |
1f4f98e0 | 554 | ftdi_usb_purge_buffers(&devc->ftdic); |
29b66a2e | 555 | while (sigma_read(&pins, 1, devc) == 1) |
28a35d8a HE |
556 | ; |
557 | ||
64fe661b MV |
558 | /* Initialize the FPGA for logic-analyzer mode. */ |
559 | ret = sigma_fpga_init_la(devc); | |
560 | if (ret != SR_OK) | |
561 | return ret; | |
28a35d8a | 562 | |
dc0906e2 | 563 | /* Keep track of successful firmware download completion. */ |
0e1357e8 | 564 | devc->cur_firmware = firmware_idx; |
47f4f073 | 565 | sr_info("Firmware uploaded."); |
e3fff420 | 566 | |
e46b8fb1 | 567 | return SR_OK; |
f6564c8d HE |
568 | } |
569 | ||
9a0a606a | 570 | /* |
5e78a564 GS |
571 | * The driver supports user specified time or sample count limits. The |
572 | * device's hardware supports neither, and hardware compression prevents | |
573 | * reliable detection of "fill levels" (currently reached sample counts) | |
574 | * from register values during acquisition. That's why the driver needs | |
575 | * to apply some heuristics: | |
9a0a606a | 576 | * |
5e78a564 GS |
577 | * - The (optional) sample count limit and the (normalized) samplerate |
578 | * get mapped to an estimated duration for these samples' acquisition. | |
579 | * - The (optional) time limit gets checked as well. The lesser of the | |
580 | * two limits will terminate the data acquisition phase. The exact | |
581 | * sample count limit gets enforced in session feed submission paths. | |
582 | * - Some slack needs to be given to account for hardware pipelines as | |
583 | * well as late storage of last chunks after compression thresholds | |
584 | * are tripped. The resulting data set will span at least the caller | |
585 | * specified period of time, which shall be perfectly acceptable. | |
586 | * | |
587 | * With RLE compression active, up to 64K sample periods can pass before | |
588 | * a cluster accumulates. Which translates to 327ms at 200kHz. Add two | |
589 | * times that period for good measure, one is not enough to flush the | |
590 | * hardware pipeline (observation from an earlier experiment). | |
9a0a606a | 591 | */ |
5e78a564 | 592 | SR_PRIV int sigma_set_acquire_timeout(struct dev_context *devc) |
9a0a606a | 593 | { |
5e78a564 GS |
594 | int ret; |
595 | GVariant *data; | |
596 | uint64_t user_count, user_msecs; | |
9a0a606a | 597 | uint64_t worst_cluster_time_ms; |
5e78a564 | 598 | uint64_t count_msecs, acquire_msecs; |
9a0a606a | 599 | |
5e78a564 GS |
600 | sr_sw_limits_init(&devc->acq_limits); |
601 | ||
602 | /* Get sample count limit, convert to msecs. */ | |
603 | ret = sr_sw_limits_config_get(&devc->cfg_limits, | |
604 | SR_CONF_LIMIT_SAMPLES, &data); | |
605 | if (ret != SR_OK) | |
606 | return ret; | |
607 | user_count = g_variant_get_uint64(data); | |
608 | g_variant_unref(data); | |
609 | count_msecs = 0; | |
610 | if (user_count) | |
611 | count_msecs = 1000 * user_count / devc->samplerate + 1; | |
612 | ||
613 | /* Get time limit, which is in msecs. */ | |
614 | ret = sr_sw_limits_config_get(&devc->cfg_limits, | |
615 | SR_CONF_LIMIT_MSEC, &data); | |
616 | if (ret != SR_OK) | |
617 | return ret; | |
618 | user_msecs = g_variant_get_uint64(data); | |
619 | g_variant_unref(data); | |
620 | ||
621 | /* Get the lesser of them, with both being optional. */ | |
622 | acquire_msecs = ~0ull; | |
623 | if (user_count && count_msecs < acquire_msecs) | |
624 | acquire_msecs = count_msecs; | |
625 | if (user_msecs && user_msecs < acquire_msecs) | |
626 | acquire_msecs = user_msecs; | |
627 | if (acquire_msecs == ~0ull) | |
628 | return SR_OK; | |
629 | ||
630 | /* Add some slack, and use that timeout for acquisition. */ | |
631 | worst_cluster_time_ms = 1000 * 65536 / devc->samplerate; | |
632 | acquire_msecs += 2 * worst_cluster_time_ms; | |
633 | data = g_variant_new_uint64(acquire_msecs); | |
634 | ret = sr_sw_limits_config_set(&devc->acq_limits, | |
635 | SR_CONF_LIMIT_MSEC, data); | |
636 | g_variant_unref(data); | |
637 | if (ret != SR_OK) | |
638 | return ret; | |
639 | ||
640 | sr_sw_limits_acquisition_start(&devc->acq_limits); | |
641 | return SR_OK; | |
9a0a606a GS |
642 | } |
643 | ||
5e78a564 GS |
644 | /* |
645 | * Check whether a caller specified samplerate matches the device's | |
646 | * hardware constraints (can be used for acquisition). Optionally yield | |
647 | * a value that approximates the original spec. | |
648 | * | |
649 | * This routine assumes that input specs are in the 200kHz to 200MHz | |
650 | * range of supported rates, and callers typically want to normalize a | |
651 | * given value to the hardware capabilities. Values in the 50MHz range | |
652 | * get rounded up by default, to avoid a more expensive check for the | |
653 | * closest match, while higher sampling rate is always desirable during | |
654 | * measurement. Input specs which exactly match hardware capabilities | |
655 | * remain unaffected. Because 100/200MHz rates also limit the number of | |
656 | * available channels, they are not suggested by this routine, instead | |
657 | * callers need to pick them consciously. | |
658 | */ | |
659 | SR_PRIV int sigma_normalize_samplerate(uint64_t want_rate, uint64_t *have_rate) | |
660 | { | |
661 | uint64_t div, rate; | |
662 | ||
663 | /* Accept exact matches for 100/200MHz. */ | |
664 | if (want_rate == SR_MHZ(200) || want_rate == SR_MHZ(100)) { | |
665 | if (have_rate) | |
666 | *have_rate = want_rate; | |
667 | return SR_OK; | |
668 | } | |
669 | ||
670 | /* Accept 200kHz to 50MHz range, and map to near value. */ | |
671 | if (want_rate >= SR_KHZ(200) && want_rate <= SR_MHZ(50)) { | |
672 | div = SR_MHZ(50) / want_rate; | |
673 | rate = SR_MHZ(50) / div; | |
674 | if (have_rate) | |
675 | *have_rate = rate; | |
676 | return SR_OK; | |
677 | } | |
678 | ||
679 | return SR_ERR_ARG; | |
680 | } | |
681 | ||
682 | SR_PRIV int sigma_set_samplerate(const struct sr_dev_inst *sdi) | |
f6564c8d | 683 | { |
2c9c0df8 | 684 | struct dev_context *devc; |
8e2d6c9d | 685 | struct drv_context *drvc; |
5e78a564 | 686 | uint64_t samplerate; |
2c9c0df8 | 687 | int ret; |
ac9534f4 | 688 | int num_channels; |
f6564c8d | 689 | |
2c9c0df8 | 690 | devc = sdi->priv; |
8e2d6c9d | 691 | drvc = sdi->driver->context; |
f4abaa9f | 692 | |
5e78a564 GS |
693 | /* Accept any caller specified rate which the hardware supports. */ |
694 | ret = sigma_normalize_samplerate(devc->samplerate, &samplerate); | |
695 | if (ret != SR_OK) | |
696 | return ret; | |
f6564c8d | 697 | |
2f7e529c GS |
698 | /* |
699 | * Depending on the samplerates of 200/100/50- MHz, specific | |
700 | * firmware is required and higher rates might limit the set | |
701 | * of available channels. | |
702 | */ | |
ac9534f4 | 703 | num_channels = devc->num_channels; |
59df0c77 | 704 | if (samplerate <= SR_MHZ(50)) { |
8e2d6c9d | 705 | ret = upload_firmware(drvc->sr_ctx, 0, devc); |
ac9534f4 | 706 | num_channels = 16; |
6b2d3385 | 707 | } else if (samplerate == SR_MHZ(100)) { |
8e2d6c9d | 708 | ret = upload_firmware(drvc->sr_ctx, 1, devc); |
ac9534f4 | 709 | num_channels = 8; |
6b2d3385 | 710 | } else if (samplerate == SR_MHZ(200)) { |
8e2d6c9d | 711 | ret = upload_firmware(drvc->sr_ctx, 2, devc); |
ac9534f4 | 712 | num_channels = 4; |
f78898e9 | 713 | } |
f6564c8d | 714 | |
2f7e529c | 715 | /* |
5e78a564 GS |
716 | * The samplerate affects the number of available logic channels |
717 | * as well as a sample memory layout detail (the number of samples | |
718 | * which the device will communicate within an "event"). | |
2f7e529c | 719 | */ |
6b2d3385 | 720 | if (ret == SR_OK) { |
ac9534f4 | 721 | devc->num_channels = num_channels; |
6b2d3385 BV |
722 | devc->samples_per_event = 16 / devc->num_channels; |
723 | devc->state.state = SIGMA_IDLE; | |
724 | } | |
f6564c8d | 725 | |
e8397563 | 726 | return ret; |
28a35d8a HE |
727 | } |
728 | ||
98b43eb3 GS |
729 | /* |
730 | * Arrange for a session feed submit buffer. A queue where a number of | |
731 | * samples gets accumulated to reduce the number of send calls. Which | |
732 | * also enforces an optional sample count limit for data acquisition. | |
733 | * | |
734 | * The buffer holds up to CHUNK_SIZE bytes. The unit size is fixed (the | |
735 | * driver provides a fixed channel layout regardless of samplerate). | |
736 | */ | |
737 | ||
738 | #define CHUNK_SIZE (4 * 1024 * 1024) | |
739 | ||
740 | struct submit_buffer { | |
741 | size_t unit_size; | |
742 | size_t max_samples, curr_samples; | |
743 | uint8_t *sample_data; | |
744 | uint8_t *write_pointer; | |
745 | struct sr_dev_inst *sdi; | |
746 | struct sr_datafeed_packet packet; | |
747 | struct sr_datafeed_logic logic; | |
98b43eb3 GS |
748 | }; |
749 | ||
750 | static int alloc_submit_buffer(struct sr_dev_inst *sdi) | |
751 | { | |
752 | struct dev_context *devc; | |
753 | struct submit_buffer *buffer; | |
754 | size_t size; | |
755 | ||
756 | devc = sdi->priv; | |
757 | ||
758 | buffer = g_malloc0(sizeof(*buffer)); | |
759 | devc->buffer = buffer; | |
760 | ||
761 | buffer->unit_size = sizeof(uint16_t); | |
762 | size = CHUNK_SIZE; | |
763 | size /= buffer->unit_size; | |
764 | buffer->max_samples = size; | |
765 | size *= buffer->unit_size; | |
766 | buffer->sample_data = g_try_malloc0(size); | |
767 | if (!buffer->sample_data) | |
768 | return SR_ERR_MALLOC; | |
769 | buffer->write_pointer = buffer->sample_data; | |
5e78a564 | 770 | sr_sw_limits_init(&devc->feed_limits); |
98b43eb3 GS |
771 | |
772 | buffer->sdi = sdi; | |
773 | memset(&buffer->logic, 0, sizeof(buffer->logic)); | |
774 | buffer->logic.unitsize = buffer->unit_size; | |
775 | buffer->logic.data = buffer->sample_data; | |
776 | memset(&buffer->packet, 0, sizeof(buffer->packet)); | |
777 | buffer->packet.type = SR_DF_LOGIC; | |
778 | buffer->packet.payload = &buffer->logic; | |
779 | ||
780 | return SR_OK; | |
781 | } | |
782 | ||
5e78a564 | 783 | static int setup_submit_limit(struct dev_context *devc) |
98b43eb3 | 784 | { |
5e78a564 | 785 | struct sr_sw_limits *limits; |
98b43eb3 GS |
786 | int ret; |
787 | GVariant *data; | |
788 | uint64_t total; | |
789 | ||
5e78a564 | 790 | limits = &devc->feed_limits; |
98b43eb3 | 791 | |
5e78a564 GS |
792 | ret = sr_sw_limits_config_get(&devc->cfg_limits, |
793 | SR_CONF_LIMIT_SAMPLES, &data); | |
794 | if (ret != SR_OK) | |
795 | return ret; | |
796 | total = g_variant_get_uint64(data); | |
797 | g_variant_unref(data); | |
798 | ||
799 | sr_sw_limits_init(limits); | |
98b43eb3 GS |
800 | if (total) { |
801 | data = g_variant_new_uint64(total); | |
5e78a564 | 802 | ret = sr_sw_limits_config_set(limits, |
98b43eb3 GS |
803 | SR_CONF_LIMIT_SAMPLES, data); |
804 | g_variant_unref(data); | |
805 | if (ret != SR_OK) | |
806 | return ret; | |
807 | } | |
808 | ||
5e78a564 | 809 | sr_sw_limits_acquisition_start(limits); |
98b43eb3 GS |
810 | |
811 | return SR_OK; | |
812 | } | |
813 | ||
814 | static void free_submit_buffer(struct dev_context *devc) | |
815 | { | |
816 | struct submit_buffer *buffer; | |
817 | ||
818 | if (!devc) | |
819 | return; | |
820 | ||
821 | buffer = devc->buffer; | |
822 | if (!buffer) | |
823 | return; | |
824 | devc->buffer = NULL; | |
825 | ||
826 | g_free(buffer->sample_data); | |
827 | g_free(buffer); | |
828 | } | |
829 | ||
830 | static int flush_submit_buffer(struct dev_context *devc) | |
831 | { | |
832 | struct submit_buffer *buffer; | |
833 | int ret; | |
834 | ||
835 | buffer = devc->buffer; | |
836 | ||
837 | /* Is queued sample data available? */ | |
838 | if (!buffer->curr_samples) | |
839 | return SR_OK; | |
840 | ||
841 | /* Submit to the session feed. */ | |
842 | buffer->logic.length = buffer->curr_samples * buffer->unit_size; | |
843 | ret = sr_session_send(buffer->sdi, &buffer->packet); | |
844 | if (ret != SR_OK) | |
845 | return ret; | |
846 | ||
847 | /* Rewind queue position. */ | |
848 | buffer->curr_samples = 0; | |
849 | buffer->write_pointer = buffer->sample_data; | |
850 | ||
851 | return SR_OK; | |
852 | } | |
853 | ||
854 | static int addto_submit_buffer(struct dev_context *devc, | |
855 | uint16_t sample, size_t count) | |
856 | { | |
857 | struct submit_buffer *buffer; | |
5e78a564 | 858 | struct sr_sw_limits *limits; |
98b43eb3 GS |
859 | int ret; |
860 | ||
861 | buffer = devc->buffer; | |
5e78a564 GS |
862 | limits = &devc->feed_limits; |
863 | if (sr_sw_limits_check(limits)) | |
98b43eb3 GS |
864 | count = 0; |
865 | ||
866 | /* | |
867 | * Individually accumulate and check each sample, such that | |
868 | * accumulation between flushes won't exceed local storage, and | |
869 | * enforcement of user specified limits is exact. | |
870 | */ | |
871 | while (count--) { | |
872 | WL16(buffer->write_pointer, sample); | |
873 | buffer->write_pointer += buffer->unit_size; | |
874 | buffer->curr_samples++; | |
875 | if (buffer->curr_samples == buffer->max_samples) { | |
876 | ret = flush_submit_buffer(devc); | |
877 | if (ret != SR_OK) | |
878 | return ret; | |
879 | } | |
5e78a564 GS |
880 | sr_sw_limits_update_samples_read(limits, 1); |
881 | if (sr_sw_limits_check(limits)) | |
98b43eb3 GS |
882 | break; |
883 | } | |
884 | ||
885 | return SR_OK; | |
886 | } | |
887 | ||
c53d793f HE |
888 | /* |
889 | * In 100 and 200 MHz mode, only a single pin rising/falling can be | |
890 | * set as trigger. In other modes, two rising/falling triggers can be set, | |
ba7dd8bb | 891 | * in addition to value/mask trigger for any number of channels. |
c53d793f HE |
892 | * |
893 | * The Sigma supports complex triggers using boolean expressions, but this | |
894 | * has not been implemented yet. | |
895 | */ | |
3ba56876 | 896 | SR_PRIV int sigma_convert_trigger(const struct sr_dev_inst *sdi) |
57bbf56b | 897 | { |
39c64c6a BV |
898 | struct dev_context *devc; |
899 | struct sr_trigger *trigger; | |
900 | struct sr_trigger_stage *stage; | |
901 | struct sr_trigger_match *match; | |
902 | const GSList *l, *m; | |
903 | int channelbit, trigger_set; | |
57bbf56b | 904 | |
39c64c6a | 905 | devc = sdi->priv; |
0e1357e8 | 906 | memset(&devc->trigger, 0, sizeof(struct sigma_trigger)); |
0812c40e | 907 | if (!(trigger = sr_session_trigger_get(sdi->session))) |
39c64c6a BV |
908 | return SR_OK; |
909 | ||
910 | trigger_set = 0; | |
911 | for (l = trigger->stages; l; l = l->next) { | |
912 | stage = l->data; | |
913 | for (m = stage->matches; m; m = m->next) { | |
914 | match = m->data; | |
915 | if (!match->channel->enabled) | |
916 | /* Ignore disabled channels with a trigger. */ | |
917 | continue; | |
918 | channelbit = 1 << (match->channel->index); | |
5e78a564 | 919 | if (devc->samplerate >= SR_MHZ(100)) { |
39c64c6a BV |
920 | /* Fast trigger support. */ |
921 | if (trigger_set) { | |
922 | sr_err("Only a single pin trigger is " | |
923 | "supported in 100 and 200MHz mode."); | |
924 | return SR_ERR; | |
925 | } | |
926 | if (match->match == SR_TRIGGER_FALLING) | |
927 | devc->trigger.fallingmask |= channelbit; | |
928 | else if (match->match == SR_TRIGGER_RISING) | |
929 | devc->trigger.risingmask |= channelbit; | |
930 | else { | |
931 | sr_err("Only rising/falling trigger is " | |
932 | "supported in 100 and 200MHz mode."); | |
933 | return SR_ERR; | |
934 | } | |
eec5275e | 935 | |
0a1f7b09 | 936 | trigger_set++; |
39c64c6a BV |
937 | } else { |
938 | /* Simple trigger support (event). */ | |
939 | if (match->match == SR_TRIGGER_ONE) { | |
940 | devc->trigger.simplevalue |= channelbit; | |
941 | devc->trigger.simplemask |= channelbit; | |
8ebad343 | 942 | } else if (match->match == SR_TRIGGER_ZERO) { |
39c64c6a BV |
943 | devc->trigger.simplevalue &= ~channelbit; |
944 | devc->trigger.simplemask |= channelbit; | |
8ebad343 | 945 | } else if (match->match == SR_TRIGGER_FALLING) { |
39c64c6a | 946 | devc->trigger.fallingmask |= channelbit; |
0a1f7b09 | 947 | trigger_set++; |
8ebad343 | 948 | } else if (match->match == SR_TRIGGER_RISING) { |
39c64c6a | 949 | devc->trigger.risingmask |= channelbit; |
0a1f7b09 | 950 | trigger_set++; |
39c64c6a BV |
951 | } |
952 | ||
953 | /* | |
954 | * Actually, Sigma supports 2 rising/falling triggers, | |
955 | * but they are ORed and the current trigger syntax | |
956 | * does not permit ORed triggers. | |
957 | */ | |
958 | if (trigger_set > 1) { | |
959 | sr_err("Only 1 rising/falling trigger " | |
960 | "is supported."); | |
961 | return SR_ERR; | |
962 | } | |
ee492173 | 963 | } |
ee492173 | 964 | } |
57bbf56b HE |
965 | } |
966 | ||
e46b8fb1 | 967 | return SR_OK; |
57bbf56b HE |
968 | } |
969 | ||
36b1c8e6 | 970 | /* Software trigger to determine exact trigger position. */ |
5fc01191 | 971 | static int get_trigger_offset(uint8_t *samples, uint16_t last_sample, |
36b1c8e6 HE |
972 | struct sigma_trigger *t) |
973 | { | |
974 | int i; | |
5fc01191 | 975 | uint16_t sample = 0; |
36b1c8e6 | 976 | |
0a1f7b09 | 977 | for (i = 0; i < 8; i++) { |
36b1c8e6 | 978 | if (i > 0) |
5fc01191 MV |
979 | last_sample = sample; |
980 | sample = samples[2 * i] | (samples[2 * i + 1] << 8); | |
36b1c8e6 HE |
981 | |
982 | /* Simple triggers. */ | |
5fc01191 | 983 | if ((sample & t->simplemask) != t->simplevalue) |
36b1c8e6 HE |
984 | continue; |
985 | ||
986 | /* Rising edge. */ | |
5fc01191 MV |
987 | if (((last_sample & t->risingmask) != 0) || |
988 | ((sample & t->risingmask) != t->risingmask)) | |
36b1c8e6 HE |
989 | continue; |
990 | ||
991 | /* Falling edge. */ | |
bdfc7a89 | 992 | if ((last_sample & t->fallingmask) != t->fallingmask || |
5fc01191 | 993 | (sample & t->fallingmask) != 0) |
36b1c8e6 HE |
994 | continue; |
995 | ||
996 | break; | |
997 | } | |
998 | ||
999 | /* If we did not match, return original trigger pos. */ | |
1000 | return i & 0x7; | |
1001 | } | |
1002 | ||
98b43eb3 GS |
1003 | static gboolean sample_matches_trigger(struct dev_context *devc, uint16_t sample) |
1004 | { | |
1005 | /* TODO | |
1006 | * Check whether the combination of this very sample and the | |
1007 | * previous state match the configured trigger condition. This | |
1008 | * improves the resolution of the trigger marker's position. | |
1009 | * The hardware provided position is coarse, and may point to | |
1010 | * a position before the actual match. | |
1011 | * | |
1012 | * See the previous get_trigger_offset() implementation. This | |
1013 | * code needs to get re-used here. | |
1014 | */ | |
1015 | (void)devc; | |
1016 | (void)sample; | |
1017 | (void)get_trigger_offset; | |
1018 | ||
1019 | return FALSE; | |
1020 | } | |
1021 | ||
1022 | static int check_and_submit_sample(struct dev_context *devc, | |
1023 | uint16_t sample, size_t count, gboolean check_trigger) | |
1024 | { | |
1025 | gboolean triggered; | |
1026 | int ret; | |
1027 | ||
1028 | triggered = check_trigger && sample_matches_trigger(devc, sample); | |
1029 | if (triggered) { | |
1030 | ret = flush_submit_buffer(devc); | |
1031 | if (ret != SR_OK) | |
1032 | return ret; | |
1033 | ret = std_session_send_df_trigger(devc->buffer->sdi); | |
1034 | if (ret != SR_OK) | |
1035 | return ret; | |
1036 | } | |
1037 | ||
1038 | ret = addto_submit_buffer(devc, sample, count); | |
1039 | if (ret != SR_OK) | |
1040 | return ret; | |
1041 | ||
1042 | return SR_OK; | |
1043 | } | |
1044 | ||
3513d965 MV |
1045 | /* |
1046 | * Return the timestamp of "DRAM cluster". | |
1047 | */ | |
1048 | static uint16_t sigma_dram_cluster_ts(struct sigma_dram_cluster *cluster) | |
1049 | { | |
1050 | return (cluster->timestamp_hi << 8) | cluster->timestamp_lo; | |
1051 | } | |
1052 | ||
0498f743 GS |
1053 | /* |
1054 | * Return one 16bit data entity of a DRAM cluster at the specified index. | |
1055 | */ | |
1056 | static uint16_t sigma_dram_cluster_data(struct sigma_dram_cluster *cl, int idx) | |
1057 | { | |
1058 | uint16_t sample; | |
1059 | ||
1060 | sample = 0; | |
1061 | sample |= cl->samples[idx].sample_lo << 0; | |
1062 | sample |= cl->samples[idx].sample_hi << 8; | |
3281cf59 | 1063 | sample = (sample >> 8) | (sample << 8); |
0498f743 GS |
1064 | return sample; |
1065 | } | |
1066 | ||
85c032e4 GS |
1067 | /* |
1068 | * Deinterlace sample data that was retrieved at 100MHz samplerate. | |
1069 | * One 16bit item contains two samples of 8bits each. The bits of | |
1070 | * multiple samples are interleaved. | |
1071 | */ | |
1072 | static uint16_t sigma_deinterlace_100mhz_data(uint16_t indata, int idx) | |
1073 | { | |
1074 | uint16_t outdata; | |
1075 | ||
1076 | indata >>= idx; | |
1077 | outdata = 0; | |
1078 | outdata |= (indata >> (0 * 2 - 0)) & (1 << 0); | |
1079 | outdata |= (indata >> (1 * 2 - 1)) & (1 << 1); | |
1080 | outdata |= (indata >> (2 * 2 - 2)) & (1 << 2); | |
1081 | outdata |= (indata >> (3 * 2 - 3)) & (1 << 3); | |
1082 | outdata |= (indata >> (4 * 2 - 4)) & (1 << 4); | |
1083 | outdata |= (indata >> (5 * 2 - 5)) & (1 << 5); | |
1084 | outdata |= (indata >> (6 * 2 - 6)) & (1 << 6); | |
1085 | outdata |= (indata >> (7 * 2 - 7)) & (1 << 7); | |
1086 | return outdata; | |
1087 | } | |
1088 | ||
1089 | /* | |
1090 | * Deinterlace sample data that was retrieved at 200MHz samplerate. | |
1091 | * One 16bit item contains four samples of 4bits each. The bits of | |
1092 | * multiple samples are interleaved. | |
1093 | */ | |
1094 | static uint16_t sigma_deinterlace_200mhz_data(uint16_t indata, int idx) | |
1095 | { | |
1096 | uint16_t outdata; | |
1097 | ||
1098 | indata >>= idx; | |
1099 | outdata = 0; | |
1100 | outdata |= (indata >> (0 * 4 - 0)) & (1 << 0); | |
1101 | outdata |= (indata >> (1 * 4 - 1)) & (1 << 1); | |
1102 | outdata |= (indata >> (2 * 4 - 2)) & (1 << 2); | |
1103 | outdata |= (indata >> (3 * 4 - 3)) & (1 << 3); | |
1104 | return outdata; | |
1105 | } | |
1106 | ||
98b43eb3 GS |
1107 | static void sigma_decode_dram_cluster(struct dev_context *devc, |
1108 | struct sigma_dram_cluster *dram_cluster, | |
1109 | size_t events_in_cluster, gboolean triggered) | |
23239b5c | 1110 | { |
98b43eb3 | 1111 | struct sigma_state *ss; |
85c032e4 | 1112 | uint16_t tsdiff, ts, sample, item16; |
23239b5c | 1113 | unsigned int i; |
23239b5c | 1114 | |
98b43eb3 GS |
1115 | if (!devc->use_triggers || !ASIX_SIGMA_WITH_TRIGGER) |
1116 | triggered = FALSE; | |
23239b5c MV |
1117 | |
1118 | /* | |
468f17f2 GS |
1119 | * If this cluster is not adjacent to the previously received |
1120 | * cluster, then send the appropriate number of samples with the | |
1121 | * previous values to the sigrok session. This "decodes RLE". | |
2c33b092 | 1122 | * |
98b43eb3 GS |
1123 | * These samples cannot match the trigger since they just repeat |
1124 | * the previously submitted data pattern. (This assumption holds | |
1125 | * for simple level and edge triggers. It would not for timed or | |
1126 | * counted conditions, which currently are not supported.) | |
23239b5c | 1127 | */ |
98b43eb3 GS |
1128 | ss = &devc->state; |
1129 | ts = sigma_dram_cluster_ts(dram_cluster); | |
1130 | tsdiff = ts - ss->lastts; | |
1131 | if (tsdiff > 0) { | |
1132 | size_t count; | |
1133 | count = tsdiff * devc->samples_per_event; | |
1134 | (void)check_and_submit_sample(devc, ss->lastsample, count, FALSE); | |
23239b5c | 1135 | } |
98b43eb3 | 1136 | ss->lastts = ts + EVENTS_PER_CLUSTER; |
23239b5c MV |
1137 | |
1138 | /* | |
98b43eb3 GS |
1139 | * Grab sample data from the current cluster and prepare their |
1140 | * submission to the session feed. Handle samplerate dependent | |
1141 | * memory layout of sample data. Accumulation of data chunks | |
1142 | * before submission is transparent to this code path, specific | |
1143 | * buffer depth is neither assumed nor required here. | |
23239b5c | 1144 | */ |
0498f743 | 1145 | sample = 0; |
23239b5c | 1146 | for (i = 0; i < events_in_cluster; i++) { |
85c032e4 | 1147 | item16 = sigma_dram_cluster_data(dram_cluster, i); |
5e78a564 | 1148 | if (devc->samplerate == SR_MHZ(200)) { |
85c032e4 | 1149 | sample = sigma_deinterlace_200mhz_data(item16, 0); |
98b43eb3 | 1150 | check_and_submit_sample(devc, sample, 1, triggered); |
85c032e4 | 1151 | sample = sigma_deinterlace_200mhz_data(item16, 1); |
98b43eb3 | 1152 | check_and_submit_sample(devc, sample, 1, triggered); |
85c032e4 | 1153 | sample = sigma_deinterlace_200mhz_data(item16, 2); |
98b43eb3 | 1154 | check_and_submit_sample(devc, sample, 1, triggered); |
85c032e4 | 1155 | sample = sigma_deinterlace_200mhz_data(item16, 3); |
98b43eb3 | 1156 | check_and_submit_sample(devc, sample, 1, triggered); |
5e78a564 | 1157 | } else if (devc->samplerate == SR_MHZ(100)) { |
85c032e4 | 1158 | sample = sigma_deinterlace_100mhz_data(item16, 0); |
98b43eb3 | 1159 | check_and_submit_sample(devc, sample, 1, triggered); |
85c032e4 | 1160 | sample = sigma_deinterlace_100mhz_data(item16, 1); |
98b43eb3 | 1161 | check_and_submit_sample(devc, sample, 1, triggered); |
85c032e4 GS |
1162 | } else { |
1163 | sample = item16; | |
98b43eb3 | 1164 | check_and_submit_sample(devc, sample, 1, triggered); |
23239b5c | 1165 | } |
23239b5c | 1166 | } |
0498f743 | 1167 | ss->lastsample = sample; |
23239b5c MV |
1168 | } |
1169 | ||
28a35d8a | 1170 | /* |
fefa1800 UH |
1171 | * Decode chunk of 1024 bytes, 64 clusters, 7 events per cluster. |
1172 | * Each event is 20ns apart, and can contain multiple samples. | |
f78898e9 HE |
1173 | * |
1174 | * For 200 MHz, events contain 4 samples for each channel, spread 5 ns apart. | |
1175 | * For 100 MHz, events contain 2 samples for each channel, spread 10 ns apart. | |
1176 | * For 50 MHz and below, events contain one sample for each channel, | |
1177 | * spread 20 ns apart. | |
28a35d8a | 1178 | */ |
98b43eb3 GS |
1179 | static int decode_chunk_ts(struct dev_context *devc, |
1180 | struct sigma_dram_line *dram_line, | |
1181 | size_t events_in_line, size_t trigger_event) | |
28a35d8a | 1182 | { |
3628074d | 1183 | struct sigma_dram_cluster *dram_cluster; |
f06fb3e9 | 1184 | unsigned int clusters_in_line; |
5fc01191 | 1185 | unsigned int events_in_cluster; |
23239b5c | 1186 | unsigned int i; |
98b43eb3 | 1187 | uint32_t trigger_cluster; |
f06fb3e9 | 1188 | |
f06fb3e9 GS |
1189 | clusters_in_line = events_in_line; |
1190 | clusters_in_line += EVENTS_PER_CLUSTER - 1; | |
1191 | clusters_in_line /= EVENTS_PER_CLUSTER; | |
1192 | trigger_cluster = ~0; | |
ee492173 | 1193 | |
4ae1f451 | 1194 | /* Check if trigger is in this chunk. */ |
2c33b092 | 1195 | if (trigger_event < EVENTS_PER_ROW) { |
5e78a564 | 1196 | if (devc->samplerate <= SR_MHZ(50)) { |
1e23158b MV |
1197 | trigger_event -= MIN(EVENTS_PER_CLUSTER - 1, |
1198 | trigger_event); | |
1199 | } | |
57bbf56b | 1200 | |
f3f19d11 | 1201 | /* Find in which cluster the trigger occurred. */ |
1e23158b | 1202 | trigger_cluster = trigger_event / EVENTS_PER_CLUSTER; |
ee492173 | 1203 | } |
28a35d8a | 1204 | |
5fc01191 MV |
1205 | /* For each full DRAM cluster. */ |
1206 | for (i = 0; i < clusters_in_line; i++) { | |
3628074d | 1207 | dram_cluster = &dram_line->cluster[i]; |
5fc01191 | 1208 | |
5fc01191 | 1209 | /* The last cluster might not be full. */ |
23239b5c MV |
1210 | if ((i == clusters_in_line - 1) && |
1211 | (events_in_line % EVENTS_PER_CLUSTER)) { | |
5fc01191 | 1212 | events_in_cluster = events_in_line % EVENTS_PER_CLUSTER; |
23239b5c | 1213 | } else { |
5fc01191 | 1214 | events_in_cluster = EVENTS_PER_CLUSTER; |
abda62ce | 1215 | } |
ee492173 | 1216 | |
98b43eb3 GS |
1217 | sigma_decode_dram_cluster(devc, dram_cluster, |
1218 | events_in_cluster, i == trigger_cluster); | |
28a35d8a HE |
1219 | } |
1220 | ||
e46b8fb1 | 1221 | return SR_OK; |
28a35d8a HE |
1222 | } |
1223 | ||
6057d9fa | 1224 | static int download_capture(struct sr_dev_inst *sdi) |
28a35d8a | 1225 | { |
e15e5873 | 1226 | const uint32_t chunks_per_read = 32; |
f06fb3e9 GS |
1227 | |
1228 | struct dev_context *devc; | |
fd830beb | 1229 | struct sigma_dram_line *dram_line; |
c6648b66 | 1230 | int bufsz; |
462fe786 | 1231 | uint32_t stoppos, triggerpos; |
6057d9fa | 1232 | uint8_t modestatus; |
c6648b66 MV |
1233 | uint32_t i; |
1234 | uint32_t dl_lines_total, dl_lines_curr, dl_lines_done; | |
74d453ab | 1235 | uint32_t dl_first_line, dl_line; |
f06fb3e9 GS |
1236 | uint32_t dl_events_in_line; |
1237 | uint32_t trg_line, trg_event; | |
98b43eb3 | 1238 | int ret; |
f06fb3e9 GS |
1239 | |
1240 | devc = sdi->priv; | |
2c33b092 | 1241 | dl_events_in_line = EVENTS_PER_ROW; |
c6648b66 | 1242 | |
6868626b | 1243 | sr_info("Downloading sample data."); |
dde0175d | 1244 | devc->state.state = SIGMA_DOWNLOAD; |
6868626b | 1245 | |
22f64ed8 GS |
1246 | /* |
1247 | * Ask the hardware to stop data acquisition. Reception of the | |
1248 | * FORCESTOP request makes the hardware "disable RLE" (store | |
1249 | * clusters to DRAM regardless of whether pin state changes) and | |
1250 | * raise the POSTTRIGGERED flag. | |
1251 | */ | |
1252 | sigma_set_register(WRITE_MODE, WMR_FORCESTOP | WMR_SDRAMWRITEEN, devc); | |
1253 | do { | |
f73b00b6 | 1254 | if (sigma_read_register(READ_MODE, &modestatus, 1, devc) != 1) { |
bfa79fbd | 1255 | sr_err("failed while waiting for RMR_POSTTRIGGERED bit"); |
f73b00b6 DT |
1256 | return FALSE; |
1257 | } | |
22f64ed8 | 1258 | } while (!(modestatus & RMR_POSTTRIGGERED)); |
6057d9fa MV |
1259 | |
1260 | /* Set SDRAM Read Enable. */ | |
22f64ed8 | 1261 | sigma_set_register(WRITE_MODE, WMR_SDRAMREADEN, devc); |
6057d9fa MV |
1262 | |
1263 | /* Get the current position. */ | |
462fe786 | 1264 | sigma_read_pos(&stoppos, &triggerpos, devc); |
6057d9fa MV |
1265 | |
1266 | /* Check if trigger has fired. */ | |
f73b00b6 | 1267 | if (sigma_read_register(READ_MODE, &modestatus, 1, devc) != 1) { |
bfa79fbd | 1268 | sr_err("failed to read READ_MODE register"); |
f73b00b6 DT |
1269 | return FALSE; |
1270 | } | |
dc400817 GS |
1271 | trg_line = ~0; |
1272 | trg_event = ~0; | |
22f64ed8 | 1273 | if (modestatus & RMR_TRIGGERED) { |
c6648b66 | 1274 | trg_line = triggerpos >> 9; |
1e23158b MV |
1275 | trg_event = triggerpos & 0x1ff; |
1276 | } | |
6057d9fa | 1277 | |
c6648b66 | 1278 | /* |
74d453ab GS |
1279 | * Determine how many "DRAM lines" of 1024 bytes each we need to |
1280 | * retrieve from the Sigma hardware, so that we have a complete | |
1281 | * set of samples. Note that the last line need not contain 64 | |
1282 | * clusters, it might be partially filled only. | |
1283 | * | |
1284 | * When RMR_ROUND is set, the circular buffer in DRAM has wrapped | |
1285 | * around. Since the status of the very next line is uncertain in | |
2c33b092 | 1286 | * that case, we skip it and start reading from the next line. |
c6648b66 | 1287 | */ |
2c33b092 GS |
1288 | dl_first_line = 0; |
1289 | dl_lines_total = (stoppos >> ROW_SHIFT) + 1; | |
74d453ab GS |
1290 | if (modestatus & RMR_ROUND) { |
1291 | dl_first_line = dl_lines_total + 1; | |
2c33b092 | 1292 | dl_lines_total = ROW_COUNT - 2; |
74d453ab | 1293 | } |
44081095 DT |
1294 | dram_line = g_try_malloc0(chunks_per_read * sizeof(*dram_line)); |
1295 | if (!dram_line) | |
1296 | return FALSE; | |
98b43eb3 GS |
1297 | ret = alloc_submit_buffer(sdi); |
1298 | if (ret != SR_OK) | |
1299 | return FALSE; | |
5e78a564 | 1300 | ret = setup_submit_limit(devc); |
98b43eb3 GS |
1301 | if (ret != SR_OK) |
1302 | return FALSE; | |
c6648b66 | 1303 | dl_lines_done = 0; |
c6648b66 MV |
1304 | while (dl_lines_total > dl_lines_done) { |
1305 | /* We can download only up-to 32 DRAM lines in one go! */ | |
547c4cdc | 1306 | dl_lines_curr = MIN(chunks_per_read, dl_lines_total - dl_lines_done); |
6868626b | 1307 | |
74d453ab | 1308 | dl_line = dl_first_line + dl_lines_done; |
2c33b092 | 1309 | dl_line %= ROW_COUNT; |
74d453ab | 1310 | bufsz = sigma_read_dram(dl_line, dl_lines_curr, |
f41a4cae | 1311 | (uint8_t *)dram_line, devc); |
c6648b66 MV |
1312 | /* TODO: Check bufsz. For now, just avoid compiler warnings. */ |
1313 | (void)bufsz; | |
6868626b | 1314 | |
c6648b66 MV |
1315 | /* This is the first DRAM line, so find the initial timestamp. */ |
1316 | if (dl_lines_done == 0) { | |
3513d965 MV |
1317 | devc->state.lastts = |
1318 | sigma_dram_cluster_ts(&dram_line[0].cluster[0]); | |
c6648b66 | 1319 | devc->state.lastsample = 0; |
6868626b BV |
1320 | } |
1321 | ||
c6648b66 | 1322 | for (i = 0; i < dl_lines_curr; i++) { |
1e23158b | 1323 | uint32_t trigger_event = ~0; |
c6648b66 MV |
1324 | /* The last "DRAM line" can be only partially full. */ |
1325 | if (dl_lines_done + i == dl_lines_total - 1) | |
46641fac | 1326 | dl_events_in_line = stoppos & 0x1ff; |
c6648b66 | 1327 | |
e69ad48e | 1328 | /* Test if the trigger happened on this line. */ |
c6648b66 | 1329 | if (dl_lines_done + i == trg_line) |
1e23158b | 1330 | trigger_event = trg_event; |
e69ad48e | 1331 | |
98b43eb3 GS |
1332 | decode_chunk_ts(devc, dram_line + i, |
1333 | dl_events_in_line, trigger_event); | |
c6648b66 | 1334 | } |
6868626b | 1335 | |
c6648b66 | 1336 | dl_lines_done += dl_lines_curr; |
6868626b | 1337 | } |
98b43eb3 GS |
1338 | flush_submit_buffer(devc); |
1339 | free_submit_buffer(devc); | |
dde0175d | 1340 | g_free(dram_line); |
6868626b | 1341 | |
bee2b016 | 1342 | std_session_send_df_end(sdi); |
6057d9fa | 1343 | |
dde0175d | 1344 | devc->state.state = SIGMA_IDLE; |
d2f7c417 | 1345 | sr_dev_acquisition_stop(sdi); |
6057d9fa MV |
1346 | |
1347 | return TRUE; | |
6868626b BV |
1348 | } |
1349 | ||
d4051930 | 1350 | /* |
74d453ab GS |
1351 | * Periodically check the Sigma status when in CAPTURE mode. This routine |
1352 | * checks whether the configured sample count or sample time have passed, | |
1353 | * and will stop acquisition and download the acquired samples. | |
d4051930 MV |
1354 | */ |
1355 | static int sigma_capture_mode(struct sr_dev_inst *sdi) | |
6868626b | 1356 | { |
f06fb3e9 | 1357 | struct dev_context *devc; |
28a35d8a | 1358 | |
f06fb3e9 | 1359 | devc = sdi->priv; |
5e78a564 | 1360 | if (sr_sw_limits_check(&devc->acq_limits)) |
6057d9fa | 1361 | return download_capture(sdi); |
00c86508 | 1362 | |
d4051930 MV |
1363 | return TRUE; |
1364 | } | |
28a35d8a | 1365 | |
3ba56876 | 1366 | SR_PRIV int sigma_receive_data(int fd, int revents, void *cb_data) |
d4051930 MV |
1367 | { |
1368 | struct sr_dev_inst *sdi; | |
1369 | struct dev_context *devc; | |
88c51afe | 1370 | |
d4051930 MV |
1371 | (void)fd; |
1372 | (void)revents; | |
88c51afe | 1373 | |
d4051930 MV |
1374 | sdi = cb_data; |
1375 | devc = sdi->priv; | |
1376 | ||
1377 | if (devc->state.state == SIGMA_IDLE) | |
1378 | return TRUE; | |
1379 | ||
dde0175d GS |
1380 | /* |
1381 | * When the application has requested to stop the acquisition, | |
1382 | * then immediately start downloading sample data. Otherwise | |
1383 | * keep checking configured limits which will terminate the | |
1384 | * acquisition and initiate download. | |
1385 | */ | |
1386 | if (devc->state.state == SIGMA_STOPPING) | |
1387 | return download_capture(sdi); | |
d4051930 MV |
1388 | if (devc->state.state == SIGMA_CAPTURE) |
1389 | return sigma_capture_mode(sdi); | |
28a35d8a | 1390 | |
28a35d8a HE |
1391 | return TRUE; |
1392 | } | |
1393 | ||
c53d793f HE |
1394 | /* Build a LUT entry used by the trigger functions. */ |
1395 | static void build_lut_entry(uint16_t value, uint16_t mask, uint16_t *entry) | |
ee492173 HE |
1396 | { |
1397 | int i, j, k, bit; | |
1398 | ||
ba7dd8bb | 1399 | /* For each quad channel. */ |
0a1f7b09 | 1400 | for (i = 0; i < 4; i++) { |
c53d793f | 1401 | entry[i] = 0xffff; |
ee492173 | 1402 | |
f758d074 | 1403 | /* For each bit in LUT. */ |
0a1f7b09 | 1404 | for (j = 0; j < 16; j++) |
ee492173 | 1405 | |
ba7dd8bb | 1406 | /* For each channel in quad. */ |
0a1f7b09 | 1407 | for (k = 0; k < 4; k++) { |
ee492173 HE |
1408 | bit = 1 << (i * 4 + k); |
1409 | ||
c53d793f | 1410 | /* Set bit in entry */ |
0a1f7b09 UH |
1411 | if ((mask & bit) && ((!(value & bit)) != |
1412 | (!(j & (1 << k))))) | |
c53d793f | 1413 | entry[i] &= ~(1 << j); |
ee492173 HE |
1414 | } |
1415 | } | |
c53d793f | 1416 | } |
ee492173 | 1417 | |
c53d793f HE |
1418 | /* Add a logical function to LUT mask. */ |
1419 | static void add_trigger_function(enum triggerop oper, enum triggerfunc func, | |
1420 | int index, int neg, uint16_t *mask) | |
1421 | { | |
1422 | int i, j; | |
1423 | int x[2][2], tmp, a, b, aset, bset, rset; | |
1424 | ||
1425 | memset(x, 0, 4 * sizeof(int)); | |
1426 | ||
1427 | /* Trigger detect condition. */ | |
1428 | switch (oper) { | |
1429 | case OP_LEVEL: | |
1430 | x[0][1] = 1; | |
1431 | x[1][1] = 1; | |
1432 | break; | |
1433 | case OP_NOT: | |
1434 | x[0][0] = 1; | |
1435 | x[1][0] = 1; | |
1436 | break; | |
1437 | case OP_RISE: | |
1438 | x[0][1] = 1; | |
1439 | break; | |
1440 | case OP_FALL: | |
1441 | x[1][0] = 1; | |
1442 | break; | |
1443 | case OP_RISEFALL: | |
1444 | x[0][1] = 1; | |
1445 | x[1][0] = 1; | |
1446 | break; | |
1447 | case OP_NOTRISE: | |
1448 | x[1][1] = 1; | |
1449 | x[0][0] = 1; | |
1450 | x[1][0] = 1; | |
1451 | break; | |
1452 | case OP_NOTFALL: | |
1453 | x[1][1] = 1; | |
1454 | x[0][0] = 1; | |
1455 | x[0][1] = 1; | |
1456 | break; | |
1457 | case OP_NOTRISEFALL: | |
1458 | x[1][1] = 1; | |
1459 | x[0][0] = 1; | |
1460 | break; | |
1461 | } | |
1462 | ||
1463 | /* Transpose if neg is set. */ | |
1464 | if (neg) { | |
0a1f7b09 UH |
1465 | for (i = 0; i < 2; i++) { |
1466 | for (j = 0; j < 2; j++) { | |
c53d793f | 1467 | tmp = x[i][j]; |
0a1f7b09 UH |
1468 | x[i][j] = x[1 - i][1 - j]; |
1469 | x[1 - i][1 - j] = tmp; | |
c53d793f | 1470 | } |
ea9cfed7 | 1471 | } |
c53d793f HE |
1472 | } |
1473 | ||
1474 | /* Update mask with function. */ | |
0a1f7b09 | 1475 | for (i = 0; i < 16; i++) { |
c53d793f HE |
1476 | a = (i >> (2 * index + 0)) & 1; |
1477 | b = (i >> (2 * index + 1)) & 1; | |
1478 | ||
1479 | aset = (*mask >> i) & 1; | |
1480 | bset = x[b][a]; | |
1481 | ||
382cb19f | 1482 | rset = 0; |
c53d793f HE |
1483 | if (func == FUNC_AND || func == FUNC_NAND) |
1484 | rset = aset & bset; | |
1485 | else if (func == FUNC_OR || func == FUNC_NOR) | |
1486 | rset = aset | bset; | |
1487 | else if (func == FUNC_XOR || func == FUNC_NXOR) | |
1488 | rset = aset ^ bset; | |
1489 | ||
1490 | if (func == FUNC_NAND || func == FUNC_NOR || func == FUNC_NXOR) | |
1491 | rset = !rset; | |
1492 | ||
1493 | *mask &= ~(1 << i); | |
1494 | ||
1495 | if (rset) | |
1496 | *mask |= 1 << i; | |
1497 | } | |
1498 | } | |
1499 | ||
1500 | /* | |
1501 | * Build trigger LUTs used by 50 MHz and lower sample rates for supporting | |
1502 | * simple pin change and state triggers. Only two transitions (rise/fall) can be | |
1503 | * set at any time, but a full mask and value can be set (0/1). | |
1504 | */ | |
3ba56876 | 1505 | SR_PRIV int sigma_build_basic_trigger(struct triggerlut *lut, struct dev_context *devc) |
c53d793f HE |
1506 | { |
1507 | int i,j; | |
4ae1f451 | 1508 | uint16_t masks[2] = { 0, 0 }; |
c53d793f HE |
1509 | |
1510 | memset(lut, 0, sizeof(struct triggerlut)); | |
1511 | ||
f3f19d11 | 1512 | /* Constant for simple triggers. */ |
c53d793f HE |
1513 | lut->m4 = 0xa000; |
1514 | ||
1515 | /* Value/mask trigger support. */ | |
0e1357e8 | 1516 | build_lut_entry(devc->trigger.simplevalue, devc->trigger.simplemask, |
99965709 | 1517 | lut->m2d); |
c53d793f HE |
1518 | |
1519 | /* Rise/fall trigger support. */ | |
0a1f7b09 | 1520 | for (i = 0, j = 0; i < 16; i++) { |
0e1357e8 BV |
1521 | if (devc->trigger.risingmask & (1 << i) || |
1522 | devc->trigger.fallingmask & (1 << i)) | |
c53d793f HE |
1523 | masks[j++] = 1 << i; |
1524 | } | |
1525 | ||
1526 | build_lut_entry(masks[0], masks[0], lut->m0d); | |
1527 | build_lut_entry(masks[1], masks[1], lut->m1d); | |
1528 | ||
1529 | /* Add glue logic */ | |
1530 | if (masks[0] || masks[1]) { | |
1531 | /* Transition trigger. */ | |
0e1357e8 | 1532 | if (masks[0] & devc->trigger.risingmask) |
c53d793f | 1533 | add_trigger_function(OP_RISE, FUNC_OR, 0, 0, &lut->m3); |
0e1357e8 | 1534 | if (masks[0] & devc->trigger.fallingmask) |
c53d793f | 1535 | add_trigger_function(OP_FALL, FUNC_OR, 0, 0, &lut->m3); |
0e1357e8 | 1536 | if (masks[1] & devc->trigger.risingmask) |
c53d793f | 1537 | add_trigger_function(OP_RISE, FUNC_OR, 1, 0, &lut->m3); |
0e1357e8 | 1538 | if (masks[1] & devc->trigger.fallingmask) |
c53d793f HE |
1539 | add_trigger_function(OP_FALL, FUNC_OR, 1, 0, &lut->m3); |
1540 | } else { | |
1541 | /* Only value/mask trigger. */ | |
1542 | lut->m3 = 0xffff; | |
1543 | } | |
ee492173 | 1544 | |
c53d793f | 1545 | /* Triggertype: event. */ |
ee492173 HE |
1546 | lut->params.selres = 3; |
1547 | ||
e46b8fb1 | 1548 | return SR_OK; |
ee492173 | 1549 | } |