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Commit | Line | Data |
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28a35d8a | 1 | /* |
50985c20 | 2 | * This file is part of the libsigrok project. |
28a35d8a | 3 | * |
868501fa | 4 | * Copyright (C) 2010-2012 Håvard Espeland <gus@ping.uio.no>, |
911f1834 UH |
5 | * Copyright (C) 2010 Martin Stensgård <mastensg@ping.uio.no> |
6 | * Copyright (C) 2010 Carl Henrik Lunde <chlunde@ping.uio.no> | |
28a35d8a HE |
7 | * |
8 | * This program is free software: you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation, either version 3 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
20 | */ | |
21 | ||
911f1834 | 22 | /* |
6352d030 | 23 | * ASIX SIGMA/SIGMA2 logic analyzer driver |
911f1834 UH |
24 | */ |
25 | ||
6ec6c43b | 26 | #include <config.h> |
3ba56876 | 27 | #include "protocol.h" |
28a35d8a | 28 | |
b1648dea MV |
29 | /* |
30 | * The ASIX Sigma supports arbitrary integer frequency divider in | |
31 | * the 50MHz mode. The divider is in range 1...256 , allowing for | |
32 | * very precise sampling rate selection. This driver supports only | |
33 | * a subset of the sampling rates. | |
34 | */ | |
3ba56876 | 35 | SR_PRIV const uint64_t samplerates[] = { |
b1648dea MV |
36 | SR_KHZ(200), /* div=250 */ |
37 | SR_KHZ(250), /* div=200 */ | |
38 | SR_KHZ(500), /* div=100 */ | |
39 | SR_MHZ(1), /* div=50 */ | |
40 | SR_MHZ(5), /* div=10 */ | |
41 | SR_MHZ(10), /* div=5 */ | |
42 | SR_MHZ(25), /* div=2 */ | |
43 | SR_MHZ(50), /* div=1 */ | |
44 | SR_MHZ(100), /* Special FW needed */ | |
45 | SR_MHZ(200), /* Special FW needed */ | |
28a35d8a HE |
46 | }; |
47 | ||
4154a516 | 48 | SR_PRIV const size_t samplerates_count = ARRAY_SIZE(samplerates); |
39c64c6a | 49 | |
4b25cbff | 50 | static const char firmware_files[][24] = { |
499b17e9 | 51 | /* 50 MHz, supports 8 bit fractions */ |
8e2d6c9d | 52 | "asix-sigma-50.fw", |
499b17e9 | 53 | /* 100 MHz */ |
8e2d6c9d | 54 | "asix-sigma-100.fw", |
499b17e9 | 55 | /* 200 MHz */ |
8e2d6c9d | 56 | "asix-sigma-200.fw", |
499b17e9 | 57 | /* Synchronous clock from pin */ |
8e2d6c9d | 58 | "asix-sigma-50sync.fw", |
499b17e9 | 59 | /* Frequency counter */ |
8e2d6c9d | 60 | "asix-sigma-phasor.fw", |
f6564c8d HE |
61 | }; |
62 | ||
0e1357e8 | 63 | static int sigma_read(void *buf, size_t size, struct dev_context *devc) |
28a35d8a HE |
64 | { |
65 | int ret; | |
fefa1800 | 66 | |
0e1357e8 | 67 | ret = ftdi_read_data(&devc->ftdic, (unsigned char *)buf, size); |
28a35d8a | 68 | if (ret < 0) { |
47f4f073 | 69 | sr_err("ftdi_read_data failed: %s", |
0e1357e8 | 70 | ftdi_get_error_string(&devc->ftdic)); |
28a35d8a HE |
71 | } |
72 | ||
73 | return ret; | |
74 | } | |
75 | ||
0e1357e8 | 76 | static int sigma_write(void *buf, size_t size, struct dev_context *devc) |
28a35d8a HE |
77 | { |
78 | int ret; | |
fefa1800 | 79 | |
0e1357e8 | 80 | ret = ftdi_write_data(&devc->ftdic, (unsigned char *)buf, size); |
8ebad343 | 81 | if (ret < 0) |
47f4f073 | 82 | sr_err("ftdi_write_data failed: %s", |
0e1357e8 | 83 | ftdi_get_error_string(&devc->ftdic)); |
8ebad343 | 84 | else if ((size_t) ret != size) |
47f4f073 | 85 | sr_err("ftdi_write_data did not complete write."); |
28a35d8a HE |
86 | |
87 | return ret; | |
88 | } | |
89 | ||
e8686e3a AG |
90 | /* |
91 | * NOTE: We chose the buffer size to be large enough to hold any write to the | |
92 | * device. We still print a message just in case. | |
93 | */ | |
3ba56876 | 94 | SR_PRIV int sigma_write_register(uint8_t reg, uint8_t *data, size_t len, |
95 | struct dev_context *devc) | |
28a35d8a HE |
96 | { |
97 | size_t i; | |
e8686e3a | 98 | uint8_t buf[80]; |
28a35d8a HE |
99 | int idx = 0; |
100 | ||
7c86d853 | 101 | if ((2 * len + 2) > sizeof(buf)) { |
e8686e3a | 102 | sr_err("Attempted to write %zu bytes, but buffer is too small.", |
7c86d853 | 103 | len); |
e8686e3a AG |
104 | return SR_ERR_BUG; |
105 | } | |
106 | ||
28a35d8a HE |
107 | buf[idx++] = REG_ADDR_LOW | (reg & 0xf); |
108 | buf[idx++] = REG_ADDR_HIGH | (reg >> 4); | |
109 | ||
0a1f7b09 | 110 | for (i = 0; i < len; i++) { |
28a35d8a HE |
111 | buf[idx++] = REG_DATA_LOW | (data[i] & 0xf); |
112 | buf[idx++] = REG_DATA_HIGH_WRITE | (data[i] >> 4); | |
113 | } | |
114 | ||
0e1357e8 | 115 | return sigma_write(buf, idx, devc); |
28a35d8a HE |
116 | } |
117 | ||
3ba56876 | 118 | SR_PRIV int sigma_set_register(uint8_t reg, uint8_t value, struct dev_context *devc) |
28a35d8a | 119 | { |
0e1357e8 | 120 | return sigma_write_register(reg, &value, 1, devc); |
28a35d8a HE |
121 | } |
122 | ||
99965709 | 123 | static int sigma_read_register(uint8_t reg, uint8_t *data, size_t len, |
0e1357e8 | 124 | struct dev_context *devc) |
28a35d8a HE |
125 | { |
126 | uint8_t buf[3]; | |
fefa1800 | 127 | |
28a35d8a HE |
128 | buf[0] = REG_ADDR_LOW | (reg & 0xf); |
129 | buf[1] = REG_ADDR_HIGH | (reg >> 4); | |
28a35d8a HE |
130 | buf[2] = REG_READ_ADDR; |
131 | ||
0e1357e8 | 132 | sigma_write(buf, sizeof(buf), devc); |
28a35d8a | 133 | |
0e1357e8 | 134 | return sigma_read(data, len, devc); |
28a35d8a HE |
135 | } |
136 | ||
0e1357e8 | 137 | static uint8_t sigma_get_register(uint8_t reg, struct dev_context *devc) |
28a35d8a HE |
138 | { |
139 | uint8_t value; | |
fefa1800 | 140 | |
0e1357e8 | 141 | if (1 != sigma_read_register(reg, &value, 1, devc)) { |
47f4f073 | 142 | sr_err("sigma_get_register: 1 byte expected"); |
28a35d8a HE |
143 | return 0; |
144 | } | |
145 | ||
146 | return value; | |
147 | } | |
148 | ||
99965709 | 149 | static int sigma_read_pos(uint32_t *stoppos, uint32_t *triggerpos, |
0e1357e8 | 150 | struct dev_context *devc) |
28a35d8a HE |
151 | { |
152 | uint8_t buf[] = { | |
153 | REG_ADDR_LOW | READ_TRIGGER_POS_LOW, | |
154 | ||
155 | REG_READ_ADDR | NEXT_REG, | |
156 | REG_READ_ADDR | NEXT_REG, | |
157 | REG_READ_ADDR | NEXT_REG, | |
158 | REG_READ_ADDR | NEXT_REG, | |
159 | REG_READ_ADDR | NEXT_REG, | |
160 | REG_READ_ADDR | NEXT_REG, | |
161 | }; | |
28a35d8a HE |
162 | uint8_t result[6]; |
163 | ||
0e1357e8 | 164 | sigma_write(buf, sizeof(buf), devc); |
28a35d8a | 165 | |
0e1357e8 | 166 | sigma_read(result, sizeof(result), devc); |
28a35d8a HE |
167 | |
168 | *triggerpos = result[0] | (result[1] << 8) | (result[2] << 16); | |
169 | *stoppos = result[3] | (result[4] << 8) | (result[5] << 16); | |
170 | ||
dc400817 GS |
171 | /* |
172 | * These "position" values point to after the event (end of | |
173 | * capture data, trigger condition matched). This is why they | |
174 | * get decremented here. Sample memory consists of 512-byte | |
175 | * chunks with meta data in the upper 64 bytes. Thus when the | |
176 | * decrements takes us into this upper part of the chunk, then | |
177 | * further move backwards to the end of the chunk's data part. | |
178 | */ | |
57bbf56b | 179 | if ((--*stoppos & 0x1ff) == 0x1ff) |
382cb19f | 180 | *stoppos -= 64; |
dc400817 | 181 | if ((--*triggerpos & 0x1ff) == 0x1ff) |
382cb19f | 182 | *triggerpos -= 64; |
57bbf56b | 183 | |
28a35d8a HE |
184 | return 1; |
185 | } | |
186 | ||
99965709 | 187 | static int sigma_read_dram(uint16_t startchunk, size_t numchunks, |
0e1357e8 | 188 | uint8_t *data, struct dev_context *devc) |
28a35d8a HE |
189 | { |
190 | size_t i; | |
191 | uint8_t buf[4096]; | |
f06fb3e9 | 192 | int idx; |
28a35d8a | 193 | |
fefa1800 | 194 | /* Send the startchunk. Index start with 1. */ |
f06fb3e9 GS |
195 | idx = 0; |
196 | buf[idx++] = startchunk >> 8; | |
197 | buf[idx++] = startchunk & 0xff; | |
198 | sigma_write_register(WRITE_MEMROW, buf, idx, devc); | |
28a35d8a | 199 | |
fefa1800 | 200 | /* Read the DRAM. */ |
f06fb3e9 | 201 | idx = 0; |
28a35d8a HE |
202 | buf[idx++] = REG_DRAM_BLOCK; |
203 | buf[idx++] = REG_DRAM_WAIT_ACK; | |
204 | ||
0a1f7b09 | 205 | for (i = 0; i < numchunks; i++) { |
fefa1800 UH |
206 | /* Alternate bit to copy from DRAM to cache. */ |
207 | if (i != (numchunks - 1)) | |
208 | buf[idx++] = REG_DRAM_BLOCK | (((i + 1) % 2) << 4); | |
28a35d8a HE |
209 | |
210 | buf[idx++] = REG_DRAM_BLOCK_DATA | ((i % 2) << 4); | |
211 | ||
fefa1800 | 212 | if (i != (numchunks - 1)) |
28a35d8a HE |
213 | buf[idx++] = REG_DRAM_WAIT_ACK; |
214 | } | |
215 | ||
0e1357e8 | 216 | sigma_write(buf, idx, devc); |
28a35d8a | 217 | |
0e1357e8 | 218 | return sigma_read(data, numchunks * CHUNK_SIZE, devc); |
28a35d8a HE |
219 | } |
220 | ||
4ae1f451 | 221 | /* Upload trigger look-up tables to Sigma. */ |
3ba56876 | 222 | SR_PRIV int sigma_write_trigger_lut(struct triggerlut *lut, struct dev_context *devc) |
ee492173 HE |
223 | { |
224 | int i; | |
225 | uint8_t tmp[2]; | |
226 | uint16_t bit; | |
227 | ||
228 | /* Transpose the table and send to Sigma. */ | |
0a1f7b09 | 229 | for (i = 0; i < 16; i++) { |
ee492173 HE |
230 | bit = 1 << i; |
231 | ||
232 | tmp[0] = tmp[1] = 0; | |
233 | ||
234 | if (lut->m2d[0] & bit) | |
235 | tmp[0] |= 0x01; | |
236 | if (lut->m2d[1] & bit) | |
237 | tmp[0] |= 0x02; | |
238 | if (lut->m2d[2] & bit) | |
239 | tmp[0] |= 0x04; | |
240 | if (lut->m2d[3] & bit) | |
241 | tmp[0] |= 0x08; | |
242 | ||
243 | if (lut->m3 & bit) | |
244 | tmp[0] |= 0x10; | |
245 | if (lut->m3s & bit) | |
246 | tmp[0] |= 0x20; | |
247 | if (lut->m4 & bit) | |
248 | tmp[0] |= 0x40; | |
249 | ||
250 | if (lut->m0d[0] & bit) | |
251 | tmp[1] |= 0x01; | |
252 | if (lut->m0d[1] & bit) | |
253 | tmp[1] |= 0x02; | |
254 | if (lut->m0d[2] & bit) | |
255 | tmp[1] |= 0x04; | |
256 | if (lut->m0d[3] & bit) | |
257 | tmp[1] |= 0x08; | |
258 | ||
259 | if (lut->m1d[0] & bit) | |
260 | tmp[1] |= 0x10; | |
261 | if (lut->m1d[1] & bit) | |
262 | tmp[1] |= 0x20; | |
263 | if (lut->m1d[2] & bit) | |
264 | tmp[1] |= 0x40; | |
265 | if (lut->m1d[3] & bit) | |
266 | tmp[1] |= 0x80; | |
267 | ||
99965709 | 268 | sigma_write_register(WRITE_TRIGGER_SELECT0, tmp, sizeof(tmp), |
0e1357e8 BV |
269 | devc); |
270 | sigma_set_register(WRITE_TRIGGER_SELECT1, 0x30 | i, devc); | |
ee492173 HE |
271 | } |
272 | ||
273 | /* Send the parameters */ | |
274 | sigma_write_register(WRITE_TRIGGER_SELECT0, (uint8_t *) &lut->params, | |
0e1357e8 | 275 | sizeof(lut->params), devc); |
ee492173 | 276 | |
e46b8fb1 | 277 | return SR_OK; |
ee492173 HE |
278 | } |
279 | ||
d5fa188a MV |
280 | /* |
281 | * Configure the FPGA for bitbang mode. | |
282 | * This sequence is documented in section 2. of the ASIX Sigma programming | |
283 | * manual. This sequence is necessary to configure the FPGA in the Sigma | |
284 | * into Bitbang mode, in which it can be programmed with the firmware. | |
285 | */ | |
286 | static int sigma_fpga_init_bitbang(struct dev_context *devc) | |
287 | { | |
288 | uint8_t suicide[] = { | |
289 | 0x84, 0x84, 0x88, 0x84, 0x88, 0x84, 0x88, 0x84, | |
290 | }; | |
291 | uint8_t init_array[] = { | |
292 | 0x01, 0x03, 0x03, 0x01, 0x01, 0x01, 0x01, 0x01, | |
293 | 0x01, 0x01, | |
294 | }; | |
1a46cc62 | 295 | int i, ret, timeout = (10 * 1000); |
d5fa188a MV |
296 | uint8_t data; |
297 | ||
298 | /* Section 2. part 1), do the FPGA suicide. */ | |
299 | sigma_write(suicide, sizeof(suicide), devc); | |
300 | sigma_write(suicide, sizeof(suicide), devc); | |
301 | sigma_write(suicide, sizeof(suicide), devc); | |
302 | sigma_write(suicide, sizeof(suicide), devc); | |
303 | ||
304 | /* Section 2. part 2), do pulse on D1. */ | |
305 | sigma_write(init_array, sizeof(init_array), devc); | |
306 | ftdi_usb_purge_buffers(&devc->ftdic); | |
307 | ||
308 | /* Wait until the FPGA asserts D6/INIT_B. */ | |
309 | for (i = 0; i < timeout; i++) { | |
310 | ret = sigma_read(&data, 1, devc); | |
311 | if (ret < 0) | |
312 | return ret; | |
313 | /* Test if pin D6 got asserted. */ | |
314 | if (data & (1 << 5)) | |
315 | return 0; | |
316 | /* The D6 was not asserted yet, wait a bit. */ | |
1a46cc62 | 317 | g_usleep(10 * 1000); |
d5fa188a MV |
318 | } |
319 | ||
320 | return SR_ERR_TIMEOUT; | |
321 | } | |
322 | ||
64fe661b MV |
323 | /* |
324 | * Configure the FPGA for logic-analyzer mode. | |
325 | */ | |
326 | static int sigma_fpga_init_la(struct dev_context *devc) | |
327 | { | |
328 | /* Initialize the logic analyzer mode. */ | |
22f64ed8 | 329 | uint8_t mode_regval = WMR_SDRAMINIT; |
64fe661b | 330 | uint8_t logic_mode_start[] = { |
011f1091 | 331 | REG_ADDR_LOW | (READ_ID & 0xf), |
84a6ed1a | 332 | REG_ADDR_HIGH | (READ_ID >> 4), |
011f1091 MV |
333 | REG_READ_ADDR, /* Read ID register. */ |
334 | ||
335 | REG_ADDR_LOW | (WRITE_TEST & 0xf), | |
336 | REG_DATA_LOW | 0x5, | |
337 | REG_DATA_HIGH_WRITE | 0x5, | |
338 | REG_READ_ADDR, /* Read scratch register. */ | |
339 | ||
340 | REG_DATA_LOW | 0xa, | |
341 | REG_DATA_HIGH_WRITE | 0xa, | |
342 | REG_READ_ADDR, /* Read scratch register. */ | |
343 | ||
344 | REG_ADDR_LOW | (WRITE_MODE & 0xf), | |
22f64ed8 GS |
345 | REG_DATA_LOW | (mode_regval & 0xf), |
346 | REG_DATA_HIGH_WRITE | (mode_regval >> 4), | |
64fe661b MV |
347 | }; |
348 | ||
349 | uint8_t result[3]; | |
350 | int ret; | |
351 | ||
352 | /* Initialize the logic analyzer mode. */ | |
353 | sigma_write(logic_mode_start, sizeof(logic_mode_start), devc); | |
354 | ||
011f1091 | 355 | /* Expect a 3 byte reply since we issued three READ requests. */ |
64fe661b MV |
356 | ret = sigma_read(result, 3, devc); |
357 | if (ret != 3) | |
358 | goto err; | |
359 | ||
360 | if (result[0] != 0xa6 || result[1] != 0x55 || result[2] != 0xaa) | |
361 | goto err; | |
362 | ||
363 | return SR_OK; | |
364 | err: | |
365 | sr_err("Configuration failed. Invalid reply received."); | |
366 | return SR_ERR; | |
367 | } | |
368 | ||
a80226bb MV |
369 | /* |
370 | * Read the firmware from a file and transform it into a series of bitbang | |
371 | * pulses used to program the FPGA. Note that the *bb_cmd must be free()'d | |
372 | * by the caller of this function. | |
373 | */ | |
8e2d6c9d | 374 | static int sigma_fw_2_bitbang(struct sr_context *ctx, const char *name, |
a80226bb MV |
375 | uint8_t **bb_cmd, gsize *bb_cmd_size) |
376 | { | |
8e2d6c9d DE |
377 | size_t i, file_size, bb_size; |
378 | char *firmware; | |
a80226bb MV |
379 | uint8_t *bb_stream, *bbs; |
380 | uint32_t imm; | |
381 | int bit, v; | |
382 | int ret = SR_OK; | |
383 | ||
387825dc | 384 | /* Retrieve the on-disk firmware file content. */ |
8e2d6c9d DE |
385 | firmware = sr_resource_load(ctx, SR_RESOURCE_FIRMWARE, |
386 | name, &file_size, 256 * 1024); | |
387 | if (!firmware) | |
388 | return SR_ERR; | |
a80226bb | 389 | |
387825dc | 390 | /* Unscramble the file content (XOR with "random" sequence). */ |
a80226bb MV |
391 | imm = 0x3f6df2ab; |
392 | for (i = 0; i < file_size; i++) { | |
393 | imm = (imm + 0xa853753) % 177 + (imm * 0x8034052); | |
394 | firmware[i] ^= imm & 0xff; | |
395 | } | |
396 | ||
397 | /* | |
387825dc GS |
398 | * Generate a sequence of bitbang samples. With two samples per |
399 | * FPGA configuration bit, providing the level for the DIN signal | |
400 | * as well as two edges for CCLK. See Xilinx UG332 for details | |
401 | * ("slave serial" mode). | |
402 | * | |
403 | * Note that CCLK is inverted in hardware. That's why the | |
404 | * respective bit is first set and then cleared in the bitbang | |
405 | * sample sets. So that the DIN level will be stable when the | |
406 | * data gets sampled at the rising CCLK edge, and the signals' | |
407 | * setup time constraint will be met. | |
408 | * | |
409 | * The caller will put the FPGA into download mode, will send | |
410 | * the bitbang samples, and release the allocated memory. | |
a80226bb | 411 | */ |
a80226bb MV |
412 | bb_size = file_size * 8 * 2; |
413 | bb_stream = (uint8_t *)g_try_malloc(bb_size); | |
414 | if (!bb_stream) { | |
415 | sr_err("%s: Failed to allocate bitbang stream", __func__); | |
416 | ret = SR_ERR_MALLOC; | |
417 | goto exit; | |
418 | } | |
a80226bb MV |
419 | bbs = bb_stream; |
420 | for (i = 0; i < file_size; i++) { | |
421 | for (bit = 7; bit >= 0; bit--) { | |
422 | v = (firmware[i] & (1 << bit)) ? 0x40 : 0x00; | |
423 | *bbs++ = v | 0x01; | |
424 | *bbs++ = v; | |
425 | } | |
426 | } | |
427 | ||
428 | /* The transformation completed successfully, return the result. */ | |
429 | *bb_cmd = bb_stream; | |
430 | *bb_cmd_size = bb_size; | |
431 | ||
432 | exit: | |
8e2d6c9d | 433 | g_free(firmware); |
a80226bb MV |
434 | return ret; |
435 | } | |
436 | ||
8e2d6c9d DE |
437 | static int upload_firmware(struct sr_context *ctx, |
438 | int firmware_idx, struct dev_context *devc) | |
28a35d8a HE |
439 | { |
440 | int ret; | |
441 | unsigned char *buf; | |
442 | unsigned char pins; | |
443 | size_t buf_size; | |
a9016883 | 444 | const char *firmware; |
a9016883 GS |
445 | |
446 | /* Avoid downloading the same firmware multiple times. */ | |
4b25cbff | 447 | firmware = firmware_files[firmware_idx]; |
a9016883 GS |
448 | if (devc->cur_firmware == firmware_idx) { |
449 | sr_info("Not uploading firmware file '%s' again.", firmware); | |
450 | return SR_OK; | |
451 | } | |
28a35d8a | 452 | |
1f4f98e0 | 453 | ret = ftdi_set_bitmode(&devc->ftdic, 0xdf, BITMODE_BITBANG); |
8bbf7627 | 454 | if (ret < 0) { |
47f4f073 | 455 | sr_err("ftdi_set_bitmode failed: %s", |
1f4f98e0 | 456 | ftdi_get_error_string(&devc->ftdic)); |
7bcf2168 | 457 | return SR_ERR; |
28a35d8a HE |
458 | } |
459 | ||
fefa1800 | 460 | /* Four times the speed of sigmalogan - Works well. */ |
1f4f98e0 | 461 | ret = ftdi_set_baudrate(&devc->ftdic, 750 * 1000); |
8bbf7627 | 462 | if (ret < 0) { |
47f4f073 | 463 | sr_err("ftdi_set_baudrate failed: %s", |
1f4f98e0 | 464 | ftdi_get_error_string(&devc->ftdic)); |
7bcf2168 | 465 | return SR_ERR; |
28a35d8a HE |
466 | } |
467 | ||
d5fa188a MV |
468 | /* Initialize the FPGA for firmware upload. */ |
469 | ret = sigma_fpga_init_bitbang(devc); | |
470 | if (ret) | |
471 | return ret; | |
28a35d8a | 472 | |
9ddb2a12 | 473 | /* Prepare firmware. */ |
8e2d6c9d | 474 | ret = sigma_fw_2_bitbang(ctx, firmware, &buf, &buf_size); |
8bbf7627 | 475 | if (ret != SR_OK) { |
f3f19d11 | 476 | sr_err("An error occurred while reading the firmware: %s", |
499b17e9 | 477 | firmware); |
b53738ba | 478 | return ret; |
28a35d8a HE |
479 | } |
480 | ||
f3f19d11 | 481 | /* Upload firmware. */ |
499b17e9 | 482 | sr_info("Uploading firmware file '%s'.", firmware); |
0e1357e8 | 483 | sigma_write(buf, buf_size, devc); |
28a35d8a HE |
484 | |
485 | g_free(buf); | |
486 | ||
1f4f98e0 | 487 | ret = ftdi_set_bitmode(&devc->ftdic, 0x00, BITMODE_RESET); |
8bbf7627 | 488 | if (ret < 0) { |
47f4f073 | 489 | sr_err("ftdi_set_bitmode failed: %s", |
1f4f98e0 | 490 | ftdi_get_error_string(&devc->ftdic)); |
e46b8fb1 | 491 | return SR_ERR; |
28a35d8a HE |
492 | } |
493 | ||
1f4f98e0 | 494 | ftdi_usb_purge_buffers(&devc->ftdic); |
28a35d8a | 495 | |
fefa1800 | 496 | /* Discard garbage. */ |
29b66a2e | 497 | while (sigma_read(&pins, 1, devc) == 1) |
28a35d8a HE |
498 | ; |
499 | ||
64fe661b MV |
500 | /* Initialize the FPGA for logic-analyzer mode. */ |
501 | ret = sigma_fpga_init_la(devc); | |
502 | if (ret != SR_OK) | |
503 | return ret; | |
28a35d8a | 504 | |
0e1357e8 | 505 | devc->cur_firmware = firmware_idx; |
f6564c8d | 506 | |
47f4f073 | 507 | sr_info("Firmware uploaded."); |
e3fff420 | 508 | |
e46b8fb1 | 509 | return SR_OK; |
f6564c8d HE |
510 | } |
511 | ||
9a0a606a GS |
512 | /* |
513 | * Sigma doesn't support limiting the number of samples, so we have to | |
514 | * translate the number and the samplerate to an elapsed time. | |
515 | * | |
516 | * In addition we need to ensure that the last data cluster has passed | |
517 | * the hardware pipeline, and became available to the PC side. With RLE | |
518 | * compression up to 327ms could pass before another cluster accumulates | |
519 | * at 200kHz samplerate when input pins don't change. | |
520 | */ | |
521 | SR_PRIV uint64_t sigma_limit_samples_to_msec(const struct dev_context *devc, | |
522 | uint64_t limit_samples) | |
523 | { | |
524 | uint64_t limit_msec; | |
525 | uint64_t worst_cluster_time_ms; | |
526 | ||
527 | limit_msec = limit_samples * 1000 / devc->cur_samplerate; | |
528 | worst_cluster_time_ms = 65536 * 1000 / devc->cur_samplerate; | |
529 | /* | |
530 | * One cluster time is not enough to flush pipeline when sampling | |
531 | * grounded pins with 1 sample limit at 200kHz. Hence the 2* fix. | |
532 | */ | |
533 | return limit_msec + 2 * worst_cluster_time_ms; | |
534 | } | |
535 | ||
3ba56876 | 536 | SR_PRIV int sigma_set_samplerate(const struct sr_dev_inst *sdi, uint64_t samplerate) |
f6564c8d | 537 | { |
2c9c0df8 | 538 | struct dev_context *devc; |
8e2d6c9d | 539 | struct drv_context *drvc; |
4154a516 | 540 | size_t i; |
2c9c0df8 | 541 | int ret; |
ac9534f4 | 542 | int num_channels; |
f6564c8d | 543 | |
2c9c0df8 | 544 | devc = sdi->priv; |
8e2d6c9d | 545 | drvc = sdi->driver->context; |
f4abaa9f UH |
546 | ret = SR_OK; |
547 | ||
2f7e529c | 548 | /* Reject rates that are not in the list of supported rates. */ |
4154a516 | 549 | for (i = 0; i < samplerates_count; i++) { |
2c9c0df8 | 550 | if (samplerates[i] == samplerate) |
f6564c8d HE |
551 | break; |
552 | } | |
4154a516 | 553 | if (i >= samplerates_count || samplerates[i] == 0) |
e46b8fb1 | 554 | return SR_ERR_SAMPLERATE; |
f6564c8d | 555 | |
2f7e529c GS |
556 | /* |
557 | * Depending on the samplerates of 200/100/50- MHz, specific | |
558 | * firmware is required and higher rates might limit the set | |
559 | * of available channels. | |
560 | */ | |
ac9534f4 | 561 | num_channels = devc->num_channels; |
59df0c77 | 562 | if (samplerate <= SR_MHZ(50)) { |
8e2d6c9d | 563 | ret = upload_firmware(drvc->sr_ctx, 0, devc); |
ac9534f4 | 564 | num_channels = 16; |
6b2d3385 | 565 | } else if (samplerate == SR_MHZ(100)) { |
8e2d6c9d | 566 | ret = upload_firmware(drvc->sr_ctx, 1, devc); |
ac9534f4 | 567 | num_channels = 8; |
6b2d3385 | 568 | } else if (samplerate == SR_MHZ(200)) { |
8e2d6c9d | 569 | ret = upload_firmware(drvc->sr_ctx, 2, devc); |
ac9534f4 | 570 | num_channels = 4; |
f78898e9 | 571 | } |
f6564c8d | 572 | |
2f7e529c GS |
573 | /* |
574 | * Derive the sample period from the sample rate as well as the | |
575 | * number of samples that the device will communicate within | |
576 | * an "event" (memory organization internal to the device). | |
577 | */ | |
6b2d3385 | 578 | if (ret == SR_OK) { |
ac9534f4 | 579 | devc->num_channels = num_channels; |
6b2d3385 | 580 | devc->cur_samplerate = samplerate; |
6b2d3385 BV |
581 | devc->samples_per_event = 16 / devc->num_channels; |
582 | devc->state.state = SIGMA_IDLE; | |
583 | } | |
f6564c8d | 584 | |
2f7e529c GS |
585 | /* |
586 | * Support for "limit_samples" is implemented by stopping | |
587 | * acquisition after a corresponding period of time. | |
588 | * Re-calculate that period of time, in case the limit is | |
589 | * set first and the samplerate gets (re-)configured later. | |
590 | */ | |
591 | if (ret == SR_OK && devc->limit_samples) { | |
592 | uint64_t msecs; | |
9a0a606a | 593 | msecs = sigma_limit_samples_to_msec(devc, devc->limit_samples); |
2f7e529c GS |
594 | devc->limit_msec = msecs; |
595 | } | |
596 | ||
e8397563 | 597 | return ret; |
28a35d8a HE |
598 | } |
599 | ||
c53d793f HE |
600 | /* |
601 | * In 100 and 200 MHz mode, only a single pin rising/falling can be | |
602 | * set as trigger. In other modes, two rising/falling triggers can be set, | |
ba7dd8bb | 603 | * in addition to value/mask trigger for any number of channels. |
c53d793f HE |
604 | * |
605 | * The Sigma supports complex triggers using boolean expressions, but this | |
606 | * has not been implemented yet. | |
607 | */ | |
3ba56876 | 608 | SR_PRIV int sigma_convert_trigger(const struct sr_dev_inst *sdi) |
57bbf56b | 609 | { |
39c64c6a BV |
610 | struct dev_context *devc; |
611 | struct sr_trigger *trigger; | |
612 | struct sr_trigger_stage *stage; | |
613 | struct sr_trigger_match *match; | |
614 | const GSList *l, *m; | |
615 | int channelbit, trigger_set; | |
57bbf56b | 616 | |
39c64c6a | 617 | devc = sdi->priv; |
0e1357e8 | 618 | memset(&devc->trigger, 0, sizeof(struct sigma_trigger)); |
0812c40e | 619 | if (!(trigger = sr_session_trigger_get(sdi->session))) |
39c64c6a BV |
620 | return SR_OK; |
621 | ||
622 | trigger_set = 0; | |
623 | for (l = trigger->stages; l; l = l->next) { | |
624 | stage = l->data; | |
625 | for (m = stage->matches; m; m = m->next) { | |
626 | match = m->data; | |
627 | if (!match->channel->enabled) | |
628 | /* Ignore disabled channels with a trigger. */ | |
629 | continue; | |
630 | channelbit = 1 << (match->channel->index); | |
631 | if (devc->cur_samplerate >= SR_MHZ(100)) { | |
632 | /* Fast trigger support. */ | |
633 | if (trigger_set) { | |
634 | sr_err("Only a single pin trigger is " | |
635 | "supported in 100 and 200MHz mode."); | |
636 | return SR_ERR; | |
637 | } | |
638 | if (match->match == SR_TRIGGER_FALLING) | |
639 | devc->trigger.fallingmask |= channelbit; | |
640 | else if (match->match == SR_TRIGGER_RISING) | |
641 | devc->trigger.risingmask |= channelbit; | |
642 | else { | |
643 | sr_err("Only rising/falling trigger is " | |
644 | "supported in 100 and 200MHz mode."); | |
645 | return SR_ERR; | |
646 | } | |
eec5275e | 647 | |
0a1f7b09 | 648 | trigger_set++; |
39c64c6a BV |
649 | } else { |
650 | /* Simple trigger support (event). */ | |
651 | if (match->match == SR_TRIGGER_ONE) { | |
652 | devc->trigger.simplevalue |= channelbit; | |
653 | devc->trigger.simplemask |= channelbit; | |
8ebad343 | 654 | } else if (match->match == SR_TRIGGER_ZERO) { |
39c64c6a BV |
655 | devc->trigger.simplevalue &= ~channelbit; |
656 | devc->trigger.simplemask |= channelbit; | |
8ebad343 | 657 | } else if (match->match == SR_TRIGGER_FALLING) { |
39c64c6a | 658 | devc->trigger.fallingmask |= channelbit; |
0a1f7b09 | 659 | trigger_set++; |
8ebad343 | 660 | } else if (match->match == SR_TRIGGER_RISING) { |
39c64c6a | 661 | devc->trigger.risingmask |= channelbit; |
0a1f7b09 | 662 | trigger_set++; |
39c64c6a BV |
663 | } |
664 | ||
665 | /* | |
666 | * Actually, Sigma supports 2 rising/falling triggers, | |
667 | * but they are ORed and the current trigger syntax | |
668 | * does not permit ORed triggers. | |
669 | */ | |
670 | if (trigger_set > 1) { | |
671 | sr_err("Only 1 rising/falling trigger " | |
672 | "is supported."); | |
673 | return SR_ERR; | |
674 | } | |
ee492173 | 675 | } |
ee492173 | 676 | } |
57bbf56b HE |
677 | } |
678 | ||
e46b8fb1 | 679 | return SR_OK; |
57bbf56b HE |
680 | } |
681 | ||
36b1c8e6 | 682 | /* Software trigger to determine exact trigger position. */ |
5fc01191 | 683 | static int get_trigger_offset(uint8_t *samples, uint16_t last_sample, |
36b1c8e6 HE |
684 | struct sigma_trigger *t) |
685 | { | |
686 | int i; | |
5fc01191 | 687 | uint16_t sample = 0; |
36b1c8e6 | 688 | |
0a1f7b09 | 689 | for (i = 0; i < 8; i++) { |
36b1c8e6 | 690 | if (i > 0) |
5fc01191 MV |
691 | last_sample = sample; |
692 | sample = samples[2 * i] | (samples[2 * i + 1] << 8); | |
36b1c8e6 HE |
693 | |
694 | /* Simple triggers. */ | |
5fc01191 | 695 | if ((sample & t->simplemask) != t->simplevalue) |
36b1c8e6 HE |
696 | continue; |
697 | ||
698 | /* Rising edge. */ | |
5fc01191 MV |
699 | if (((last_sample & t->risingmask) != 0) || |
700 | ((sample & t->risingmask) != t->risingmask)) | |
36b1c8e6 HE |
701 | continue; |
702 | ||
703 | /* Falling edge. */ | |
bdfc7a89 | 704 | if ((last_sample & t->fallingmask) != t->fallingmask || |
5fc01191 | 705 | (sample & t->fallingmask) != 0) |
36b1c8e6 HE |
706 | continue; |
707 | ||
708 | break; | |
709 | } | |
710 | ||
711 | /* If we did not match, return original trigger pos. */ | |
712 | return i & 0x7; | |
713 | } | |
714 | ||
3513d965 MV |
715 | /* |
716 | * Return the timestamp of "DRAM cluster". | |
717 | */ | |
718 | static uint16_t sigma_dram_cluster_ts(struct sigma_dram_cluster *cluster) | |
719 | { | |
720 | return (cluster->timestamp_hi << 8) | cluster->timestamp_lo; | |
721 | } | |
722 | ||
0498f743 GS |
723 | /* |
724 | * Return one 16bit data entity of a DRAM cluster at the specified index. | |
725 | */ | |
726 | static uint16_t sigma_dram_cluster_data(struct sigma_dram_cluster *cl, int idx) | |
727 | { | |
728 | uint16_t sample; | |
729 | ||
730 | sample = 0; | |
731 | sample |= cl->samples[idx].sample_lo << 0; | |
732 | sample |= cl->samples[idx].sample_hi << 8; | |
3281cf59 | 733 | sample = (sample >> 8) | (sample << 8); |
0498f743 GS |
734 | return sample; |
735 | } | |
736 | ||
85c032e4 GS |
737 | /* |
738 | * Deinterlace sample data that was retrieved at 100MHz samplerate. | |
739 | * One 16bit item contains two samples of 8bits each. The bits of | |
740 | * multiple samples are interleaved. | |
741 | */ | |
742 | static uint16_t sigma_deinterlace_100mhz_data(uint16_t indata, int idx) | |
743 | { | |
744 | uint16_t outdata; | |
745 | ||
746 | indata >>= idx; | |
747 | outdata = 0; | |
748 | outdata |= (indata >> (0 * 2 - 0)) & (1 << 0); | |
749 | outdata |= (indata >> (1 * 2 - 1)) & (1 << 1); | |
750 | outdata |= (indata >> (2 * 2 - 2)) & (1 << 2); | |
751 | outdata |= (indata >> (3 * 2 - 3)) & (1 << 3); | |
752 | outdata |= (indata >> (4 * 2 - 4)) & (1 << 4); | |
753 | outdata |= (indata >> (5 * 2 - 5)) & (1 << 5); | |
754 | outdata |= (indata >> (6 * 2 - 6)) & (1 << 6); | |
755 | outdata |= (indata >> (7 * 2 - 7)) & (1 << 7); | |
756 | return outdata; | |
757 | } | |
758 | ||
759 | /* | |
760 | * Deinterlace sample data that was retrieved at 200MHz samplerate. | |
761 | * One 16bit item contains four samples of 4bits each. The bits of | |
762 | * multiple samples are interleaved. | |
763 | */ | |
764 | static uint16_t sigma_deinterlace_200mhz_data(uint16_t indata, int idx) | |
765 | { | |
766 | uint16_t outdata; | |
767 | ||
768 | indata >>= idx; | |
769 | outdata = 0; | |
770 | outdata |= (indata >> (0 * 4 - 0)) & (1 << 0); | |
771 | outdata |= (indata >> (1 * 4 - 1)) & (1 << 1); | |
772 | outdata |= (indata >> (2 * 4 - 2)) & (1 << 2); | |
773 | outdata |= (indata >> (3 * 4 - 3)) & (1 << 3); | |
774 | return outdata; | |
775 | } | |
776 | ||
0498f743 GS |
777 | static void store_sr_sample(uint8_t *samples, int idx, uint16_t data) |
778 | { | |
779 | samples[2 * idx + 0] = (data >> 0) & 0xff; | |
780 | samples[2 * idx + 1] = (data >> 8) & 0xff; | |
781 | } | |
782 | ||
735ed8a1 GS |
783 | /* |
784 | * Local wrapper around sr_session_send() calls. Make sure to not send | |
785 | * more samples to the session's datafeed than what was requested by a | |
786 | * previously configured (optional) sample count. | |
787 | */ | |
788 | static void sigma_session_send(struct sr_dev_inst *sdi, | |
789 | struct sr_datafeed_packet *packet) | |
790 | { | |
791 | struct dev_context *devc; | |
792 | struct sr_datafeed_logic *logic; | |
793 | uint64_t send_now; | |
794 | ||
795 | devc = sdi->priv; | |
796 | if (devc->limit_samples) { | |
797 | logic = (void *)packet->payload; | |
798 | send_now = logic->length / logic->unitsize; | |
799 | if (devc->sent_samples + send_now > devc->limit_samples) { | |
800 | send_now = devc->limit_samples - devc->sent_samples; | |
801 | logic->length = send_now * logic->unitsize; | |
802 | } | |
803 | if (!send_now) | |
804 | return; | |
805 | devc->sent_samples += send_now; | |
806 | } | |
807 | ||
808 | sr_session_send(sdi, packet); | |
809 | } | |
810 | ||
85c032e4 GS |
811 | /* |
812 | * This size translates to: event count (1K events per cluster), times | |
813 | * the sample width (unitsize, 16bits per event), times the maximum | |
814 | * number of samples per event. | |
815 | */ | |
816 | #define SAMPLES_BUFFER_SIZE (1024 * 2 * 4) | |
817 | ||
23239b5c MV |
818 | static void sigma_decode_dram_cluster(struct sigma_dram_cluster *dram_cluster, |
819 | unsigned int events_in_cluster, | |
1e23158b | 820 | unsigned int triggered, |
23239b5c MV |
821 | struct sr_dev_inst *sdi) |
822 | { | |
823 | struct dev_context *devc = sdi->priv; | |
824 | struct sigma_state *ss = &devc->state; | |
825 | struct sr_datafeed_packet packet; | |
826 | struct sr_datafeed_logic logic; | |
85c032e4 GS |
827 | uint16_t tsdiff, ts, sample, item16; |
828 | uint8_t samples[SAMPLES_BUFFER_SIZE]; | |
829 | uint8_t *send_ptr; | |
830 | size_t send_count, trig_count; | |
23239b5c | 831 | unsigned int i; |
85c032e4 | 832 | int j; |
23239b5c | 833 | |
23239b5c MV |
834 | ts = sigma_dram_cluster_ts(dram_cluster); |
835 | tsdiff = ts - ss->lastts; | |
a44b3b3f | 836 | ss->lastts = ts + EVENTS_PER_CLUSTER; |
23239b5c MV |
837 | |
838 | packet.type = SR_DF_LOGIC; | |
839 | packet.payload = &logic; | |
840 | logic.unitsize = 2; | |
841 | logic.data = samples; | |
842 | ||
843 | /* | |
468f17f2 GS |
844 | * If this cluster is not adjacent to the previously received |
845 | * cluster, then send the appropriate number of samples with the | |
846 | * previous values to the sigrok session. This "decodes RLE". | |
23239b5c | 847 | */ |
a44b3b3f | 848 | for (ts = 0; ts < tsdiff; ts++) { |
23239b5c | 849 | i = ts % 1024; |
0498f743 | 850 | store_sr_sample(samples, i, ss->lastsample); |
23239b5c MV |
851 | |
852 | /* | |
853 | * If we have 1024 samples ready or we're at the | |
854 | * end of submitting the padding samples, submit | |
85c032e4 GS |
855 | * the packet to Sigrok. Since constant data is |
856 | * sent, duplication of data for rates above 50MHz | |
857 | * is simple. | |
23239b5c | 858 | */ |
a44b3b3f | 859 | if ((i == 1023) || (ts == tsdiff - 1)) { |
23239b5c | 860 | logic.length = (i + 1) * logic.unitsize; |
85c032e4 | 861 | for (j = 0; j < devc->samples_per_event; j++) |
735ed8a1 | 862 | sigma_session_send(sdi, &packet); |
23239b5c MV |
863 | } |
864 | } | |
865 | ||
866 | /* | |
867 | * Parse the samples in current cluster and prepare them | |
85c032e4 GS |
868 | * to be submitted to Sigrok. Cope with memory layouts that |
869 | * vary with the samplerate. | |
23239b5c | 870 | */ |
85c032e4 GS |
871 | send_ptr = &samples[0]; |
872 | send_count = 0; | |
0498f743 | 873 | sample = 0; |
23239b5c | 874 | for (i = 0; i < events_in_cluster; i++) { |
85c032e4 GS |
875 | item16 = sigma_dram_cluster_data(dram_cluster, i); |
876 | if (devc->cur_samplerate == SR_MHZ(200)) { | |
877 | sample = sigma_deinterlace_200mhz_data(item16, 0); | |
878 | store_sr_sample(samples, send_count++, sample); | |
879 | sample = sigma_deinterlace_200mhz_data(item16, 1); | |
880 | store_sr_sample(samples, send_count++, sample); | |
881 | sample = sigma_deinterlace_200mhz_data(item16, 2); | |
882 | store_sr_sample(samples, send_count++, sample); | |
883 | sample = sigma_deinterlace_200mhz_data(item16, 3); | |
884 | store_sr_sample(samples, send_count++, sample); | |
885 | } else if (devc->cur_samplerate == SR_MHZ(100)) { | |
886 | sample = sigma_deinterlace_100mhz_data(item16, 0); | |
887 | store_sr_sample(samples, send_count++, sample); | |
888 | sample = sigma_deinterlace_100mhz_data(item16, 1); | |
889 | store_sr_sample(samples, send_count++, sample); | |
890 | } else { | |
891 | sample = item16; | |
892 | store_sr_sample(samples, send_count++, sample); | |
893 | } | |
23239b5c MV |
894 | } |
895 | ||
de3f7acb GS |
896 | /* |
897 | * If a trigger position applies, then provide the datafeed with | |
898 | * the first part of data up to that position, then send the | |
899 | * trigger marker. | |
900 | */ | |
23239b5c | 901 | int trigger_offset = 0; |
1e23158b | 902 | if (triggered) { |
23239b5c MV |
903 | /* |
904 | * Trigger is not always accurate to sample because of | |
905 | * pipeline delay. However, it always triggers before | |
906 | * the actual event. We therefore look at the next | |
907 | * samples to pinpoint the exact position of the trigger. | |
908 | */ | |
909 | trigger_offset = get_trigger_offset(samples, | |
910 | ss->lastsample, &devc->trigger); | |
911 | ||
912 | if (trigger_offset > 0) { | |
85c032e4 | 913 | trig_count = trigger_offset * devc->samples_per_event; |
23239b5c | 914 | packet.type = SR_DF_LOGIC; |
85c032e4 | 915 | logic.length = trig_count * logic.unitsize; |
735ed8a1 | 916 | sigma_session_send(sdi, &packet); |
85c032e4 GS |
917 | send_ptr += trig_count * logic.unitsize; |
918 | send_count -= trig_count; | |
23239b5c MV |
919 | } |
920 | ||
921 | /* Only send trigger if explicitly enabled. */ | |
922 | if (devc->use_triggers) { | |
923 | packet.type = SR_DF_TRIGGER; | |
102f1239 | 924 | sr_session_send(sdi, &packet); |
23239b5c MV |
925 | } |
926 | } | |
927 | ||
de3f7acb GS |
928 | /* |
929 | * Send the data after the trigger, or all of the received data | |
930 | * if no trigger position applies. | |
931 | */ | |
85c032e4 | 932 | if (send_count) { |
23239b5c | 933 | packet.type = SR_DF_LOGIC; |
85c032e4 GS |
934 | logic.length = send_count * logic.unitsize; |
935 | logic.data = send_ptr; | |
735ed8a1 | 936 | sigma_session_send(sdi, &packet); |
23239b5c MV |
937 | } |
938 | ||
0498f743 | 939 | ss->lastsample = sample; |
23239b5c MV |
940 | } |
941 | ||
28a35d8a | 942 | /* |
fefa1800 UH |
943 | * Decode chunk of 1024 bytes, 64 clusters, 7 events per cluster. |
944 | * Each event is 20ns apart, and can contain multiple samples. | |
f78898e9 HE |
945 | * |
946 | * For 200 MHz, events contain 4 samples for each channel, spread 5 ns apart. | |
947 | * For 100 MHz, events contain 2 samples for each channel, spread 10 ns apart. | |
948 | * For 50 MHz and below, events contain one sample for each channel, | |
949 | * spread 20 ns apart. | |
28a35d8a | 950 | */ |
1e23158b MV |
951 | static int decode_chunk_ts(struct sigma_dram_line *dram_line, |
952 | uint16_t events_in_line, | |
953 | uint32_t trigger_event, | |
102f1239 | 954 | struct sr_dev_inst *sdi) |
28a35d8a | 955 | { |
3628074d | 956 | struct sigma_dram_cluster *dram_cluster; |
f06fb3e9 GS |
957 | struct dev_context *devc; |
958 | unsigned int clusters_in_line; | |
5fc01191 | 959 | unsigned int events_in_cluster; |
23239b5c | 960 | unsigned int i; |
f06fb3e9 GS |
961 | uint32_t trigger_cluster, triggered; |
962 | ||
963 | devc = sdi->priv; | |
964 | clusters_in_line = events_in_line; | |
965 | clusters_in_line += EVENTS_PER_CLUSTER - 1; | |
966 | clusters_in_line /= EVENTS_PER_CLUSTER; | |
967 | trigger_cluster = ~0; | |
968 | triggered = 0; | |
ee492173 | 969 | |
4ae1f451 | 970 | /* Check if trigger is in this chunk. */ |
1e23158b MV |
971 | if (trigger_event < (64 * 7)) { |
972 | if (devc->cur_samplerate <= SR_MHZ(50)) { | |
973 | trigger_event -= MIN(EVENTS_PER_CLUSTER - 1, | |
974 | trigger_event); | |
975 | } | |
57bbf56b | 976 | |
f3f19d11 | 977 | /* Find in which cluster the trigger occurred. */ |
1e23158b | 978 | trigger_cluster = trigger_event / EVENTS_PER_CLUSTER; |
ee492173 | 979 | } |
28a35d8a | 980 | |
5fc01191 MV |
981 | /* For each full DRAM cluster. */ |
982 | for (i = 0; i < clusters_in_line; i++) { | |
3628074d | 983 | dram_cluster = &dram_line->cluster[i]; |
5fc01191 | 984 | |
5fc01191 | 985 | /* The last cluster might not be full. */ |
23239b5c MV |
986 | if ((i == clusters_in_line - 1) && |
987 | (events_in_line % EVENTS_PER_CLUSTER)) { | |
5fc01191 | 988 | events_in_cluster = events_in_line % EVENTS_PER_CLUSTER; |
23239b5c | 989 | } else { |
5fc01191 | 990 | events_in_cluster = EVENTS_PER_CLUSTER; |
abda62ce | 991 | } |
ee492173 | 992 | |
1e23158b MV |
993 | triggered = (i == trigger_cluster); |
994 | sigma_decode_dram_cluster(dram_cluster, events_in_cluster, | |
995 | triggered, sdi); | |
28a35d8a HE |
996 | } |
997 | ||
e46b8fb1 | 998 | return SR_OK; |
28a35d8a HE |
999 | } |
1000 | ||
6057d9fa | 1001 | static int download_capture(struct sr_dev_inst *sdi) |
28a35d8a | 1002 | { |
e15e5873 | 1003 | const uint32_t chunks_per_read = 32; |
f06fb3e9 GS |
1004 | |
1005 | struct dev_context *devc; | |
fd830beb | 1006 | struct sigma_dram_line *dram_line; |
c6648b66 | 1007 | int bufsz; |
462fe786 | 1008 | uint32_t stoppos, triggerpos; |
6057d9fa | 1009 | uint8_t modestatus; |
c6648b66 MV |
1010 | uint32_t i; |
1011 | uint32_t dl_lines_total, dl_lines_curr, dl_lines_done; | |
74d453ab | 1012 | uint32_t dl_first_line, dl_line; |
f06fb3e9 GS |
1013 | uint32_t dl_events_in_line; |
1014 | uint32_t trg_line, trg_event; | |
1015 | ||
1016 | devc = sdi->priv; | |
1017 | dl_events_in_line = 64 * 7; | |
c6648b66 | 1018 | |
fd830beb MV |
1019 | dram_line = g_try_malloc0(chunks_per_read * sizeof(*dram_line)); |
1020 | if (!dram_line) | |
1021 | return FALSE; | |
1022 | ||
6868626b | 1023 | sr_info("Downloading sample data."); |
dde0175d | 1024 | devc->state.state = SIGMA_DOWNLOAD; |
6868626b | 1025 | |
22f64ed8 GS |
1026 | /* |
1027 | * Ask the hardware to stop data acquisition. Reception of the | |
1028 | * FORCESTOP request makes the hardware "disable RLE" (store | |
1029 | * clusters to DRAM regardless of whether pin state changes) and | |
1030 | * raise the POSTTRIGGERED flag. | |
1031 | */ | |
1032 | sigma_set_register(WRITE_MODE, WMR_FORCESTOP | WMR_SDRAMWRITEEN, devc); | |
1033 | do { | |
1034 | modestatus = sigma_get_register(READ_MODE, devc); | |
1035 | } while (!(modestatus & RMR_POSTTRIGGERED)); | |
6057d9fa MV |
1036 | |
1037 | /* Set SDRAM Read Enable. */ | |
22f64ed8 | 1038 | sigma_set_register(WRITE_MODE, WMR_SDRAMREADEN, devc); |
6057d9fa MV |
1039 | |
1040 | /* Get the current position. */ | |
462fe786 | 1041 | sigma_read_pos(&stoppos, &triggerpos, devc); |
6057d9fa MV |
1042 | |
1043 | /* Check if trigger has fired. */ | |
1044 | modestatus = sigma_get_register(READ_MODE, devc); | |
dc400817 GS |
1045 | trg_line = ~0; |
1046 | trg_event = ~0; | |
22f64ed8 | 1047 | if (modestatus & RMR_TRIGGERED) { |
c6648b66 | 1048 | trg_line = triggerpos >> 9; |
1e23158b MV |
1049 | trg_event = triggerpos & 0x1ff; |
1050 | } | |
6057d9fa | 1051 | |
735ed8a1 GS |
1052 | devc->sent_samples = 0; |
1053 | ||
c6648b66 | 1054 | /* |
74d453ab GS |
1055 | * Determine how many "DRAM lines" of 1024 bytes each we need to |
1056 | * retrieve from the Sigma hardware, so that we have a complete | |
1057 | * set of samples. Note that the last line need not contain 64 | |
1058 | * clusters, it might be partially filled only. | |
1059 | * | |
1060 | * When RMR_ROUND is set, the circular buffer in DRAM has wrapped | |
1061 | * around. Since the status of the very next line is uncertain in | |
1062 | * that case, we skip it and start reading from the next line. The | |
1063 | * circular buffer has 32K lines (0x8000). | |
c6648b66 MV |
1064 | */ |
1065 | dl_lines_total = (stoppos >> 9) + 1; | |
74d453ab GS |
1066 | if (modestatus & RMR_ROUND) { |
1067 | dl_first_line = dl_lines_total + 1; | |
1068 | dl_lines_total = 0x8000 - 2; | |
1069 | } else { | |
1070 | dl_first_line = 0; | |
1071 | } | |
c6648b66 | 1072 | dl_lines_done = 0; |
c6648b66 MV |
1073 | while (dl_lines_total > dl_lines_done) { |
1074 | /* We can download only up-to 32 DRAM lines in one go! */ | |
547c4cdc | 1075 | dl_lines_curr = MIN(chunks_per_read, dl_lines_total - dl_lines_done); |
6868626b | 1076 | |
74d453ab GS |
1077 | dl_line = dl_first_line + dl_lines_done; |
1078 | dl_line %= 0x8000; | |
1079 | bufsz = sigma_read_dram(dl_line, dl_lines_curr, | |
f41a4cae | 1080 | (uint8_t *)dram_line, devc); |
c6648b66 MV |
1081 | /* TODO: Check bufsz. For now, just avoid compiler warnings. */ |
1082 | (void)bufsz; | |
6868626b | 1083 | |
c6648b66 MV |
1084 | /* This is the first DRAM line, so find the initial timestamp. */ |
1085 | if (dl_lines_done == 0) { | |
3513d965 MV |
1086 | devc->state.lastts = |
1087 | sigma_dram_cluster_ts(&dram_line[0].cluster[0]); | |
c6648b66 | 1088 | devc->state.lastsample = 0; |
6868626b BV |
1089 | } |
1090 | ||
c6648b66 | 1091 | for (i = 0; i < dl_lines_curr; i++) { |
1e23158b | 1092 | uint32_t trigger_event = ~0; |
c6648b66 MV |
1093 | /* The last "DRAM line" can be only partially full. */ |
1094 | if (dl_lines_done + i == dl_lines_total - 1) | |
46641fac | 1095 | dl_events_in_line = stoppos & 0x1ff; |
c6648b66 | 1096 | |
e69ad48e | 1097 | /* Test if the trigger happened on this line. */ |
c6648b66 | 1098 | if (dl_lines_done + i == trg_line) |
1e23158b | 1099 | trigger_event = trg_event; |
e69ad48e | 1100 | |
1e23158b MV |
1101 | decode_chunk_ts(dram_line + i, dl_events_in_line, |
1102 | trigger_event, sdi); | |
c6648b66 | 1103 | } |
6868626b | 1104 | |
c6648b66 | 1105 | dl_lines_done += dl_lines_curr; |
6868626b | 1106 | } |
dde0175d | 1107 | g_free(dram_line); |
6868626b | 1108 | |
bee2b016 | 1109 | std_session_send_df_end(sdi); |
6057d9fa | 1110 | |
dde0175d | 1111 | devc->state.state = SIGMA_IDLE; |
d2f7c417 | 1112 | sr_dev_acquisition_stop(sdi); |
6057d9fa MV |
1113 | |
1114 | return TRUE; | |
6868626b BV |
1115 | } |
1116 | ||
d4051930 | 1117 | /* |
74d453ab GS |
1118 | * Periodically check the Sigma status when in CAPTURE mode. This routine |
1119 | * checks whether the configured sample count or sample time have passed, | |
1120 | * and will stop acquisition and download the acquired samples. | |
d4051930 MV |
1121 | */ |
1122 | static int sigma_capture_mode(struct sr_dev_inst *sdi) | |
6868626b | 1123 | { |
f06fb3e9 | 1124 | struct dev_context *devc; |
94ba4bd6 | 1125 | uint64_t running_msec; |
2f425a56 | 1126 | uint64_t current_time; |
28a35d8a | 1127 | |
f06fb3e9 GS |
1128 | devc = sdi->priv; |
1129 | ||
74d453ab GS |
1130 | /* |
1131 | * Check if the selected sampling duration passed. Sample count | |
1132 | * limits are covered by this enforced timeout as well. | |
1133 | */ | |
2f425a56 GS |
1134 | current_time = g_get_monotonic_time(); |
1135 | running_msec = (current_time - devc->start_time) / 1000; | |
00c86508 | 1136 | if (running_msec >= devc->limit_msec) |
6057d9fa | 1137 | return download_capture(sdi); |
00c86508 | 1138 | |
d4051930 MV |
1139 | return TRUE; |
1140 | } | |
28a35d8a | 1141 | |
3ba56876 | 1142 | SR_PRIV int sigma_receive_data(int fd, int revents, void *cb_data) |
d4051930 MV |
1143 | { |
1144 | struct sr_dev_inst *sdi; | |
1145 | struct dev_context *devc; | |
88c51afe | 1146 | |
d4051930 MV |
1147 | (void)fd; |
1148 | (void)revents; | |
88c51afe | 1149 | |
d4051930 MV |
1150 | sdi = cb_data; |
1151 | devc = sdi->priv; | |
1152 | ||
1153 | if (devc->state.state == SIGMA_IDLE) | |
1154 | return TRUE; | |
1155 | ||
dde0175d GS |
1156 | /* |
1157 | * When the application has requested to stop the acquisition, | |
1158 | * then immediately start downloading sample data. Otherwise | |
1159 | * keep checking configured limits which will terminate the | |
1160 | * acquisition and initiate download. | |
1161 | */ | |
1162 | if (devc->state.state == SIGMA_STOPPING) | |
1163 | return download_capture(sdi); | |
d4051930 MV |
1164 | if (devc->state.state == SIGMA_CAPTURE) |
1165 | return sigma_capture_mode(sdi); | |
28a35d8a | 1166 | |
28a35d8a HE |
1167 | return TRUE; |
1168 | } | |
1169 | ||
c53d793f HE |
1170 | /* Build a LUT entry used by the trigger functions. */ |
1171 | static void build_lut_entry(uint16_t value, uint16_t mask, uint16_t *entry) | |
ee492173 HE |
1172 | { |
1173 | int i, j, k, bit; | |
1174 | ||
ba7dd8bb | 1175 | /* For each quad channel. */ |
0a1f7b09 | 1176 | for (i = 0; i < 4; i++) { |
c53d793f | 1177 | entry[i] = 0xffff; |
ee492173 | 1178 | |
f758d074 | 1179 | /* For each bit in LUT. */ |
0a1f7b09 | 1180 | for (j = 0; j < 16; j++) |
ee492173 | 1181 | |
ba7dd8bb | 1182 | /* For each channel in quad. */ |
0a1f7b09 | 1183 | for (k = 0; k < 4; k++) { |
ee492173 HE |
1184 | bit = 1 << (i * 4 + k); |
1185 | ||
c53d793f | 1186 | /* Set bit in entry */ |
0a1f7b09 UH |
1187 | if ((mask & bit) && ((!(value & bit)) != |
1188 | (!(j & (1 << k))))) | |
c53d793f | 1189 | entry[i] &= ~(1 << j); |
ee492173 HE |
1190 | } |
1191 | } | |
c53d793f | 1192 | } |
ee492173 | 1193 | |
c53d793f HE |
1194 | /* Add a logical function to LUT mask. */ |
1195 | static void add_trigger_function(enum triggerop oper, enum triggerfunc func, | |
1196 | int index, int neg, uint16_t *mask) | |
1197 | { | |
1198 | int i, j; | |
1199 | int x[2][2], tmp, a, b, aset, bset, rset; | |
1200 | ||
1201 | memset(x, 0, 4 * sizeof(int)); | |
1202 | ||
1203 | /* Trigger detect condition. */ | |
1204 | switch (oper) { | |
1205 | case OP_LEVEL: | |
1206 | x[0][1] = 1; | |
1207 | x[1][1] = 1; | |
1208 | break; | |
1209 | case OP_NOT: | |
1210 | x[0][0] = 1; | |
1211 | x[1][0] = 1; | |
1212 | break; | |
1213 | case OP_RISE: | |
1214 | x[0][1] = 1; | |
1215 | break; | |
1216 | case OP_FALL: | |
1217 | x[1][0] = 1; | |
1218 | break; | |
1219 | case OP_RISEFALL: | |
1220 | x[0][1] = 1; | |
1221 | x[1][0] = 1; | |
1222 | break; | |
1223 | case OP_NOTRISE: | |
1224 | x[1][1] = 1; | |
1225 | x[0][0] = 1; | |
1226 | x[1][0] = 1; | |
1227 | break; | |
1228 | case OP_NOTFALL: | |
1229 | x[1][1] = 1; | |
1230 | x[0][0] = 1; | |
1231 | x[0][1] = 1; | |
1232 | break; | |
1233 | case OP_NOTRISEFALL: | |
1234 | x[1][1] = 1; | |
1235 | x[0][0] = 1; | |
1236 | break; | |
1237 | } | |
1238 | ||
1239 | /* Transpose if neg is set. */ | |
1240 | if (neg) { | |
0a1f7b09 UH |
1241 | for (i = 0; i < 2; i++) { |
1242 | for (j = 0; j < 2; j++) { | |
c53d793f | 1243 | tmp = x[i][j]; |
0a1f7b09 UH |
1244 | x[i][j] = x[1 - i][1 - j]; |
1245 | x[1 - i][1 - j] = tmp; | |
c53d793f | 1246 | } |
ea9cfed7 | 1247 | } |
c53d793f HE |
1248 | } |
1249 | ||
1250 | /* Update mask with function. */ | |
0a1f7b09 | 1251 | for (i = 0; i < 16; i++) { |
c53d793f HE |
1252 | a = (i >> (2 * index + 0)) & 1; |
1253 | b = (i >> (2 * index + 1)) & 1; | |
1254 | ||
1255 | aset = (*mask >> i) & 1; | |
1256 | bset = x[b][a]; | |
1257 | ||
382cb19f | 1258 | rset = 0; |
c53d793f HE |
1259 | if (func == FUNC_AND || func == FUNC_NAND) |
1260 | rset = aset & bset; | |
1261 | else if (func == FUNC_OR || func == FUNC_NOR) | |
1262 | rset = aset | bset; | |
1263 | else if (func == FUNC_XOR || func == FUNC_NXOR) | |
1264 | rset = aset ^ bset; | |
1265 | ||
1266 | if (func == FUNC_NAND || func == FUNC_NOR || func == FUNC_NXOR) | |
1267 | rset = !rset; | |
1268 | ||
1269 | *mask &= ~(1 << i); | |
1270 | ||
1271 | if (rset) | |
1272 | *mask |= 1 << i; | |
1273 | } | |
1274 | } | |
1275 | ||
1276 | /* | |
1277 | * Build trigger LUTs used by 50 MHz and lower sample rates for supporting | |
1278 | * simple pin change and state triggers. Only two transitions (rise/fall) can be | |
1279 | * set at any time, but a full mask and value can be set (0/1). | |
1280 | */ | |
3ba56876 | 1281 | SR_PRIV int sigma_build_basic_trigger(struct triggerlut *lut, struct dev_context *devc) |
c53d793f HE |
1282 | { |
1283 | int i,j; | |
4ae1f451 | 1284 | uint16_t masks[2] = { 0, 0 }; |
c53d793f HE |
1285 | |
1286 | memset(lut, 0, sizeof(struct triggerlut)); | |
1287 | ||
f3f19d11 | 1288 | /* Constant for simple triggers. */ |
c53d793f HE |
1289 | lut->m4 = 0xa000; |
1290 | ||
1291 | /* Value/mask trigger support. */ | |
0e1357e8 | 1292 | build_lut_entry(devc->trigger.simplevalue, devc->trigger.simplemask, |
99965709 | 1293 | lut->m2d); |
c53d793f HE |
1294 | |
1295 | /* Rise/fall trigger support. */ | |
0a1f7b09 | 1296 | for (i = 0, j = 0; i < 16; i++) { |
0e1357e8 BV |
1297 | if (devc->trigger.risingmask & (1 << i) || |
1298 | devc->trigger.fallingmask & (1 << i)) | |
c53d793f HE |
1299 | masks[j++] = 1 << i; |
1300 | } | |
1301 | ||
1302 | build_lut_entry(masks[0], masks[0], lut->m0d); | |
1303 | build_lut_entry(masks[1], masks[1], lut->m1d); | |
1304 | ||
1305 | /* Add glue logic */ | |
1306 | if (masks[0] || masks[1]) { | |
1307 | /* Transition trigger. */ | |
0e1357e8 | 1308 | if (masks[0] & devc->trigger.risingmask) |
c53d793f | 1309 | add_trigger_function(OP_RISE, FUNC_OR, 0, 0, &lut->m3); |
0e1357e8 | 1310 | if (masks[0] & devc->trigger.fallingmask) |
c53d793f | 1311 | add_trigger_function(OP_FALL, FUNC_OR, 0, 0, &lut->m3); |
0e1357e8 | 1312 | if (masks[1] & devc->trigger.risingmask) |
c53d793f | 1313 | add_trigger_function(OP_RISE, FUNC_OR, 1, 0, &lut->m3); |
0e1357e8 | 1314 | if (masks[1] & devc->trigger.fallingmask) |
c53d793f HE |
1315 | add_trigger_function(OP_FALL, FUNC_OR, 1, 0, &lut->m3); |
1316 | } else { | |
1317 | /* Only value/mask trigger. */ | |
1318 | lut->m3 = 0xffff; | |
1319 | } | |
ee492173 | 1320 | |
c53d793f | 1321 | /* Triggertype: event. */ |
ee492173 HE |
1322 | lut->params.selres = 3; |
1323 | ||
e46b8fb1 | 1324 | return SR_OK; |
ee492173 | 1325 | } |