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Commit | Line | Data |
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28a35d8a | 1 | /* |
50985c20 | 2 | * This file is part of the libsigrok project. |
28a35d8a | 3 | * |
868501fa | 4 | * Copyright (C) 2010-2012 Håvard Espeland <gus@ping.uio.no>, |
911f1834 UH |
5 | * Copyright (C) 2010 Martin Stensgård <mastensg@ping.uio.no> |
6 | * Copyright (C) 2010 Carl Henrik Lunde <chlunde@ping.uio.no> | |
28a35d8a HE |
7 | * |
8 | * This program is free software: you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation, either version 3 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
20 | */ | |
21 | ||
911f1834 | 22 | /* |
6352d030 | 23 | * ASIX SIGMA/SIGMA2 logic analyzer driver |
911f1834 UH |
24 | */ |
25 | ||
6ec6c43b | 26 | #include <config.h> |
3ba56876 | 27 | #include "protocol.h" |
28a35d8a HE |
28 | |
29 | #define USB_VENDOR 0xa600 | |
30 | #define USB_PRODUCT 0xa000 | |
31 | #define USB_DESCRIPTION "ASIX SIGMA" | |
32 | #define USB_VENDOR_NAME "ASIX" | |
33 | #define USB_MODEL_NAME "SIGMA" | |
28a35d8a | 34 | |
b1648dea MV |
35 | /* |
36 | * The ASIX Sigma supports arbitrary integer frequency divider in | |
37 | * the 50MHz mode. The divider is in range 1...256 , allowing for | |
38 | * very precise sampling rate selection. This driver supports only | |
39 | * a subset of the sampling rates. | |
40 | */ | |
3ba56876 | 41 | SR_PRIV const uint64_t samplerates[] = { |
b1648dea MV |
42 | SR_KHZ(200), /* div=250 */ |
43 | SR_KHZ(250), /* div=200 */ | |
44 | SR_KHZ(500), /* div=100 */ | |
45 | SR_MHZ(1), /* div=50 */ | |
46 | SR_MHZ(5), /* div=10 */ | |
47 | SR_MHZ(10), /* div=5 */ | |
48 | SR_MHZ(25), /* div=2 */ | |
49 | SR_MHZ(50), /* div=1 */ | |
50 | SR_MHZ(100), /* Special FW needed */ | |
51 | SR_MHZ(200), /* Special FW needed */ | |
28a35d8a HE |
52 | }; |
53 | ||
3ba56876 | 54 | SR_PRIV const int SAMPLERATES_COUNT = ARRAY_SIZE(samplerates); |
39c64c6a | 55 | |
8e2d6c9d | 56 | static const char sigma_firmware_files[][24] = { |
499b17e9 | 57 | /* 50 MHz, supports 8 bit fractions */ |
8e2d6c9d | 58 | "asix-sigma-50.fw", |
499b17e9 | 59 | /* 100 MHz */ |
8e2d6c9d | 60 | "asix-sigma-100.fw", |
499b17e9 | 61 | /* 200 MHz */ |
8e2d6c9d | 62 | "asix-sigma-200.fw", |
499b17e9 | 63 | /* Synchronous clock from pin */ |
8e2d6c9d | 64 | "asix-sigma-50sync.fw", |
499b17e9 | 65 | /* Frequency counter */ |
8e2d6c9d | 66 | "asix-sigma-phasor.fw", |
f6564c8d HE |
67 | }; |
68 | ||
0e1357e8 | 69 | static int sigma_read(void *buf, size_t size, struct dev_context *devc) |
28a35d8a HE |
70 | { |
71 | int ret; | |
fefa1800 | 72 | |
0e1357e8 | 73 | ret = ftdi_read_data(&devc->ftdic, (unsigned char *)buf, size); |
28a35d8a | 74 | if (ret < 0) { |
47f4f073 | 75 | sr_err("ftdi_read_data failed: %s", |
0e1357e8 | 76 | ftdi_get_error_string(&devc->ftdic)); |
28a35d8a HE |
77 | } |
78 | ||
79 | return ret; | |
80 | } | |
81 | ||
0e1357e8 | 82 | static int sigma_write(void *buf, size_t size, struct dev_context *devc) |
28a35d8a HE |
83 | { |
84 | int ret; | |
fefa1800 | 85 | |
0e1357e8 | 86 | ret = ftdi_write_data(&devc->ftdic, (unsigned char *)buf, size); |
28a35d8a | 87 | if (ret < 0) { |
47f4f073 | 88 | sr_err("ftdi_write_data failed: %s", |
0e1357e8 | 89 | ftdi_get_error_string(&devc->ftdic)); |
fefa1800 | 90 | } else if ((size_t) ret != size) { |
47f4f073 | 91 | sr_err("ftdi_write_data did not complete write."); |
28a35d8a HE |
92 | } |
93 | ||
94 | return ret; | |
95 | } | |
96 | ||
e8686e3a AG |
97 | /* |
98 | * NOTE: We chose the buffer size to be large enough to hold any write to the | |
99 | * device. We still print a message just in case. | |
100 | */ | |
3ba56876 | 101 | SR_PRIV int sigma_write_register(uint8_t reg, uint8_t *data, size_t len, |
102 | struct dev_context *devc) | |
28a35d8a HE |
103 | { |
104 | size_t i; | |
e8686e3a | 105 | uint8_t buf[80]; |
28a35d8a HE |
106 | int idx = 0; |
107 | ||
e8686e3a AG |
108 | if ((len + 2) > sizeof(buf)) { |
109 | sr_err("Attempted to write %zu bytes, but buffer is too small.", | |
110 | len + 2); | |
111 | return SR_ERR_BUG; | |
112 | } | |
113 | ||
28a35d8a HE |
114 | buf[idx++] = REG_ADDR_LOW | (reg & 0xf); |
115 | buf[idx++] = REG_ADDR_HIGH | (reg >> 4); | |
116 | ||
0a1f7b09 | 117 | for (i = 0; i < len; i++) { |
28a35d8a HE |
118 | buf[idx++] = REG_DATA_LOW | (data[i] & 0xf); |
119 | buf[idx++] = REG_DATA_HIGH_WRITE | (data[i] >> 4); | |
120 | } | |
121 | ||
0e1357e8 | 122 | return sigma_write(buf, idx, devc); |
28a35d8a HE |
123 | } |
124 | ||
3ba56876 | 125 | SR_PRIV int sigma_set_register(uint8_t reg, uint8_t value, struct dev_context *devc) |
28a35d8a | 126 | { |
0e1357e8 | 127 | return sigma_write_register(reg, &value, 1, devc); |
28a35d8a HE |
128 | } |
129 | ||
99965709 | 130 | static int sigma_read_register(uint8_t reg, uint8_t *data, size_t len, |
0e1357e8 | 131 | struct dev_context *devc) |
28a35d8a HE |
132 | { |
133 | uint8_t buf[3]; | |
fefa1800 | 134 | |
28a35d8a HE |
135 | buf[0] = REG_ADDR_LOW | (reg & 0xf); |
136 | buf[1] = REG_ADDR_HIGH | (reg >> 4); | |
28a35d8a HE |
137 | buf[2] = REG_READ_ADDR; |
138 | ||
0e1357e8 | 139 | sigma_write(buf, sizeof(buf), devc); |
28a35d8a | 140 | |
0e1357e8 | 141 | return sigma_read(data, len, devc); |
28a35d8a HE |
142 | } |
143 | ||
0e1357e8 | 144 | static uint8_t sigma_get_register(uint8_t reg, struct dev_context *devc) |
28a35d8a HE |
145 | { |
146 | uint8_t value; | |
fefa1800 | 147 | |
0e1357e8 | 148 | if (1 != sigma_read_register(reg, &value, 1, devc)) { |
47f4f073 | 149 | sr_err("sigma_get_register: 1 byte expected"); |
28a35d8a HE |
150 | return 0; |
151 | } | |
152 | ||
153 | return value; | |
154 | } | |
155 | ||
99965709 | 156 | static int sigma_read_pos(uint32_t *stoppos, uint32_t *triggerpos, |
0e1357e8 | 157 | struct dev_context *devc) |
28a35d8a HE |
158 | { |
159 | uint8_t buf[] = { | |
160 | REG_ADDR_LOW | READ_TRIGGER_POS_LOW, | |
161 | ||
162 | REG_READ_ADDR | NEXT_REG, | |
163 | REG_READ_ADDR | NEXT_REG, | |
164 | REG_READ_ADDR | NEXT_REG, | |
165 | REG_READ_ADDR | NEXT_REG, | |
166 | REG_READ_ADDR | NEXT_REG, | |
167 | REG_READ_ADDR | NEXT_REG, | |
168 | }; | |
28a35d8a HE |
169 | uint8_t result[6]; |
170 | ||
0e1357e8 | 171 | sigma_write(buf, sizeof(buf), devc); |
28a35d8a | 172 | |
0e1357e8 | 173 | sigma_read(result, sizeof(result), devc); |
28a35d8a HE |
174 | |
175 | *triggerpos = result[0] | (result[1] << 8) | (result[2] << 16); | |
176 | *stoppos = result[3] | (result[4] << 8) | (result[5] << 16); | |
177 | ||
57bbf56b HE |
178 | /* Not really sure why this must be done, but according to spec. */ |
179 | if ((--*stoppos & 0x1ff) == 0x1ff) | |
382cb19f | 180 | *stoppos -= 64; |
57bbf56b HE |
181 | |
182 | if ((*--triggerpos & 0x1ff) == 0x1ff) | |
382cb19f | 183 | *triggerpos -= 64; |
57bbf56b | 184 | |
28a35d8a HE |
185 | return 1; |
186 | } | |
187 | ||
99965709 | 188 | static int sigma_read_dram(uint16_t startchunk, size_t numchunks, |
0e1357e8 | 189 | uint8_t *data, struct dev_context *devc) |
28a35d8a HE |
190 | { |
191 | size_t i; | |
192 | uint8_t buf[4096]; | |
193 | int idx = 0; | |
194 | ||
fefa1800 | 195 | /* Send the startchunk. Index start with 1. */ |
28a35d8a HE |
196 | buf[0] = startchunk >> 8; |
197 | buf[1] = startchunk & 0xff; | |
0e1357e8 | 198 | sigma_write_register(WRITE_MEMROW, buf, 2, devc); |
28a35d8a | 199 | |
fefa1800 | 200 | /* Read the DRAM. */ |
28a35d8a HE |
201 | buf[idx++] = REG_DRAM_BLOCK; |
202 | buf[idx++] = REG_DRAM_WAIT_ACK; | |
203 | ||
0a1f7b09 | 204 | for (i = 0; i < numchunks; i++) { |
fefa1800 UH |
205 | /* Alternate bit to copy from DRAM to cache. */ |
206 | if (i != (numchunks - 1)) | |
207 | buf[idx++] = REG_DRAM_BLOCK | (((i + 1) % 2) << 4); | |
28a35d8a HE |
208 | |
209 | buf[idx++] = REG_DRAM_BLOCK_DATA | ((i % 2) << 4); | |
210 | ||
fefa1800 | 211 | if (i != (numchunks - 1)) |
28a35d8a HE |
212 | buf[idx++] = REG_DRAM_WAIT_ACK; |
213 | } | |
214 | ||
0e1357e8 | 215 | sigma_write(buf, idx, devc); |
28a35d8a | 216 | |
0e1357e8 | 217 | return sigma_read(data, numchunks * CHUNK_SIZE, devc); |
28a35d8a HE |
218 | } |
219 | ||
4ae1f451 | 220 | /* Upload trigger look-up tables to Sigma. */ |
3ba56876 | 221 | SR_PRIV int sigma_write_trigger_lut(struct triggerlut *lut, struct dev_context *devc) |
ee492173 HE |
222 | { |
223 | int i; | |
224 | uint8_t tmp[2]; | |
225 | uint16_t bit; | |
226 | ||
227 | /* Transpose the table and send to Sigma. */ | |
0a1f7b09 | 228 | for (i = 0; i < 16; i++) { |
ee492173 HE |
229 | bit = 1 << i; |
230 | ||
231 | tmp[0] = tmp[1] = 0; | |
232 | ||
233 | if (lut->m2d[0] & bit) | |
234 | tmp[0] |= 0x01; | |
235 | if (lut->m2d[1] & bit) | |
236 | tmp[0] |= 0x02; | |
237 | if (lut->m2d[2] & bit) | |
238 | tmp[0] |= 0x04; | |
239 | if (lut->m2d[3] & bit) | |
240 | tmp[0] |= 0x08; | |
241 | ||
242 | if (lut->m3 & bit) | |
243 | tmp[0] |= 0x10; | |
244 | if (lut->m3s & bit) | |
245 | tmp[0] |= 0x20; | |
246 | if (lut->m4 & bit) | |
247 | tmp[0] |= 0x40; | |
248 | ||
249 | if (lut->m0d[0] & bit) | |
250 | tmp[1] |= 0x01; | |
251 | if (lut->m0d[1] & bit) | |
252 | tmp[1] |= 0x02; | |
253 | if (lut->m0d[2] & bit) | |
254 | tmp[1] |= 0x04; | |
255 | if (lut->m0d[3] & bit) | |
256 | tmp[1] |= 0x08; | |
257 | ||
258 | if (lut->m1d[0] & bit) | |
259 | tmp[1] |= 0x10; | |
260 | if (lut->m1d[1] & bit) | |
261 | tmp[1] |= 0x20; | |
262 | if (lut->m1d[2] & bit) | |
263 | tmp[1] |= 0x40; | |
264 | if (lut->m1d[3] & bit) | |
265 | tmp[1] |= 0x80; | |
266 | ||
99965709 | 267 | sigma_write_register(WRITE_TRIGGER_SELECT0, tmp, sizeof(tmp), |
0e1357e8 BV |
268 | devc); |
269 | sigma_set_register(WRITE_TRIGGER_SELECT1, 0x30 | i, devc); | |
ee492173 HE |
270 | } |
271 | ||
272 | /* Send the parameters */ | |
273 | sigma_write_register(WRITE_TRIGGER_SELECT0, (uint8_t *) &lut->params, | |
0e1357e8 | 274 | sizeof(lut->params), devc); |
ee492173 | 275 | |
e46b8fb1 | 276 | return SR_OK; |
ee492173 HE |
277 | } |
278 | ||
3ba56876 | 279 | SR_PRIV void sigma_clear_helper(void *priv) |
0448d110 | 280 | { |
0e1357e8 | 281 | struct dev_context *devc; |
ce4d26dd | 282 | |
3678cf73 | 283 | devc = priv; |
0e1357e8 | 284 | |
3678cf73 UH |
285 | ftdi_deinit(&devc->ftdic); |
286 | } | |
0448d110 | 287 | |
d5fa188a MV |
288 | /* |
289 | * Configure the FPGA for bitbang mode. | |
290 | * This sequence is documented in section 2. of the ASIX Sigma programming | |
291 | * manual. This sequence is necessary to configure the FPGA in the Sigma | |
292 | * into Bitbang mode, in which it can be programmed with the firmware. | |
293 | */ | |
294 | static int sigma_fpga_init_bitbang(struct dev_context *devc) | |
295 | { | |
296 | uint8_t suicide[] = { | |
297 | 0x84, 0x84, 0x88, 0x84, 0x88, 0x84, 0x88, 0x84, | |
298 | }; | |
299 | uint8_t init_array[] = { | |
300 | 0x01, 0x03, 0x03, 0x01, 0x01, 0x01, 0x01, 0x01, | |
301 | 0x01, 0x01, | |
302 | }; | |
1a46cc62 | 303 | int i, ret, timeout = (10 * 1000); |
d5fa188a MV |
304 | uint8_t data; |
305 | ||
306 | /* Section 2. part 1), do the FPGA suicide. */ | |
307 | sigma_write(suicide, sizeof(suicide), devc); | |
308 | sigma_write(suicide, sizeof(suicide), devc); | |
309 | sigma_write(suicide, sizeof(suicide), devc); | |
310 | sigma_write(suicide, sizeof(suicide), devc); | |
311 | ||
312 | /* Section 2. part 2), do pulse on D1. */ | |
313 | sigma_write(init_array, sizeof(init_array), devc); | |
314 | ftdi_usb_purge_buffers(&devc->ftdic); | |
315 | ||
316 | /* Wait until the FPGA asserts D6/INIT_B. */ | |
317 | for (i = 0; i < timeout; i++) { | |
318 | ret = sigma_read(&data, 1, devc); | |
319 | if (ret < 0) | |
320 | return ret; | |
321 | /* Test if pin D6 got asserted. */ | |
322 | if (data & (1 << 5)) | |
323 | return 0; | |
324 | /* The D6 was not asserted yet, wait a bit. */ | |
1a46cc62 | 325 | g_usleep(10 * 1000); |
d5fa188a MV |
326 | } |
327 | ||
328 | return SR_ERR_TIMEOUT; | |
329 | } | |
330 | ||
64fe661b MV |
331 | /* |
332 | * Configure the FPGA for logic-analyzer mode. | |
333 | */ | |
334 | static int sigma_fpga_init_la(struct dev_context *devc) | |
335 | { | |
336 | /* Initialize the logic analyzer mode. */ | |
337 | uint8_t logic_mode_start[] = { | |
011f1091 MV |
338 | REG_ADDR_LOW | (READ_ID & 0xf), |
339 | REG_ADDR_HIGH | (READ_ID >> 8), | |
340 | REG_READ_ADDR, /* Read ID register. */ | |
341 | ||
342 | REG_ADDR_LOW | (WRITE_TEST & 0xf), | |
343 | REG_DATA_LOW | 0x5, | |
344 | REG_DATA_HIGH_WRITE | 0x5, | |
345 | REG_READ_ADDR, /* Read scratch register. */ | |
346 | ||
347 | REG_DATA_LOW | 0xa, | |
348 | REG_DATA_HIGH_WRITE | 0xa, | |
349 | REG_READ_ADDR, /* Read scratch register. */ | |
350 | ||
351 | REG_ADDR_LOW | (WRITE_MODE & 0xf), | |
352 | REG_DATA_LOW | 0x0, | |
353 | REG_DATA_HIGH_WRITE | 0x8, | |
64fe661b MV |
354 | }; |
355 | ||
356 | uint8_t result[3]; | |
357 | int ret; | |
358 | ||
359 | /* Initialize the logic analyzer mode. */ | |
360 | sigma_write(logic_mode_start, sizeof(logic_mode_start), devc); | |
361 | ||
011f1091 | 362 | /* Expect a 3 byte reply since we issued three READ requests. */ |
64fe661b MV |
363 | ret = sigma_read(result, 3, devc); |
364 | if (ret != 3) | |
365 | goto err; | |
366 | ||
367 | if (result[0] != 0xa6 || result[1] != 0x55 || result[2] != 0xaa) | |
368 | goto err; | |
369 | ||
370 | return SR_OK; | |
371 | err: | |
372 | sr_err("Configuration failed. Invalid reply received."); | |
373 | return SR_ERR; | |
374 | } | |
375 | ||
a80226bb MV |
376 | /* |
377 | * Read the firmware from a file and transform it into a series of bitbang | |
378 | * pulses used to program the FPGA. Note that the *bb_cmd must be free()'d | |
379 | * by the caller of this function. | |
380 | */ | |
8e2d6c9d | 381 | static int sigma_fw_2_bitbang(struct sr_context *ctx, const char *name, |
a80226bb MV |
382 | uint8_t **bb_cmd, gsize *bb_cmd_size) |
383 | { | |
8e2d6c9d DE |
384 | size_t i, file_size, bb_size; |
385 | char *firmware; | |
a80226bb MV |
386 | uint8_t *bb_stream, *bbs; |
387 | uint32_t imm; | |
388 | int bit, v; | |
389 | int ret = SR_OK; | |
390 | ||
8e2d6c9d DE |
391 | firmware = sr_resource_load(ctx, SR_RESOURCE_FIRMWARE, |
392 | name, &file_size, 256 * 1024); | |
393 | if (!firmware) | |
394 | return SR_ERR; | |
a80226bb MV |
395 | |
396 | /* Weird magic transformation below, I have no idea what it does. */ | |
397 | imm = 0x3f6df2ab; | |
398 | for (i = 0; i < file_size; i++) { | |
399 | imm = (imm + 0xa853753) % 177 + (imm * 0x8034052); | |
400 | firmware[i] ^= imm & 0xff; | |
401 | } | |
402 | ||
403 | /* | |
404 | * Now that the firmware is "transformed", we will transcribe the | |
405 | * firmware blob into a sequence of toggles of the Dx wires. This | |
406 | * sequence will be fed directly into the Sigma, which must be in | |
407 | * the FPGA bitbang programming mode. | |
408 | */ | |
409 | ||
410 | /* Each bit of firmware is transcribed as two toggles of Dx wires. */ | |
411 | bb_size = file_size * 8 * 2; | |
412 | bb_stream = (uint8_t *)g_try_malloc(bb_size); | |
413 | if (!bb_stream) { | |
414 | sr_err("%s: Failed to allocate bitbang stream", __func__); | |
415 | ret = SR_ERR_MALLOC; | |
416 | goto exit; | |
417 | } | |
418 | ||
419 | bbs = bb_stream; | |
420 | for (i = 0; i < file_size; i++) { | |
421 | for (bit = 7; bit >= 0; bit--) { | |
422 | v = (firmware[i] & (1 << bit)) ? 0x40 : 0x00; | |
423 | *bbs++ = v | 0x01; | |
424 | *bbs++ = v; | |
425 | } | |
426 | } | |
427 | ||
428 | /* The transformation completed successfully, return the result. */ | |
429 | *bb_cmd = bb_stream; | |
430 | *bb_cmd_size = bb_size; | |
431 | ||
432 | exit: | |
8e2d6c9d | 433 | g_free(firmware); |
a80226bb MV |
434 | return ret; |
435 | } | |
436 | ||
8e2d6c9d DE |
437 | static int upload_firmware(struct sr_context *ctx, |
438 | int firmware_idx, struct dev_context *devc) | |
28a35d8a HE |
439 | { |
440 | int ret; | |
441 | unsigned char *buf; | |
442 | unsigned char pins; | |
443 | size_t buf_size; | |
499b17e9 | 444 | const char *firmware = sigma_firmware_files[firmware_idx]; |
8bbf7627 | 445 | struct ftdi_context *ftdic = &devc->ftdic; |
28a35d8a | 446 | |
fefa1800 | 447 | /* Make sure it's an ASIX SIGMA. */ |
8bbf7627 MV |
448 | ret = ftdi_usb_open_desc(ftdic, USB_VENDOR, USB_PRODUCT, |
449 | USB_DESCRIPTION, NULL); | |
450 | if (ret < 0) { | |
47f4f073 | 451 | sr_err("ftdi_usb_open failed: %s", |
8bbf7627 | 452 | ftdi_get_error_string(ftdic)); |
28a35d8a HE |
453 | return 0; |
454 | } | |
455 | ||
8bbf7627 MV |
456 | ret = ftdi_set_bitmode(ftdic, 0xdf, BITMODE_BITBANG); |
457 | if (ret < 0) { | |
47f4f073 | 458 | sr_err("ftdi_set_bitmode failed: %s", |
8bbf7627 | 459 | ftdi_get_error_string(ftdic)); |
28a35d8a HE |
460 | return 0; |
461 | } | |
462 | ||
fefa1800 | 463 | /* Four times the speed of sigmalogan - Works well. */ |
1a46cc62 | 464 | ret = ftdi_set_baudrate(ftdic, 750 * 1000); |
8bbf7627 | 465 | if (ret < 0) { |
47f4f073 | 466 | sr_err("ftdi_set_baudrate failed: %s", |
8bbf7627 | 467 | ftdi_get_error_string(ftdic)); |
28a35d8a HE |
468 | return 0; |
469 | } | |
470 | ||
d5fa188a MV |
471 | /* Initialize the FPGA for firmware upload. */ |
472 | ret = sigma_fpga_init_bitbang(devc); | |
473 | if (ret) | |
474 | return ret; | |
28a35d8a | 475 | |
9ddb2a12 | 476 | /* Prepare firmware. */ |
8e2d6c9d | 477 | ret = sigma_fw_2_bitbang(ctx, firmware, &buf, &buf_size); |
8bbf7627 | 478 | if (ret != SR_OK) { |
f3f19d11 | 479 | sr_err("An error occurred while reading the firmware: %s", |
499b17e9 | 480 | firmware); |
b53738ba | 481 | return ret; |
28a35d8a HE |
482 | } |
483 | ||
f3f19d11 | 484 | /* Upload firmware. */ |
499b17e9 | 485 | sr_info("Uploading firmware file '%s'.", firmware); |
0e1357e8 | 486 | sigma_write(buf, buf_size, devc); |
28a35d8a HE |
487 | |
488 | g_free(buf); | |
489 | ||
8bbf7627 MV |
490 | ret = ftdi_set_bitmode(ftdic, 0x00, BITMODE_RESET); |
491 | if (ret < 0) { | |
47f4f073 | 492 | sr_err("ftdi_set_bitmode failed: %s", |
8bbf7627 | 493 | ftdi_get_error_string(ftdic)); |
e46b8fb1 | 494 | return SR_ERR; |
28a35d8a HE |
495 | } |
496 | ||
8bbf7627 | 497 | ftdi_usb_purge_buffers(ftdic); |
28a35d8a | 498 | |
fefa1800 | 499 | /* Discard garbage. */ |
29b66a2e | 500 | while (sigma_read(&pins, 1, devc) == 1) |
28a35d8a HE |
501 | ; |
502 | ||
64fe661b MV |
503 | /* Initialize the FPGA for logic-analyzer mode. */ |
504 | ret = sigma_fpga_init_la(devc); | |
505 | if (ret != SR_OK) | |
506 | return ret; | |
28a35d8a | 507 | |
0e1357e8 | 508 | devc->cur_firmware = firmware_idx; |
f6564c8d | 509 | |
47f4f073 | 510 | sr_info("Firmware uploaded."); |
e3fff420 | 511 | |
e46b8fb1 | 512 | return SR_OK; |
f6564c8d HE |
513 | } |
514 | ||
3ba56876 | 515 | SR_PRIV int sigma_set_samplerate(const struct sr_dev_inst *sdi, uint64_t samplerate) |
f6564c8d | 516 | { |
2c9c0df8 | 517 | struct dev_context *devc; |
8e2d6c9d | 518 | struct drv_context *drvc; |
2c9c0df8 BV |
519 | unsigned int i; |
520 | int ret; | |
f6564c8d | 521 | |
2c9c0df8 | 522 | devc = sdi->priv; |
8e2d6c9d | 523 | drvc = sdi->driver->context; |
f4abaa9f UH |
524 | ret = SR_OK; |
525 | ||
2c9c0df8 BV |
526 | for (i = 0; i < ARRAY_SIZE(samplerates); i++) { |
527 | if (samplerates[i] == samplerate) | |
f6564c8d HE |
528 | break; |
529 | } | |
2c9c0df8 | 530 | if (samplerates[i] == 0) |
e46b8fb1 | 531 | return SR_ERR_SAMPLERATE; |
f6564c8d | 532 | |
59df0c77 | 533 | if (samplerate <= SR_MHZ(50)) { |
8e2d6c9d | 534 | ret = upload_firmware(drvc->sr_ctx, 0, devc); |
ba7dd8bb | 535 | devc->num_channels = 16; |
6b2d3385 | 536 | } else if (samplerate == SR_MHZ(100)) { |
8e2d6c9d | 537 | ret = upload_firmware(drvc->sr_ctx, 1, devc); |
ba7dd8bb | 538 | devc->num_channels = 8; |
6b2d3385 | 539 | } else if (samplerate == SR_MHZ(200)) { |
8e2d6c9d | 540 | ret = upload_firmware(drvc->sr_ctx, 2, devc); |
ba7dd8bb | 541 | devc->num_channels = 4; |
f78898e9 | 542 | } |
f6564c8d | 543 | |
6b2d3385 BV |
544 | if (ret == SR_OK) { |
545 | devc->cur_samplerate = samplerate; | |
546 | devc->period_ps = 1000000000000ULL / samplerate; | |
547 | devc->samples_per_event = 16 / devc->num_channels; | |
548 | devc->state.state = SIGMA_IDLE; | |
549 | } | |
f6564c8d | 550 | |
e8397563 | 551 | return ret; |
28a35d8a HE |
552 | } |
553 | ||
c53d793f HE |
554 | /* |
555 | * In 100 and 200 MHz mode, only a single pin rising/falling can be | |
556 | * set as trigger. In other modes, two rising/falling triggers can be set, | |
ba7dd8bb | 557 | * in addition to value/mask trigger for any number of channels. |
c53d793f HE |
558 | * |
559 | * The Sigma supports complex triggers using boolean expressions, but this | |
560 | * has not been implemented yet. | |
561 | */ | |
3ba56876 | 562 | SR_PRIV int sigma_convert_trigger(const struct sr_dev_inst *sdi) |
57bbf56b | 563 | { |
39c64c6a BV |
564 | struct dev_context *devc; |
565 | struct sr_trigger *trigger; | |
566 | struct sr_trigger_stage *stage; | |
567 | struct sr_trigger_match *match; | |
568 | const GSList *l, *m; | |
569 | int channelbit, trigger_set; | |
57bbf56b | 570 | |
39c64c6a | 571 | devc = sdi->priv; |
0e1357e8 | 572 | memset(&devc->trigger, 0, sizeof(struct sigma_trigger)); |
0812c40e | 573 | if (!(trigger = sr_session_trigger_get(sdi->session))) |
39c64c6a BV |
574 | return SR_OK; |
575 | ||
576 | trigger_set = 0; | |
577 | for (l = trigger->stages; l; l = l->next) { | |
578 | stage = l->data; | |
579 | for (m = stage->matches; m; m = m->next) { | |
580 | match = m->data; | |
581 | if (!match->channel->enabled) | |
582 | /* Ignore disabled channels with a trigger. */ | |
583 | continue; | |
584 | channelbit = 1 << (match->channel->index); | |
585 | if (devc->cur_samplerate >= SR_MHZ(100)) { | |
586 | /* Fast trigger support. */ | |
587 | if (trigger_set) { | |
588 | sr_err("Only a single pin trigger is " | |
589 | "supported in 100 and 200MHz mode."); | |
590 | return SR_ERR; | |
591 | } | |
592 | if (match->match == SR_TRIGGER_FALLING) | |
593 | devc->trigger.fallingmask |= channelbit; | |
594 | else if (match->match == SR_TRIGGER_RISING) | |
595 | devc->trigger.risingmask |= channelbit; | |
596 | else { | |
597 | sr_err("Only rising/falling trigger is " | |
598 | "supported in 100 and 200MHz mode."); | |
599 | return SR_ERR; | |
600 | } | |
eec5275e | 601 | |
0a1f7b09 | 602 | trigger_set++; |
39c64c6a BV |
603 | } else { |
604 | /* Simple trigger support (event). */ | |
605 | if (match->match == SR_TRIGGER_ONE) { | |
606 | devc->trigger.simplevalue |= channelbit; | |
607 | devc->trigger.simplemask |= channelbit; | |
608 | } | |
609 | else if (match->match == SR_TRIGGER_ZERO) { | |
610 | devc->trigger.simplevalue &= ~channelbit; | |
611 | devc->trigger.simplemask |= channelbit; | |
612 | } | |
613 | else if (match->match == SR_TRIGGER_FALLING) { | |
614 | devc->trigger.fallingmask |= channelbit; | |
0a1f7b09 | 615 | trigger_set++; |
39c64c6a BV |
616 | } |
617 | else if (match->match == SR_TRIGGER_RISING) { | |
618 | devc->trigger.risingmask |= channelbit; | |
0a1f7b09 | 619 | trigger_set++; |
39c64c6a BV |
620 | } |
621 | ||
622 | /* | |
623 | * Actually, Sigma supports 2 rising/falling triggers, | |
624 | * but they are ORed and the current trigger syntax | |
625 | * does not permit ORed triggers. | |
626 | */ | |
627 | if (trigger_set > 1) { | |
628 | sr_err("Only 1 rising/falling trigger " | |
629 | "is supported."); | |
630 | return SR_ERR; | |
631 | } | |
ee492173 | 632 | } |
ee492173 | 633 | } |
57bbf56b HE |
634 | } |
635 | ||
e46b8fb1 | 636 | return SR_OK; |
57bbf56b HE |
637 | } |
638 | ||
a1c743fc | 639 | |
36b1c8e6 | 640 | /* Software trigger to determine exact trigger position. */ |
5fc01191 | 641 | static int get_trigger_offset(uint8_t *samples, uint16_t last_sample, |
36b1c8e6 HE |
642 | struct sigma_trigger *t) |
643 | { | |
644 | int i; | |
5fc01191 | 645 | uint16_t sample = 0; |
36b1c8e6 | 646 | |
0a1f7b09 | 647 | for (i = 0; i < 8; i++) { |
36b1c8e6 | 648 | if (i > 0) |
5fc01191 MV |
649 | last_sample = sample; |
650 | sample = samples[2 * i] | (samples[2 * i + 1] << 8); | |
36b1c8e6 HE |
651 | |
652 | /* Simple triggers. */ | |
5fc01191 | 653 | if ((sample & t->simplemask) != t->simplevalue) |
36b1c8e6 HE |
654 | continue; |
655 | ||
656 | /* Rising edge. */ | |
5fc01191 MV |
657 | if (((last_sample & t->risingmask) != 0) || |
658 | ((sample & t->risingmask) != t->risingmask)) | |
36b1c8e6 HE |
659 | continue; |
660 | ||
661 | /* Falling edge. */ | |
bdfc7a89 | 662 | if ((last_sample & t->fallingmask) != t->fallingmask || |
5fc01191 | 663 | (sample & t->fallingmask) != 0) |
36b1c8e6 HE |
664 | continue; |
665 | ||
666 | break; | |
667 | } | |
668 | ||
669 | /* If we did not match, return original trigger pos. */ | |
670 | return i & 0x7; | |
671 | } | |
672 | ||
3513d965 MV |
673 | /* |
674 | * Return the timestamp of "DRAM cluster". | |
675 | */ | |
676 | static uint16_t sigma_dram_cluster_ts(struct sigma_dram_cluster *cluster) | |
677 | { | |
678 | return (cluster->timestamp_hi << 8) | cluster->timestamp_lo; | |
679 | } | |
680 | ||
23239b5c MV |
681 | static void sigma_decode_dram_cluster(struct sigma_dram_cluster *dram_cluster, |
682 | unsigned int events_in_cluster, | |
1e23158b | 683 | unsigned int triggered, |
23239b5c MV |
684 | struct sr_dev_inst *sdi) |
685 | { | |
686 | struct dev_context *devc = sdi->priv; | |
687 | struct sigma_state *ss = &devc->state; | |
688 | struct sr_datafeed_packet packet; | |
689 | struct sr_datafeed_logic logic; | |
690 | uint16_t tsdiff, ts; | |
691 | uint8_t samples[2048]; | |
692 | unsigned int i; | |
693 | ||
23239b5c MV |
694 | ts = sigma_dram_cluster_ts(dram_cluster); |
695 | tsdiff = ts - ss->lastts; | |
696 | ss->lastts = ts; | |
697 | ||
698 | packet.type = SR_DF_LOGIC; | |
699 | packet.payload = &logic; | |
700 | logic.unitsize = 2; | |
701 | logic.data = samples; | |
702 | ||
703 | /* | |
704 | * First of all, send Sigrok a copy of the last sample from | |
705 | * previous cluster as many times as needed to make up for | |
706 | * the differential characteristics of data we get from the | |
707 | * Sigma. Sigrok needs one sample of data per period. | |
708 | * | |
709 | * One DRAM cluster contains a timestamp and seven samples, | |
710 | * the units of timestamp are "devc->period_ps" , the first | |
711 | * sample in the cluster happens at the time of the timestamp | |
712 | * and the remaining samples happen at timestamp +1...+6 . | |
713 | */ | |
714 | for (ts = 0; ts < tsdiff - (EVENTS_PER_CLUSTER - 1); ts++) { | |
715 | i = ts % 1024; | |
716 | samples[2 * i + 0] = ss->lastsample & 0xff; | |
717 | samples[2 * i + 1] = ss->lastsample >> 8; | |
718 | ||
719 | /* | |
720 | * If we have 1024 samples ready or we're at the | |
721 | * end of submitting the padding samples, submit | |
722 | * the packet to Sigrok. | |
723 | */ | |
724 | if ((i == 1023) || (ts == (tsdiff - EVENTS_PER_CLUSTER))) { | |
725 | logic.length = (i + 1) * logic.unitsize; | |
102f1239 | 726 | sr_session_send(sdi, &packet); |
23239b5c MV |
727 | } |
728 | } | |
729 | ||
730 | /* | |
731 | * Parse the samples in current cluster and prepare them | |
732 | * to be submitted to Sigrok. | |
733 | */ | |
734 | for (i = 0; i < events_in_cluster; i++) { | |
735 | samples[2 * i + 1] = dram_cluster->samples[i].sample_lo; | |
736 | samples[2 * i + 0] = dram_cluster->samples[i].sample_hi; | |
737 | } | |
738 | ||
739 | /* Send data up to trigger point (if triggered). */ | |
740 | int trigger_offset = 0; | |
1e23158b | 741 | if (triggered) { |
23239b5c MV |
742 | /* |
743 | * Trigger is not always accurate to sample because of | |
744 | * pipeline delay. However, it always triggers before | |
745 | * the actual event. We therefore look at the next | |
746 | * samples to pinpoint the exact position of the trigger. | |
747 | */ | |
748 | trigger_offset = get_trigger_offset(samples, | |
749 | ss->lastsample, &devc->trigger); | |
750 | ||
751 | if (trigger_offset > 0) { | |
752 | packet.type = SR_DF_LOGIC; | |
753 | logic.length = trigger_offset * logic.unitsize; | |
102f1239 | 754 | sr_session_send(sdi, &packet); |
23239b5c MV |
755 | events_in_cluster -= trigger_offset; |
756 | } | |
757 | ||
758 | /* Only send trigger if explicitly enabled. */ | |
759 | if (devc->use_triggers) { | |
760 | packet.type = SR_DF_TRIGGER; | |
102f1239 | 761 | sr_session_send(sdi, &packet); |
23239b5c MV |
762 | } |
763 | } | |
764 | ||
765 | if (events_in_cluster > 0) { | |
766 | packet.type = SR_DF_LOGIC; | |
767 | logic.length = events_in_cluster * logic.unitsize; | |
768 | logic.data = samples + (trigger_offset * logic.unitsize); | |
102f1239 | 769 | sr_session_send(sdi, &packet); |
23239b5c MV |
770 | } |
771 | ||
772 | ss->lastsample = | |
773 | samples[2 * (events_in_cluster - 1) + 0] | | |
774 | (samples[2 * (events_in_cluster - 1) + 1] << 8); | |
775 | ||
776 | } | |
777 | ||
28a35d8a | 778 | /* |
fefa1800 UH |
779 | * Decode chunk of 1024 bytes, 64 clusters, 7 events per cluster. |
780 | * Each event is 20ns apart, and can contain multiple samples. | |
f78898e9 HE |
781 | * |
782 | * For 200 MHz, events contain 4 samples for each channel, spread 5 ns apart. | |
783 | * For 100 MHz, events contain 2 samples for each channel, spread 10 ns apart. | |
784 | * For 50 MHz and below, events contain one sample for each channel, | |
785 | * spread 20 ns apart. | |
28a35d8a | 786 | */ |
1e23158b MV |
787 | static int decode_chunk_ts(struct sigma_dram_line *dram_line, |
788 | uint16_t events_in_line, | |
789 | uint32_t trigger_event, | |
102f1239 | 790 | struct sr_dev_inst *sdi) |
28a35d8a | 791 | { |
3628074d | 792 | struct sigma_dram_cluster *dram_cluster; |
0e1357e8 | 793 | struct dev_context *devc = sdi->priv; |
5fc01191 MV |
794 | unsigned int clusters_in_line = |
795 | (events_in_line + (EVENTS_PER_CLUSTER - 1)) / EVENTS_PER_CLUSTER; | |
796 | unsigned int events_in_cluster; | |
23239b5c | 797 | unsigned int i; |
1e23158b | 798 | uint32_t trigger_cluster = ~0, triggered = 0; |
ee492173 | 799 | |
4ae1f451 | 800 | /* Check if trigger is in this chunk. */ |
1e23158b MV |
801 | if (trigger_event < (64 * 7)) { |
802 | if (devc->cur_samplerate <= SR_MHZ(50)) { | |
803 | trigger_event -= MIN(EVENTS_PER_CLUSTER - 1, | |
804 | trigger_event); | |
805 | } | |
57bbf56b | 806 | |
f3f19d11 | 807 | /* Find in which cluster the trigger occurred. */ |
1e23158b | 808 | trigger_cluster = trigger_event / EVENTS_PER_CLUSTER; |
ee492173 | 809 | } |
28a35d8a | 810 | |
5fc01191 MV |
811 | /* For each full DRAM cluster. */ |
812 | for (i = 0; i < clusters_in_line; i++) { | |
3628074d | 813 | dram_cluster = &dram_line->cluster[i]; |
5fc01191 | 814 | |
5fc01191 | 815 | /* The last cluster might not be full. */ |
23239b5c MV |
816 | if ((i == clusters_in_line - 1) && |
817 | (events_in_line % EVENTS_PER_CLUSTER)) { | |
5fc01191 | 818 | events_in_cluster = events_in_line % EVENTS_PER_CLUSTER; |
23239b5c | 819 | } else { |
5fc01191 | 820 | events_in_cluster = EVENTS_PER_CLUSTER; |
abda62ce | 821 | } |
ee492173 | 822 | |
1e23158b MV |
823 | triggered = (i == trigger_cluster); |
824 | sigma_decode_dram_cluster(dram_cluster, events_in_cluster, | |
825 | triggered, sdi); | |
28a35d8a HE |
826 | } |
827 | ||
e46b8fb1 | 828 | return SR_OK; |
28a35d8a HE |
829 | } |
830 | ||
6057d9fa | 831 | static int download_capture(struct sr_dev_inst *sdi) |
28a35d8a | 832 | { |
6057d9fa | 833 | struct dev_context *devc = sdi->priv; |
e15e5873 | 834 | const uint32_t chunks_per_read = 32; |
fd830beb | 835 | struct sigma_dram_line *dram_line; |
c6648b66 | 836 | int bufsz; |
462fe786 | 837 | uint32_t stoppos, triggerpos; |
6057d9fa MV |
838 | struct sr_datafeed_packet packet; |
839 | uint8_t modestatus; | |
840 | ||
c6648b66 MV |
841 | uint32_t i; |
842 | uint32_t dl_lines_total, dl_lines_curr, dl_lines_done; | |
46641fac | 843 | uint32_t dl_events_in_line = 64 * 7; |
1e23158b | 844 | uint32_t trg_line = ~0, trg_event = ~0; |
c6648b66 | 845 | |
fd830beb MV |
846 | dram_line = g_try_malloc0(chunks_per_read * sizeof(*dram_line)); |
847 | if (!dram_line) | |
848 | return FALSE; | |
849 | ||
6868626b BV |
850 | sr_info("Downloading sample data."); |
851 | ||
6057d9fa MV |
852 | /* Stop acquisition. */ |
853 | sigma_set_register(WRITE_MODE, 0x11, devc); | |
854 | ||
855 | /* Set SDRAM Read Enable. */ | |
856 | sigma_set_register(WRITE_MODE, 0x02, devc); | |
857 | ||
858 | /* Get the current position. */ | |
462fe786 | 859 | sigma_read_pos(&stoppos, &triggerpos, devc); |
6057d9fa MV |
860 | |
861 | /* Check if trigger has fired. */ | |
862 | modestatus = sigma_get_register(READ_MODE, devc); | |
1e23158b | 863 | if (modestatus & 0x20) { |
c6648b66 | 864 | trg_line = triggerpos >> 9; |
1e23158b MV |
865 | trg_event = triggerpos & 0x1ff; |
866 | } | |
6057d9fa | 867 | |
c6648b66 MV |
868 | /* |
869 | * Determine how many 1024b "DRAM lines" do we need to read from the | |
870 | * Sigma so we have a complete set of samples. Note that the last | |
871 | * line can be only partial, containing less than 64 clusters. | |
872 | */ | |
873 | dl_lines_total = (stoppos >> 9) + 1; | |
6868626b | 874 | |
c6648b66 | 875 | dl_lines_done = 0; |
6868626b | 876 | |
c6648b66 MV |
877 | while (dl_lines_total > dl_lines_done) { |
878 | /* We can download only up-to 32 DRAM lines in one go! */ | |
879 | dl_lines_curr = MIN(chunks_per_read, dl_lines_total); | |
6868626b | 880 | |
f41a4cae MV |
881 | bufsz = sigma_read_dram(dl_lines_done, dl_lines_curr, |
882 | (uint8_t *)dram_line, devc); | |
c6648b66 MV |
883 | /* TODO: Check bufsz. For now, just avoid compiler warnings. */ |
884 | (void)bufsz; | |
6868626b | 885 | |
c6648b66 MV |
886 | /* This is the first DRAM line, so find the initial timestamp. */ |
887 | if (dl_lines_done == 0) { | |
3513d965 MV |
888 | devc->state.lastts = |
889 | sigma_dram_cluster_ts(&dram_line[0].cluster[0]); | |
c6648b66 | 890 | devc->state.lastsample = 0; |
6868626b BV |
891 | } |
892 | ||
c6648b66 | 893 | for (i = 0; i < dl_lines_curr; i++) { |
1e23158b | 894 | uint32_t trigger_event = ~0; |
c6648b66 MV |
895 | /* The last "DRAM line" can be only partially full. */ |
896 | if (dl_lines_done + i == dl_lines_total - 1) | |
46641fac | 897 | dl_events_in_line = stoppos & 0x1ff; |
c6648b66 | 898 | |
e69ad48e | 899 | /* Test if the trigger happened on this line. */ |
c6648b66 | 900 | if (dl_lines_done + i == trg_line) |
1e23158b | 901 | trigger_event = trg_event; |
e69ad48e | 902 | |
1e23158b MV |
903 | decode_chunk_ts(dram_line + i, dl_events_in_line, |
904 | trigger_event, sdi); | |
c6648b66 | 905 | } |
6868626b | 906 | |
c6648b66 | 907 | dl_lines_done += dl_lines_curr; |
6868626b BV |
908 | } |
909 | ||
6057d9fa MV |
910 | /* All done. */ |
911 | packet.type = SR_DF_END; | |
912 | sr_session_send(sdi, &packet); | |
913 | ||
3ba56876 | 914 | sdi->driver->dev_acquisition_stop(sdi, sdi); |
6057d9fa | 915 | |
fd830beb MV |
916 | g_free(dram_line); |
917 | ||
6057d9fa | 918 | return TRUE; |
6868626b BV |
919 | } |
920 | ||
d4051930 MV |
921 | /* |
922 | * Handle the Sigma when in CAPTURE mode. This function checks: | |
923 | * - Sampling time ended | |
924 | * - DRAM capacity overflow | |
925 | * This function triggers download of the samples from Sigma | |
926 | * in case either of the above conditions is true. | |
927 | */ | |
928 | static int sigma_capture_mode(struct sr_dev_inst *sdi) | |
6868626b | 929 | { |
d4051930 MV |
930 | struct dev_context *devc = sdi->priv; |
931 | ||
94ba4bd6 | 932 | uint64_t running_msec; |
28a35d8a | 933 | struct timeval tv; |
28a35d8a | 934 | |
00c86508 | 935 | uint32_t stoppos, triggerpos; |
28a35d8a | 936 | |
00c86508 | 937 | /* Check if the selected sampling duration passed. */ |
d4051930 MV |
938 | gettimeofday(&tv, 0); |
939 | running_msec = (tv.tv_sec - devc->start_tv.tv_sec) * 1000 + | |
00c86508 MV |
940 | (tv.tv_usec - devc->start_tv.tv_usec) / 1000; |
941 | if (running_msec >= devc->limit_msec) | |
6057d9fa | 942 | return download_capture(sdi); |
00c86508 MV |
943 | |
944 | /* Get the position in DRAM to which the FPGA is writing now. */ | |
945 | sigma_read_pos(&stoppos, &triggerpos, devc); | |
946 | /* Test if DRAM is full and if so, download the data. */ | |
947 | if ((stoppos >> 9) == 32767) | |
6057d9fa | 948 | return download_capture(sdi); |
28a35d8a | 949 | |
d4051930 MV |
950 | return TRUE; |
951 | } | |
28a35d8a | 952 | |
3ba56876 | 953 | SR_PRIV int sigma_receive_data(int fd, int revents, void *cb_data) |
d4051930 MV |
954 | { |
955 | struct sr_dev_inst *sdi; | |
956 | struct dev_context *devc; | |
88c51afe | 957 | |
d4051930 MV |
958 | (void)fd; |
959 | (void)revents; | |
88c51afe | 960 | |
d4051930 MV |
961 | sdi = cb_data; |
962 | devc = sdi->priv; | |
963 | ||
964 | if (devc->state.state == SIGMA_IDLE) | |
965 | return TRUE; | |
966 | ||
967 | if (devc->state.state == SIGMA_CAPTURE) | |
968 | return sigma_capture_mode(sdi); | |
28a35d8a | 969 | |
28a35d8a HE |
970 | return TRUE; |
971 | } | |
972 | ||
c53d793f HE |
973 | /* Build a LUT entry used by the trigger functions. */ |
974 | static void build_lut_entry(uint16_t value, uint16_t mask, uint16_t *entry) | |
ee492173 HE |
975 | { |
976 | int i, j, k, bit; | |
977 | ||
ba7dd8bb | 978 | /* For each quad channel. */ |
0a1f7b09 | 979 | for (i = 0; i < 4; i++) { |
c53d793f | 980 | entry[i] = 0xffff; |
ee492173 | 981 | |
f758d074 | 982 | /* For each bit in LUT. */ |
0a1f7b09 | 983 | for (j = 0; j < 16; j++) |
ee492173 | 984 | |
ba7dd8bb | 985 | /* For each channel in quad. */ |
0a1f7b09 | 986 | for (k = 0; k < 4; k++) { |
ee492173 HE |
987 | bit = 1 << (i * 4 + k); |
988 | ||
c53d793f | 989 | /* Set bit in entry */ |
0a1f7b09 UH |
990 | if ((mask & bit) && ((!(value & bit)) != |
991 | (!(j & (1 << k))))) | |
c53d793f | 992 | entry[i] &= ~(1 << j); |
ee492173 HE |
993 | } |
994 | } | |
c53d793f | 995 | } |
ee492173 | 996 | |
c53d793f HE |
997 | /* Add a logical function to LUT mask. */ |
998 | static void add_trigger_function(enum triggerop oper, enum triggerfunc func, | |
999 | int index, int neg, uint16_t *mask) | |
1000 | { | |
1001 | int i, j; | |
1002 | int x[2][2], tmp, a, b, aset, bset, rset; | |
1003 | ||
1004 | memset(x, 0, 4 * sizeof(int)); | |
1005 | ||
1006 | /* Trigger detect condition. */ | |
1007 | switch (oper) { | |
1008 | case OP_LEVEL: | |
1009 | x[0][1] = 1; | |
1010 | x[1][1] = 1; | |
1011 | break; | |
1012 | case OP_NOT: | |
1013 | x[0][0] = 1; | |
1014 | x[1][0] = 1; | |
1015 | break; | |
1016 | case OP_RISE: | |
1017 | x[0][1] = 1; | |
1018 | break; | |
1019 | case OP_FALL: | |
1020 | x[1][0] = 1; | |
1021 | break; | |
1022 | case OP_RISEFALL: | |
1023 | x[0][1] = 1; | |
1024 | x[1][0] = 1; | |
1025 | break; | |
1026 | case OP_NOTRISE: | |
1027 | x[1][1] = 1; | |
1028 | x[0][0] = 1; | |
1029 | x[1][0] = 1; | |
1030 | break; | |
1031 | case OP_NOTFALL: | |
1032 | x[1][1] = 1; | |
1033 | x[0][0] = 1; | |
1034 | x[0][1] = 1; | |
1035 | break; | |
1036 | case OP_NOTRISEFALL: | |
1037 | x[1][1] = 1; | |
1038 | x[0][0] = 1; | |
1039 | break; | |
1040 | } | |
1041 | ||
1042 | /* Transpose if neg is set. */ | |
1043 | if (neg) { | |
0a1f7b09 UH |
1044 | for (i = 0; i < 2; i++) { |
1045 | for (j = 0; j < 2; j++) { | |
c53d793f | 1046 | tmp = x[i][j]; |
0a1f7b09 UH |
1047 | x[i][j] = x[1 - i][1 - j]; |
1048 | x[1 - i][1 - j] = tmp; | |
c53d793f | 1049 | } |
ea9cfed7 | 1050 | } |
c53d793f HE |
1051 | } |
1052 | ||
1053 | /* Update mask with function. */ | |
0a1f7b09 | 1054 | for (i = 0; i < 16; i++) { |
c53d793f HE |
1055 | a = (i >> (2 * index + 0)) & 1; |
1056 | b = (i >> (2 * index + 1)) & 1; | |
1057 | ||
1058 | aset = (*mask >> i) & 1; | |
1059 | bset = x[b][a]; | |
1060 | ||
382cb19f | 1061 | rset = 0; |
c53d793f HE |
1062 | if (func == FUNC_AND || func == FUNC_NAND) |
1063 | rset = aset & bset; | |
1064 | else if (func == FUNC_OR || func == FUNC_NOR) | |
1065 | rset = aset | bset; | |
1066 | else if (func == FUNC_XOR || func == FUNC_NXOR) | |
1067 | rset = aset ^ bset; | |
1068 | ||
1069 | if (func == FUNC_NAND || func == FUNC_NOR || func == FUNC_NXOR) | |
1070 | rset = !rset; | |
1071 | ||
1072 | *mask &= ~(1 << i); | |
1073 | ||
1074 | if (rset) | |
1075 | *mask |= 1 << i; | |
1076 | } | |
1077 | } | |
1078 | ||
1079 | /* | |
1080 | * Build trigger LUTs used by 50 MHz and lower sample rates for supporting | |
1081 | * simple pin change and state triggers. Only two transitions (rise/fall) can be | |
1082 | * set at any time, but a full mask and value can be set (0/1). | |
1083 | */ | |
3ba56876 | 1084 | SR_PRIV int sigma_build_basic_trigger(struct triggerlut *lut, struct dev_context *devc) |
c53d793f HE |
1085 | { |
1086 | int i,j; | |
4ae1f451 | 1087 | uint16_t masks[2] = { 0, 0 }; |
c53d793f HE |
1088 | |
1089 | memset(lut, 0, sizeof(struct triggerlut)); | |
1090 | ||
f3f19d11 | 1091 | /* Constant for simple triggers. */ |
c53d793f HE |
1092 | lut->m4 = 0xa000; |
1093 | ||
1094 | /* Value/mask trigger support. */ | |
0e1357e8 | 1095 | build_lut_entry(devc->trigger.simplevalue, devc->trigger.simplemask, |
99965709 | 1096 | lut->m2d); |
c53d793f HE |
1097 | |
1098 | /* Rise/fall trigger support. */ | |
0a1f7b09 | 1099 | for (i = 0, j = 0; i < 16; i++) { |
0e1357e8 BV |
1100 | if (devc->trigger.risingmask & (1 << i) || |
1101 | devc->trigger.fallingmask & (1 << i)) | |
c53d793f HE |
1102 | masks[j++] = 1 << i; |
1103 | } | |
1104 | ||
1105 | build_lut_entry(masks[0], masks[0], lut->m0d); | |
1106 | build_lut_entry(masks[1], masks[1], lut->m1d); | |
1107 | ||
1108 | /* Add glue logic */ | |
1109 | if (masks[0] || masks[1]) { | |
1110 | /* Transition trigger. */ | |
0e1357e8 | 1111 | if (masks[0] & devc->trigger.risingmask) |
c53d793f | 1112 | add_trigger_function(OP_RISE, FUNC_OR, 0, 0, &lut->m3); |
0e1357e8 | 1113 | if (masks[0] & devc->trigger.fallingmask) |
c53d793f | 1114 | add_trigger_function(OP_FALL, FUNC_OR, 0, 0, &lut->m3); |
0e1357e8 | 1115 | if (masks[1] & devc->trigger.risingmask) |
c53d793f | 1116 | add_trigger_function(OP_RISE, FUNC_OR, 1, 0, &lut->m3); |
0e1357e8 | 1117 | if (masks[1] & devc->trigger.fallingmask) |
c53d793f HE |
1118 | add_trigger_function(OP_FALL, FUNC_OR, 1, 0, &lut->m3); |
1119 | } else { | |
1120 | /* Only value/mask trigger. */ | |
1121 | lut->m3 = 0xffff; | |
1122 | } | |
ee492173 | 1123 | |
c53d793f | 1124 | /* Triggertype: event. */ |
ee492173 HE |
1125 | lut->params.selres = 3; |
1126 | ||
e46b8fb1 | 1127 | return SR_OK; |
ee492173 | 1128 | } |