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Commit | Line | Data |
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28a35d8a HE |
1 | /* |
2 | * This file is part of the sigrok project. | |
3 | * | |
868501fa | 4 | * Copyright (C) 2010-2012 Håvard Espeland <gus@ping.uio.no>, |
911f1834 UH |
5 | * Copyright (C) 2010 Martin Stensgård <mastensg@ping.uio.no> |
6 | * Copyright (C) 2010 Carl Henrik Lunde <chlunde@ping.uio.no> | |
28a35d8a HE |
7 | * |
8 | * This program is free software: you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation, either version 3 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
20 | */ | |
21 | ||
911f1834 | 22 | /* |
6352d030 | 23 | * ASIX SIGMA/SIGMA2 logic analyzer driver |
911f1834 UH |
24 | */ |
25 | ||
3bbd9849 UH |
26 | #include <glib.h> |
27 | #include <glib/gstdio.h> | |
28a35d8a HE |
28 | #include <ftdi.h> |
29 | #include <string.h> | |
45c59c8b BV |
30 | #include "libsigrok.h" |
31 | #include "libsigrok-internal.h" | |
28a35d8a HE |
32 | #include "asix-sigma.h" |
33 | ||
34 | #define USB_VENDOR 0xa600 | |
35 | #define USB_PRODUCT 0xa000 | |
36 | #define USB_DESCRIPTION "ASIX SIGMA" | |
37 | #define USB_VENDOR_NAME "ASIX" | |
38 | #define USB_MODEL_NAME "SIGMA" | |
39 | #define USB_MODEL_VERSION "" | |
ee492173 | 40 | #define TRIGGER_TYPES "rf10" |
464d12c7 | 41 | #define NUM_PROBES 16 |
28a35d8a | 42 | |
ed300b9f BV |
43 | SR_PRIV struct sr_dev_driver asix_sigma_driver_info; |
44 | static struct sr_dev_driver *adi = &asix_sigma_driver_info; | |
28a35d8a | 45 | |
a533743d | 46 | static const uint64_t supported_samplerates[] = { |
59df0c77 UH |
47 | SR_KHZ(200), |
48 | SR_KHZ(250), | |
49 | SR_KHZ(500), | |
50 | SR_MHZ(1), | |
51 | SR_MHZ(5), | |
52 | SR_MHZ(10), | |
53 | SR_MHZ(25), | |
54 | SR_MHZ(50), | |
55 | SR_MHZ(100), | |
56 | SR_MHZ(200), | |
28a35d8a HE |
57 | 0, |
58 | }; | |
59 | ||
d261dbbf UH |
60 | /* |
61 | * Probe numbers seem to go from 1-16, according to this image: | |
62 | * http://tools.asix.net/img/sigma_sigmacab_pins_720.jpg | |
63 | * (the cable has two additional GND pins, and a TI and TO pin) | |
64 | */ | |
c37d2b1b | 65 | static const char *probe_names[NUM_PROBES + 1] = { |
464d12c7 KS |
66 | "1", |
67 | "2", | |
68 | "3", | |
69 | "4", | |
70 | "5", | |
71 | "6", | |
72 | "7", | |
73 | "8", | |
74 | "9", | |
75 | "10", | |
76 | "11", | |
77 | "12", | |
78 | "13", | |
79 | "14", | |
80 | "15", | |
d261dbbf | 81 | "16", |
464d12c7 KS |
82 | NULL, |
83 | }; | |
84 | ||
a533743d | 85 | static const struct sr_samplerates samplerates = { |
590b9f9a UH |
86 | 0, |
87 | 0, | |
88 | 0, | |
28a35d8a HE |
89 | supported_samplerates, |
90 | }; | |
91 | ||
915f7cc8 | 92 | static const int hwcaps[] = { |
5a2326a7 UH |
93 | SR_HWCAP_LOGIC_ANALYZER, |
94 | SR_HWCAP_SAMPLERATE, | |
95 | SR_HWCAP_CAPTURE_RATIO, | |
96 | SR_HWCAP_PROBECONFIG, | |
28a35d8a | 97 | |
5a2326a7 | 98 | SR_HWCAP_LIMIT_MSEC, |
28a35d8a HE |
99 | 0, |
100 | }; | |
101 | ||
fefa1800 UH |
102 | /* Force the FPGA to reboot. */ |
103 | static uint8_t suicide[] = { | |
104 | 0x84, 0x84, 0x88, 0x84, 0x88, 0x84, 0x88, 0x84, | |
105 | }; | |
106 | ||
107 | /* Prepare to upload firmware (FPGA specific). */ | |
108 | static uint8_t init[] = { | |
109 | 0x03, 0x03, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, | |
110 | }; | |
111 | ||
112 | /* Initialize the logic analyzer mode. */ | |
113 | static uint8_t logic_mode_start[] = { | |
114 | 0x00, 0x40, 0x0f, 0x25, 0x35, 0x40, | |
115 | 0x2a, 0x3a, 0x40, 0x03, 0x20, 0x38, | |
116 | }; | |
117 | ||
eec5275e | 118 | static const char *firmware_files[] = { |
a8116d76 HE |
119 | "asix-sigma-50.fw", /* 50 MHz, supports 8 bit fractions */ |
120 | "asix-sigma-100.fw", /* 100 MHz */ | |
121 | "asix-sigma-200.fw", /* 200 MHz */ | |
ed09fd07 | 122 | "asix-sigma-50sync.fw", /* Synchronous clock from pin */ |
a8116d76 | 123 | "asix-sigma-phasor.fw", /* Frequency counter */ |
f6564c8d HE |
124 | }; |
125 | ||
3ffb6964 BV |
126 | static int hw_dev_acquisition_stop(const struct sr_dev_inst *sdi, |
127 | void *cb_data); | |
6aac7737 | 128 | |
ea9cfed7 | 129 | static int sigma_read(void *buf, size_t size, struct context *ctx) |
28a35d8a HE |
130 | { |
131 | int ret; | |
fefa1800 | 132 | |
ea9cfed7 | 133 | ret = ftdi_read_data(&ctx->ftdic, (unsigned char *)buf, size); |
28a35d8a | 134 | if (ret < 0) { |
7b48d6e1 | 135 | sr_err("sigma: ftdi_read_data failed: %s", |
ea9cfed7 | 136 | ftdi_get_error_string(&ctx->ftdic)); |
28a35d8a HE |
137 | } |
138 | ||
139 | return ret; | |
140 | } | |
141 | ||
ea9cfed7 | 142 | static int sigma_write(void *buf, size_t size, struct context *ctx) |
28a35d8a HE |
143 | { |
144 | int ret; | |
fefa1800 | 145 | |
ea9cfed7 | 146 | ret = ftdi_write_data(&ctx->ftdic, (unsigned char *)buf, size); |
28a35d8a | 147 | if (ret < 0) { |
7b48d6e1 | 148 | sr_err("sigma: ftdi_write_data failed: %s", |
ea9cfed7 | 149 | ftdi_get_error_string(&ctx->ftdic)); |
fefa1800 | 150 | } else if ((size_t) ret != size) { |
0aeb0ccd | 151 | sr_err("sigma: ftdi_write_data did not complete write."); |
28a35d8a HE |
152 | } |
153 | ||
154 | return ret; | |
155 | } | |
156 | ||
99965709 | 157 | static int sigma_write_register(uint8_t reg, uint8_t *data, size_t len, |
ea9cfed7 | 158 | struct context *ctx) |
28a35d8a HE |
159 | { |
160 | size_t i; | |
161 | uint8_t buf[len + 2]; | |
162 | int idx = 0; | |
163 | ||
164 | buf[idx++] = REG_ADDR_LOW | (reg & 0xf); | |
165 | buf[idx++] = REG_ADDR_HIGH | (reg >> 4); | |
166 | ||
fefa1800 | 167 | for (i = 0; i < len; ++i) { |
28a35d8a HE |
168 | buf[idx++] = REG_DATA_LOW | (data[i] & 0xf); |
169 | buf[idx++] = REG_DATA_HIGH_WRITE | (data[i] >> 4); | |
170 | } | |
171 | ||
ea9cfed7 | 172 | return sigma_write(buf, idx, ctx); |
28a35d8a HE |
173 | } |
174 | ||
ea9cfed7 | 175 | static int sigma_set_register(uint8_t reg, uint8_t value, struct context *ctx) |
28a35d8a | 176 | { |
ea9cfed7 | 177 | return sigma_write_register(reg, &value, 1, ctx); |
28a35d8a HE |
178 | } |
179 | ||
99965709 | 180 | static int sigma_read_register(uint8_t reg, uint8_t *data, size_t len, |
ea9cfed7 | 181 | struct context *ctx) |
28a35d8a HE |
182 | { |
183 | uint8_t buf[3]; | |
fefa1800 | 184 | |
28a35d8a HE |
185 | buf[0] = REG_ADDR_LOW | (reg & 0xf); |
186 | buf[1] = REG_ADDR_HIGH | (reg >> 4); | |
28a35d8a HE |
187 | buf[2] = REG_READ_ADDR; |
188 | ||
ea9cfed7 | 189 | sigma_write(buf, sizeof(buf), ctx); |
28a35d8a | 190 | |
ea9cfed7 | 191 | return sigma_read(data, len, ctx); |
28a35d8a HE |
192 | } |
193 | ||
ea9cfed7 | 194 | static uint8_t sigma_get_register(uint8_t reg, struct context *ctx) |
28a35d8a HE |
195 | { |
196 | uint8_t value; | |
fefa1800 | 197 | |
ea9cfed7 | 198 | if (1 != sigma_read_register(reg, &value, 1, ctx)) { |
7b48d6e1 | 199 | sr_err("sigma: sigma_get_register: 1 byte expected"); |
28a35d8a HE |
200 | return 0; |
201 | } | |
202 | ||
203 | return value; | |
204 | } | |
205 | ||
99965709 | 206 | static int sigma_read_pos(uint32_t *stoppos, uint32_t *triggerpos, |
ea9cfed7 | 207 | struct context *ctx) |
28a35d8a HE |
208 | { |
209 | uint8_t buf[] = { | |
210 | REG_ADDR_LOW | READ_TRIGGER_POS_LOW, | |
211 | ||
212 | REG_READ_ADDR | NEXT_REG, | |
213 | REG_READ_ADDR | NEXT_REG, | |
214 | REG_READ_ADDR | NEXT_REG, | |
215 | REG_READ_ADDR | NEXT_REG, | |
216 | REG_READ_ADDR | NEXT_REG, | |
217 | REG_READ_ADDR | NEXT_REG, | |
218 | }; | |
28a35d8a HE |
219 | uint8_t result[6]; |
220 | ||
ea9cfed7 | 221 | sigma_write(buf, sizeof(buf), ctx); |
28a35d8a | 222 | |
ea9cfed7 | 223 | sigma_read(result, sizeof(result), ctx); |
28a35d8a HE |
224 | |
225 | *triggerpos = result[0] | (result[1] << 8) | (result[2] << 16); | |
226 | *stoppos = result[3] | (result[4] << 8) | (result[5] << 16); | |
227 | ||
57bbf56b HE |
228 | /* Not really sure why this must be done, but according to spec. */ |
229 | if ((--*stoppos & 0x1ff) == 0x1ff) | |
230 | stoppos -= 64; | |
231 | ||
232 | if ((*--triggerpos & 0x1ff) == 0x1ff) | |
233 | triggerpos -= 64; | |
234 | ||
28a35d8a HE |
235 | return 1; |
236 | } | |
237 | ||
99965709 | 238 | static int sigma_read_dram(uint16_t startchunk, size_t numchunks, |
ea9cfed7 | 239 | uint8_t *data, struct context *ctx) |
28a35d8a HE |
240 | { |
241 | size_t i; | |
242 | uint8_t buf[4096]; | |
243 | int idx = 0; | |
244 | ||
fefa1800 | 245 | /* Send the startchunk. Index start with 1. */ |
28a35d8a HE |
246 | buf[0] = startchunk >> 8; |
247 | buf[1] = startchunk & 0xff; | |
ea9cfed7 | 248 | sigma_write_register(WRITE_MEMROW, buf, 2, ctx); |
28a35d8a | 249 | |
fefa1800 | 250 | /* Read the DRAM. */ |
28a35d8a HE |
251 | buf[idx++] = REG_DRAM_BLOCK; |
252 | buf[idx++] = REG_DRAM_WAIT_ACK; | |
253 | ||
254 | for (i = 0; i < numchunks; ++i) { | |
fefa1800 UH |
255 | /* Alternate bit to copy from DRAM to cache. */ |
256 | if (i != (numchunks - 1)) | |
257 | buf[idx++] = REG_DRAM_BLOCK | (((i + 1) % 2) << 4); | |
28a35d8a HE |
258 | |
259 | buf[idx++] = REG_DRAM_BLOCK_DATA | ((i % 2) << 4); | |
260 | ||
fefa1800 | 261 | if (i != (numchunks - 1)) |
28a35d8a HE |
262 | buf[idx++] = REG_DRAM_WAIT_ACK; |
263 | } | |
264 | ||
ea9cfed7 | 265 | sigma_write(buf, idx, ctx); |
28a35d8a | 266 | |
ea9cfed7 | 267 | return sigma_read(data, numchunks * CHUNK_SIZE, ctx); |
28a35d8a HE |
268 | } |
269 | ||
4ae1f451 | 270 | /* Upload trigger look-up tables to Sigma. */ |
ea9cfed7 | 271 | static int sigma_write_trigger_lut(struct triggerlut *lut, struct context *ctx) |
ee492173 HE |
272 | { |
273 | int i; | |
274 | uint8_t tmp[2]; | |
275 | uint16_t bit; | |
276 | ||
277 | /* Transpose the table and send to Sigma. */ | |
278 | for (i = 0; i < 16; ++i) { | |
279 | bit = 1 << i; | |
280 | ||
281 | tmp[0] = tmp[1] = 0; | |
282 | ||
283 | if (lut->m2d[0] & bit) | |
284 | tmp[0] |= 0x01; | |
285 | if (lut->m2d[1] & bit) | |
286 | tmp[0] |= 0x02; | |
287 | if (lut->m2d[2] & bit) | |
288 | tmp[0] |= 0x04; | |
289 | if (lut->m2d[3] & bit) | |
290 | tmp[0] |= 0x08; | |
291 | ||
292 | if (lut->m3 & bit) | |
293 | tmp[0] |= 0x10; | |
294 | if (lut->m3s & bit) | |
295 | tmp[0] |= 0x20; | |
296 | if (lut->m4 & bit) | |
297 | tmp[0] |= 0x40; | |
298 | ||
299 | if (lut->m0d[0] & bit) | |
300 | tmp[1] |= 0x01; | |
301 | if (lut->m0d[1] & bit) | |
302 | tmp[1] |= 0x02; | |
303 | if (lut->m0d[2] & bit) | |
304 | tmp[1] |= 0x04; | |
305 | if (lut->m0d[3] & bit) | |
306 | tmp[1] |= 0x08; | |
307 | ||
308 | if (lut->m1d[0] & bit) | |
309 | tmp[1] |= 0x10; | |
310 | if (lut->m1d[1] & bit) | |
311 | tmp[1] |= 0x20; | |
312 | if (lut->m1d[2] & bit) | |
313 | tmp[1] |= 0x40; | |
314 | if (lut->m1d[3] & bit) | |
315 | tmp[1] |= 0x80; | |
316 | ||
99965709 | 317 | sigma_write_register(WRITE_TRIGGER_SELECT0, tmp, sizeof(tmp), |
ea9cfed7 UH |
318 | ctx); |
319 | sigma_set_register(WRITE_TRIGGER_SELECT1, 0x30 | i, ctx); | |
ee492173 HE |
320 | } |
321 | ||
322 | /* Send the parameters */ | |
323 | sigma_write_register(WRITE_TRIGGER_SELECT0, (uint8_t *) &lut->params, | |
ea9cfed7 | 324 | sizeof(lut->params), ctx); |
ee492173 | 325 | |
e46b8fb1 | 326 | return SR_OK; |
ee492173 HE |
327 | } |
328 | ||
fefa1800 | 329 | /* Generate the bitbang stream for programming the FPGA. */ |
28a35d8a | 330 | static int bin2bitbang(const char *filename, |
fefa1800 | 331 | unsigned char **buf, size_t *buf_size) |
28a35d8a | 332 | { |
fefa1800 | 333 | FILE *f; |
e3fff420 | 334 | unsigned long file_size; |
28a35d8a HE |
335 | unsigned long offset = 0; |
336 | unsigned char *p; | |
e3fff420 HE |
337 | uint8_t *firmware; |
338 | unsigned long fwsize = 0; | |
28a35d8a HE |
339 | const int buffer_size = 65536; |
340 | size_t i; | |
e3fff420 | 341 | int c, bit, v; |
fefa1800 | 342 | uint32_t imm = 0x3f6df2ab; |
28a35d8a | 343 | |
868d8cef | 344 | f = g_fopen(filename, "rb"); |
28a35d8a | 345 | if (!f) { |
7b48d6e1 | 346 | sr_err("sigma: g_fopen(\"%s\", \"rb\")", filename); |
b53738ba | 347 | return SR_ERR; |
28a35d8a HE |
348 | } |
349 | ||
350 | if (-1 == fseek(f, 0, SEEK_END)) { | |
7b48d6e1 | 351 | sr_err("sigma: fseek on %s failed", filename); |
28a35d8a | 352 | fclose(f); |
b53738ba | 353 | return SR_ERR; |
28a35d8a HE |
354 | } |
355 | ||
356 | file_size = ftell(f); | |
357 | ||
358 | fseek(f, 0, SEEK_SET); | |
359 | ||
b53738ba | 360 | if (!(firmware = g_try_malloc(buffer_size))) { |
340cfac0 | 361 | sr_err("sigma: %s: firmware malloc failed", __func__); |
12ad53f5 | 362 | fclose(f); |
b53738ba | 363 | return SR_ERR_MALLOC; |
28a35d8a HE |
364 | } |
365 | ||
28a35d8a HE |
366 | while ((c = getc(f)) != EOF) { |
367 | imm = (imm + 0xa853753) % 177 + (imm * 0x8034052); | |
e3fff420 | 368 | firmware[fwsize++] = c ^ imm; |
28a35d8a HE |
369 | } |
370 | fclose(f); | |
371 | ||
e3fff420 HE |
372 | if(fwsize != file_size) { |
373 | sr_err("sigma: %s: Error reading firmware", filename); | |
374 | fclose(f); | |
375 | g_free(firmware); | |
376 | return SR_ERR; | |
28a35d8a HE |
377 | } |
378 | ||
28a35d8a HE |
379 | *buf_size = fwsize * 2 * 8; |
380 | ||
b53738ba | 381 | *buf = p = (unsigned char *)g_try_malloc(*buf_size); |
28a35d8a | 382 | if (!p) { |
340cfac0 | 383 | sr_err("sigma: %s: buf/p malloc failed", __func__); |
12ad53f5 | 384 | g_free(firmware); |
b53738ba | 385 | return SR_ERR_MALLOC; |
28a35d8a HE |
386 | } |
387 | ||
388 | for (i = 0; i < fwsize; ++i) { | |
28a35d8a | 389 | for (bit = 7; bit >= 0; --bit) { |
fefa1800 | 390 | v = firmware[i] & 1 << bit ? 0x40 : 0x00; |
28a35d8a HE |
391 | p[offset++] = v | 0x01; |
392 | p[offset++] = v; | |
393 | } | |
394 | } | |
395 | ||
396 | g_free(firmware); | |
397 | ||
398 | if (offset != *buf_size) { | |
399 | g_free(*buf); | |
7b48d6e1 | 400 | sr_err("sigma: Error reading firmware %s " |
0aeb0ccd | 401 | "offset=%ld, file_size=%ld, buf_size=%zd.", |
133a37bf | 402 | filename, offset, file_size, *buf_size); |
28a35d8a | 403 | |
b53738ba | 404 | return SR_ERR; |
28a35d8a HE |
405 | } |
406 | ||
b53738ba | 407 | return SR_OK; |
28a35d8a HE |
408 | } |
409 | ||
0448d110 BV |
410 | static void clear_instances(void) |
411 | { | |
412 | GSList *l; | |
413 | struct sr_dev_inst *sdi; | |
414 | struct context *ctx; | |
415 | ||
416 | /* Properly close all devices. */ | |
417 | for (l = adi->instances; l; l = l->next) { | |
418 | if (!(sdi = l->data)) { | |
419 | /* Log error, but continue cleaning up the rest. */ | |
420 | sr_err("sigma: %s: sdi was NULL, continuing", __func__); | |
421 | continue; | |
422 | } | |
423 | if (sdi->priv) { | |
424 | ctx = sdi->priv; | |
425 | ftdi_free(&ctx->ftdic); | |
426 | g_free(ctx); | |
427 | } | |
428 | sr_dev_inst_free(sdi); | |
429 | } | |
430 | g_slist_free(adi->instances); | |
431 | adi->instances = NULL; | |
432 | ||
433 | } | |
434 | ||
40dda2c3 | 435 | static int hw_init(void) |
61136ea6 BV |
436 | { |
437 | ||
438 | /* Nothing to do. */ | |
439 | ||
440 | return SR_OK; | |
441 | } | |
442 | ||
0448d110 | 443 | static GSList *hw_scan(GSList *options) |
28a35d8a | 444 | { |
d68e2d1a | 445 | struct sr_dev_inst *sdi; |
ea9cfed7 | 446 | struct context *ctx; |
0448d110 | 447 | GSList *devices; |
e3fff420 HE |
448 | struct ftdi_device_list *devlist; |
449 | char serial_txt[10]; | |
450 | uint32_t serial; | |
eec944c5 | 451 | int ret; |
28a35d8a | 452 | |
0448d110 BV |
453 | (void)options; |
454 | devices = NULL; | |
455 | clear_instances(); | |
456 | ||
ea9cfed7 UH |
457 | if (!(ctx = g_try_malloc(sizeof(struct context)))) { |
458 | sr_err("sigma: %s: ctx malloc failed", __func__); | |
0448d110 | 459 | return NULL; |
b53738ba | 460 | } |
99965709 | 461 | |
ea9cfed7 | 462 | ftdi_init(&ctx->ftdic); |
28a35d8a | 463 | |
fefa1800 | 464 | /* Look for SIGMAs. */ |
e3fff420 | 465 | |
eec944c5 BV |
466 | if ((ret = ftdi_usb_find_all(&ctx->ftdic, &devlist, |
467 | USB_VENDOR, USB_PRODUCT)) <= 0) { | |
468 | if (ret < 0) | |
469 | sr_err("ftdi_usb_find_all(): %d", ret); | |
99965709 | 470 | goto free; |
eec944c5 | 471 | } |
99965709 | 472 | |
e3fff420 HE |
473 | /* Make sure it's a version 1 or 2 SIGMA. */ |
474 | ftdi_usb_get_strings(&ctx->ftdic, devlist->dev, NULL, 0, NULL, 0, | |
6352d030 | 475 | serial_txt, sizeof(serial_txt)); |
e3fff420 HE |
476 | sscanf(serial_txt, "%x", &serial); |
477 | ||
6352d030 | 478 | if (serial < 0xa6010000 || serial > 0xa602ffff) { |
e3fff420 | 479 | sr_err("sigma: Only SIGMA and SIGMA2 are supported " |
6352d030 | 480 | "in this version of sigrok."); |
e3fff420 HE |
481 | goto free; |
482 | } | |
483 | ||
484 | sr_info("Found ASIX SIGMA - Serial: %s", serial_txt); | |
485 | ||
ea9cfed7 UH |
486 | ctx->cur_samplerate = 0; |
487 | ctx->period_ps = 0; | |
488 | ctx->limit_msec = 0; | |
489 | ctx->cur_firmware = -1; | |
490 | ctx->num_probes = 0; | |
491 | ctx->samples_per_event = 0; | |
492 | ctx->capture_ratio = 50; | |
493 | ctx->use_triggers = 0; | |
28a35d8a | 494 | |
fefa1800 | 495 | /* Register SIGMA device. */ |
d68e2d1a UH |
496 | if (!(sdi = sr_dev_inst_new(0, SR_ST_INITIALIZING, USB_VENDOR_NAME, |
497 | USB_MODEL_NAME, USB_MODEL_VERSION))) { | |
498 | sr_err("sigma: %s: sdi was NULL", __func__); | |
99965709 | 499 | goto free; |
d68e2d1a | 500 | } |
d7bbecfd | 501 | sdi->driver = adi; |
0448d110 | 502 | devices = g_slist_append(devices, sdi); |
ed300b9f | 503 | adi->instances = g_slist_append(adi->instances, sdi); |
0448d110 | 504 | sdi->priv = ctx; |
28a35d8a | 505 | |
fefa1800 | 506 | /* We will open the device again when we need it. */ |
e3fff420 | 507 | ftdi_list_free(&devlist); |
28a35d8a | 508 | |
0448d110 | 509 | return devices; |
ea9cfed7 | 510 | |
99965709 | 511 | free: |
eec944c5 | 512 | ftdi_deinit(&ctx->ftdic); |
ea9cfed7 | 513 | g_free(ctx); |
0448d110 | 514 | return NULL; |
28a35d8a HE |
515 | } |
516 | ||
ea9cfed7 | 517 | static int upload_firmware(int firmware_idx, struct context *ctx) |
28a35d8a HE |
518 | { |
519 | int ret; | |
520 | unsigned char *buf; | |
521 | unsigned char pins; | |
522 | size_t buf_size; | |
28a35d8a | 523 | unsigned char result[32]; |
e8397563 | 524 | char firmware_path[128]; |
28a35d8a | 525 | |
fefa1800 | 526 | /* Make sure it's an ASIX SIGMA. */ |
ea9cfed7 | 527 | if ((ret = ftdi_usb_open_desc(&ctx->ftdic, |
28a35d8a | 528 | USB_VENDOR, USB_PRODUCT, USB_DESCRIPTION, NULL)) < 0) { |
7b48d6e1 | 529 | sr_err("sigma: ftdi_usb_open failed: %s", |
ea9cfed7 | 530 | ftdi_get_error_string(&ctx->ftdic)); |
28a35d8a HE |
531 | return 0; |
532 | } | |
533 | ||
ea9cfed7 | 534 | if ((ret = ftdi_set_bitmode(&ctx->ftdic, 0xdf, BITMODE_BITBANG)) < 0) { |
7b48d6e1 | 535 | sr_err("sigma: ftdi_set_bitmode failed: %s", |
ea9cfed7 | 536 | ftdi_get_error_string(&ctx->ftdic)); |
28a35d8a HE |
537 | return 0; |
538 | } | |
539 | ||
fefa1800 | 540 | /* Four times the speed of sigmalogan - Works well. */ |
ea9cfed7 | 541 | if ((ret = ftdi_set_baudrate(&ctx->ftdic, 750000)) < 0) { |
7b48d6e1 | 542 | sr_err("sigma: ftdi_set_baudrate failed: %s", |
ea9cfed7 | 543 | ftdi_get_error_string(&ctx->ftdic)); |
28a35d8a HE |
544 | return 0; |
545 | } | |
546 | ||
fefa1800 | 547 | /* Force the FPGA to reboot. */ |
ea9cfed7 UH |
548 | sigma_write(suicide, sizeof(suicide), ctx); |
549 | sigma_write(suicide, sizeof(suicide), ctx); | |
550 | sigma_write(suicide, sizeof(suicide), ctx); | |
551 | sigma_write(suicide, sizeof(suicide), ctx); | |
28a35d8a | 552 | |
fefa1800 | 553 | /* Prepare to upload firmware (FPGA specific). */ |
ea9cfed7 | 554 | sigma_write(init, sizeof(init), ctx); |
28a35d8a | 555 | |
ea9cfed7 | 556 | ftdi_usb_purge_buffers(&ctx->ftdic); |
28a35d8a | 557 | |
fefa1800 | 558 | /* Wait until the FPGA asserts INIT_B. */ |
28a35d8a | 559 | while (1) { |
ea9cfed7 | 560 | ret = sigma_read(result, 1, ctx); |
28a35d8a HE |
561 | if (result[0] & 0x20) |
562 | break; | |
563 | } | |
564 | ||
9ddb2a12 | 565 | /* Prepare firmware. */ |
e8397563 | 566 | snprintf(firmware_path, sizeof(firmware_path), "%s/%s", FIRMWARE_DIR, |
f6564c8d HE |
567 | firmware_files[firmware_idx]); |
568 | ||
b53738ba | 569 | if ((ret = bin2bitbang(firmware_path, &buf, &buf_size)) != SR_OK) { |
7b48d6e1 | 570 | sr_err("sigma: An error occured while reading the firmware: %s", |
133a37bf | 571 | firmware_path); |
b53738ba | 572 | return ret; |
28a35d8a HE |
573 | } |
574 | ||
fefa1800 | 575 | /* Upload firmare. */ |
e3fff420 | 576 | sr_info("sigma: Uploading firmware %s", firmware_files[firmware_idx]); |
ea9cfed7 | 577 | sigma_write(buf, buf_size, ctx); |
28a35d8a HE |
578 | |
579 | g_free(buf); | |
580 | ||
ea9cfed7 | 581 | if ((ret = ftdi_set_bitmode(&ctx->ftdic, 0x00, BITMODE_RESET)) < 0) { |
7b48d6e1 | 582 | sr_err("sigma: ftdi_set_bitmode failed: %s", |
ea9cfed7 | 583 | ftdi_get_error_string(&ctx->ftdic)); |
e46b8fb1 | 584 | return SR_ERR; |
28a35d8a HE |
585 | } |
586 | ||
ea9cfed7 | 587 | ftdi_usb_purge_buffers(&ctx->ftdic); |
28a35d8a | 588 | |
fefa1800 | 589 | /* Discard garbage. */ |
ea9cfed7 | 590 | while (1 == sigma_read(&pins, 1, ctx)) |
28a35d8a HE |
591 | ; |
592 | ||
fefa1800 | 593 | /* Initialize the logic analyzer mode. */ |
ea9cfed7 | 594 | sigma_write(logic_mode_start, sizeof(logic_mode_start), ctx); |
28a35d8a | 595 | |
fefa1800 | 596 | /* Expect a 3 byte reply. */ |
ea9cfed7 | 597 | ret = sigma_read(result, 3, ctx); |
28a35d8a HE |
598 | if (ret != 3 || |
599 | result[0] != 0xa6 || result[1] != 0x55 || result[2] != 0xaa) { | |
7b48d6e1 | 600 | sr_err("sigma: Configuration failed. Invalid reply received."); |
e46b8fb1 | 601 | return SR_ERR; |
28a35d8a HE |
602 | } |
603 | ||
ea9cfed7 | 604 | ctx->cur_firmware = firmware_idx; |
f6564c8d | 605 | |
e3fff420 HE |
606 | sr_info("sigma: Firmware uploaded"); |
607 | ||
e46b8fb1 | 608 | return SR_OK; |
f6564c8d HE |
609 | } |
610 | ||
25a0f108 | 611 | static int hw_dev_open(struct sr_dev_inst *sdi) |
f6564c8d | 612 | { |
ea9cfed7 | 613 | struct context *ctx; |
f6564c8d HE |
614 | int ret; |
615 | ||
ea9cfed7 | 616 | ctx = sdi->priv; |
99965709 | 617 | |
9ddb2a12 | 618 | /* Make sure it's an ASIX SIGMA. */ |
ea9cfed7 | 619 | if ((ret = ftdi_usb_open_desc(&ctx->ftdic, |
f6564c8d HE |
620 | USB_VENDOR, USB_PRODUCT, USB_DESCRIPTION, NULL)) < 0) { |
621 | ||
7b48d6e1 | 622 | sr_err("sigma: ftdi_usb_open failed: %s", |
ea9cfed7 | 623 | ftdi_get_error_string(&ctx->ftdic)); |
f6564c8d HE |
624 | |
625 | return 0; | |
626 | } | |
28a35d8a | 627 | |
5a2326a7 | 628 | sdi->status = SR_ST_ACTIVE; |
28a35d8a | 629 | |
e46b8fb1 | 630 | return SR_OK; |
f6564c8d HE |
631 | } |
632 | ||
6f4b1868 | 633 | static int set_samplerate(const struct sr_dev_inst *sdi, uint64_t samplerate) |
f6564c8d | 634 | { |
e8397563 | 635 | int i, ret; |
ea9cfed7 | 636 | struct context *ctx = sdi->priv; |
f6564c8d HE |
637 | |
638 | for (i = 0; supported_samplerates[i]; i++) { | |
639 | if (supported_samplerates[i] == samplerate) | |
640 | break; | |
641 | } | |
642 | if (supported_samplerates[i] == 0) | |
e46b8fb1 | 643 | return SR_ERR_SAMPLERATE; |
f6564c8d | 644 | |
59df0c77 | 645 | if (samplerate <= SR_MHZ(50)) { |
ea9cfed7 UH |
646 | ret = upload_firmware(0, ctx); |
647 | ctx->num_probes = 16; | |
e8397563 | 648 | } |
59df0c77 | 649 | if (samplerate == SR_MHZ(100)) { |
ea9cfed7 UH |
650 | ret = upload_firmware(1, ctx); |
651 | ctx->num_probes = 8; | |
f78898e9 | 652 | } |
59df0c77 | 653 | else if (samplerate == SR_MHZ(200)) { |
ea9cfed7 UH |
654 | ret = upload_firmware(2, ctx); |
655 | ctx->num_probes = 4; | |
f78898e9 | 656 | } |
f6564c8d | 657 | |
ea9cfed7 UH |
658 | ctx->cur_samplerate = samplerate; |
659 | ctx->period_ps = 1000000000000 / samplerate; | |
660 | ctx->samples_per_event = 16 / ctx->num_probes; | |
661 | ctx->state.state = SIGMA_IDLE; | |
f6564c8d | 662 | |
e8397563 | 663 | return ret; |
28a35d8a HE |
664 | } |
665 | ||
c53d793f HE |
666 | /* |
667 | * In 100 and 200 MHz mode, only a single pin rising/falling can be | |
668 | * set as trigger. In other modes, two rising/falling triggers can be set, | |
669 | * in addition to value/mask trigger for any number of probes. | |
670 | * | |
671 | * The Sigma supports complex triggers using boolean expressions, but this | |
672 | * has not been implemented yet. | |
673 | */ | |
6f4b1868 | 674 | static int configure_probes(const struct sr_dev_inst *sdi, const GSList *probes) |
57bbf56b | 675 | { |
ea9cfed7 | 676 | struct context *ctx = sdi->priv; |
1b79df2f JH |
677 | const struct sr_probe *probe; |
678 | const GSList *l; | |
57bbf56b | 679 | int trigger_set = 0; |
a42aec7f | 680 | int probebit; |
57bbf56b | 681 | |
ea9cfed7 | 682 | memset(&ctx->trigger, 0, sizeof(struct sigma_trigger)); |
eec5275e | 683 | |
57bbf56b | 684 | for (l = probes; l; l = l->next) { |
1afe8989 | 685 | probe = (struct sr_probe *)l->data; |
a42aec7f | 686 | probebit = 1 << (probe->index - 1); |
57bbf56b HE |
687 | |
688 | if (!probe->enabled || !probe->trigger) | |
689 | continue; | |
690 | ||
ea9cfed7 | 691 | if (ctx->cur_samplerate >= SR_MHZ(100)) { |
c53d793f | 692 | /* Fast trigger support. */ |
ee492173 | 693 | if (trigger_set) { |
7b48d6e1 | 694 | sr_err("sigma: ASIX SIGMA only supports a single " |
133a37bf | 695 | "pin trigger in 100 and 200MHz mode."); |
e46b8fb1 | 696 | return SR_ERR; |
ee492173 HE |
697 | } |
698 | if (probe->trigger[0] == 'f') | |
ea9cfed7 | 699 | ctx->trigger.fallingmask |= probebit; |
ee492173 | 700 | else if (probe->trigger[0] == 'r') |
ea9cfed7 | 701 | ctx->trigger.risingmask |= probebit; |
ee492173 | 702 | else { |
7b48d6e1 | 703 | sr_err("sigma: ASIX SIGMA only supports " |
133a37bf UH |
704 | "rising/falling trigger in 100 " |
705 | "and 200MHz mode."); | |
e46b8fb1 | 706 | return SR_ERR; |
ee492173 | 707 | } |
57bbf56b | 708 | |
c53d793f | 709 | ++trigger_set; |
ee492173 | 710 | } else { |
c53d793f HE |
711 | /* Simple trigger support (event). */ |
712 | if (probe->trigger[0] == '1') { | |
ea9cfed7 UH |
713 | ctx->trigger.simplevalue |= probebit; |
714 | ctx->trigger.simplemask |= probebit; | |
c53d793f HE |
715 | } |
716 | else if (probe->trigger[0] == '0') { | |
ea9cfed7 UH |
717 | ctx->trigger.simplevalue &= ~probebit; |
718 | ctx->trigger.simplemask |= probebit; | |
c53d793f HE |
719 | } |
720 | else if (probe->trigger[0] == 'f') { | |
ea9cfed7 | 721 | ctx->trigger.fallingmask |= probebit; |
c53d793f HE |
722 | ++trigger_set; |
723 | } | |
724 | else if (probe->trigger[0] == 'r') { | |
ea9cfed7 | 725 | ctx->trigger.risingmask |= probebit; |
c53d793f HE |
726 | ++trigger_set; |
727 | } | |
ee492173 | 728 | |
ea9cfed7 UH |
729 | /* |
730 | * Actually, Sigma supports 2 rising/falling triggers, | |
731 | * but they are ORed and the current trigger syntax | |
732 | * does not permit ORed triggers. | |
733 | */ | |
98b8cbc1 | 734 | if (trigger_set > 1) { |
7b48d6e1 UH |
735 | sr_err("sigma: ASIX SIGMA only supports 1 " |
736 | "rising/falling triggers."); | |
e46b8fb1 | 737 | return SR_ERR; |
ee492173 | 738 | } |
ee492173 | 739 | } |
5b5ea7c6 HE |
740 | |
741 | if (trigger_set) | |
ea9cfed7 | 742 | ctx->use_triggers = 1; |
57bbf56b HE |
743 | } |
744 | ||
e46b8fb1 | 745 | return SR_OK; |
57bbf56b HE |
746 | } |
747 | ||
25a0f108 | 748 | static int hw_dev_close(struct sr_dev_inst *sdi) |
28a35d8a | 749 | { |
ea9cfed7 | 750 | struct context *ctx; |
28a35d8a | 751 | |
ea9cfed7 | 752 | if (!(ctx = sdi->priv)) { |
340cfac0 | 753 | sr_err("sigma: %s: sdi->priv was NULL", __func__); |
0abee507 | 754 | return SR_ERR_BUG; |
9be9893e | 755 | } |
697785d1 UH |
756 | |
757 | /* TODO */ | |
758 | if (sdi->status == SR_ST_ACTIVE) | |
ea9cfed7 | 759 | ftdi_usb_close(&ctx->ftdic); |
697785d1 UH |
760 | |
761 | sdi->status = SR_ST_INACTIVE; | |
762 | ||
763 | return SR_OK; | |
28a35d8a HE |
764 | } |
765 | ||
57ab7d9f | 766 | static int hw_cleanup(void) |
28a35d8a | 767 | { |
99965709 | 768 | |
0448d110 | 769 | clear_instances(); |
57ab7d9f | 770 | |
0448d110 | 771 | return SR_OK; |
28a35d8a HE |
772 | } |
773 | ||
41479605 BV |
774 | static int hw_info_get(int info_id, const void **data, |
775 | const struct sr_dev_inst *sdi) | |
28a35d8a | 776 | { |
ea9cfed7 | 777 | struct context *ctx; |
99965709 | 778 | |
41479605 | 779 | switch (info_id) { |
1d9a8a5f | 780 | case SR_DI_INST: |
41479605 | 781 | *data = sdi; |
28a35d8a | 782 | break; |
b2b5445c BV |
783 | case SR_DI_HWCAPS: |
784 | *data = hwcaps; | |
785 | break; | |
5a2326a7 | 786 | case SR_DI_NUM_PROBES: |
41479605 | 787 | *data = GINT_TO_POINTER(NUM_PROBES); |
464d12c7 KS |
788 | break; |
789 | case SR_DI_PROBE_NAMES: | |
41479605 | 790 | *data = probe_names; |
28a35d8a | 791 | break; |
5a2326a7 | 792 | case SR_DI_SAMPLERATES: |
41479605 | 793 | *data = &samplerates; |
28a35d8a | 794 | break; |
5a2326a7 | 795 | case SR_DI_TRIGGER_TYPES: |
41479605 | 796 | *data = (char *)TRIGGER_TYPES; |
28a35d8a | 797 | break; |
5a2326a7 | 798 | case SR_DI_CUR_SAMPLERATE: |
41479605 BV |
799 | if (sdi) { |
800 | ctx = sdi->priv; | |
801 | *data = &ctx->cur_samplerate; | |
802 | } else | |
803 | return SR_ERR; | |
28a35d8a | 804 | break; |
d7bbecfd BV |
805 | default: |
806 | return SR_ERR_ARG; | |
28a35d8a HE |
807 | } |
808 | ||
41479605 | 809 | return SR_OK; |
28a35d8a HE |
810 | } |
811 | ||
6f4b1868 BV |
812 | static int hw_dev_config_set(const struct sr_dev_inst *sdi, int hwcap, |
813 | const void *value) | |
28a35d8a | 814 | { |
ea9cfed7 | 815 | struct context *ctx; |
28a35d8a | 816 | int ret; |
f6564c8d | 817 | |
ea9cfed7 | 818 | ctx = sdi->priv; |
99965709 | 819 | |
ffedd0bf | 820 | if (hwcap == SR_HWCAP_SAMPLERATE) { |
1b79df2f | 821 | ret = set_samplerate(sdi, *(const uint64_t *)value); |
ffedd0bf | 822 | } else if (hwcap == SR_HWCAP_PROBECONFIG) { |
99965709 | 823 | ret = configure_probes(sdi, value); |
ffedd0bf | 824 | } else if (hwcap == SR_HWCAP_LIMIT_MSEC) { |
1b79df2f | 825 | ctx->limit_msec = *(const uint64_t *)value; |
ea9cfed7 | 826 | if (ctx->limit_msec > 0) |
e46b8fb1 | 827 | ret = SR_OK; |
94ba4bd6 | 828 | else |
e46b8fb1 | 829 | ret = SR_ERR; |
ffedd0bf | 830 | } else if (hwcap == SR_HWCAP_CAPTURE_RATIO) { |
1b79df2f | 831 | ctx->capture_ratio = *(const uint64_t *)value; |
ea9cfed7 | 832 | if (ctx->capture_ratio < 0 || ctx->capture_ratio > 100) |
e46b8fb1 | 833 | ret = SR_ERR; |
94ba4bd6 | 834 | else |
e46b8fb1 | 835 | ret = SR_OK; |
28a35d8a | 836 | } else { |
e46b8fb1 | 837 | ret = SR_ERR; |
28a35d8a HE |
838 | } |
839 | ||
840 | return ret; | |
841 | } | |
842 | ||
36b1c8e6 HE |
843 | /* Software trigger to determine exact trigger position. */ |
844 | static int get_trigger_offset(uint16_t *samples, uint16_t last_sample, | |
845 | struct sigma_trigger *t) | |
846 | { | |
847 | int i; | |
848 | ||
849 | for (i = 0; i < 8; ++i) { | |
850 | if (i > 0) | |
851 | last_sample = samples[i-1]; | |
852 | ||
853 | /* Simple triggers. */ | |
854 | if ((samples[i] & t->simplemask) != t->simplevalue) | |
855 | continue; | |
856 | ||
857 | /* Rising edge. */ | |
858 | if ((last_sample & t->risingmask) != 0 || (samples[i] & | |
859 | t->risingmask) != t->risingmask) | |
860 | continue; | |
861 | ||
862 | /* Falling edge. */ | |
bdfc7a89 HE |
863 | if ((last_sample & t->fallingmask) != t->fallingmask || |
864 | (samples[i] & t->fallingmask) != 0) | |
36b1c8e6 HE |
865 | continue; |
866 | ||
867 | break; | |
868 | } | |
869 | ||
870 | /* If we did not match, return original trigger pos. */ | |
871 | return i & 0x7; | |
872 | } | |
873 | ||
28a35d8a | 874 | /* |
fefa1800 UH |
875 | * Decode chunk of 1024 bytes, 64 clusters, 7 events per cluster. |
876 | * Each event is 20ns apart, and can contain multiple samples. | |
f78898e9 HE |
877 | * |
878 | * For 200 MHz, events contain 4 samples for each channel, spread 5 ns apart. | |
879 | * For 100 MHz, events contain 2 samples for each channel, spread 10 ns apart. | |
880 | * For 50 MHz and below, events contain one sample for each channel, | |
881 | * spread 20 ns apart. | |
28a35d8a HE |
882 | */ |
883 | static int decode_chunk_ts(uint8_t *buf, uint16_t *lastts, | |
88c51afe | 884 | uint16_t *lastsample, int triggerpos, |
3cd3a20b | 885 | uint16_t limit_chunk, void *cb_data) |
28a35d8a | 886 | { |
3cd3a20b | 887 | struct sr_dev_inst *sdi = cb_data; |
ea9cfed7 | 888 | struct context *ctx = sdi->priv; |
fefa1800 | 889 | uint16_t tsdiff, ts; |
ea9cfed7 | 890 | uint16_t samples[65536 * ctx->samples_per_event]; |
b9c735a2 | 891 | struct sr_datafeed_packet packet; |
9c939c51 | 892 | struct sr_datafeed_logic logic; |
f78898e9 | 893 | int i, j, k, l, numpad, tosend; |
fefa1800 | 894 | size_t n = 0, sent = 0; |
ea9cfed7 | 895 | int clustersize = EVENTS_PER_CLUSTER * ctx->samples_per_event; |
fefa1800 | 896 | uint16_t *event; |
f78898e9 | 897 | uint16_t cur_sample; |
57bbf56b | 898 | int triggerts = -1; |
ee492173 | 899 | |
4ae1f451 | 900 | /* Check if trigger is in this chunk. */ |
ee492173 | 901 | if (triggerpos != -1) { |
ea9cfed7 | 902 | if (ctx->cur_samplerate <= SR_MHZ(50)) |
36b1c8e6 | 903 | triggerpos -= EVENTS_PER_CLUSTER - 1; |
ee492173 HE |
904 | |
905 | if (triggerpos < 0) | |
906 | triggerpos = 0; | |
57bbf56b | 907 | |
ee492173 HE |
908 | /* Find in which cluster the trigger occured. */ |
909 | triggerts = triggerpos / 7; | |
910 | } | |
28a35d8a | 911 | |
eec5275e | 912 | /* For each ts. */ |
28a35d8a | 913 | for (i = 0; i < 64; ++i) { |
fefa1800 | 914 | ts = *(uint16_t *) &buf[i * 16]; |
28a35d8a HE |
915 | tsdiff = ts - *lastts; |
916 | *lastts = ts; | |
917 | ||
88c51afe HE |
918 | /* Decode partial chunk. */ |
919 | if (limit_chunk && ts > limit_chunk) | |
e46b8fb1 | 920 | return SR_OK; |
88c51afe | 921 | |
fefa1800 | 922 | /* Pad last sample up to current point. */ |
ea9cfed7 | 923 | numpad = tsdiff * ctx->samples_per_event - clustersize; |
28a35d8a | 924 | if (numpad > 0) { |
f78898e9 HE |
925 | for (j = 0; j < numpad; ++j) |
926 | samples[j] = *lastsample; | |
927 | ||
928 | n = numpad; | |
28a35d8a HE |
929 | } |
930 | ||
57bbf56b HE |
931 | /* Send samples between previous and this timestamp to sigrok. */ |
932 | sent = 0; | |
933 | while (sent < n) { | |
934 | tosend = MIN(2048, n - sent); | |
935 | ||
5a2326a7 | 936 | packet.type = SR_DF_LOGIC; |
9c939c51 BV |
937 | packet.payload = &logic; |
938 | logic.length = tosend * sizeof(uint16_t); | |
939 | logic.unitsize = 2; | |
940 | logic.data = samples + sent; | |
3cd3a20b | 941 | sr_session_send(ctx->session_dev_id, &packet); |
28a35d8a | 942 | |
57bbf56b HE |
943 | sent += tosend; |
944 | } | |
945 | n = 0; | |
946 | ||
947 | event = (uint16_t *) &buf[i * 16 + 2]; | |
f78898e9 HE |
948 | cur_sample = 0; |
949 | ||
950 | /* For each event in cluster. */ | |
28a35d8a | 951 | for (j = 0; j < 7; ++j) { |
f78898e9 HE |
952 | |
953 | /* For each sample in event. */ | |
ea9cfed7 | 954 | for (k = 0; k < ctx->samples_per_event; ++k) { |
f78898e9 HE |
955 | cur_sample = 0; |
956 | ||
957 | /* For each probe. */ | |
ea9cfed7 | 958 | for (l = 0; l < ctx->num_probes; ++l) |
edca2c5c | 959 | cur_sample |= (!!(event[j] & (1 << (l * |
ea9cfed7 | 960 | ctx->samples_per_event + k)))) << l; |
f78898e9 HE |
961 | |
962 | samples[n++] = cur_sample; | |
28a35d8a HE |
963 | } |
964 | } | |
965 | ||
eec5275e | 966 | /* Send data up to trigger point (if triggered). */ |
fefa1800 | 967 | sent = 0; |
57bbf56b HE |
968 | if (i == triggerts) { |
969 | /* | |
36b1c8e6 HE |
970 | * Trigger is not always accurate to sample because of |
971 | * pipeline delay. However, it always triggers before | |
972 | * the actual event. We therefore look at the next | |
973 | * samples to pinpoint the exact position of the trigger. | |
57bbf56b | 974 | */ |
bdfc7a89 | 975 | tosend = get_trigger_offset(samples, *lastsample, |
ea9cfed7 | 976 | &ctx->trigger); |
57bbf56b HE |
977 | |
978 | if (tosend > 0) { | |
5a2326a7 | 979 | packet.type = SR_DF_LOGIC; |
9c939c51 BV |
980 | packet.payload = &logic; |
981 | logic.length = tosend * sizeof(uint16_t); | |
982 | logic.unitsize = 2; | |
983 | logic.data = samples; | |
3cd3a20b | 984 | sr_session_send(ctx->session_dev_id, &packet); |
57bbf56b HE |
985 | |
986 | sent += tosend; | |
987 | } | |
28a35d8a | 988 | |
5b5ea7c6 | 989 | /* Only send trigger if explicitly enabled. */ |
ea9cfed7 | 990 | if (ctx->use_triggers) { |
5a2326a7 | 991 | packet.type = SR_DF_TRIGGER; |
3cd3a20b | 992 | sr_session_send(ctx->session_dev_id, &packet); |
5b5ea7c6 | 993 | } |
28a35d8a | 994 | } |
57bbf56b | 995 | |
eec5275e | 996 | /* Send rest of the chunk to sigrok. */ |
57bbf56b HE |
997 | tosend = n - sent; |
998 | ||
abda62ce | 999 | if (tosend > 0) { |
5a2326a7 | 1000 | packet.type = SR_DF_LOGIC; |
9c939c51 BV |
1001 | packet.payload = &logic; |
1002 | logic.length = tosend * sizeof(uint16_t); | |
1003 | logic.unitsize = 2; | |
1004 | logic.data = samples + sent; | |
3cd3a20b | 1005 | sr_session_send(ctx->session_dev_id, &packet); |
abda62ce | 1006 | } |
ee492173 HE |
1007 | |
1008 | *lastsample = samples[n - 1]; | |
28a35d8a HE |
1009 | } |
1010 | ||
e46b8fb1 | 1011 | return SR_OK; |
28a35d8a HE |
1012 | } |
1013 | ||
1f9813eb | 1014 | static int receive_data(int fd, int revents, void *cb_data) |
28a35d8a | 1015 | { |
1f9813eb | 1016 | struct sr_dev_inst *sdi = cb_data; |
ea9cfed7 | 1017 | struct context *ctx = sdi->priv; |
b9c735a2 | 1018 | struct sr_datafeed_packet packet; |
28a35d8a HE |
1019 | const int chunks_per_read = 32; |
1020 | unsigned char buf[chunks_per_read * CHUNK_SIZE]; | |
6aac7737 | 1021 | int bufsz, numchunks, i, newchunks; |
94ba4bd6 | 1022 | uint64_t running_msec; |
28a35d8a | 1023 | struct timeval tv; |
28a35d8a | 1024 | |
cb93f8a9 UH |
1025 | /* Avoid compiler warnings. */ |
1026 | (void)fd; | |
1027 | (void)revents; | |
28a35d8a | 1028 | |
805919b0 HE |
1029 | /* Get the current position. */ |
1030 | sigma_read_pos(&ctx->state.stoppos, &ctx->state.triggerpos, ctx); | |
1031 | ||
ea9cfed7 | 1032 | numchunks = (ctx->state.stoppos + 511) / 512; |
28a35d8a | 1033 | |
ea9cfed7 | 1034 | if (ctx->state.state == SIGMA_IDLE) |
805919b0 | 1035 | return TRUE; |
28a35d8a | 1036 | |
ea9cfed7 | 1037 | if (ctx->state.state == SIGMA_CAPTURE) { |
6aac7737 HE |
1038 | /* Check if the timer has expired, or memory is full. */ |
1039 | gettimeofday(&tv, 0); | |
ea9cfed7 UH |
1040 | running_msec = (tv.tv_sec - ctx->start_tv.tv_sec) * 1000 + |
1041 | (tv.tv_usec - ctx->start_tv.tv_usec) / 1000; | |
28a35d8a | 1042 | |
ea9cfed7 | 1043 | if (running_msec < ctx->limit_msec && numchunks < 32767) |
805919b0 | 1044 | return TRUE; /* While capturing... */ |
e3fff420 | 1045 | else |
3ffb6964 | 1046 | hw_dev_acquisition_stop(sdi, sdi); |
6aac7737 | 1047 | |
ea9cfed7 UH |
1048 | } else if (ctx->state.state == SIGMA_DOWNLOAD) { |
1049 | if (ctx->state.chunks_downloaded >= numchunks) { | |
6aac7737 | 1050 | /* End of samples. */ |
5a2326a7 | 1051 | packet.type = SR_DF_END; |
3cd3a20b | 1052 | sr_session_send(ctx->session_dev_id, &packet); |
6aac7737 | 1053 | |
ea9cfed7 | 1054 | ctx->state.state = SIGMA_IDLE; |
f78898e9 | 1055 | |
6aac7737 HE |
1056 | return TRUE; |
1057 | } | |
1058 | ||
1059 | newchunks = MIN(chunks_per_read, | |
ea9cfed7 | 1060 | numchunks - ctx->state.chunks_downloaded); |
28a35d8a | 1061 | |
7b48d6e1 | 1062 | sr_info("sigma: Downloading sample data: %.0f %%", |
ea9cfed7 | 1063 | 100.0 * ctx->state.chunks_downloaded / numchunks); |
28a35d8a | 1064 | |
ea9cfed7 UH |
1065 | bufsz = sigma_read_dram(ctx->state.chunks_downloaded, |
1066 | newchunks, buf, ctx); | |
719c5a93 UH |
1067 | /* TODO: Check bufsz. For now, just avoid compiler warnings. */ |
1068 | (void)bufsz; | |
28a35d8a | 1069 | |
fefa1800 | 1070 | /* Find first ts. */ |
ea9cfed7 UH |
1071 | if (ctx->state.chunks_downloaded == 0) { |
1072 | ctx->state.lastts = *(uint16_t *) buf - 1; | |
1073 | ctx->state.lastsample = 0; | |
6aac7737 | 1074 | } |
28a35d8a | 1075 | |
fefa1800 | 1076 | /* Decode chunks and send them to sigrok. */ |
28a35d8a | 1077 | for (i = 0; i < newchunks; ++i) { |
88c51afe HE |
1078 | int limit_chunk = 0; |
1079 | ||
1080 | /* The last chunk may potentially be only in part. */ | |
ea9cfed7 | 1081 | if (ctx->state.chunks_downloaded == numchunks - 1) { |
88c51afe | 1082 | /* Find the last valid timestamp */ |
ea9cfed7 | 1083 | limit_chunk = ctx->state.stoppos % 512 + ctx->state.lastts; |
88c51afe HE |
1084 | } |
1085 | ||
ea9cfed7 | 1086 | if (ctx->state.chunks_downloaded + i == ctx->state.triggerchunk) |
57bbf56b | 1087 | decode_chunk_ts(buf + (i * CHUNK_SIZE), |
ea9cfed7 UH |
1088 | &ctx->state.lastts, |
1089 | &ctx->state.lastsample, | |
1090 | ctx->state.triggerpos & 0x1ff, | |
1f9813eb | 1091 | limit_chunk, sdi); |
57bbf56b HE |
1092 | else |
1093 | decode_chunk_ts(buf + (i * CHUNK_SIZE), | |
ea9cfed7 UH |
1094 | &ctx->state.lastts, |
1095 | &ctx->state.lastsample, | |
1f9813eb | 1096 | -1, limit_chunk, sdi); |
28a35d8a | 1097 | |
ea9cfed7 | 1098 | ++ctx->state.chunks_downloaded; |
88c51afe | 1099 | } |
28a35d8a HE |
1100 | } |
1101 | ||
28a35d8a HE |
1102 | return TRUE; |
1103 | } | |
1104 | ||
c53d793f HE |
1105 | /* Build a LUT entry used by the trigger functions. */ |
1106 | static void build_lut_entry(uint16_t value, uint16_t mask, uint16_t *entry) | |
ee492173 HE |
1107 | { |
1108 | int i, j, k, bit; | |
1109 | ||
f758d074 | 1110 | /* For each quad probe. */ |
ee492173 | 1111 | for (i = 0; i < 4; ++i) { |
c53d793f | 1112 | entry[i] = 0xffff; |
ee492173 | 1113 | |
f758d074 | 1114 | /* For each bit in LUT. */ |
ee492173 HE |
1115 | for (j = 0; j < 16; ++j) |
1116 | ||
f758d074 | 1117 | /* For each probe in quad. */ |
ee492173 HE |
1118 | for (k = 0; k < 4; ++k) { |
1119 | bit = 1 << (i * 4 + k); | |
1120 | ||
c53d793f HE |
1121 | /* Set bit in entry */ |
1122 | if ((mask & bit) && | |
1123 | ((!(value & bit)) != | |
4ae1f451 | 1124 | (!(j & (1 << k))))) |
c53d793f | 1125 | entry[i] &= ~(1 << j); |
ee492173 HE |
1126 | } |
1127 | } | |
c53d793f | 1128 | } |
ee492173 | 1129 | |
c53d793f HE |
1130 | /* Add a logical function to LUT mask. */ |
1131 | static void add_trigger_function(enum triggerop oper, enum triggerfunc func, | |
1132 | int index, int neg, uint16_t *mask) | |
1133 | { | |
1134 | int i, j; | |
1135 | int x[2][2], tmp, a, b, aset, bset, rset; | |
1136 | ||
1137 | memset(x, 0, 4 * sizeof(int)); | |
1138 | ||
1139 | /* Trigger detect condition. */ | |
1140 | switch (oper) { | |
1141 | case OP_LEVEL: | |
1142 | x[0][1] = 1; | |
1143 | x[1][1] = 1; | |
1144 | break; | |
1145 | case OP_NOT: | |
1146 | x[0][0] = 1; | |
1147 | x[1][0] = 1; | |
1148 | break; | |
1149 | case OP_RISE: | |
1150 | x[0][1] = 1; | |
1151 | break; | |
1152 | case OP_FALL: | |
1153 | x[1][0] = 1; | |
1154 | break; | |
1155 | case OP_RISEFALL: | |
1156 | x[0][1] = 1; | |
1157 | x[1][0] = 1; | |
1158 | break; | |
1159 | case OP_NOTRISE: | |
1160 | x[1][1] = 1; | |
1161 | x[0][0] = 1; | |
1162 | x[1][0] = 1; | |
1163 | break; | |
1164 | case OP_NOTFALL: | |
1165 | x[1][1] = 1; | |
1166 | x[0][0] = 1; | |
1167 | x[0][1] = 1; | |
1168 | break; | |
1169 | case OP_NOTRISEFALL: | |
1170 | x[1][1] = 1; | |
1171 | x[0][0] = 1; | |
1172 | break; | |
1173 | } | |
1174 | ||
1175 | /* Transpose if neg is set. */ | |
1176 | if (neg) { | |
ea9cfed7 | 1177 | for (i = 0; i < 2; ++i) { |
c53d793f HE |
1178 | for (j = 0; j < 2; ++j) { |
1179 | tmp = x[i][j]; | |
1180 | x[i][j] = x[1-i][1-j]; | |
1181 | x[1-i][1-j] = tmp; | |
1182 | } | |
ea9cfed7 | 1183 | } |
c53d793f HE |
1184 | } |
1185 | ||
1186 | /* Update mask with function. */ | |
1187 | for (i = 0; i < 16; ++i) { | |
1188 | a = (i >> (2 * index + 0)) & 1; | |
1189 | b = (i >> (2 * index + 1)) & 1; | |
1190 | ||
1191 | aset = (*mask >> i) & 1; | |
1192 | bset = x[b][a]; | |
1193 | ||
1194 | if (func == FUNC_AND || func == FUNC_NAND) | |
1195 | rset = aset & bset; | |
1196 | else if (func == FUNC_OR || func == FUNC_NOR) | |
1197 | rset = aset | bset; | |
1198 | else if (func == FUNC_XOR || func == FUNC_NXOR) | |
1199 | rset = aset ^ bset; | |
1200 | ||
1201 | if (func == FUNC_NAND || func == FUNC_NOR || func == FUNC_NXOR) | |
1202 | rset = !rset; | |
1203 | ||
1204 | *mask &= ~(1 << i); | |
1205 | ||
1206 | if (rset) | |
1207 | *mask |= 1 << i; | |
1208 | } | |
1209 | } | |
1210 | ||
1211 | /* | |
1212 | * Build trigger LUTs used by 50 MHz and lower sample rates for supporting | |
1213 | * simple pin change and state triggers. Only two transitions (rise/fall) can be | |
1214 | * set at any time, but a full mask and value can be set (0/1). | |
1215 | */ | |
ea9cfed7 | 1216 | static int build_basic_trigger(struct triggerlut *lut, struct context *ctx) |
c53d793f HE |
1217 | { |
1218 | int i,j; | |
4ae1f451 | 1219 | uint16_t masks[2] = { 0, 0 }; |
c53d793f HE |
1220 | |
1221 | memset(lut, 0, sizeof(struct triggerlut)); | |
1222 | ||
1223 | /* Contant for simple triggers. */ | |
1224 | lut->m4 = 0xa000; | |
1225 | ||
1226 | /* Value/mask trigger support. */ | |
ea9cfed7 | 1227 | build_lut_entry(ctx->trigger.simplevalue, ctx->trigger.simplemask, |
99965709 | 1228 | lut->m2d); |
c53d793f HE |
1229 | |
1230 | /* Rise/fall trigger support. */ | |
1231 | for (i = 0, j = 0; i < 16; ++i) { | |
ea9cfed7 UH |
1232 | if (ctx->trigger.risingmask & (1 << i) || |
1233 | ctx->trigger.fallingmask & (1 << i)) | |
c53d793f HE |
1234 | masks[j++] = 1 << i; |
1235 | } | |
1236 | ||
1237 | build_lut_entry(masks[0], masks[0], lut->m0d); | |
1238 | build_lut_entry(masks[1], masks[1], lut->m1d); | |
1239 | ||
1240 | /* Add glue logic */ | |
1241 | if (masks[0] || masks[1]) { | |
1242 | /* Transition trigger. */ | |
ea9cfed7 | 1243 | if (masks[0] & ctx->trigger.risingmask) |
c53d793f | 1244 | add_trigger_function(OP_RISE, FUNC_OR, 0, 0, &lut->m3); |
ea9cfed7 | 1245 | if (masks[0] & ctx->trigger.fallingmask) |
c53d793f | 1246 | add_trigger_function(OP_FALL, FUNC_OR, 0, 0, &lut->m3); |
ea9cfed7 | 1247 | if (masks[1] & ctx->trigger.risingmask) |
c53d793f | 1248 | add_trigger_function(OP_RISE, FUNC_OR, 1, 0, &lut->m3); |
ea9cfed7 | 1249 | if (masks[1] & ctx->trigger.fallingmask) |
c53d793f HE |
1250 | add_trigger_function(OP_FALL, FUNC_OR, 1, 0, &lut->m3); |
1251 | } else { | |
1252 | /* Only value/mask trigger. */ | |
1253 | lut->m3 = 0xffff; | |
1254 | } | |
ee492173 | 1255 | |
c53d793f | 1256 | /* Triggertype: event. */ |
ee492173 HE |
1257 | lut->params.selres = 3; |
1258 | ||
e46b8fb1 | 1259 | return SR_OK; |
ee492173 HE |
1260 | } |
1261 | ||
3ffb6964 BV |
1262 | static int hw_dev_acquisition_start(const struct sr_dev_inst *sdi, |
1263 | void *cb_data) | |
28a35d8a | 1264 | { |
ea9cfed7 | 1265 | struct context *ctx; |
3c36c403 HE |
1266 | struct sr_datafeed_packet *packet; |
1267 | struct sr_datafeed_header *header; | |
f366e86c | 1268 | struct sr_datafeed_meta_logic meta; |
9ddb2a12 | 1269 | struct clockselect_50 clockselect; |
82957b65 | 1270 | int frac, triggerpin, ret; |
57bbf56b HE |
1271 | uint8_t triggerselect; |
1272 | struct triggerinout triggerinout_conf; | |
ee492173 | 1273 | struct triggerlut lut; |
28a35d8a | 1274 | |
ea9cfed7 | 1275 | ctx = sdi->priv; |
28a35d8a | 1276 | |
ea9cfed7 UH |
1277 | /* If the samplerate has not been set, default to 200 kHz. */ |
1278 | if (ctx->cur_firmware == -1) { | |
82957b65 UH |
1279 | if ((ret = set_samplerate(sdi, SR_KHZ(200))) != SR_OK) |
1280 | return ret; | |
1281 | } | |
e8397563 | 1282 | |
eec5275e | 1283 | /* Enter trigger programming mode. */ |
ea9cfed7 | 1284 | sigma_set_register(WRITE_TRIGGER_SELECT1, 0x20, ctx); |
28a35d8a | 1285 | |
eec5275e | 1286 | /* 100 and 200 MHz mode. */ |
ea9cfed7 UH |
1287 | if (ctx->cur_samplerate >= SR_MHZ(100)) { |
1288 | sigma_set_register(WRITE_TRIGGER_SELECT1, 0x81, ctx); | |
57bbf56b | 1289 | |
a42aec7f HE |
1290 | /* Find which pin to trigger on from mask. */ |
1291 | for (triggerpin = 0; triggerpin < 8; ++triggerpin) | |
ea9cfed7 | 1292 | if ((ctx->trigger.risingmask | ctx->trigger.fallingmask) & |
a42aec7f HE |
1293 | (1 << triggerpin)) |
1294 | break; | |
1295 | ||
1296 | /* Set trigger pin and light LED on trigger. */ | |
1297 | triggerselect = (1 << LEDSEL1) | (triggerpin & 0x7); | |
1298 | ||
1299 | /* Default rising edge. */ | |
ea9cfed7 | 1300 | if (ctx->trigger.fallingmask) |
a42aec7f | 1301 | triggerselect |= 1 << 3; |
57bbf56b | 1302 | |
eec5275e | 1303 | /* All other modes. */ |
ea9cfed7 UH |
1304 | } else if (ctx->cur_samplerate <= SR_MHZ(50)) { |
1305 | build_basic_trigger(&lut, ctx); | |
ee492173 | 1306 | |
ea9cfed7 | 1307 | sigma_write_trigger_lut(&lut, ctx); |
57bbf56b HE |
1308 | |
1309 | triggerselect = (1 << LEDSEL1) | (1 << LEDSEL0); | |
1310 | } | |
1311 | ||
eec5275e | 1312 | /* Setup trigger in and out pins to default values. */ |
57bbf56b HE |
1313 | memset(&triggerinout_conf, 0, sizeof(struct triggerinout)); |
1314 | triggerinout_conf.trgout_bytrigger = 1; | |
1315 | triggerinout_conf.trgout_enable = 1; | |
1316 | ||
28a35d8a | 1317 | sigma_write_register(WRITE_TRIGGER_OPTION, |
57bbf56b | 1318 | (uint8_t *) &triggerinout_conf, |
ea9cfed7 | 1319 | sizeof(struct triggerinout), ctx); |
28a35d8a | 1320 | |
eec5275e | 1321 | /* Go back to normal mode. */ |
ea9cfed7 | 1322 | sigma_set_register(WRITE_TRIGGER_SELECT1, triggerselect, ctx); |
28a35d8a | 1323 | |
edca2c5c | 1324 | /* Set clock select register. */ |
ea9cfed7 | 1325 | if (ctx->cur_samplerate == SR_MHZ(200)) |
edca2c5c | 1326 | /* Enable 4 probes. */ |
ea9cfed7 UH |
1327 | sigma_set_register(WRITE_CLOCK_SELECT, 0xf0, ctx); |
1328 | else if (ctx->cur_samplerate == SR_MHZ(100)) | |
edca2c5c | 1329 | /* Enable 8 probes. */ |
ea9cfed7 | 1330 | sigma_set_register(WRITE_CLOCK_SELECT, 0x00, ctx); |
edca2c5c HE |
1331 | else { |
1332 | /* | |
9ddb2a12 | 1333 | * 50 MHz mode (or fraction thereof). Any fraction down to |
eec5275e | 1334 | * 50 MHz / 256 can be used, but is not supported by sigrok API. |
edca2c5c | 1335 | */ |
ea9cfed7 | 1336 | frac = SR_MHZ(50) / ctx->cur_samplerate - 1; |
edca2c5c | 1337 | |
9ddb2a12 UH |
1338 | clockselect.async = 0; |
1339 | clockselect.fraction = frac; | |
1340 | clockselect.disabled_probes = 0; | |
edca2c5c HE |
1341 | |
1342 | sigma_write_register(WRITE_CLOCK_SELECT, | |
9ddb2a12 | 1343 | (uint8_t *) &clockselect, |
ea9cfed7 | 1344 | sizeof(clockselect), ctx); |
edca2c5c HE |
1345 | } |
1346 | ||
fefa1800 | 1347 | /* Setup maximum post trigger time. */ |
99965709 | 1348 | sigma_set_register(WRITE_POST_TRIGGER, |
6352d030 | 1349 | (ctx->capture_ratio * 255) / 100, ctx); |
28a35d8a | 1350 | |
eec5275e | 1351 | /* Start acqusition. */ |
ea9cfed7 UH |
1352 | gettimeofday(&ctx->start_tv, 0); |
1353 | sigma_set_register(WRITE_MODE, 0x0d, ctx); | |
99965709 | 1354 | |
3cd3a20b | 1355 | ctx->session_dev_id = cb_data; |
28a35d8a | 1356 | |
3c36c403 HE |
1357 | if (!(packet = g_try_malloc(sizeof(struct sr_datafeed_packet)))) { |
1358 | sr_err("sigma: %s: packet malloc failed.", __func__); | |
1359 | return SR_ERR_MALLOC; | |
1360 | } | |
1361 | ||
1362 | if (!(header = g_try_malloc(sizeof(struct sr_datafeed_header)))) { | |
1363 | sr_err("sigma: %s: header malloc failed.", __func__); | |
1364 | return SR_ERR_MALLOC; | |
1365 | } | |
28a35d8a | 1366 | |
3c36c403 HE |
1367 | /* Send header packet to the session bus. */ |
1368 | packet->type = SR_DF_HEADER; | |
1369 | packet->payload = header; | |
1370 | header->feed_version = 1; | |
1371 | gettimeofday(&header->starttime, NULL); | |
3c36c403 | 1372 | sr_session_send(ctx->session_dev_id, packet); |
f366e86c BV |
1373 | |
1374 | /* Send metadata about the SR_DF_LOGIC packets to come. */ | |
1375 | packet->type = SR_DF_META_LOGIC; | |
1376 | packet->payload = &meta; | |
1377 | meta.samplerate = ctx->cur_samplerate; | |
1378 | meta.num_probes = ctx->num_probes; | |
1379 | sr_session_send(ctx->session_dev_id, packet); | |
1380 | ||
1381 | /* Add capture source. */ | |
3ffb6964 | 1382 | sr_source_add(0, G_IO_IN, 10, receive_data, (void *)sdi); |
f366e86c | 1383 | |
3c36c403 HE |
1384 | g_free(header); |
1385 | g_free(packet); | |
1386 | ||
ea9cfed7 | 1387 | ctx->state.state = SIGMA_CAPTURE; |
6aac7737 | 1388 | |
e46b8fb1 | 1389 | return SR_OK; |
28a35d8a HE |
1390 | } |
1391 | ||
3ffb6964 BV |
1392 | static int hw_dev_acquisition_stop(const struct sr_dev_inst *sdi, |
1393 | void *cb_data) | |
28a35d8a | 1394 | { |
ea9cfed7 | 1395 | struct context *ctx; |
6aac7737 HE |
1396 | uint8_t modestatus; |
1397 | ||
cb93f8a9 | 1398 | /* Avoid compiler warnings. */ |
3cd3a20b | 1399 | (void)cb_data; |
28a35d8a | 1400 | |
ea9cfed7 | 1401 | if (!(ctx = sdi->priv)) { |
7b48d6e1 | 1402 | sr_err("sigma: %s: sdi->priv was NULL", __func__); |
3010f21c UH |
1403 | return SR_ERR_BUG; |
1404 | } | |
1405 | ||
fefa1800 | 1406 | /* Stop acquisition. */ |
ea9cfed7 | 1407 | sigma_set_register(WRITE_MODE, 0x11, ctx); |
28a35d8a | 1408 | |
6aac7737 | 1409 | /* Set SDRAM Read Enable. */ |
ea9cfed7 | 1410 | sigma_set_register(WRITE_MODE, 0x02, ctx); |
6aac7737 HE |
1411 | |
1412 | /* Get the current position. */ | |
ea9cfed7 | 1413 | sigma_read_pos(&ctx->state.stoppos, &ctx->state.triggerpos, ctx); |
6aac7737 HE |
1414 | |
1415 | /* Check if trigger has fired. */ | |
ea9cfed7 | 1416 | modestatus = sigma_get_register(READ_MODE, ctx); |
3010f21c | 1417 | if (modestatus & 0x20) |
ea9cfed7 | 1418 | ctx->state.triggerchunk = ctx->state.triggerpos / 512; |
3010f21c | 1419 | else |
ea9cfed7 | 1420 | ctx->state.triggerchunk = -1; |
6aac7737 | 1421 | |
ea9cfed7 | 1422 | ctx->state.chunks_downloaded = 0; |
6aac7737 | 1423 | |
ea9cfed7 | 1424 | ctx->state.state = SIGMA_DOWNLOAD; |
3010f21c UH |
1425 | |
1426 | return SR_OK; | |
28a35d8a HE |
1427 | } |
1428 | ||
c09f0b57 | 1429 | SR_PRIV struct sr_dev_driver asix_sigma_driver_info = { |
e519ba86 | 1430 | .name = "asix-sigma", |
6352d030 | 1431 | .longname = "ASIX SIGMA/SIGMA2", |
e519ba86 UH |
1432 | .api_version = 1, |
1433 | .init = hw_init, | |
1434 | .cleanup = hw_cleanup, | |
61136ea6 | 1435 | .scan = hw_scan, |
e7eb703f UH |
1436 | .dev_open = hw_dev_open, |
1437 | .dev_close = hw_dev_close, | |
41479605 | 1438 | .info_get = hw_info_get, |
a9a245b4 | 1439 | .dev_config_set = hw_dev_config_set, |
6b3dfec8 UH |
1440 | .dev_acquisition_start = hw_dev_acquisition_start, |
1441 | .dev_acquisition_stop = hw_dev_acquisition_stop, | |
ed300b9f | 1442 | .instances = NULL, |
28a35d8a | 1443 | }; |