]> sigrok.org Git - libsigrok.git/blame - src/hardware/scpi-pps/profiles.c
projects / libsigrok.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
scpi-pps: Support for the EEZ PSU series
[libsigrok.git] / src / hardware / scpi-pps / profiles.c
CommitLineData
d4eabea8
BV		 1/*
2 * This file is part of the libsigrok project.
3 *
4 * Copyright (C) 2014 Bert Vermeulen <bert@biot.com>
4ee1e2f3
AG		 5 * Copyright (C) 2015 Google, Inc.
6 * (Written by Alexandru Gagniuc <mrnuke@google.com> for Google, Inc.)
7e66bf05 7 * Copyright (C) 2017,2019 Frank Stettner <frank-stettner@gmx.net>
d4eabea8
BV		 8 *
9 * This program is free software: you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation, either version 3 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program. If not, see <http://www.gnu.org/licenses/>.
21 */
22
6ec6c43b 23#include <config.h>
22c18b03 24#include <string.h>
ba464a12 25#include <strings.h>
d4eabea8
BV		 26#include "protocol.h"
27
28#define CH_IDX(x) (1 << x)
6ed709fe 29#define FREQ_DC_ONLY {0, 0, 0, 0, 0}
49a468ed
FS		 30#define NO_OVP_LIMITS {0, 0, 0, 0, 0}
31#define NO_OCP_LIMITS {0, 0, 0, 0, 0}
d4eabea8 32
5c9e56c9
AG		 33/* Agilent/Keysight N5700A series */
34static const uint32_t agilent_n5700a_devopts[] = {
e91bb0a6 35 SR_CONF_CONTINUOUS,
88e4daa9
ML		 36 SR_CONF_LIMIT_SAMPLES | SR_CONF_GET | SR_CONF_SET,
37 SR_CONF_LIMIT_MSEC | SR_CONF_GET | SR_CONF_SET,
5c9e56c9
AG		 38};
39
40static const uint32_t agilent_n5700a_devopts_cg[] = {
41 SR_CONF_OVER_VOLTAGE_PROTECTION_THRESHOLD | SR_CONF_GET | SR_CONF_SET,
42 SR_CONF_OVER_CURRENT_PROTECTION_ENABLED | SR_CONF_GET | SR_CONF_SET,
43 SR_CONF_OVER_CURRENT_PROTECTION_THRESHOLD | SR_CONF_GET | SR_CONF_SET,
da005885
UH		 44 SR_CONF_VOLTAGE | SR_CONF_GET,
45 SR_CONF_VOLTAGE_TARGET | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
46 SR_CONF_CURRENT | SR_CONF_GET,
47 SR_CONF_ENABLED | SR_CONF_GET | SR_CONF_SET,
5c9e56c9
AG		 48};
49
6cc93128 50static const struct channel_group_spec agilent_n5700a_cg[] = {
f2bbcc33 51 { "1", CH_IDX(0), PPS_OVP | PPS_OCP, SR_MQFLAG_DC },
6cc93128
AG		 52};
53
8cb5affe 54static const struct channel_spec agilent_n5767a_ch[] = {
49a468ed 55 { "1", { 0, 60, 0.0072, 3, 4 }, { 0, 25, 0.003, 3, 4 }, { 0, 1500 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS },
5c9e56c9
AG		 56};
57
6cc93128 58static const struct channel_spec agilent_n5763a_ch[] = {
49a468ed 59 { "1", { 0, 12.5, 0.0015, 3, 4 }, { 0, 120, 0.0144, 3, 4 }, { 0, 1500 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS },
5c9e56c9
AG		 60};
61
62/*
63 * TODO: OVER_CURRENT_PROTECTION_ACTIVE status can be determined by the OC bit
562a3490 64 * in STAT:QUES:EVEN?, but this is not implemented.
5c9e56c9 65 */
8cb5affe 66static const struct scpi_command agilent_n5700a_cmd[] = {
5c9e56c9
AG		 67 { SCPI_CMD_REMOTE, "SYST:COMM:RLST REM" },
68 { SCPI_CMD_LOCAL, "SYST:COMM:RLST LOC" },
69 { SCPI_CMD_GET_MEAS_VOLTAGE, ":MEAS:VOLT?" },
70 { SCPI_CMD_GET_MEAS_CURRENT, "MEAS:CURR?" },
71 { SCPI_CMD_GET_VOLTAGE_TARGET, ":SOUR:VOLT?" },
72 { SCPI_CMD_SET_VOLTAGE_TARGET, ":SOUR:VOLT %.6f" },
73 { SCPI_CMD_GET_CURRENT_LIMIT, ":SOUR:CURR?" },
74 { SCPI_CMD_SET_CURRENT_LIMIT, ":SOUR:CURR %.6f" },
75 { SCPI_CMD_GET_OUTPUT_ENABLED, ":OUTP:STAT?" },
76 { SCPI_CMD_SET_OUTPUT_ENABLE, ":OUTP ON" },
77 { SCPI_CMD_SET_OUTPUT_DISABLE, ":OUTP OFF" },
78 { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_THRESHOLD, ":VOLT:PROT?" },
79 { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_THRESHOLD, ":VOLT:PROT %.6f" },
80 { SCPI_CMD_GET_OVER_CURRENT_PROTECTION_ENABLED, ":CURR:PROT:STAT?" },
81 { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_ENABLE, ":CURR:PROT:STAT ON?"},
82 { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_DISABLE, ":CURR:PROT:STAT OFF?"},
562a3490 83 /* Current limit (CC mode) and OCP are set using the same command. */
5c9e56c9
AG		 84 { SCPI_CMD_GET_OVER_CURRENT_PROTECTION_THRESHOLD, ":SOUR:CURR?" },
85 { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_THRESHOLD, ":SOUR:CURR %.6f" },
91ef511d 86 ALL_ZERO
5c9e56c9
AG		 87};
88
c3bfb959
MW		 89/* BK Precision 9130 series */
90static const uint32_t bk_9130_devopts[] = {
91 SR_CONF_CONTINUOUS,
92 SR_CONF_LIMIT_SAMPLES | SR_CONF_GET | SR_CONF_SET,
93 SR_CONF_LIMIT_MSEC | SR_CONF_GET | SR_CONF_SET,
94};
95
96static const uint32_t bk_9130_devopts_cg[] = {
97 SR_CONF_OVER_VOLTAGE_PROTECTION_THRESHOLD | SR_CONF_GET | SR_CONF_SET,
98 SR_CONF_VOLTAGE | SR_CONF_GET,
99 SR_CONF_VOLTAGE_TARGET | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
100 SR_CONF_CURRENT | SR_CONF_GET,
101 SR_CONF_CURRENT_LIMIT | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
102 SR_CONF_ENABLED | SR_CONF_GET | SR_CONF_SET,
103};
104
105static const struct channel_spec bk_9130_ch[] = {
106 { "1", { 0, 30, 0.001, 3, 3 }, { 0, 3, 0.001, 3, 3 }, { 0, 90, 0, 3, 3 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS },
107 { "2", { 0, 30, 0.001, 3, 3 }, { 0, 3, 0.001, 3, 3 }, { 0, 90, 0, 3, 3 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS },
108 { "3", { 0, 5, 0.001, 3, 3 }, { 0, 3, 0.001, 3, 3 }, { 0, 15, 0, 3, 3 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS },
109};
110
111static const struct channel_group_spec bk_9130_cg[] = {
f2bbcc33
FS		 112 { "1", CH_IDX(0), PPS_OVP, SR_MQFLAG_DC },
113 { "2", CH_IDX(1), PPS_OVP, SR_MQFLAG_DC },
114 { "3", CH_IDX(2), PPS_OVP, SR_MQFLAG_DC },
c3bfb959
MW		 115};
116
117static const struct scpi_command bk_9130_cmd[] = {
118 { SCPI_CMD_REMOTE, "SYST:REMOTE" },
119 { SCPI_CMD_LOCAL, "SYST:LOCAL" },
120 { SCPI_CMD_SELECT_CHANNEL, ":INST:NSEL %s" },
121 { SCPI_CMD_GET_MEAS_VOLTAGE, ":MEAS:VOLT?" },
122 { SCPI_CMD_GET_MEAS_CURRENT, ":MEAS:CURR?" },
123 { SCPI_CMD_GET_MEAS_POWER, ":MEAS:POWER?" },
124 { SCPI_CMD_GET_VOLTAGE_TARGET, ":SOUR:VOLT?" },
125 { SCPI_CMD_SET_VOLTAGE_TARGET, ":SOUR:VOLT %.6f" },
126 { SCPI_CMD_GET_CURRENT_LIMIT, ":SOUR:CURR?" },
127 { SCPI_CMD_SET_CURRENT_LIMIT, ":SOUR:CURR %.6f" },
128 { SCPI_CMD_GET_OUTPUT_ENABLED, ":OUTP?" },
129 { SCPI_CMD_SET_OUTPUT_ENABLE, ":OUTP 1" },
130 { SCPI_CMD_SET_OUTPUT_DISABLE, ":OUTP 0" },
131 { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_THRESHOLD, ":SOUR:VOLT:PROT?" },
132 { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_THRESHOLD, ":SOUR:VOLT:PROT %.6f" },
133 ALL_ZERO
134};
135
4ee1e2f3
AG		 136/* Chroma 61600 series AC source */
137static const uint32_t chroma_61604_devopts[] = {
e91bb0a6 138 SR_CONF_CONTINUOUS,
88e4daa9
ML		 139 SR_CONF_LIMIT_SAMPLES | SR_CONF_GET | SR_CONF_SET,
140 SR_CONF_LIMIT_MSEC | SR_CONF_GET | SR_CONF_SET,
4ee1e2f3
AG		 141};
142
143static const uint32_t chroma_61604_devopts_cg[] = {
144 SR_CONF_OVER_VOLTAGE_PROTECTION_THRESHOLD | SR_CONF_GET | SR_CONF_SET,
145 SR_CONF_OVER_CURRENT_PROTECTION_THRESHOLD | SR_CONF_GET | SR_CONF_SET,
da005885
UH		 146 SR_CONF_VOLTAGE | SR_CONF_GET,
147 SR_CONF_VOLTAGE_TARGET | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
6c0c9dd2
AG		 148 SR_CONF_OUTPUT_FREQUENCY | SR_CONF_GET,
149 SR_CONF_OUTPUT_FREQUENCY_TARGET | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
da005885
UH		 150 SR_CONF_CURRENT | SR_CONF_GET,
151 SR_CONF_ENABLED | SR_CONF_GET | SR_CONF_SET,
4ee1e2f3
AG		 152};
153
8cb5affe 154static const struct channel_spec chroma_61604_ch[] = {
49a468ed 155 { "1", { 0, 300, 0.1, 1, 1 }, { 0, 16, 0.1, 2, 2 }, { 0, 2000, 0, 1, 1 }, { 1.0, 1000.0, 0.01 }, NO_OVP_LIMITS, NO_OCP_LIMITS },
4ee1e2f3
AG		 156};
157
8cb5affe 158static const struct channel_group_spec chroma_61604_cg[] = {
f2bbcc33 159 { "1", CH_IDX(0), PPS_OVP | PPS_OCP, SR_MQFLAG_AC },
4ee1e2f3
AG		 160};
161
8cb5affe 162static const struct scpi_command chroma_61604_cmd[] = {
4ee1e2f3
AG		 163 { SCPI_CMD_REMOTE, "SYST:REM" },
164 { SCPI_CMD_LOCAL, "SYST:LOC" },
165 { SCPI_CMD_GET_MEAS_VOLTAGE, ":FETC:VOLT:ACDC?" },
6c0c9dd2 166 { SCPI_CMD_GET_MEAS_FREQUENCY, ":FETC:FREQ?" },
4ee1e2f3
AG		 167 { SCPI_CMD_GET_MEAS_CURRENT, ":FETC:CURR:AC?" },
168 { SCPI_CMD_GET_MEAS_POWER, ":FETC:POW:AC?" },
169 { SCPI_CMD_GET_VOLTAGE_TARGET, ":SOUR:VOLT:AC?" },
170 { SCPI_CMD_SET_VOLTAGE_TARGET, ":SOUR:VOLT:AC %.1f" },
6c0c9dd2
AG		 171 { SCPI_CMD_GET_FREQUENCY_TARGET, ":SOUR:FREQ?" },
172 { SCPI_CMD_SET_FREQUENCY_TARGET, ":SOUR:FREQ %.2f" },
4ee1e2f3
AG		 173 { SCPI_CMD_GET_OUTPUT_ENABLED, ":OUTP?" },
174 { SCPI_CMD_SET_OUTPUT_ENABLE, ":OUTP ON" },
175 { SCPI_CMD_SET_OUTPUT_DISABLE, ":OUTP OFF" },
176 { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_THRESHOLD, ":SOUR:VOLT:LIM:AC?" },
177 { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_THRESHOLD, ":SOUR:VOLT:LIM:AC %.1f" },
562a3490 178 /* This is not a current limit mode. It is overcurrent protection. */
4ee1e2f3
AG		 179 { SCPI_CMD_GET_OVER_CURRENT_PROTECTION_THRESHOLD, ":SOUR:CURR:LIM?" },
180 { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_THRESHOLD, ":SOUR:CURR:LIM %.2f" },
91ef511d 181 ALL_ZERO
4ee1e2f3
AG		 182};
183
5281993e 184/* Chroma 62000 series DC source */
5281993e 185static const uint32_t chroma_62000_devopts[] = {
e91bb0a6 186 SR_CONF_CONTINUOUS,
88e4daa9
ML		 187 SR_CONF_LIMIT_SAMPLES | SR_CONF_GET | SR_CONF_SET,
188 SR_CONF_LIMIT_MSEC | SR_CONF_GET | SR_CONF_SET,
5281993e
AG		 189};
190
191static const uint32_t chroma_62000_devopts_cg[] = {
192 SR_CONF_OVER_VOLTAGE_PROTECTION_THRESHOLD | SR_CONF_GET | SR_CONF_SET,
193 SR_CONF_OVER_CURRENT_PROTECTION_THRESHOLD | SR_CONF_GET | SR_CONF_SET,
194 SR_CONF_VOLTAGE | SR_CONF_GET,
195 SR_CONF_VOLTAGE_TARGET | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
196 SR_CONF_CURRENT | SR_CONF_GET,
197 SR_CONF_CURRENT_LIMIT | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
198 SR_CONF_ENABLED | SR_CONF_GET | SR_CONF_SET,
199};
200
5281993e 201static const struct channel_group_spec chroma_62000_cg[] = {
f2bbcc33 202 { "1", CH_IDX(0), PPS_OVP | PPS_OCP, SR_MQFLAG_DC },
5281993e
AG		 203};
204
205static const struct scpi_command chroma_62000_cmd[] = {
206 { SCPI_CMD_REMOTE, ":CONF:REM ON" },
207 { SCPI_CMD_LOCAL, ":CONF:REM OFF" },
208 { SCPI_CMD_BEEPER, ":CONF:BEEP?" },
209 { SCPI_CMD_BEEPER_ENABLE, ":CONF:BEEP ON" },
210 { SCPI_CMD_BEEPER_DISABLE, ":CONF:BEEP OFF" },
211 { SCPI_CMD_GET_MEAS_VOLTAGE, ":MEAS:VOLT?" },
212 { SCPI_CMD_GET_MEAS_CURRENT, ":MEAS:CURR?" },
213 { SCPI_CMD_GET_MEAS_POWER, ":MEAS:POW?" },
214 { SCPI_CMD_GET_VOLTAGE_TARGET, ":SOUR:VOLT?" },
215 { SCPI_CMD_SET_VOLTAGE_TARGET, ":SOUR:VOLT %.2f" },
216 { SCPI_CMD_GET_CURRENT_LIMIT, ":SOUR:CURR?" },
217 { SCPI_CMD_SET_CURRENT_LIMIT, ":SOUR:CURR %.6f" },
218 { SCPI_CMD_GET_OUTPUT_ENABLED, ":CONF:OUTP?" },
219 { SCPI_CMD_SET_OUTPUT_ENABLE, ":CONF:OUTP ON" },
220 { SCPI_CMD_SET_OUTPUT_DISABLE, ":CONF:OUTP OFF" },
221 { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_THRESHOLD, ":SOUR:VOLT:PROT:HIGH?" },
222 { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_THRESHOLD, ":SOUR:VOLT:PROT:HIGH %.6f" },
223 { SCPI_CMD_GET_OVER_CURRENT_PROTECTION_THRESHOLD, ":SOUR:CURR:PROT:HIGH?" },
224 { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_THRESHOLD, ":SOUR:CURR:PROT:HIGH %.6f" },
91ef511d 225 ALL_ZERO
5281993e
AG		 226};
227
9a5185c7
AG		 228static int chroma_62000p_probe_channels(struct sr_dev_inst *sdi,
229 struct sr_scpi_hw_info *hw_info,
230 struct channel_spec **channels, unsigned int *num_channels,
231 struct channel_group_spec **channel_groups,
232 unsigned int *num_channel_groups)
233{
6ed709fe 234 unsigned int volts, amps, watts;
9a5185c7
AG		 235 struct channel_spec *channel;
236
237 (void)sdi;
238
6ed709fe
AJ		 239 sscanf(hw_info->model, "620%uP-%u-%u", &watts, &volts, &amps);
240 watts *= 100;
241 sr_dbg("Found device rated for %d V, %d A and %d W", volts, amps, watts);
9a5185c7
AG		 242
243 if (volts > 600) {
244 sr_err("Probed max voltage of %u V is out of spec.", volts);
245 return SR_ERR_BUG;
246 }
247
6ed709fe 248 if (amps > 120) {
9a5185c7
AG		 249 sr_err("Probed max current of %u A is out of spec.", amps);
250 return SR_ERR_BUG;
251 }
252
6ed709fe
AJ		 253 if (watts > 5000) {
254 sr_err("Probed max power of %u W is out of spec.", watts);
255 return SR_ERR_BUG;
256 }
257
9a5185c7
AG		 258 channel = g_malloc0(sizeof(struct channel_spec));
259 channel->name = "1";
6ed709fe 260 channel->voltage[0] = channel->current[0] = channel->power[0] = 0.0;
bcee1299
UH		 261 channel->voltage[1] = volts;
262 channel->current[1] = amps;
263 channel->power[1] = watts;
9a5185c7 264 channel->voltage[2] = channel->current[2] = 0.01;
6ed709fe
AJ		 265 channel->voltage[3] = channel->voltage[4] = 3;
266 channel->current[3] = channel->current[4] = 4;
9a5185c7
AG		 267 *channels = channel;
268 *num_channels = 1;
269
270 *channel_groups = g_malloc(sizeof(struct channel_group_spec));
271 **channel_groups = chroma_62000_cg[0];
272 *num_channel_groups = 1;
273
274 return SR_OK;
275}
276
22fdb67f
MA		 277/* Envox EEZ PSU Series */
278static const uint32_t eez_psu_devopts[] = {
279 SR_CONF_CONTINUOUS,
280 SR_CONF_LIMIT_SAMPLES | SR_CONF_GET | SR_CONF_SET,
281 SR_CONF_LIMIT_MSEC | SR_CONF_GET | SR_CONF_SET,
282};
283
284static const uint32_t eez_psu_devopts_cg[] = {
285 SR_CONF_VOLTAGE | SR_CONF_GET,
286 SR_CONF_VOLTAGE_TARGET | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
287 SR_CONF_CURRENT | SR_CONF_GET,
288 SR_CONF_CURRENT_LIMIT | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
289 SR_CONF_ENABLED | SR_CONF_GET | SR_CONF_SET,
290 SR_CONF_REGULATION | SR_CONF_GET,
291 SR_CONF_OVER_VOLTAGE_PROTECTION_ACTIVE | SR_CONF_GET,
292 SR_CONF_OVER_VOLTAGE_PROTECTION_THRESHOLD | SR_CONF_GET,
293 SR_CONF_OVER_CURRENT_PROTECTION_ACTIVE | SR_CONF_GET,
294 SR_CONF_OVER_CURRENT_PROTECTION_THRESHOLD | SR_CONF_GET,
295};
296
297static const struct scpi_command eez_psu_cmd[] = {
298 { SCPI_CMD_REMOTE, "SYST:REMOTE" },
299 { SCPI_CMD_LOCAL, "SYST:LOCAL" },
300 { SCPI_CMD_SELECT_CHANNEL, ":INST:NSEL %s" },
301 { SCPI_CMD_GET_MEAS_VOLTAGE, ":MEAS:VOLT?" },
302 { SCPI_CMD_GET_MEAS_CURRENT, ":MEAS:CURR?" },
303 { SCPI_CMD_GET_MEAS_POWER, ":MEAS:POWER?" },
304 { SCPI_CMD_GET_OUTPUT_REGULATION, ":OUTP:MODE?" },
305 { SCPI_CMD_GET_VOLTAGE_TARGET, ":SOUR:VOLT?" },
306 { SCPI_CMD_SET_VOLTAGE_TARGET, ":SOUR:VOLT %.2f" },
307 { SCPI_CMD_GET_CURRENT_LIMIT, ":SOUR:CURR?" },
308 { SCPI_CMD_SET_CURRENT_LIMIT, ":SOUR:CURR %.6f" },
309 { SCPI_CMD_GET_OUTPUT_ENABLED, ":OUTP?" },
310 { SCPI_CMD_SET_OUTPUT_ENABLE, ":OUTP ON" },
311 { SCPI_CMD_SET_OUTPUT_DISABLE, ":OUTP OFF" },
312 { SCPI_CMD_GET_OVER_CURRENT_PROTECTION_THRESHOLD, ":SOUR:CURR:PROT?" },
313 { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_THRESHOLD, ":SOUR:VOLT:PROT?" },
314 ALL_ZERO
315};
316
317/*
318 * The EEZ BB3 protocol currently specifies up to six channels. The older
319 * EEZ PSU design only has room for two in its enclosure design.
320 *
321 * If a future model's SCPI spec allows more than six models then we can
322 * extend this to support more.
323 */
324static const char *eez_psu_channel_names[] = { "1", "2", "3", "4", "5", "6", };
325
326static int eez_psu_probe_channels(struct sr_dev_inst *sdi,
327 struct sr_scpi_hw_info *hw_info,
328 struct channel_spec **channels, unsigned int *num_channels,
329 struct channel_group_spec **channel_groups,
330 unsigned int *num_channel_groups)
331{
332 struct sr_scpi_dev_inst *scpi;
333 int ret, intval;
334 size_t i, channel_count;
335 double limit_val;
336 const char *channel_name;
337
338 /*
339 * The EEZ PSU family is intended by the designer to be end-user
340 * customizable, so this is intentionally a little more dynamic
341 * than strictly necessary for the "stock" models, to make it
342 * more likely to automatically support end-user upgrades of the
343 * various ranges.
344 *
345 * The BB3 in particular supports various different modular
346 * power supply frontends that offer different voltage/current
347 * limits and different numbers of independent channels, such as
348 * three PSU modules that have two channels each for a total of
349 * six controllable channels.
350 *
351 * This currently supports both the original EEZ PSU design
352 * (H24005, when in its stock build configuration) and the
353 * successor EEZ BB3 design.
354 */
355
356 scpi = sdi->conn;
357 ret = sr_scpi_get_int(scpi, ":SYST:CHAN:COUN?", &intval);
358 if (ret != SR_OK) {
359 sr_err("Failed to probe EEZ PSU channel count.");
360 return ret;
361 }
362 if (intval < 0) {
363 sr_err("Suspicious channel count %d, ignoring.", intval);
364 return SR_ERR_DATA;
365 }
366 channel_count = intval;
367 if (channel_count > ARRAY_SIZE(eez_psu_channel_names)) {
368 /*
369 * No known EEZ PSU specifies more than six channels at
370 * the time of writing, so it would be weird to get here
371 * but we'll allow it to be robust.
372 */
373 sr_warn("Only using first %zu of %zu EEZ PSU channels.",
374 channel_count, ARRAY_SIZE(eez_psu_channel_names));
375 channel_count = ARRAY_SIZE(eez_psu_channel_names);
376 }
377
378 sr_spew("EEZ PSU (%s) has channel count %zu.",
379 hw_info->model, channel_count);
380
381 *channels = g_malloc0(sizeof(**channels) * channel_count);
382 *channel_groups = g_malloc0(sizeof(**channel_groups) * channel_count);
383 for (i = 0; i < channel_count; i++) {
384 channel_name = eez_psu_channel_names[i];
385
386 /*
387 * Select the channel to prepare for our various "get"
388 * calls below.
389 */
390 ret = sr_scpi_send(scpi, ":INST:NSEL %s", channel_name);
391 if (ret != SR_OK) {
392 sr_err("Failed to select %s to retrieve its limits.",
393 channel_name);
394 return ret;
395 }
396
397 (*channel_groups)[i].name = channel_name;
398 (*channel_groups)[i].channel_index_mask = CH_IDX(i);
399 (*channel_groups)[i].features = PPS_OVP | PPS_OCP;
400 (*channel_groups)[i].mqflags = SR_MQFLAG_DC;
401
402 (*channels)[i].name = channel_name;
403
404 ret = sr_scpi_get_double(scpi,
405 ":SYST:CHAN:INFO:CURR?", &limit_val);
406 if (ret != SR_OK) {
407 sr_err("Failed to read the current limit for %s.",
408 channel_name);
409 return ret;
410 }
411 (*channels)[i].current[0] = 0.0;
412 (*channels)[i].current[1] = limit_val;
413 (*channels)[i].current[2] = 0.01; /* Programming resolution. */
414 (*channels)[i].current[3] = 2; /* Spec digits. */
415 (*channels)[i].current[4] = 2; /* Encoding digits. */
416
417 ret = sr_scpi_get_double(scpi,
418 ":SYST:CHAN:INFO:VOLT?", &limit_val);
419 if (ret != SR_OK) {
420 sr_err("Failed to read the voltage limit for %s.",
421 channel_name);
422 return ret;
423 }
424 (*channels)[i].voltage[0] = 0.0;
425 (*channels)[i].voltage[1] = limit_val;
426 (*channels)[i].voltage[2] = 0.01; /* Programming resolution. */
427 (*channels)[i].voltage[3] = 2; /* Spec digits. */
428 (*channels)[i].voltage[4] = 2; /* Encoding digits. */
429
430 ret = sr_scpi_get_double(scpi,
431 ":SYST:CHAN:INFO:POW?", &limit_val);
432 if (ret != SR_OK) {
433 sr_err("Failed to read the power limit for %s.",
434 channel_name);
435 return ret;
436 }
437 (*channels)[i].power[0] = 0.0;
438 (*channels)[i].power[1] = limit_val;
439 (*channels)[i].power[2] = 0.01; /* Programming resolution. */
440 (*channels)[i].power[3] = 2; /* Spec digits. */
441 (*channels)[i].power[4] = 2; /* Encoding digits. */
442 }
443 *num_channels = *num_channel_groups = channel_count;
444
445 return SR_OK;
446}
447
319fe9ce
UH		 448/* Rigol DP700 series */
449static const uint32_t rigol_dp700_devopts[] = {
450 SR_CONF_CONTINUOUS,
88e4daa9
ML		 451 SR_CONF_LIMIT_SAMPLES | SR_CONF_GET | SR_CONF_SET,
452 SR_CONF_LIMIT_MSEC | SR_CONF_GET | SR_CONF_SET,
319fe9ce
UH		 453};
454
455static const uint32_t rigol_dp700_devopts_cg[] = {
456 SR_CONF_REGULATION | SR_CONF_GET,
457 SR_CONF_OVER_VOLTAGE_PROTECTION_ENABLED | SR_CONF_GET | SR_CONF_SET,
458 SR_CONF_OVER_VOLTAGE_PROTECTION_ACTIVE | SR_CONF_GET,
d828b05e 459 SR_CONF_OVER_VOLTAGE_PROTECTION_THRESHOLD | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
319fe9ce
UH		 460 SR_CONF_OVER_CURRENT_PROTECTION_ENABLED | SR_CONF_GET | SR_CONF_SET,
461 SR_CONF_OVER_CURRENT_PROTECTION_ACTIVE | SR_CONF_GET,
d828b05e 462 SR_CONF_OVER_CURRENT_PROTECTION_THRESHOLD | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
319fe9ce
UH		 463 SR_CONF_VOLTAGE | SR_CONF_GET,
464 SR_CONF_VOLTAGE_TARGET | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
465 SR_CONF_CURRENT | SR_CONF_GET,
466 SR_CONF_CURRENT_LIMIT | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
467 SR_CONF_ENABLED | SR_CONF_GET | SR_CONF_SET,
468};
469
470static const struct channel_spec rigol_dp711_ch[] = {
d828b05e 471 { "1", { 0, 30, 0.01, 3, 3 }, { 0, 5, 0.01, 3, 3 }, { 0, 150, 0, 3, 3 }, FREQ_DC_ONLY, { 0.01, 33, 0.01}, { 0.01, 5.5, 0.01 } },
319fe9ce
UH		 472};
473
474static const struct channel_spec rigol_dp712_ch[] = {
d828b05e 475 { "1", { 0, 50, 0.01, 3, 3 }, { 0, 3, 0.01, 3, 3 }, { 0, 150, 0, 3, 3 }, FREQ_DC_ONLY, { 0.01, 55, 0.01}, { 0.01, 3.3, 0.01 } },
319fe9ce
UH		 476};
477
478static const struct channel_group_spec rigol_dp700_cg[] = {
f2bbcc33 479 { "1", CH_IDX(0), PPS_OVP | PPS_OCP, SR_MQFLAG_DC },
319fe9ce
UH		 480};
481
482/* Same as the DP800 series, except for the missing :SYST:OTP* commands. */
483static const struct scpi_command rigol_dp700_cmd[] = {
484 { SCPI_CMD_REMOTE, "SYST:REMOTE" },
485 { SCPI_CMD_LOCAL, "SYST:LOCAL" },
486 { SCPI_CMD_BEEPER, "SYST:BEEP:STAT?" },
487 { SCPI_CMD_BEEPER_ENABLE, "SYST:BEEP:STAT ON" },
488 { SCPI_CMD_BEEPER_DISABLE, "SYST:BEEP:STAT OFF" },
489 { SCPI_CMD_SELECT_CHANNEL, ":INST:NSEL %s" },
490 { SCPI_CMD_GET_MEAS_VOLTAGE, ":MEAS:VOLT?" },
491 { SCPI_CMD_GET_MEAS_CURRENT, ":MEAS:CURR?" },
492 { SCPI_CMD_GET_MEAS_POWER, ":MEAS:POWE?" },
493 { SCPI_CMD_GET_VOLTAGE_TARGET, ":SOUR:VOLT?" },
494 { SCPI_CMD_SET_VOLTAGE_TARGET, ":SOUR:VOLT %.6f" },
495 { SCPI_CMD_GET_CURRENT_LIMIT, ":SOUR:CURR?" },
496 { SCPI_CMD_SET_CURRENT_LIMIT, ":SOUR:CURR %.6f" },
497 { SCPI_CMD_GET_OUTPUT_ENABLED, ":OUTP?" },
498 { SCPI_CMD_SET_OUTPUT_ENABLE, ":OUTP ON" },
499 { SCPI_CMD_SET_OUTPUT_DISABLE, ":OUTP OFF" },
500 { SCPI_CMD_GET_OUTPUT_REGULATION, ":OUTP:MODE?" },
501 { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_ENABLED, ":OUTP:OVP?" },
502 { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_ENABLE, ":OUTP:OVP ON" },
503 { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_DISABLE, ":OUTP:OVP OFF" },
504 { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_ACTIVE, ":OUTP:OVP:QUES?" },
505 { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_THRESHOLD, ":OUTP:OVP:VAL?" },
506 { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_THRESHOLD, ":OUTP:OVP:VAL %.6f" },
507 { SCPI_CMD_GET_OVER_CURRENT_PROTECTION_ENABLED, ":OUTP:OCP?" },
508 { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_ENABLE, ":OUTP:OCP:STAT ON" },
509 { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_DISABLE, ":OUTP:OCP:STAT OFF" },
510 { SCPI_CMD_GET_OVER_CURRENT_PROTECTION_ACTIVE, ":OUTP:OCP:QUES?" },
511 { SCPI_CMD_GET_OVER_CURRENT_PROTECTION_THRESHOLD, ":OUTP:OCP:VAL?" },
512 { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_THRESHOLD, ":OUTP:OCP:VAL %.6f" },
513 ALL_ZERO
514};
515
d4eabea8 516/* Rigol DP800 series */
584560f1 517static const uint32_t rigol_dp800_devopts[] = {
e91bb0a6 518 SR_CONF_CONTINUOUS,
5827f61b 519 SR_CONF_OVER_TEMPERATURE_PROTECTION | SR_CONF_GET | SR_CONF_SET,
88e4daa9
ML		 520 SR_CONF_LIMIT_SAMPLES | SR_CONF_GET | SR_CONF_SET,
521 SR_CONF_LIMIT_MSEC | SR_CONF_GET | SR_CONF_SET,
d4eabea8
BV		 522};
523
584560f1 524static const uint32_t rigol_dp800_devopts_cg[] = {
7a0b98b5 525 SR_CONF_REGULATION | SR_CONF_GET,
5827f61b
BV		 526 SR_CONF_OVER_VOLTAGE_PROTECTION_ENABLED | SR_CONF_GET | SR_CONF_SET,
527 SR_CONF_OVER_VOLTAGE_PROTECTION_ACTIVE | SR_CONF_GET,
528 SR_CONF_OVER_VOLTAGE_PROTECTION_THRESHOLD | SR_CONF_GET | SR_CONF_SET,
529 SR_CONF_OVER_CURRENT_PROTECTION_ENABLED | SR_CONF_GET | SR_CONF_SET,
530 SR_CONF_OVER_CURRENT_PROTECTION_ACTIVE | SR_CONF_GET,
531 SR_CONF_OVER_CURRENT_PROTECTION_THRESHOLD | SR_CONF_GET | SR_CONF_SET,
7a0b98b5
AJ		 532 SR_CONF_VOLTAGE | SR_CONF_GET,
533 SR_CONF_VOLTAGE_TARGET | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
534 SR_CONF_CURRENT | SR_CONF_GET,
535 SR_CONF_CURRENT_LIMIT | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
536 SR_CONF_ENABLED | SR_CONF_GET | SR_CONF_SET,
d4eabea8
BV		 537};
538
8cb5affe 539static const struct channel_spec rigol_dp821a_ch[] = {
49a468ed
FS		 540 { "1", { 0, 60, 0.001, 3, 3 }, { 0, 1, 0.0001, 4, 4 }, { 0, 60, 0, 3, 4 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS },
541 { "2", { 0, 8, 0.001, 3, 3 }, { 0, 10, 0.001, 3, 3 }, { 0, 80, 0, 3, 3 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS },
cfcdf576
ML		 542};
543
8cb5affe 544static const struct channel_spec rigol_dp831_ch[] = {
49a468ed
FS		 545 { "1", { 0, 8, 0.001, 3, 4 }, { 0, 5, 0.0003, 3, 4 }, { 0, 40, 0, 3, 4 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS },
546 { "2", { 0, 30, 0.001, 3, 4 }, { 0, 2, 0.0001, 3, 4 }, { 0, 60, 0, 3, 4 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS },
547 { "3", { 0, -30, 0.001, 3, 4 }, { 0, 2, 0.0001, 3, 4 }, { 0, 60, 0, 3, 4 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS },
d4eabea8
BV		 548};
549
8cb5affe 550static const struct channel_spec rigol_dp832_ch[] = {
49a468ed
FS		 551 { "1", { 0, 30, 0.001, 3, 4 }, { 0, 3, 0.001, 3, 4 }, { 0, 90, 0, 3, 4 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS },
552 { "2", { 0, 30, 0.001, 3, 4 }, { 0, 3, 0.001, 3, 4 }, { 0, 90, 0, 3, 4 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS },
553 { "3", { 0, 5, 0.001, 3, 4 }, { 0, 3, 0.001, 3, 4 }, { 0, 90, 0, 3, 4 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS },
3222ee10
BV		 554};
555
8cb5affe 556static const struct channel_group_spec rigol_dp820_cg[] = {
f2bbcc33
FS		 557 { "1", CH_IDX(0), PPS_OVP | PPS_OCP, SR_MQFLAG_DC },
558 { "2", CH_IDX(1), PPS_OVP | PPS_OCP, SR_MQFLAG_DC },
cfcdf576
ML		 559};
560
8cb5affe 561static const struct channel_group_spec rigol_dp830_cg[] = {
f2bbcc33
FS		 562 { "1", CH_IDX(0), PPS_OVP | PPS_OCP, SR_MQFLAG_DC },
563 { "2", CH_IDX(1), PPS_OVP | PPS_OCP, SR_MQFLAG_DC },
564 { "3", CH_IDX(2), PPS_OVP | PPS_OCP, SR_MQFLAG_DC },
d4eabea8
BV		 565};
566
8cb5affe 567static const struct scpi_command rigol_dp800_cmd[] = {
60475cd7
BV		 568 { SCPI_CMD_REMOTE, "SYST:REMOTE" },
569 { SCPI_CMD_LOCAL, "SYST:LOCAL" },
ee2860ee
BV		 570 { SCPI_CMD_BEEPER, "SYST:BEEP:STAT?" },
571 { SCPI_CMD_BEEPER_ENABLE, "SYST:BEEP:STAT ON" },
572 { SCPI_CMD_BEEPER_DISABLE, "SYST:BEEP:STAT OFF" },
60475cd7
BV		 573 { SCPI_CMD_SELECT_CHANNEL, ":INST:NSEL %s" },
574 { SCPI_CMD_GET_MEAS_VOLTAGE, ":MEAS:VOLT?" },
575 { SCPI_CMD_GET_MEAS_CURRENT, ":MEAS:CURR?" },
576 { SCPI_CMD_GET_MEAS_POWER, ":MEAS:POWE?" },
577 { SCPI_CMD_GET_VOLTAGE_TARGET, ":SOUR:VOLT?" },
578 { SCPI_CMD_SET_VOLTAGE_TARGET, ":SOUR:VOLT %.6f" },
579 { SCPI_CMD_GET_CURRENT_LIMIT, ":SOUR:CURR?" },
580 { SCPI_CMD_SET_CURRENT_LIMIT, ":SOUR:CURR %.6f" },
581 { SCPI_CMD_GET_OUTPUT_ENABLED, ":OUTP?" },
582 { SCPI_CMD_SET_OUTPUT_ENABLE, ":OUTP ON" },
583 { SCPI_CMD_SET_OUTPUT_DISABLE, ":OUTP OFF" },
584 { SCPI_CMD_GET_OUTPUT_REGULATION, ":OUTP:MODE?" },
d4eabea8 585 { SCPI_CMD_GET_OVER_TEMPERATURE_PROTECTION, ":SYST:OTP?" },
53a81803
BV		 586 { SCPI_CMD_SET_OVER_TEMPERATURE_PROTECTION_ENABLE, ":SYST:OTP ON" },
587 { SCPI_CMD_SET_OVER_TEMPERATURE_PROTECTION_DISABLE, ":SYST:OTP OFF" },
60475cd7
BV		 588 { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_ENABLED, ":OUTP:OVP?" },
589 { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_ENABLE, ":OUTP:OVP ON" },
590 { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_DISABLE, ":OUTP:OVP OFF" },
591 { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_ACTIVE, ":OUTP:OVP:QUES?" },
592 { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_THRESHOLD, ":OUTP:OVP:VAL?" },
593 { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_THRESHOLD, ":OUTP:OVP:VAL %.6f" },
594 { SCPI_CMD_GET_OVER_CURRENT_PROTECTION_ENABLED, ":OUTP:OCP?" },
595 { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_ENABLE, ":OUTP:OCP:STAT ON" },
596 { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_DISABLE, ":OUTP:OCP:STAT OFF" },
597 { SCPI_CMD_GET_OVER_CURRENT_PROTECTION_ACTIVE, ":OUTP:OCP:QUES?" },
598 { SCPI_CMD_GET_OVER_CURRENT_PROTECTION_THRESHOLD, ":OUTP:OCP:VAL?" },
599 { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_THRESHOLD, ":OUTP:OCP:VAL %.6f" },
91ef511d 600 ALL_ZERO
d4eabea8
BV		 601};
602
dbc519f7 603/* HP 663xA series */
e76a3575
AG		 604static const uint32_t hp_6630a_devopts[] = {
605 SR_CONF_CONTINUOUS,
88e4daa9
ML		 606 SR_CONF_LIMIT_SAMPLES | SR_CONF_GET | SR_CONF_SET,
607 SR_CONF_LIMIT_MSEC | SR_CONF_GET | SR_CONF_SET,
7c517d02
FS		 608};
609
610static const uint32_t hp_6630a_devopts_cg[] = {
e76a3575
AG		 611 SR_CONF_ENABLED | SR_CONF_SET,
612 SR_CONF_VOLTAGE | SR_CONF_GET,
613 SR_CONF_CURRENT | SR_CONF_GET,
614 SR_CONF_VOLTAGE_TARGET | SR_CONF_SET | SR_CONF_LIST,
615 SR_CONF_CURRENT_LIMIT | SR_CONF_SET | SR_CONF_LIST,
f083ae63 616 SR_CONF_OVER_VOLTAGE_PROTECTION_ACTIVE | SR_CONF_GET,
49a468ed 617 SR_CONF_OVER_VOLTAGE_PROTECTION_THRESHOLD | SR_CONF_SET | SR_CONF_LIST,
e76a3575 618 SR_CONF_OVER_CURRENT_PROTECTION_ENABLED | SR_CONF_SET,
f083ae63
FS		 619 SR_CONF_OVER_CURRENT_PROTECTION_ACTIVE | SR_CONF_GET,
620 SR_CONF_OVER_TEMPERATURE_PROTECTION_ACTIVE | SR_CONF_GET,
0ad7074c 621 SR_CONF_REGULATION | SR_CONF_GET,
e76a3575
AG		 622};
623
5ce427c7
FS		 624static const struct channel_spec hp_6632a_ch[] = {
625 { "1", { 0, 20.475, 0.005, 3, 4 }, { 0, 5.1188, 0.00125, 4, 5 }, { 0, 104.80743 }, FREQ_DC_ONLY, { 0, 22, 0.1 }, NO_OCP_LIMITS },
626};
627
dbc519f7
FS		 628static const struct channel_spec hp_6633a_ch[] = {
629 { "1", { 0, 51.188, 0.0125, 3, 4 }, { 0, 2.0475, 0.0005, 4, 5 }, { 0, 104.80743 }, FREQ_DC_ONLY, { 0, 55, 0.25 }, NO_OCP_LIMITS },
630};
631
5ce427c7
FS		 632static const struct channel_spec hp_6634a_ch[] = {
633 { "1", { 0, 102.38, 0.025, 3, 4 }, { 0, 1.0238, 0.00025, 4, 5 }, { 0, 104.81664 }, FREQ_DC_ONLY, { 0, 110, 0.5 }, NO_OCP_LIMITS },
634};
635
dbc519f7
FS		 636static const struct channel_group_spec hp_6630a_cg[] = {
637 { "1", CH_IDX(0), PPS_OVP | PPS_OCP, SR_MQFLAG_DC },
638};
639
640static const struct scpi_command hp_6630a_cmd[] = {
641 { SCPI_CMD_SET_OUTPUT_ENABLE, "OUT 1" },
642 { SCPI_CMD_SET_OUTPUT_DISABLE, "OUT 0" },
643 { SCPI_CMD_GET_MEAS_VOLTAGE, "VOUT?" },
644 { SCPI_CMD_GET_MEAS_CURRENT, "IOUT?" },
645 { SCPI_CMD_SET_VOLTAGE_TARGET, "VSET %.4f" },
646 { SCPI_CMD_SET_CURRENT_LIMIT, "ISET %.4f" },
f083ae63
FS		 647 { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_ACTIVE, "STS?" },
648 { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_THRESHOLD, "OVSET %.4f" },
dbc519f7
FS		 649 { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_ENABLE, "OCP 1" },
650 { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_DISABLE, "OCP 0" },
f083ae63
FS		 651 { SCPI_CMD_GET_OVER_CURRENT_PROTECTION_ACTIVE, "STS?" },
652 { SCPI_CMD_GET_OVER_TEMPERATURE_PROTECTION_ACTIVE, "STS?" },
0ad7074c 653 { SCPI_CMD_GET_OUTPUT_REGULATION, "STS?" },
dbc519f7
FS		 654 ALL_ZERO
655};
656
fd243315 657static int hp_6630a_init_acquisition(const struct sr_dev_inst *sdi)
fdf03652
FS		 658{
659 struct sr_scpi_dev_inst *scpi;
fdf03652
FS		 660
661 scpi = sdi->conn;
662
663 /*
664 * Monitor CV (1), CC+ (2), UR (4), OVP (8), OTP (16), OCP (64) and
665 * CC- (256) bits of the Status Register for the FAULT? query.
666 */
b89e6db9 667 return sr_scpi_send(scpi, "UNMASK 607");
fdf03652
FS		 668}
669
670static int hp_6630a_update_status(const struct sr_dev_inst *sdi)
671{
672 struct sr_scpi_dev_inst *scpi;
673 int ret;
674 int fault;
675 gboolean cv, cc_pos, unreg, cc_neg;
676 gboolean regulation_changed;
677 char *regulation;
678
679 scpi = sdi->conn;
680
681 /*
682 * Use the FAULT register (only 0->1 transitions), this way multiple set
683 * regulation bits in the STS/ASTS registers are ignored. In rare cases
684 * we will miss some changes (1->0 transitions, e.g. no regulation at all),
685 * but SPS/ASPS doesn't work either, unless all states are stored and
686 * compared to the states in STS/ASTS.
687 * TODO: Use SPoll or SRQ when SCPI over GPIB is used.
688 */
689 ret = sr_scpi_get_int(scpi, "FAULT?", &fault);
690 if (ret != SR_OK)
691 return ret;
692
693 /* OVP */
694 if (fault & (1 << 3))
695 sr_session_send_meta(sdi, SR_CONF_OVER_VOLTAGE_PROTECTION_ACTIVE,
696 g_variant_new_boolean(fault & (1 << 3)));
697
698 /* OCP */
699 if (fault & (1 << 6))
700 sr_session_send_meta(sdi, SR_CONF_OVER_CURRENT_PROTECTION_ACTIVE,
701 g_variant_new_boolean(fault & (1 << 6)));
702
703 /* OTP */
704 if (fault & (1 << 4))
705 sr_session_send_meta(sdi, SR_CONF_OVER_TEMPERATURE_PROTECTION_ACTIVE,
706 g_variant_new_boolean(fault & (1 << 4)));
707
708 /* CV */
709 cv = (fault & (1 << 0));
710 regulation_changed = (fault & (1 << 0));
711 /* CC+ */
712 cc_pos = (fault & (1 << 1));
713 regulation_changed = (fault & (1 << 1)) | regulation_changed;
714 /* UNREG */
715 unreg = (fault & (1 << 2));
716 regulation_changed = (fault & (1 << 2)) | regulation_changed;
717 /* CC- */
718 cc_neg = (fault & (1 << 9));
719 regulation_changed = (fault & (1 << 9)) | regulation_changed;
720
721 if (regulation_changed) {
b89e6db9 722 if (cv && !cc_pos && !cc_neg && !unreg)
fdf03652
FS		 723 regulation = "CV";
724 else if (cc_pos && !cv && !cc_neg && !unreg)
725 regulation = "CC";
726 else if (cc_neg && !cv && !cc_pos && !unreg)
727 regulation = "CC-";
728 else if (unreg && !cv && !cc_pos && !cc_neg)
729 regulation = "UR";
b89e6db9 730 else if (!cv && !cc_pos && !cc_neg && !unreg)
fdf03652
FS		 731 regulation = "";
732 else {
733 sr_dbg("Undefined regulation for HP 66xxA "
734 "(CV=%i, CC+=%i, CC-=%i, UR=%i).",
735 cv, cc_pos, cc_neg, unreg);
736 return FALSE;
737 }
738 sr_session_send_meta(sdi, SR_CONF_REGULATION,
739 g_variant_new_string(regulation));
740 }
741
742 return SR_OK;
743}
744
dbc519f7 745/* HP 663xB series */
a61c8cce 746static const uint32_t hp_6630b_devopts[] = {
e91bb0a6 747 SR_CONF_CONTINUOUS,
88e4daa9
ML		 748 SR_CONF_LIMIT_SAMPLES | SR_CONF_GET | SR_CONF_SET,
749 SR_CONF_LIMIT_MSEC | SR_CONF_GET | SR_CONF_SET,
7c517d02
FS		 750};
751
a61c8cce 752static const uint32_t hp_6630b_devopts_cg[] = {
7a0b98b5
AJ		 753 SR_CONF_ENABLED | SR_CONF_GET | SR_CONF_SET,
754 SR_CONF_VOLTAGE | SR_CONF_GET,
755 SR_CONF_CURRENT | SR_CONF_GET,
756 SR_CONF_VOLTAGE_TARGET | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
757 SR_CONF_CURRENT_LIMIT | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
8b5eadf4 758 SR_CONF_OVER_VOLTAGE_PROTECTION_ACTIVE | SR_CONF_GET,
49a468ed 759 SR_CONF_OVER_VOLTAGE_PROTECTION_THRESHOLD | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
7e381bfc 760 SR_CONF_OVER_CURRENT_PROTECTION_ENABLED | SR_CONF_GET | SR_CONF_SET,
8b5eadf4
FS		 761 SR_CONF_OVER_CURRENT_PROTECTION_ACTIVE | SR_CONF_GET,
762 SR_CONF_OVER_TEMPERATURE_PROTECTION_ACTIVE | SR_CONF_GET,
43ff1110 763 SR_CONF_REGULATION | SR_CONF_GET,
bc4a2a46
BV		 764};
765
5ce427c7
FS		 766static const struct channel_spec hp_6611c_ch[] = {
767 { "1", { 0, 8.19, 0.002, 3, 4 }, { 0, 5.1188, 0.00125, 4, 5 }, { 0, 41.92297 }, FREQ_DC_ONLY, { 0, 12, 0.06 }, NO_OCP_LIMITS },
768};
769
770static const struct channel_spec hp_6612c_ch[] = {
771 { "1", { 0, 20.475, 0.005, 3, 4 }, { 0, 2.0475, 0.0005, 4, 5 }, { 0, 41.92256 }, FREQ_DC_ONLY, { 0, 22, 0.1 }, NO_OCP_LIMITS },
772};
773
774static const struct channel_spec hp_6613c_ch[] = {
775 { "1", { 0, 51.188, 0.0125, 3, 4 }, { 0, 1.0238, 0.00025, 4, 5 }, { 0, 52.40627 }, FREQ_DC_ONLY, { 0, 55, 0.25 }, NO_OCP_LIMITS },
776};
777
778static const struct channel_spec hp_6614c_ch[] = {
779 { "1", { 0, 102.38, 0.025, 3, 4 }, { 0, 0.5118, 0.000125, 4, 5 }, { 0, 52.39808 }, FREQ_DC_ONLY, { 0, 110, 0.5 }, NO_OCP_LIMITS },
780};
781
a61c8cce 782static const struct channel_spec hp_6631b_ch[] = {
49a468ed 783 { "1", { 0, 8.19, 0.002, 3, 4 }, { 0, 10.237, 0.00263, 4, 5 }, { 0, 83.84103 }, FREQ_DC_ONLY, { 0, 12, 0.06 }, NO_OCP_LIMITS },
a61c8cce
FS		 784};
785
8cb5affe 786static const struct channel_spec hp_6632b_ch[] = {
49a468ed 787 { "1", { 0, 20.475, 0.005, 3, 4 }, { 0, 5.1188, 0.00132, 4, 5 }, { 0, 104.80743 }, FREQ_DC_ONLY, { 0, 22, 0.1 }, NO_OCP_LIMITS },
bc4a2a46
BV		 788};
789
0b0f40d8
MW		 790static const struct channel_spec hp_66312a_ch[] = {
791 { "1", { 0, 20.475, 0.0001, 4, 5 }, { 0, 2.0475, 0.0001, 4, 5 }, { 0, 41.92256 }, FREQ_DC_ONLY, { 0, 22, 0.01 }, NO_OCP_LIMITS },
792};
793
a61c8cce 794static const struct channel_spec hp_66332a_ch[] = {
49a468ed 795 { "1", { 0, 20.475, 0.005, 3, 4 }, { 0, 5.1188, 0.00132, 4, 5 }, { 0, 104.80743 }, FREQ_DC_ONLY, { 0, 22, 0.1 }, NO_OCP_LIMITS },
a61c8cce
FS		 796};
797
798static const struct channel_spec hp_6633b_ch[] = {
49a468ed 799 { "1", { 0, 51.188, 0.0125, 3, 4 }, { 0, 2.0475, 0.000526, 4, 5 }, { 0, 104.80743 }, FREQ_DC_ONLY, { 0, 55, 0.25 }, NO_OCP_LIMITS },
a61c8cce
FS		 800};
801
802static const struct channel_spec hp_6634b_ch[] = {
49a468ed 803 { "1", { 0, 102.38, 0.025, 3, 4 }, { 0, 1.0238, 0.000263, 4, 5 }, { 0, 104.81664 }, FREQ_DC_ONLY, { 0, 110, 0.5 }, NO_OCP_LIMITS },
a61c8cce
FS		 804};
805
dbc519f7 806static const struct channel_group_spec hp_6630b_cg[] = {
3d1aa50f 807 { "1", CH_IDX(0), PPS_OVP | PPS_OCP, SR_MQFLAG_DC },
bc4a2a46
BV		 808};
809
a61c8cce 810static const struct scpi_command hp_6630b_cmd[] = {
26e96658
FS		 811 /*
812 * SCPI_CMD_REMOTE and SCPI_CMD_LOCAL are not used when GPIB is used,
813 * otherwise the device will report (non critical) error 602.
814 */
7e381bfc
FS		 815 { SCPI_CMD_REMOTE, "SYST:REM" },
816 { SCPI_CMD_LOCAL, "SYST:LOC" },
bc4a2a46 817 { SCPI_CMD_GET_OUTPUT_ENABLED, "OUTP:STAT?" },
53a81803
BV		 818 { SCPI_CMD_SET_OUTPUT_ENABLE, "OUTP:STAT ON" },
819 { SCPI_CMD_SET_OUTPUT_DISABLE, "OUTP:STAT OFF" },
bc4a2a46
BV		 820 { SCPI_CMD_GET_MEAS_VOLTAGE, ":MEAS:VOLT?" },
821 { SCPI_CMD_GET_MEAS_CURRENT, ":MEAS:CURR?" },
ca95e90f
BV		 822 { SCPI_CMD_GET_VOLTAGE_TARGET, ":SOUR:VOLT?" },
823 { SCPI_CMD_SET_VOLTAGE_TARGET, ":SOUR:VOLT %.6f" },
824 { SCPI_CMD_GET_CURRENT_LIMIT, ":SOUR:CURR?" },
825 { SCPI_CMD_SET_CURRENT_LIMIT, ":SOUR:CURR %.6f" },
7e381bfc
FS		 826 { SCPI_CMD_GET_OVER_CURRENT_PROTECTION_ENABLED, ":CURR:PROT:STAT?" },
827 { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_ENABLE, ":CURR:PROT:STAT 1" },
828 { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_DISABLE, ":CURR:PROT:STAT 0" },
8b5eadf4
FS		 829 { SCPI_CMD_GET_OVER_CURRENT_PROTECTION_ACTIVE, "STAT:QUES:COND?" },
830 { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_ACTIVE, "STAT:QUES:COND?" },
7e381bfc
FS		 831 { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_THRESHOLD, ":VOLT:PROT?" },
832 { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_THRESHOLD, ":VOLT:PROT %.6f" },
8b5eadf4 833 { SCPI_CMD_GET_OVER_TEMPERATURE_PROTECTION_ACTIVE, "STAT:QUES:COND?" },
43ff1110 834 { SCPI_CMD_GET_OUTPUT_REGULATION, "STAT:OPER:COND?" },
91ef511d 835 ALL_ZERO
bc4a2a46
BV		 836};
837
fd243315 838static int hp_6630b_init_acquisition(const struct sr_dev_inst *sdi)
fe4bb774
FS		 839{
840 struct sr_scpi_dev_inst *scpi;
841 int ret;
842
843 scpi = sdi->conn;
844
845 /*
846 * Monitor CV (256), CC+ (1024) and CC- (2048) bits of the
847 * Operational Status Register.
848 * Use both positive and negative transitions of the status bits.
849 */
850 ret = sr_scpi_send(scpi, "STAT:OPER:PTR 3328;NTR 3328;ENAB 3328");
851 if (ret != SR_OK)
852 return ret;
853
854 /*
855 * Monitor OVP (1), OCP (2), OTP (16) and Unreg (1024) bits of the
856 * Questionable Status Register.
857 * Use both positive and negative transitions of the status bits.
858 */
859 ret = sr_scpi_send(scpi, "STAT:QUES:PTR 1043;NTR 1043;ENAB 1043");
860 if (ret != SR_OK)
861 return ret;
862
863 /*
864 * Service Request Enable Register set for Operational Status Register
865 * bits (128) and Questionable Status Register bits (8).
866 * This masks the Status Register generating a SRQ/RQS. Not implemented yet!
867 */
868 /*
869 ret = sr_scpi_send(scpi, "*SRE 136");
870 if (ret != SR_OK)
871 return ret;
872 */
873
874 return SR_OK;
875}
876
877static int hp_6630b_update_status(const struct sr_dev_inst *sdi)
878{
879 struct sr_scpi_dev_inst *scpi;
880 int ret;
881 int stb;
882 int ques_even, ques_cond;
883 int oper_even, oper_cond;
884 gboolean output_enabled;
885 gboolean unreg, cv, cc_pos, cc_neg;
886 gboolean regulation_changed;
887 char *regulation;
888
889 scpi = sdi->conn;
890
891 unreg = FALSE;
892 cv = FALSE;
893 cc_pos = FALSE;
894 cc_neg = FALSE;
895 regulation_changed = FALSE;
896
897 /*
898 * Use SPoll when SCPI uses GPIB as transport layer.
899 * SPoll is approx. twice as fast as a normal GPIB write + read would be!
900 */
901#ifdef HAVE_LIBGPIB
902 char spoll_buf;
903
904 if (scpi->transport == SCPI_TRANSPORT_LIBGPIB) {
905 ret = sr_scpi_gpib_spoll(scpi, &spoll_buf);
906 if (ret != SR_OK)
907 return ret;
908 stb = (uint8_t)spoll_buf;
909 }
910 else {
911#endif
912 ret = sr_scpi_get_int(scpi, "*STB?", &stb);
913 if (ret != SR_OK)
914 return ret;
915#ifdef HAVE_LIBGPIB
916 }
917#endif
918
919 /* Questionable status summary bit */
920 if (stb & (1 << 3)) {
921 /* Read the event register to clear it! */
922 ret = sr_scpi_get_int(scpi, "STAT:QUES:EVEN?", &ques_even);
923 if (ret != SR_OK)
924 return ret;
925 /* Now get the values. */
926 ret = sr_scpi_get_int(scpi, "STAT:QUES:COND?", &ques_cond);
927 if (ret != SR_OK)
928 return ret;
929
930 /* OVP */
931 if (ques_even & (1 << 0))
932 sr_session_send_meta(sdi, SR_CONF_OVER_VOLTAGE_PROTECTION_ACTIVE,
933 g_variant_new_boolean(ques_cond & (1 << 0)));
934
935 /* OCP */
936 if (ques_even & (1 << 1))
937 sr_session_send_meta(sdi, SR_CONF_OVER_CURRENT_PROTECTION_ACTIVE,
938 g_variant_new_boolean(ques_cond & (1 << 1)));
939
940 /* OTP */
941 if (ques_even & (1 << 4))
942 sr_session_send_meta(sdi, SR_CONF_OVER_TEMPERATURE_PROTECTION_ACTIVE,
943 g_variant_new_boolean(ques_cond & (1 << 4)));
944
945 /* UNREG */
946 unreg = (ques_cond & (1 << 10));
947 regulation_changed = (ques_even & (1 << 10)) | regulation_changed;
948
949 /*
950 * Check if output state has changed, due to one of the
951 * questionable states changed.
b89e6db9
UH		 952 * NOTE: The output state is sent even if it hasn't changed,
953 * but that only happens rarely.
fe4bb774
FS		 954 */
955 ret = sr_scpi_get_bool(scpi, "OUTP:STAT?", &output_enabled);
956 if (ret != SR_OK)
957 return ret;
958 sr_session_send_meta(sdi, SR_CONF_ENABLED,
959 g_variant_new_boolean(output_enabled));
960 }
961
962 /* Operation status summary bit */
963 if (stb & (1 << 7)) {
964 /* Read the event register to clear it! */
965 ret = sr_scpi_get_int(scpi, "STAT:OPER:EVEN?", &oper_even);
966 if (ret != SR_OK)
967 return ret;
968 /* Now get the values. */
969 ret = sr_scpi_get_int(scpi, "STAT:OPER:COND?", &oper_cond);
970 if (ret != SR_OK)
971 return ret;
972
973 /* CV */
974 cv = (oper_cond & (1 << 8));
975 regulation_changed = (oper_even & (1 << 8)) | regulation_changed;
976 /* CC+ */
977 cc_pos = (oper_cond & (1 << 10));
978 regulation_changed = (oper_even & (1 << 10)) | regulation_changed;
979 /* CC- */
980 cc_neg = (oper_cond & (1 << 11));
981 regulation_changed = (oper_even & (1 << 11)) | regulation_changed;
982 }
983
984 if (regulation_changed) {
b89e6db9 985 if (cv && !cc_pos && !cc_neg && !unreg)
fe4bb774
FS		 986 regulation = "CV";
987 else if (cc_pos && !cv && !cc_neg && !unreg)
988 regulation = "CC";
989 else if (cc_neg && !cv && !cc_pos && !unreg)
990 regulation = "CC-";
991 else if (unreg && !cv && !cc_pos && !cc_neg)
992 regulation = "UR";
b89e6db9
UH		 993 else if (!cv && !cc_pos && !cc_neg && !unreg)
994 /* This happens in case of OCP active. */
fe4bb774
FS		 995 regulation = "";
996 else {
b89e6db9 997 /* This happens from time to time (CV and CC+ active). */
fe4bb774
FS		 998 sr_dbg("Undefined regulation for HP 66xxB "
999 "(CV=%i, CC+=%i, CC-=%i, UR=%i).",
1000 cv, cc_pos, cc_neg, unreg);
1001 return FALSE;
1002 }
1003 sr_session_send_meta(sdi, SR_CONF_REGULATION,
1004 g_variant_new_string(regulation));
1005 }
1006
1007 return SR_OK;
1008}
1009
5433907e
PA		 1010/* Owon P4000 series */
1011static const uint32_t owon_p4000_devopts[] = {
1012 SR_CONF_CONTINUOUS,
1013 SR_CONF_LIMIT_SAMPLES | SR_CONF_GET | SR_CONF_SET,
1014 SR_CONF_LIMIT_MSEC | SR_CONF_GET | SR_CONF_SET
1015};
1016
1017static const uint32_t owon_p4000_devopts_cg[] = {
1018 SR_CONF_ENABLED | SR_CONF_GET | SR_CONF_SET,
1019 SR_CONF_VOLTAGE | SR_CONF_GET,
1020 SR_CONF_VOLTAGE_TARGET | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
1021 SR_CONF_CURRENT | SR_CONF_GET,
1022 SR_CONF_CURRENT_LIMIT | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
1023 SR_CONF_OVER_VOLTAGE_PROTECTION_THRESHOLD | SR_CONF_GET | SR_CONF_SET,
1024 SR_CONF_OVER_CURRENT_PROTECTION_THRESHOLD | SR_CONF_GET | SR_CONF_SET,
1025};
1026
1027static const struct channel_spec owon_p4603_ch[] = {
1028 { "1", { 0.01, 60, 0.001, 3, 3 }, { 0.001, 3, 0.001, 3, 3 }, { 0, 180, 0, 3, 3 }, FREQ_DC_ONLY, { 0.01, 61, 0.001}, { 0.001, 3.1, 0.001} },
1029};
1030
1031static const struct channel_spec owon_p4305_ch[] = {
1032 { "1", { 0.01, 30, 0.001, 3, 3 }, { 0.001, 5, 0.001, 3, 3 }, { 0, 180, 0, 3, 3 }, FREQ_DC_ONLY, { 0.01, 31, 0.001}, { 0.001, 3.1, 0.001} },
1033};
1034
1035static const struct channel_group_spec owon_p4000_cg[] = {
1036 { "1", CH_IDX(0), PPS_OVP | PPS_OCP, SR_MQFLAG_DC },
1037};
1038
1039static const struct scpi_command owon_p4000_cmd[] = {
1040 { SCPI_CMD_GET_MEAS_VOLTAGE, "MEAS:VOLT?" },
1041 { SCPI_CMD_GET_MEAS_CURRENT, "MEAS:CURR?" },
1042 { SCPI_CMD_GET_MEAS_POWER, "MEAS:POW?" },
1043 { SCPI_CMD_GET_VOLTAGE_TARGET, "VOLT?" },
1044 { SCPI_CMD_SET_VOLTAGE_TARGET, "VOLT %.6f" },
1045 { SCPI_CMD_GET_CURRENT_LIMIT, "CURR?" },
1046 { SCPI_CMD_SET_CURRENT_LIMIT, "CURR %.6f" },
1047 { SCPI_CMD_GET_OUTPUT_ENABLED, "OUTP?" },
1048 { SCPI_CMD_SET_OUTPUT_ENABLE, "OUTP 1" },
1049 { SCPI_CMD_SET_OUTPUT_DISABLE, "OUTP 0" },
1050 { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_THRESHOLD, "VOLT:LIM?" },
1051 { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_THRESHOLD, "VOLT:LIM %.6f" },
1052 { SCPI_CMD_GET_OVER_CURRENT_PROTECTION_THRESHOLD, "CURR:LIM?" },
1053 { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_THRESHOLD, "CURR:LIM %.6f" },
1054 ALL_ZERO
1055};
1056
c3eadb07 1057/* Philips/Fluke PM2800 series */
9d9cf1c4 1058static const uint32_t philips_pm2800_devopts[] = {
e91bb0a6 1059 SR_CONF_CONTINUOUS,
88e4daa9
ML		 1060 SR_CONF_LIMIT_SAMPLES | SR_CONF_GET | SR_CONF_SET,
1061 SR_CONF_LIMIT_MSEC | SR_CONF_GET | SR_CONF_SET,
9d9cf1c4
BV		 1062};
1063
c3eadb07 1064static const uint32_t philips_pm2800_devopts_cg[] = {
7a0b98b5
AJ		 1065 SR_CONF_ENABLED | SR_CONF_GET | SR_CONF_SET,
1066 SR_CONF_VOLTAGE | SR_CONF_GET,
1067 SR_CONF_VOLTAGE_TARGET | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
1068 SR_CONF_CURRENT | SR_CONF_GET,
1069 SR_CONF_CURRENT_LIMIT | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
c3eadb07
BV		 1070 SR_CONF_OVER_VOLTAGE_PROTECTION_ACTIVE | SR_CONF_GET,
1071 SR_CONF_OVER_VOLTAGE_PROTECTION_THRESHOLD | SR_CONF_GET | SR_CONF_SET,
1072 SR_CONF_OVER_CURRENT_PROTECTION_ENABLED | SR_CONF_GET | SR_CONF_SET,
1073 SR_CONF_OVER_CURRENT_PROTECTION_ACTIVE | SR_CONF_GET,
7a0b98b5 1074 SR_CONF_REGULATION | SR_CONF_GET,
c3eadb07
BV		 1075};
1076
1077enum philips_pm2800_modules {
1078 PM2800_MOD_30V_10A = 1,
1079 PM2800_MOD_60V_5A,
1080 PM2800_MOD_60V_10A,
1081 PM2800_MOD_8V_15A,
1082 PM2800_MOD_60V_2A,
1083 PM2800_MOD_120V_1A,
1084};
1085
329733d9 1086static const struct philips_pm2800_module_spec {
c3eadb07 1087 /* Min, max, programming resolution. */
bcee1299
UH		 1088 double voltage[5];
1089 double current[5];
1090 double power[5];
c3eadb07
BV		 1091} philips_pm2800_module_specs[] = {
1092 /* Autoranging modules. */
6ed709fe
AJ		 1093 [PM2800_MOD_30V_10A] = { { 0, 30, 0.0075, 2, 4 }, { 0, 10, 0.0025, 2, 4 }, { 0, 60 } },
1094 [PM2800_MOD_60V_5A] = { { 0, 60, 0.015, 2, 3 }, { 0, 5, 0.00125, 2, 5 }, { 0, 60 } },
1095 [PM2800_MOD_60V_10A] = { { 0, 60, 0.015, 2, 3 }, { 0, 10, 0.0025, 2, 5 }, { 0, 120 } },
c3eadb07 1096 /* Linear modules. */
6ed709fe
AJ		 1097 [PM2800_MOD_8V_15A] = { { 0, 8, 0.002, 3, 3 }, { -15, 15, 0.00375, 3, 5 }, { 0, 120 } },
1098 [PM2800_MOD_60V_2A] = { { 0, 60, 0.015, 2, 3 }, { -2, 2, 0.0005, 3, 4 }, { 0, 120 } },
1099 [PM2800_MOD_120V_1A] = { { 0, 120, 0.030, 2, 2 }, { -1, 1, 0.00025, 3, 5 }, { 0, 120 } },
c3eadb07
BV		 1100};
1101
329733d9 1102static const struct philips_pm2800_model {
c3eadb07
BV		 1103 unsigned int chassis;
1104 unsigned int num_modules;
1105 unsigned int set;
1106 unsigned int modules[3];
1107} philips_pm2800_matrix[] = {
1108 /* Autoranging chassis. */
1109 { 1, 1, 0, { PM2800_MOD_30V_10A, 0, 0 } },
1110 { 1, 1, 1, { PM2800_MOD_60V_5A, 0, 0 } },
1111 { 1, 2, 0, { PM2800_MOD_30V_10A, PM2800_MOD_30V_10A, 0 } },
1112 { 1, 2, 1, { PM2800_MOD_60V_5A, PM2800_MOD_60V_5A, 0 } },
1113 { 1, 2, 2, { PM2800_MOD_30V_10A, PM2800_MOD_60V_5A, 0 } },
1114 { 1, 2, 3, { PM2800_MOD_30V_10A, PM2800_MOD_60V_10A, 0 } },
1115 { 1, 2, 4, { PM2800_MOD_60V_5A, PM2800_MOD_60V_10A, 0 } },
1116 { 1, 3, 0, { PM2800_MOD_30V_10A, PM2800_MOD_30V_10A, PM2800_MOD_30V_10A } },
1117 { 1, 3, 1, { PM2800_MOD_60V_5A, PM2800_MOD_60V_5A, PM2800_MOD_60V_5A } },
1118 { 1, 3, 2, { PM2800_MOD_30V_10A, PM2800_MOD_30V_10A, PM2800_MOD_60V_5A } },
1119 { 1, 3, 3, { PM2800_MOD_30V_10A, PM2800_MOD_60V_5A, PM2800_MOD_60V_5A } },
1120 /* Linear chassis. */
1121 { 3, 1, 0, { PM2800_MOD_60V_2A, 0, 0 } },
1122 { 3, 1, 1, { PM2800_MOD_120V_1A, 0, 0 } },
1123 { 3, 1, 2, { PM2800_MOD_8V_15A, 0, 0 } },
1124 { 3, 2, 0, { PM2800_MOD_60V_2A, 0, 0 } },
1125 { 3, 2, 1, { PM2800_MOD_120V_1A, 0, 0 } },
1126 { 3, 2, 2, { PM2800_MOD_60V_2A, PM2800_MOD_120V_1A, 0 } },
1127 { 3, 2, 3, { PM2800_MOD_8V_15A, PM2800_MOD_8V_15A, 0 } },
1128};
1129
329733d9 1130static const char *philips_pm2800_names[] = { "1", "2", "3" };
c3eadb07
BV		 1131
1132static int philips_pm2800_probe_channels(struct sr_dev_inst *sdi,
1133 struct sr_scpi_hw_info *hw_info,
1134 struct channel_spec **channels, unsigned int *num_channels,
1135 struct channel_group_spec **channel_groups, unsigned int *num_channel_groups)
1136{
329733d9
UH		 1137 const struct philips_pm2800_model *model;
1138 const struct philips_pm2800_module_spec *spec;
c3eadb07
BV		 1139 unsigned int chassis, num_modules, set, module, m, i;
1140
1141 (void)sdi;
1142
1143 /*
1144 * The model number as reported by *IDN? looks like e.g. PM2813/11,
1145 * Where "PM28" is fixed, followed by the chassis code (1 = autoranging,
1146 * 3 = linear series) and the number of modules: 1-3 for autoranging,
1147 * 1-2 for linear.
1148 * After the slash, the first digit denotes the module set. The
1149 * digit after that denotes front (5) or rear (1) binding posts.
1150 */
1151 chassis = hw_info->model[4] - 0x30;
1152 num_modules = hw_info->model[5] - 0x30;
1153 set = hw_info->model[7] - 0x30;
1154 for (m = 0; m < ARRAY_SIZE(philips_pm2800_matrix); m++) {
1155 model = &philips_pm2800_matrix[m];
1156 if (model->chassis == chassis && model->num_modules == num_modules
1157 && model->set == set)
1158 break;
1159 }
1160 if (m == ARRAY_SIZE(philips_pm2800_matrix)) {
1161 sr_dbg("Model %s not found in matrix.", hw_info->model);
1162 return SR_ERR;
1163 }
1164
1165 sr_dbg("Found %d output channel%s:", num_modules, num_modules > 1 ? "s" : "");
1166 *channels = g_malloc0(sizeof(struct channel_spec) * num_modules);
1167 *channel_groups = g_malloc0(sizeof(struct channel_group_spec) * num_modules);
1168 for (i = 0; i < num_modules; i++) {
1169 module = model->modules[i];
1170 spec = &philips_pm2800_module_specs[module];
6ed709fe 1171 sr_dbg("output %d: %.0f - %.0fV, %.0f - %.0fA, %.0f - %.0fW", i + 1,
c3eadb07 1172 spec->voltage[0], spec->voltage[1],
6ed709fe 1173 spec->current[0], spec->current[1],
d9251a2c 1174 spec->power[0], spec->power[1]);
329733d9 1175 (*channels)[i].name = (char *)philips_pm2800_names[i];
bcee1299 1176 memcpy(&((*channels)[i].voltage), spec, sizeof(double) * 15);
329733d9 1177 (*channel_groups)[i].name = (char *)philips_pm2800_names[i];
c3eadb07
BV		 1178 (*channel_groups)[i].channel_index_mask = 1 << i;
1179 (*channel_groups)[i].features = PPS_OTP | PPS_OVP | PPS_OCP;
f2bbcc33 1180 (*channel_groups)[i].mqflags = SR_MQFLAG_DC;
c3eadb07
BV		 1181 }
1182 *num_channels = *num_channel_groups = num_modules;
1183
1184 return SR_OK;
1185}
1186
8cb5affe 1187static const struct scpi_command philips_pm2800_cmd[] = {
c3eadb07
BV		 1188 { SCPI_CMD_SELECT_CHANNEL, ":INST:NSEL %s" },
1189 { SCPI_CMD_GET_MEAS_VOLTAGE, ":MEAS:VOLT?" },
1190 { SCPI_CMD_GET_MEAS_CURRENT, ":MEAS:CURR?" },
1191 { SCPI_CMD_GET_VOLTAGE_TARGET, ":SOUR:VOLT?" },
1192 { SCPI_CMD_SET_VOLTAGE_TARGET, ":SOUR:VOLT %.6f" },
1193 { SCPI_CMD_GET_CURRENT_LIMIT, ":SOUR:CURR?" },
1194 { SCPI_CMD_SET_CURRENT_LIMIT, ":SOUR:CURR %.6f" },
1195 { SCPI_CMD_GET_OUTPUT_ENABLED, ":OUTP?" },
1196 { SCPI_CMD_SET_OUTPUT_ENABLE, ":OUTP ON" },
1197 { SCPI_CMD_SET_OUTPUT_DISABLE, ":OUTP OFF" },
1198 { SCPI_CMD_GET_OUTPUT_REGULATION, ":SOUR:FUNC:MODE?" },
1199 { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_ACTIVE, ":SOUR:VOLT:PROT:TRIP?" },
1200 { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_THRESHOLD, ":SOUR:VOLT:PROT:LEV?" },
1201 { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_THRESHOLD, ":SOUR:VOLT:PROT:LEV %.6f" },
1202 { SCPI_CMD_GET_OVER_CURRENT_PROTECTION_ENABLED, ":SOUR:CURR:PROT:STAT?" },
1203 { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_ENABLE, ":SOUR:CURR:PROT:STAT ON" },
1204 { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_DISABLE, ":SOUR:CURR:PROT:STAT OFF" },
1205 { SCPI_CMD_GET_OVER_CURRENT_PROTECTION_ACTIVE, ":SOUR:CURR:PROT:TRIP?" },
91ef511d 1206 ALL_ZERO
c3eadb07
BV		 1207};
1208
81eb36d6
MS		 1209static const uint32_t rs_hmc8043_devopts[] = {
1210 SR_CONF_CONTINUOUS,
88e4daa9
ML		 1211 SR_CONF_LIMIT_SAMPLES | SR_CONF_GET | SR_CONF_SET,
1212 SR_CONF_LIMIT_MSEC | SR_CONF_GET | SR_CONF_SET,
81eb36d6
MS		 1213};
1214
1215static const uint32_t rs_hmc8043_devopts_cg[] = {
1216 SR_CONF_OVER_VOLTAGE_PROTECTION_ENABLED | SR_CONF_GET | SR_CONF_SET,
1217 SR_CONF_OVER_VOLTAGE_PROTECTION_ACTIVE | SR_CONF_GET,
1218 SR_CONF_OVER_VOLTAGE_PROTECTION_THRESHOLD | SR_CONF_GET | SR_CONF_SET,
1219 SR_CONF_VOLTAGE | SR_CONF_GET,
1220 SR_CONF_VOLTAGE_TARGET | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
1221 SR_CONF_CURRENT | SR_CONF_GET,
1222 SR_CONF_CURRENT_LIMIT | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
1223 SR_CONF_ENABLED | SR_CONF_GET | SR_CONF_SET,
1224};
1225
1226static const struct channel_spec rs_hmc8043_ch[] = {
49a468ed
FS		 1227 { "1", { 0, 32.050, 0.001, 3, 4 }, { 0.001, 3, 0.001, 3, 4 }, { 0, 0, 0, 0, 4 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS },
1228 { "2", { 0, 32.050, 0.001, 3, 4 }, { 0.001, 3, 0.001, 3, 4 }, { 0, 0, 0, 0, 4 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS },
1229 { "3", { 0, 32.050, 0.001, 3, 4 }, { 0.001, 3, 0.001, 3, 4 }, { 0, 0, 0, 0, 4 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS },
81eb36d6
MS		 1230};
1231
1232static const struct channel_group_spec rs_hmc8043_cg[] = {
f2bbcc33
FS		 1233 { "1", CH_IDX(0), PPS_OVP, SR_MQFLAG_DC },
1234 { "2", CH_IDX(1), PPS_OVP, SR_MQFLAG_DC },
1235 { "3", CH_IDX(2), PPS_OVP, SR_MQFLAG_DC },
81eb36d6
MS		 1236};
1237
1238static const struct scpi_command rs_hmc8043_cmd[] = {
1239 { SCPI_CMD_SELECT_CHANNEL, "INST:NSEL %s" },
1240 { SCPI_CMD_GET_MEAS_VOLTAGE, "MEAS:VOLT?" },
1241 { SCPI_CMD_GET_MEAS_CURRENT, "MEAS:CURR?" },
1242 { SCPI_CMD_GET_VOLTAGE_TARGET, "VOLT?" },
1243 { SCPI_CMD_SET_VOLTAGE_TARGET, "VOLT %.6f" },
1244 { SCPI_CMD_GET_CURRENT_LIMIT, "CURR?" },
1245 { SCPI_CMD_SET_CURRENT_LIMIT, "CURR %.6f" },
1246 { SCPI_CMD_GET_OUTPUT_ENABLED, "OUTP?" },
1247 { SCPI_CMD_SET_OUTPUT_ENABLE, "OUTP ON" },
1248 { SCPI_CMD_SET_OUTPUT_DISABLE, "OUTP OFF" },
1249 { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_ACTIVE, "VOLT:PROT:TRIP?" },
1250 { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_THRESHOLD, "VOLT:PROT:LEV?" },
1251 { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_THRESHOLD, "VOLT:PROT:LEV %.6f" },
1252 { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_ENABLED, "VOLT:PROT:STAT?" },
1253 { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_ENABLE, "VOLT:PROT:STAT ON" },
1254 { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_DISABLE, "VOLT:PROT:STAT OFF" },
1255 ALL_ZERO
1256};
1257
bd5f0a14
FS		 1258static const uint32_t rs_hmp4040_devopts[] = {
1259 SR_CONF_CONTINUOUS,
1260 SR_CONF_LIMIT_SAMPLES | SR_CONF_GET | SR_CONF_SET,
1261 SR_CONF_LIMIT_MSEC | SR_CONF_GET | SR_CONF_SET,
1262};
1263
1264static const uint32_t rs_hmp4040_devopts_cg[] = {
1265 SR_CONF_OVER_VOLTAGE_PROTECTION_ENABLED | SR_CONF_GET,
1266 SR_CONF_OVER_VOLTAGE_PROTECTION_ACTIVE | SR_CONF_GET,
1267 SR_CONF_OVER_VOLTAGE_PROTECTION_THRESHOLD | SR_CONF_GET | SR_CONF_SET,
1268 SR_CONF_VOLTAGE | SR_CONF_GET,
1269 SR_CONF_VOLTAGE_TARGET | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
1270 SR_CONF_CURRENT | SR_CONF_GET,
1271 SR_CONF_CURRENT_LIMIT | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
1272 SR_CONF_ENABLED | SR_CONF_GET | SR_CONF_SET,
1273 SR_CONF_OVER_TEMPERATURE_PROTECTION_ACTIVE | SR_CONF_GET,
1274 SR_CONF_REGULATION | SR_CONF_GET,
1275};
1276
1c5d5905
GS		 1277static const struct channel_spec rs_hmp2020_ch[] = {
1278 { "1", { 0, 32.050, 0.001, 3, 4 }, { 0.001, 10.01, 0.0002, 3, 4 }, { 0, 0, 0, 0, 4 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS },
1279 { "2", { 0, 32.050, 0.001, 3, 4 }, { 0.001, 5.01, 0.0001, 3, 4 }, { 0, 0, 0, 0, 4 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS },
1280};
1281
1282static const struct channel_spec rs_hmp2030_ch[] = {
1283 { "1", { 0, 32.050, 0.001, 3, 4 }, { 0.001, 5.01, 0.0001, 3, 4 }, { 0, 0, 0, 0, 4 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS },
1284 { "2", { 0, 32.050, 0.001, 3, 4 }, { 0.001, 5.01, 0.0001, 3, 4 }, { 0, 0, 0, 0, 4 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS },
1285 { "3", { 0, 32.050, 0.001, 3, 4 }, { 0.001, 5.01, 0.0001, 3, 4 }, { 0, 0, 0, 0, 4 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS },
1286};
1287
bd5f0a14 1288static const struct channel_spec rs_hmp4040_ch[] = {
7320ce5e
GS		 1289 { "1", { 0, 32.050, 0.001, 3, 4 }, { 0.001, 10.01, 0.0002, 3, 4 }, { 0, 0, 0, 0, 4 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS },
1290 { "2", { 0, 32.050, 0.001, 3, 4 }, { 0.001, 10.01, 0.0002, 3, 4 }, { 0, 0, 0, 0, 4 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS },
1291 { "3", { 0, 32.050, 0.001, 3, 4 }, { 0.001, 10.01, 0.0002, 3, 4 }, { 0, 0, 0, 0, 4 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS },
1292 { "4", { 0, 32.050, 0.001, 3, 4 }, { 0.001, 10.01, 0.0002, 3, 4 }, { 0, 0, 0, 0, 4 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS },
bd5f0a14
FS		 1293};
1294
1295static const struct channel_group_spec rs_hmp4040_cg[] = {
1296 { "1", CH_IDX(0), PPS_OVP | PPS_OTP, SR_MQFLAG_DC },
1297 { "2", CH_IDX(1), PPS_OVP | PPS_OTP, SR_MQFLAG_DC },
1298 { "3", CH_IDX(2), PPS_OVP | PPS_OTP, SR_MQFLAG_DC },
1299 { "4", CH_IDX(3), PPS_OVP | PPS_OTP, SR_MQFLAG_DC },
1300};
1301
1302/*
1303 * Developer's note: Currently unused device commands. Some of them
1304 * are not in use because SCPI_CMD codes are not defined yet.
1305 * OUTP:GEN
1306 * VOLT? MAX, CURR? MAX
1307 * VOLT:PROT:CLE (could set SR_CONF_OVER_VOLTAGE_PROTECTION_ACTIVE)
1308 * VOLT:PROT:MODE
1309 * FUSE:STAT, FUSE:TRIP?, FUSE:LINK, FUSE:UNL
1310 * ARB:...
1311 * SYST:LOC, SYST:REM, SYST:RWL, SYST:MIX
1312 * SYST:BEEP:IMM
1313 */
1314static const struct scpi_command rs_hmp4040_cmd[] = {
f403cb9d
GS		 1315 { SCPI_CMD_REMOTE, "SYST:REM" },
1316 { SCPI_CMD_LOCAL, "SYST:LOC" },
bd5f0a14
FS		 1317 { SCPI_CMD_SELECT_CHANNEL, "INST:NSEL %s" },
1318 { SCPI_CMD_GET_MEAS_VOLTAGE, "MEAS:VOLT?" },
1319 { SCPI_CMD_GET_MEAS_CURRENT, "MEAS:CURR?" },
1320 { SCPI_CMD_GET_VOLTAGE_TARGET, "VOLT?" },
1321 { SCPI_CMD_SET_VOLTAGE_TARGET, "VOLT %.6f" },
1322 { SCPI_CMD_GET_CURRENT_LIMIT, "CURR?" },
1323 { SCPI_CMD_SET_CURRENT_LIMIT, "CURR %.6f" },
1324 { SCPI_CMD_GET_OUTPUT_ENABLED, "OUTP?" },
1325 { SCPI_CMD_SET_OUTPUT_ENABLE, "OUTP ON" },
1326 { SCPI_CMD_SET_OUTPUT_DISABLE, "OUTP OFF" },
1327 { SCPI_CMD_GET_OUTPUT_REGULATION, "STAT:QUES:INST:ISUM%s:COND?" },
1328 { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_ACTIVE, "VOLT:PROT:TRIP?" },
1329 { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_THRESHOLD, "VOLT:PROT:LEV?" },
1330 { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_THRESHOLD, "VOLT:PROT:LEV %.6f" },
1331 { SCPI_CMD_GET_OVER_TEMPERATURE_PROTECTION_ACTIVE, "STAT:QUES:INST:ISUM%s:COND?" },
1332 ALL_ZERO
1333};
1334
d4eabea8 1335SR_PRIV const struct scpi_pps pps_profiles[] = {
6cc93128 1336 /* Agilent N5763A */
5e7377f4 1337 { "Agilent", "N5763A", SCPI_DIALECT_UNKNOWN, 0,
6cc93128
AG		 1338 ARRAY_AND_SIZE(agilent_n5700a_devopts),
1339 ARRAY_AND_SIZE(agilent_n5700a_devopts_cg),
1340 ARRAY_AND_SIZE(agilent_n5763a_ch),
1341 ARRAY_AND_SIZE(agilent_n5700a_cg),
1342 agilent_n5700a_cmd,
1343 .probe_channels = NULL,
fd243315 1344 .init_acquisition = NULL,
7e66bf05 1345 .update_status = NULL,
6cc93128 1346 },
ca314e06 1347
5c9e56c9 1348 /* Agilent N5767A */
5e7377f4 1349 { "Agilent", "N5767A", SCPI_DIALECT_UNKNOWN, 0,
5c9e56c9
AG		 1350 ARRAY_AND_SIZE(agilent_n5700a_devopts),
1351 ARRAY_AND_SIZE(agilent_n5700a_devopts_cg),
1352 ARRAY_AND_SIZE(agilent_n5767a_ch),
6cc93128 1353 ARRAY_AND_SIZE(agilent_n5700a_cg),
91ef511d 1354 agilent_n5700a_cmd,
5c9e56c9 1355 .probe_channels = NULL,
fd243315 1356 .init_acquisition = NULL,
7e66bf05 1357 .update_status = NULL,
5c9e56c9 1358 },
ca314e06 1359
c3bfb959 1360 /* BK Precision 9310 */
5e7377f4 1361 { "BK", "^9130$", SCPI_DIALECT_UNKNOWN, 0,
c3bfb959
MW		 1362 ARRAY_AND_SIZE(bk_9130_devopts),
1363 ARRAY_AND_SIZE(bk_9130_devopts_cg),
1364 ARRAY_AND_SIZE(bk_9130_ch),
1365 ARRAY_AND_SIZE(bk_9130_cg),
1366 bk_9130_cmd,
1367 .probe_channels = NULL,
fd243315 1368 .init_acquisition = NULL,
7e66bf05 1369 .update_status = NULL,
c3bfb959
MW		 1370 },
1371
4ee1e2f3 1372 /* Chroma 61604 */
5e7377f4 1373 { "Chroma", "61604", SCPI_DIALECT_UNKNOWN, 0,
4ee1e2f3
AG		 1374 ARRAY_AND_SIZE(chroma_61604_devopts),
1375 ARRAY_AND_SIZE(chroma_61604_devopts_cg),
1376 ARRAY_AND_SIZE(chroma_61604_ch),
1377 ARRAY_AND_SIZE(chroma_61604_cg),
91ef511d 1378 chroma_61604_cmd,
4ee1e2f3 1379 .probe_channels = NULL,
fd243315 1380 .init_acquisition = NULL,
7e66bf05 1381 .update_status = NULL,
4ee1e2f3 1382 },
ca314e06 1383
5281993e 1384 /* Chroma 62000 series */
5e7377f4 1385 { "Chroma", "620[0-9]{2}P-[0-9]{2,3}-[0-9]{1,3}", SCPI_DIALECT_UNKNOWN, 0,
5281993e
AG		 1386 ARRAY_AND_SIZE(chroma_62000_devopts),
1387 ARRAY_AND_SIZE(chroma_62000_devopts_cg),
9a5185c7
AG		 1388 NULL, 0,
1389 NULL, 0,
91ef511d 1390 chroma_62000_cmd,
9a5185c7 1391 .probe_channels = chroma_62000p_probe_channels,
22fdb67f
MA		 1392 .init_acquisition = NULL,
1393 .update_status = NULL,
1394 },
1395
1396 /*
1397 * Envox EEZ PSU Series
1398 * The documented identification strings disagree with the behavior
1399 * of at least some real units (returning "EEZ"). The first of these
1400 * is the documented one, while the second seems to be returned by
1401 * firmware v1.02 and earlier.
1402 */
1403 { "Envox", "^EEZ H24005 ", SCPI_DIALECT_UNKNOWN, 0,
1404 ARRAY_AND_SIZE(eez_psu_devopts),
1405 ARRAY_AND_SIZE(eez_psu_devopts_cg),
1406 NULL, 0,
1407 NULL, 0,
1408 eez_psu_cmd,
1409 .probe_channels = eez_psu_probe_channels,
1410 .init_acquisition = NULL,
1411 .update_status = NULL,
1412 },
1413 { "EEZ", "^PSU ", SCPI_DIALECT_UNKNOWN, 0,
1414 ARRAY_AND_SIZE(eez_psu_devopts),
1415 ARRAY_AND_SIZE(eez_psu_devopts_cg),
1416 NULL, 0,
1417 NULL, 0,
1418 eez_psu_cmd,
1419 .probe_channels = eez_psu_probe_channels,
1420 .init_acquisition = NULL,
1421 .update_status = NULL,
1422 },
1423
1424 /* Envox EEZ BB3 Series */
1425 { "Envox", "^BB3 ", SCPI_DIALECT_UNKNOWN, 0,
1426 ARRAY_AND_SIZE(eez_psu_devopts),
1427 ARRAY_AND_SIZE(eez_psu_devopts_cg),
1428 NULL, 0,
1429 NULL, 0,
1430 eez_psu_cmd,
1431 .probe_channels = eez_psu_probe_channels,
fd243315 1432 .init_acquisition = NULL,
7e66bf05 1433 .update_status = NULL,
5281993e 1434 },
ca314e06 1435
5ce427c7
FS		 1436 /*
1437 * This entry is for testing the HP COMP language with a HP 6632B power
1438 * supply switched to the COMP language ("SYST:LANG COMP"). When used,
1439 * disable the entry for the HP 6632B below!
1440 */
1441 /*
1442 { "HP", "6632B", SCPI_DIALECT_HP_COMP, 0,
1443 ARRAY_AND_SIZE(hp_6630a_devopts),
1444 ARRAY_AND_SIZE(hp_6630a_devopts_cg),
1445 ARRAY_AND_SIZE(hp_6632a_ch),
1446 ARRAY_AND_SIZE(hp_6630a_cg),
1447 hp_6630a_cmd,
1448 .probe_channels = NULL,
fd243315 1449 hp_6630a_init_acquisition,
5ce427c7
FS		 1450 hp_6630a_update_status,
1451 },
1452 */
1453
1454 /* HP 6632A */
1455 { "HP", "6632A", SCPI_DIALECT_HP_COMP, 0,
1456 ARRAY_AND_SIZE(hp_6630a_devopts),
1457 ARRAY_AND_SIZE(hp_6630a_devopts_cg),
1458 ARRAY_AND_SIZE(hp_6632a_ch),
1459 ARRAY_AND_SIZE(hp_6630a_cg),
1460 hp_6630a_cmd,
1461 .probe_channels = NULL,
fd243315 1462 hp_6630a_init_acquisition,
5ce427c7
FS		 1463 hp_6630a_update_status,
1464 },
1465
e76a3575 1466 /* HP 6633A */
5e7377f4 1467 { "HP", "6633A", SCPI_DIALECT_HP_COMP, 0,
e76a3575 1468 ARRAY_AND_SIZE(hp_6630a_devopts),
7c517d02 1469 ARRAY_AND_SIZE(hp_6630a_devopts_cg),
e76a3575 1470 ARRAY_AND_SIZE(hp_6633a_ch),
dbc519f7 1471 ARRAY_AND_SIZE(hp_6630a_cg),
e76a3575
AG		 1472 hp_6630a_cmd,
1473 .probe_channels = NULL,
fd243315 1474 hp_6630a_init_acquisition,
fdf03652 1475 hp_6630a_update_status,
e76a3575
AG		 1476 },
1477
5ce427c7
FS		 1478 /* HP 6634A */
1479 { "HP", "6634A", SCPI_DIALECT_HP_COMP, 0,
1480 ARRAY_AND_SIZE(hp_6630a_devopts),
1481 ARRAY_AND_SIZE(hp_6630a_devopts_cg),
1482 ARRAY_AND_SIZE(hp_6634a_ch),
1483 ARRAY_AND_SIZE(hp_6630a_cg),
1484 hp_6630a_cmd,
1485 .probe_channels = NULL,
fd243315 1486 hp_6630a_init_acquisition,
5ce427c7
FS		 1487 hp_6630a_update_status,
1488 },
1489
1490 /* HP 6611C */
1491 { "HP", "6611C", SCPI_DIALECT_HP_66XXB, PPS_OTP,
1492 ARRAY_AND_SIZE(hp_6630b_devopts),
1493 ARRAY_AND_SIZE(hp_6630b_devopts_cg),
1494 ARRAY_AND_SIZE(hp_6611c_ch),
1495 ARRAY_AND_SIZE(hp_6630b_cg),
1496 hp_6630b_cmd,
1497 .probe_channels = NULL,
fd243315 1498 hp_6630b_init_acquisition,
5ce427c7
FS		 1499 hp_6630b_update_status,
1500 },
1501
1502 /* HP 6612C */
1503 { "HP", "6612C", SCPI_DIALECT_HP_66XXB, PPS_OTP,
1504 ARRAY_AND_SIZE(hp_6630b_devopts),
1505 ARRAY_AND_SIZE(hp_6630b_devopts_cg),
1506 ARRAY_AND_SIZE(hp_6612c_ch),
1507 ARRAY_AND_SIZE(hp_6630b_cg),
1508 hp_6630b_cmd,
1509 .probe_channels = NULL,
fd243315 1510 hp_6630b_init_acquisition,
5ce427c7
FS		 1511 hp_6630b_update_status,
1512 },
1513
1514 /* HP 6613C */
1515 { "HP", "6613C", SCPI_DIALECT_HP_66XXB, PPS_OTP,
1516 ARRAY_AND_SIZE(hp_6630b_devopts),
1517 ARRAY_AND_SIZE(hp_6630b_devopts_cg),
1518 ARRAY_AND_SIZE(hp_6613c_ch),
1519 ARRAY_AND_SIZE(hp_6630b_cg),
1520 hp_6630b_cmd,
1521 .probe_channels = NULL,
fd243315 1522 hp_6630b_init_acquisition,
5ce427c7
FS		 1523 hp_6630b_update_status,
1524 },
1525
1526 /* HP 6614C */
1527 { "HP", "6614C", SCPI_DIALECT_HP_66XXB, PPS_OTP,
1528 ARRAY_AND_SIZE(hp_6630b_devopts),
1529 ARRAY_AND_SIZE(hp_6630b_devopts_cg),
1530 ARRAY_AND_SIZE(hp_6614c_ch),
1531 ARRAY_AND_SIZE(hp_6630b_cg),
1532 hp_6630b_cmd,
1533 .probe_channels = NULL,
fd243315 1534 hp_6630b_init_acquisition,
5ce427c7
FS		 1535 hp_6630b_update_status,
1536 },
1537
a61c8cce 1538 /* HP 6631B */
3d1aa50f 1539 { "HP", "6631B", SCPI_DIALECT_HP_66XXB, PPS_OTP,
a61c8cce
FS		 1540 ARRAY_AND_SIZE(hp_6630b_devopts),
1541 ARRAY_AND_SIZE(hp_6630b_devopts_cg),
1542 ARRAY_AND_SIZE(hp_6631b_ch),
dbc519f7 1543 ARRAY_AND_SIZE(hp_6630b_cg),
a61c8cce
FS		 1544 hp_6630b_cmd,
1545 .probe_channels = NULL,
fd243315 1546 hp_6630b_init_acquisition,
fe4bb774 1547 hp_6630b_update_status,
a61c8cce
FS		 1548 },
1549
bc4a2a46 1550 /* HP 6632B */
3d1aa50f 1551 { "HP", "6632B", SCPI_DIALECT_HP_66XXB, PPS_OTP,
a61c8cce
FS		 1552 ARRAY_AND_SIZE(hp_6630b_devopts),
1553 ARRAY_AND_SIZE(hp_6630b_devopts_cg),
bc4a2a46 1554 ARRAY_AND_SIZE(hp_6632b_ch),
dbc519f7 1555 ARRAY_AND_SIZE(hp_6630b_cg),
a61c8cce
FS		 1556 hp_6630b_cmd,
1557 .probe_channels = NULL,
fd243315 1558 hp_6630b_init_acquisition,
fe4bb774 1559 hp_6630b_update_status,
a61c8cce
FS		 1560 },
1561
0b0f40d8
MW		 1562 /* HP 66312A */
1563 { "HP", "66312A", SCPI_DIALECT_HP_66XXB, PPS_OTP,
1564 ARRAY_AND_SIZE(hp_6630b_devopts),
1565 ARRAY_AND_SIZE(hp_6630b_devopts_cg),
1566 ARRAY_AND_SIZE(hp_66312a_ch),
1567 ARRAY_AND_SIZE(hp_6630b_cg),
1568 hp_6630b_cmd,
1569 .probe_channels = NULL,
1570 hp_6630b_init_acquisition,
1571 hp_6630b_update_status,
1572 },
1573
a61c8cce 1574 /* HP 66332A */
3d1aa50f 1575 { "HP", "66332A", SCPI_DIALECT_HP_66XXB, PPS_OTP,
a61c8cce
FS		 1576 ARRAY_AND_SIZE(hp_6630b_devopts),
1577 ARRAY_AND_SIZE(hp_6630b_devopts_cg),
1578 ARRAY_AND_SIZE(hp_66332a_ch),
dbc519f7 1579 ARRAY_AND_SIZE(hp_6630b_cg),
a61c8cce
FS		 1580 hp_6630b_cmd,
1581 .probe_channels = NULL,
fd243315 1582 hp_6630b_init_acquisition,
fe4bb774 1583 hp_6630b_update_status,
a61c8cce
FS		 1584 },
1585
1586 /* HP 6633B */
3d1aa50f 1587 { "HP", "6633B", SCPI_DIALECT_HP_66XXB, PPS_OTP,
a61c8cce
FS		 1588 ARRAY_AND_SIZE(hp_6630b_devopts),
1589 ARRAY_AND_SIZE(hp_6630b_devopts_cg),
1590 ARRAY_AND_SIZE(hp_6633b_ch),
dbc519f7 1591 ARRAY_AND_SIZE(hp_6630b_cg),
a61c8cce
FS		 1592 hp_6630b_cmd,
1593 .probe_channels = NULL,
fd243315 1594 hp_6630b_init_acquisition,
fe4bb774 1595 hp_6630b_update_status,
a61c8cce
FS		 1596 },
1597
1598 /* HP 6634B */
3d1aa50f 1599 { "HP", "6634B", SCPI_DIALECT_HP_66XXB, PPS_OTP,
a61c8cce
FS		 1600 ARRAY_AND_SIZE(hp_6630b_devopts),
1601 ARRAY_AND_SIZE(hp_6630b_devopts_cg),
1602 ARRAY_AND_SIZE(hp_6634b_ch),
dbc519f7 1603 ARRAY_AND_SIZE(hp_6630b_cg),
a61c8cce 1604 hp_6630b_cmd,
c3eadb07 1605 .probe_channels = NULL,
fd243315 1606 hp_6630b_init_acquisition,
fe4bb774 1607 hp_6630b_update_status,
bc4a2a46
BV		 1608 },
1609
319fe9ce 1610 /* Rigol DP700 series */
5e7377f4 1611 { "Rigol", "^DP711$", SCPI_DIALECT_UNKNOWN, 0,
319fe9ce
UH		 1612 ARRAY_AND_SIZE(rigol_dp700_devopts),
1613 ARRAY_AND_SIZE(rigol_dp700_devopts_cg),
1614 ARRAY_AND_SIZE(rigol_dp711_ch),
1615 ARRAY_AND_SIZE(rigol_dp700_cg),
1616 rigol_dp700_cmd,
1617 .probe_channels = NULL,
fd243315 1618 .init_acquisition = NULL,
7e66bf05 1619 .update_status = NULL,
319fe9ce 1620 },
5e7377f4 1621 { "Rigol", "^DP712$", SCPI_DIALECT_UNKNOWN, 0,
319fe9ce
UH		 1622 ARRAY_AND_SIZE(rigol_dp700_devopts),
1623 ARRAY_AND_SIZE(rigol_dp700_devopts_cg),
1624 ARRAY_AND_SIZE(rigol_dp712_ch),
1625 ARRAY_AND_SIZE(rigol_dp700_cg),
1626 rigol_dp700_cmd,
1627 .probe_channels = NULL,
fd243315 1628 .init_acquisition = NULL,
7e66bf05 1629 .update_status = NULL,
319fe9ce
UH		 1630 },
1631
d4eabea8 1632 /* Rigol DP800 series */
5e7377f4 1633 { "Rigol", "^DP821A$", SCPI_DIALECT_UNKNOWN, PPS_OTP,
cfcdf576
ML		 1634 ARRAY_AND_SIZE(rigol_dp800_devopts),
1635 ARRAY_AND_SIZE(rigol_dp800_devopts_cg),
1636 ARRAY_AND_SIZE(rigol_dp821a_ch),
1637 ARRAY_AND_SIZE(rigol_dp820_cg),
91ef511d 1638 rigol_dp800_cmd,
cfcdf576 1639 .probe_channels = NULL,
fd243315 1640 .init_acquisition = NULL,
7e66bf05 1641 .update_status = NULL,
cfcdf576 1642 },
5e7377f4 1643 { "Rigol", "^DP831A$", SCPI_DIALECT_UNKNOWN, PPS_OTP,
3222ee10
BV		 1644 ARRAY_AND_SIZE(rigol_dp800_devopts),
1645 ARRAY_AND_SIZE(rigol_dp800_devopts_cg),
1646 ARRAY_AND_SIZE(rigol_dp831_ch),
cfcdf576 1647 ARRAY_AND_SIZE(rigol_dp830_cg),
91ef511d 1648 rigol_dp800_cmd,
c3eadb07 1649 .probe_channels = NULL,
fd243315 1650 .init_acquisition = NULL,
7e66bf05 1651 .update_status = NULL,
3222ee10 1652 },
5e7377f4 1653 { "Rigol", "^(DP832|DP832A)$", SCPI_DIALECT_UNKNOWN, PPS_OTP,
3222ee10
BV		 1654 ARRAY_AND_SIZE(rigol_dp800_devopts),
1655 ARRAY_AND_SIZE(rigol_dp800_devopts_cg),
1656 ARRAY_AND_SIZE(rigol_dp832_ch),
cfcdf576 1657 ARRAY_AND_SIZE(rigol_dp830_cg),
91ef511d 1658 rigol_dp800_cmd,
c3eadb07 1659 .probe_channels = NULL,
fd243315 1660 .init_acquisition = NULL,
7e66bf05 1661 .update_status = NULL,
c3eadb07
BV		 1662 },
1663
5433907e
PA		 1664 /* Owon P4000 series */
1665 { "OWON", "^P4305$", SCPI_DIALECT_UNKNOWN, 0,
1666 ARRAY_AND_SIZE(owon_p4000_devopts),
1667 ARRAY_AND_SIZE(owon_p4000_devopts_cg),
1668 ARRAY_AND_SIZE(owon_p4305_ch),
1669 ARRAY_AND_SIZE(owon_p4000_cg),
1670 owon_p4000_cmd,
1671 .probe_channels = NULL,
1672 .init_acquisition = NULL,
1673 .update_status = NULL,
1674 },
1675 { "OWON", "^P4603$", SCPI_DIALECT_UNKNOWN, 0,
1676 ARRAY_AND_SIZE(owon_p4000_devopts),
1677 ARRAY_AND_SIZE(owon_p4000_devopts_cg),
1678 ARRAY_AND_SIZE(owon_p4603_ch),
1679 ARRAY_AND_SIZE(owon_p4000_cg),
1680 owon_p4000_cmd,
1681 .probe_channels = NULL,
1682 .init_acquisition = NULL,
1683 .update_status = NULL,
1684 },
1685
c3eadb07 1686 /* Philips/Fluke PM2800 series */
5e7377f4 1687 { "Philips", "^PM28[13][123]/[01234]{1,2}$", SCPI_DIALECT_PHILIPS, 0,
9d9cf1c4 1688 ARRAY_AND_SIZE(philips_pm2800_devopts),
c3eadb07
BV		 1689 ARRAY_AND_SIZE(philips_pm2800_devopts_cg),
1690 NULL, 0,
1691 NULL, 0,
91ef511d 1692 philips_pm2800_cmd,
c3eadb07 1693 philips_pm2800_probe_channels,
fd243315 1694 .init_acquisition = NULL,
7e66bf05 1695 .update_status = NULL,
d4eabea8 1696 },
81eb36d6
MS		 1697
1698 /* Rohde & Schwarz HMC8043 */
5e7377f4 1699 { "Rohde&Schwarz", "HMC8043", SCPI_DIALECT_UNKNOWN, 0,
81eb36d6
MS		 1700 ARRAY_AND_SIZE(rs_hmc8043_devopts),
1701 ARRAY_AND_SIZE(rs_hmc8043_devopts_cg),
1702 ARRAY_AND_SIZE(rs_hmc8043_ch),
1703 ARRAY_AND_SIZE(rs_hmc8043_cg),
1704 rs_hmc8043_cmd,
1705 .probe_channels = NULL,
fd243315 1706 .init_acquisition = NULL,
7e66bf05 1707 .update_status = NULL,
81eb36d6 1708 },
bd5f0a14
FS		 1709
1710 /* Hameg / Rohde&Schwarz HMP4000 series */
22f76e18
GS		 1711 /* TODO Match on regex, pass scpi_pps item to .probe_channels(). */
1712 { "HAMEG", "HMP4030", SCPI_DIALECT_HMP, 0,
1713 ARRAY_AND_SIZE(rs_hmp4040_devopts),
1714 ARRAY_AND_SIZE(rs_hmp4040_devopts_cg),
1715 rs_hmp4040_ch, 3,
1716 rs_hmp4040_cg, 3,
1717 rs_hmp4040_cmd,
1718 .probe_channels = NULL,
f403cb9d 1719 .init_acquisition = NULL,
22f76e18
GS		 1720 .update_status = NULL,
1721 },
bd5f0a14
FS		 1722 { "HAMEG", "HMP4040", SCPI_DIALECT_HMP, 0,
1723 ARRAY_AND_SIZE(rs_hmp4040_devopts),
1724 ARRAY_AND_SIZE(rs_hmp4040_devopts_cg),
1725 ARRAY_AND_SIZE(rs_hmp4040_ch),
1726 ARRAY_AND_SIZE(rs_hmp4040_cg),
1727 rs_hmp4040_cmd,
1728 .probe_channels = NULL,
f403cb9d 1729 .init_acquisition = NULL,
bd5f0a14
FS		 1730 .update_status = NULL,
1731 },
1c5d5905
GS		 1732 { "ROHDE&SCHWARZ", "HMP2020", SCPI_DIALECT_HMP, 0,
1733 ARRAY_AND_SIZE(rs_hmp4040_devopts),
1734 ARRAY_AND_SIZE(rs_hmp4040_devopts_cg),
1735 rs_hmp2020_ch, 2,
1736 rs_hmp4040_cg, 2,
1737 rs_hmp4040_cmd,
1738 .probe_channels = NULL,
1739 .init_acquisition = NULL,
1740 .update_status = NULL,
1741 },
1742 { "ROHDE&SCHWARZ", "HMP2030", SCPI_DIALECT_HMP, 0,
1743 ARRAY_AND_SIZE(rs_hmp4040_devopts),
1744 ARRAY_AND_SIZE(rs_hmp4040_devopts_cg),
1745 rs_hmp2030_ch, 3,
1746 rs_hmp4040_cg, 3,
1747 rs_hmp4040_cmd,
1748 .probe_channels = NULL,
1749 .init_acquisition = NULL,
1750 .update_status = NULL,
1751 },
22f76e18
GS		 1752 { "ROHDE&SCHWARZ", "HMP4030", SCPI_DIALECT_HMP, 0,
1753 ARRAY_AND_SIZE(rs_hmp4040_devopts),
1754 ARRAY_AND_SIZE(rs_hmp4040_devopts_cg),
1755 rs_hmp4040_ch, 3,
1756 rs_hmp4040_cg, 3,
1757 rs_hmp4040_cmd,
1758 .probe_channels = NULL,
f403cb9d 1759 .init_acquisition = NULL,
22f76e18
GS		 1760 .update_status = NULL,
1761 },
1762 { "ROHDE&SCHWARZ", "HMP4040", SCPI_DIALECT_HMP, 0,
1763 ARRAY_AND_SIZE(rs_hmp4040_devopts),
1764 ARRAY_AND_SIZE(rs_hmp4040_devopts_cg),
1765 ARRAY_AND_SIZE(rs_hmp4040_ch),
1766 ARRAY_AND_SIZE(rs_hmp4040_cg),
1767 rs_hmp4040_cmd,
1768 .probe_channels = NULL,
f403cb9d 1769 .init_acquisition = NULL,
22f76e18
GS		 1770 .update_status = NULL,
1771 },
d4eabea8 1772};
d4eabea8 1773
1beccaed 1774SR_PRIV unsigned int num_pps_profiles = ARRAY_SIZE(pps_profiles);
Hardware access and backend lib