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scpi-pps: Add configurable sr_mqflags.
[libsigrok.git] / src / hardware / scpi-pps / profiles.c
CommitLineData
d4eabea8
BV		 1/*
2 * This file is part of the libsigrok project.
3 *
4 * Copyright (C) 2014 Bert Vermeulen <bert@biot.com>
4ee1e2f3
AG		 5 * Copyright (C) 2015 Google, Inc.
6 * (Written by Alexandru Gagniuc <mrnuke@google.com> for Google, Inc.)
7e66bf05 7 * Copyright (C) 2017,2019 Frank Stettner <frank-stettner@gmx.net>
d4eabea8
BV		 8 *
9 * This program is free software: you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation, either version 3 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program. If not, see <http://www.gnu.org/licenses/>.
21 */
22
6ec6c43b 23#include <config.h>
22c18b03 24#include <string.h>
ba464a12 25#include <strings.h>
d4eabea8
BV		 26#include "protocol.h"
27
28#define CH_IDX(x) (1 << x)
6ed709fe 29#define FREQ_DC_ONLY {0, 0, 0, 0, 0}
49a468ed
FS		 30#define NO_OVP_LIMITS {0, 0, 0, 0, 0}
31#define NO_OCP_LIMITS {0, 0, 0, 0, 0}
d4eabea8 32
5c9e56c9
AG		 33/* Agilent/Keysight N5700A series */
34static const uint32_t agilent_n5700a_devopts[] = {
e91bb0a6 35 SR_CONF_CONTINUOUS,
88e4daa9
ML		 36 SR_CONF_LIMIT_SAMPLES | SR_CONF_GET | SR_CONF_SET,
37 SR_CONF_LIMIT_MSEC | SR_CONF_GET | SR_CONF_SET,
5c9e56c9
AG		 38};
39
40static const uint32_t agilent_n5700a_devopts_cg[] = {
41 SR_CONF_OVER_VOLTAGE_PROTECTION_THRESHOLD | SR_CONF_GET | SR_CONF_SET,
42 SR_CONF_OVER_CURRENT_PROTECTION_ENABLED | SR_CONF_GET | SR_CONF_SET,
43 SR_CONF_OVER_CURRENT_PROTECTION_THRESHOLD | SR_CONF_GET | SR_CONF_SET,
da005885
UH		 44 SR_CONF_VOLTAGE | SR_CONF_GET,
45 SR_CONF_VOLTAGE_TARGET | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
46 SR_CONF_CURRENT | SR_CONF_GET,
47 SR_CONF_ENABLED | SR_CONF_GET | SR_CONF_SET,
5c9e56c9
AG		 48};
49
6cc93128 50static const struct channel_group_spec agilent_n5700a_cg[] = {
f2bbcc33 51 { "1", CH_IDX(0), PPS_OVP | PPS_OCP, SR_MQFLAG_DC },
6cc93128
AG		 52};
53
8cb5affe 54static const struct channel_spec agilent_n5767a_ch[] = {
49a468ed 55 { "1", { 0, 60, 0.0072, 3, 4 }, { 0, 25, 0.003, 3, 4 }, { 0, 1500 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS },
5c9e56c9
AG		 56};
57
6cc93128 58static const struct channel_spec agilent_n5763a_ch[] = {
49a468ed 59 { "1", { 0, 12.5, 0.0015, 3, 4 }, { 0, 120, 0.0144, 3, 4 }, { 0, 1500 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS },
5c9e56c9
AG		 60};
61
62/*
63 * TODO: OVER_CURRENT_PROTECTION_ACTIVE status can be determined by the OC bit
562a3490 64 * in STAT:QUES:EVEN?, but this is not implemented.
5c9e56c9 65 */
8cb5affe 66static const struct scpi_command agilent_n5700a_cmd[] = {
5c9e56c9
AG		 67 { SCPI_CMD_REMOTE, "SYST:COMM:RLST REM" },
68 { SCPI_CMD_LOCAL, "SYST:COMM:RLST LOC" },
69 { SCPI_CMD_GET_MEAS_VOLTAGE, ":MEAS:VOLT?" },
70 { SCPI_CMD_GET_MEAS_CURRENT, "MEAS:CURR?" },
71 { SCPI_CMD_GET_VOLTAGE_TARGET, ":SOUR:VOLT?" },
72 { SCPI_CMD_SET_VOLTAGE_TARGET, ":SOUR:VOLT %.6f" },
73 { SCPI_CMD_GET_CURRENT_LIMIT, ":SOUR:CURR?" },
74 { SCPI_CMD_SET_CURRENT_LIMIT, ":SOUR:CURR %.6f" },
75 { SCPI_CMD_GET_OUTPUT_ENABLED, ":OUTP:STAT?" },
76 { SCPI_CMD_SET_OUTPUT_ENABLE, ":OUTP ON" },
77 { SCPI_CMD_SET_OUTPUT_DISABLE, ":OUTP OFF" },
78 { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_THRESHOLD, ":VOLT:PROT?" },
79 { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_THRESHOLD, ":VOLT:PROT %.6f" },
80 { SCPI_CMD_GET_OVER_CURRENT_PROTECTION_ENABLED, ":CURR:PROT:STAT?" },
81 { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_ENABLE, ":CURR:PROT:STAT ON?"},
82 { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_DISABLE, ":CURR:PROT:STAT OFF?"},
562a3490 83 /* Current limit (CC mode) and OCP are set using the same command. */
5c9e56c9
AG		 84 { SCPI_CMD_GET_OVER_CURRENT_PROTECTION_THRESHOLD, ":SOUR:CURR?" },
85 { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_THRESHOLD, ":SOUR:CURR %.6f" },
91ef511d 86 ALL_ZERO
5c9e56c9
AG		 87};
88
c3bfb959
MW		 89/* BK Precision 9130 series */
90static const uint32_t bk_9130_devopts[] = {
91 SR_CONF_CONTINUOUS,
92 SR_CONF_LIMIT_SAMPLES | SR_CONF_GET | SR_CONF_SET,
93 SR_CONF_LIMIT_MSEC | SR_CONF_GET | SR_CONF_SET,
94};
95
96static const uint32_t bk_9130_devopts_cg[] = {
97 SR_CONF_OVER_VOLTAGE_PROTECTION_THRESHOLD | SR_CONF_GET | SR_CONF_SET,
98 SR_CONF_VOLTAGE | SR_CONF_GET,
99 SR_CONF_VOLTAGE_TARGET | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
100 SR_CONF_CURRENT | SR_CONF_GET,
101 SR_CONF_CURRENT_LIMIT | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
102 SR_CONF_ENABLED | SR_CONF_GET | SR_CONF_SET,
103};
104
105static const struct channel_spec bk_9130_ch[] = {
106 { "1", { 0, 30, 0.001, 3, 3 }, { 0, 3, 0.001, 3, 3 }, { 0, 90, 0, 3, 3 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS },
107 { "2", { 0, 30, 0.001, 3, 3 }, { 0, 3, 0.001, 3, 3 }, { 0, 90, 0, 3, 3 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS },
108 { "3", { 0, 5, 0.001, 3, 3 }, { 0, 3, 0.001, 3, 3 }, { 0, 15, 0, 3, 3 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS },
109};
110
111static const struct channel_group_spec bk_9130_cg[] = {
f2bbcc33
FS		 112 { "1", CH_IDX(0), PPS_OVP, SR_MQFLAG_DC },
113 { "2", CH_IDX(1), PPS_OVP, SR_MQFLAG_DC },
114 { "3", CH_IDX(2), PPS_OVP, SR_MQFLAG_DC },
c3bfb959
MW		 115};
116
117static const struct scpi_command bk_9130_cmd[] = {
118 { SCPI_CMD_REMOTE, "SYST:REMOTE" },
119 { SCPI_CMD_LOCAL, "SYST:LOCAL" },
120 { SCPI_CMD_SELECT_CHANNEL, ":INST:NSEL %s" },
121 { SCPI_CMD_GET_MEAS_VOLTAGE, ":MEAS:VOLT?" },
122 { SCPI_CMD_GET_MEAS_CURRENT, ":MEAS:CURR?" },
123 { SCPI_CMD_GET_MEAS_POWER, ":MEAS:POWER?" },
124 { SCPI_CMD_GET_VOLTAGE_TARGET, ":SOUR:VOLT?" },
125 { SCPI_CMD_SET_VOLTAGE_TARGET, ":SOUR:VOLT %.6f" },
126 { SCPI_CMD_GET_CURRENT_LIMIT, ":SOUR:CURR?" },
127 { SCPI_CMD_SET_CURRENT_LIMIT, ":SOUR:CURR %.6f" },
128 { SCPI_CMD_GET_OUTPUT_ENABLED, ":OUTP?" },
129 { SCPI_CMD_SET_OUTPUT_ENABLE, ":OUTP 1" },
130 { SCPI_CMD_SET_OUTPUT_DISABLE, ":OUTP 0" },
131 { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_THRESHOLD, ":SOUR:VOLT:PROT?" },
132 { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_THRESHOLD, ":SOUR:VOLT:PROT %.6f" },
133 ALL_ZERO
134};
135
4ee1e2f3
AG		 136/* Chroma 61600 series AC source */
137static const uint32_t chroma_61604_devopts[] = {
e91bb0a6 138 SR_CONF_CONTINUOUS,
88e4daa9
ML		 139 SR_CONF_LIMIT_SAMPLES | SR_CONF_GET | SR_CONF_SET,
140 SR_CONF_LIMIT_MSEC | SR_CONF_GET | SR_CONF_SET,
4ee1e2f3
AG		 141};
142
143static const uint32_t chroma_61604_devopts_cg[] = {
144 SR_CONF_OVER_VOLTAGE_PROTECTION_THRESHOLD | SR_CONF_GET | SR_CONF_SET,
145 SR_CONF_OVER_CURRENT_PROTECTION_THRESHOLD | SR_CONF_GET | SR_CONF_SET,
da005885
UH		 146 SR_CONF_VOLTAGE | SR_CONF_GET,
147 SR_CONF_VOLTAGE_TARGET | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
6c0c9dd2
AG		 148 SR_CONF_OUTPUT_FREQUENCY | SR_CONF_GET,
149 SR_CONF_OUTPUT_FREQUENCY_TARGET | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
da005885
UH		 150 SR_CONF_CURRENT | SR_CONF_GET,
151 SR_CONF_ENABLED | SR_CONF_GET | SR_CONF_SET,
4ee1e2f3
AG		 152};
153
8cb5affe 154static const struct channel_spec chroma_61604_ch[] = {
49a468ed 155 { "1", { 0, 300, 0.1, 1, 1 }, { 0, 16, 0.1, 2, 2 }, { 0, 2000, 0, 1, 1 }, { 1.0, 1000.0, 0.01 }, NO_OVP_LIMITS, NO_OCP_LIMITS },
4ee1e2f3
AG		 156};
157
8cb5affe 158static const struct channel_group_spec chroma_61604_cg[] = {
f2bbcc33 159 { "1", CH_IDX(0), PPS_OVP | PPS_OCP, SR_MQFLAG_AC },
4ee1e2f3
AG		 160};
161
8cb5affe 162static const struct scpi_command chroma_61604_cmd[] = {
4ee1e2f3
AG		 163 { SCPI_CMD_REMOTE, "SYST:REM" },
164 { SCPI_CMD_LOCAL, "SYST:LOC" },
165 { SCPI_CMD_GET_MEAS_VOLTAGE, ":FETC:VOLT:ACDC?" },
6c0c9dd2 166 { SCPI_CMD_GET_MEAS_FREQUENCY, ":FETC:FREQ?" },
4ee1e2f3
AG		 167 { SCPI_CMD_GET_MEAS_CURRENT, ":FETC:CURR:AC?" },
168 { SCPI_CMD_GET_MEAS_POWER, ":FETC:POW:AC?" },
169 { SCPI_CMD_GET_VOLTAGE_TARGET, ":SOUR:VOLT:AC?" },
170 { SCPI_CMD_SET_VOLTAGE_TARGET, ":SOUR:VOLT:AC %.1f" },
6c0c9dd2
AG		 171 { SCPI_CMD_GET_FREQUENCY_TARGET, ":SOUR:FREQ?" },
172 { SCPI_CMD_SET_FREQUENCY_TARGET, ":SOUR:FREQ %.2f" },
4ee1e2f3
AG		 173 { SCPI_CMD_GET_OUTPUT_ENABLED, ":OUTP?" },
174 { SCPI_CMD_SET_OUTPUT_ENABLE, ":OUTP ON" },
175 { SCPI_CMD_SET_OUTPUT_DISABLE, ":OUTP OFF" },
176 { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_THRESHOLD, ":SOUR:VOLT:LIM:AC?" },
177 { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_THRESHOLD, ":SOUR:VOLT:LIM:AC %.1f" },
562a3490 178 /* This is not a current limit mode. It is overcurrent protection. */
4ee1e2f3
AG		 179 { SCPI_CMD_GET_OVER_CURRENT_PROTECTION_THRESHOLD, ":SOUR:CURR:LIM?" },
180 { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_THRESHOLD, ":SOUR:CURR:LIM %.2f" },
91ef511d 181 ALL_ZERO
4ee1e2f3
AG		 182};
183
5281993e 184/* Chroma 62000 series DC source */
5281993e 185static const uint32_t chroma_62000_devopts[] = {
e91bb0a6 186 SR_CONF_CONTINUOUS,
88e4daa9
ML		 187 SR_CONF_LIMIT_SAMPLES | SR_CONF_GET | SR_CONF_SET,
188 SR_CONF_LIMIT_MSEC | SR_CONF_GET | SR_CONF_SET,
5281993e
AG		 189};
190
191static const uint32_t chroma_62000_devopts_cg[] = {
192 SR_CONF_OVER_VOLTAGE_PROTECTION_THRESHOLD | SR_CONF_GET | SR_CONF_SET,
193 SR_CONF_OVER_CURRENT_PROTECTION_THRESHOLD | SR_CONF_GET | SR_CONF_SET,
194 SR_CONF_VOLTAGE | SR_CONF_GET,
195 SR_CONF_VOLTAGE_TARGET | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
196 SR_CONF_CURRENT | SR_CONF_GET,
197 SR_CONF_CURRENT_LIMIT | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
198 SR_CONF_ENABLED | SR_CONF_GET | SR_CONF_SET,
199};
200
5281993e 201static const struct channel_group_spec chroma_62000_cg[] = {
f2bbcc33 202 { "1", CH_IDX(0), PPS_OVP | PPS_OCP, SR_MQFLAG_DC },
5281993e
AG		 203};
204
205static const struct scpi_command chroma_62000_cmd[] = {
206 { SCPI_CMD_REMOTE, ":CONF:REM ON" },
207 { SCPI_CMD_LOCAL, ":CONF:REM OFF" },
208 { SCPI_CMD_BEEPER, ":CONF:BEEP?" },
209 { SCPI_CMD_BEEPER_ENABLE, ":CONF:BEEP ON" },
210 { SCPI_CMD_BEEPER_DISABLE, ":CONF:BEEP OFF" },
211 { SCPI_CMD_GET_MEAS_VOLTAGE, ":MEAS:VOLT?" },
212 { SCPI_CMD_GET_MEAS_CURRENT, ":MEAS:CURR?" },
213 { SCPI_CMD_GET_MEAS_POWER, ":MEAS:POW?" },
214 { SCPI_CMD_GET_VOLTAGE_TARGET, ":SOUR:VOLT?" },
215 { SCPI_CMD_SET_VOLTAGE_TARGET, ":SOUR:VOLT %.2f" },
216 { SCPI_CMD_GET_CURRENT_LIMIT, ":SOUR:CURR?" },
217 { SCPI_CMD_SET_CURRENT_LIMIT, ":SOUR:CURR %.6f" },
218 { SCPI_CMD_GET_OUTPUT_ENABLED, ":CONF:OUTP?" },
219 { SCPI_CMD_SET_OUTPUT_ENABLE, ":CONF:OUTP ON" },
220 { SCPI_CMD_SET_OUTPUT_DISABLE, ":CONF:OUTP OFF" },
221 { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_THRESHOLD, ":SOUR:VOLT:PROT:HIGH?" },
222 { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_THRESHOLD, ":SOUR:VOLT:PROT:HIGH %.6f" },
223 { SCPI_CMD_GET_OVER_CURRENT_PROTECTION_THRESHOLD, ":SOUR:CURR:PROT:HIGH?" },
224 { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_THRESHOLD, ":SOUR:CURR:PROT:HIGH %.6f" },
91ef511d 225 ALL_ZERO
5281993e
AG		 226};
227
9a5185c7
AG		 228static int chroma_62000p_probe_channels(struct sr_dev_inst *sdi,
229 struct sr_scpi_hw_info *hw_info,
230 struct channel_spec **channels, unsigned int *num_channels,
231 struct channel_group_spec **channel_groups,
232 unsigned int *num_channel_groups)
233{
6ed709fe 234 unsigned int volts, amps, watts;
9a5185c7
AG		 235 struct channel_spec *channel;
236
237 (void)sdi;
238
6ed709fe
AJ		 239 sscanf(hw_info->model, "620%uP-%u-%u", &watts, &volts, &amps);
240 watts *= 100;
241 sr_dbg("Found device rated for %d V, %d A and %d W", volts, amps, watts);
9a5185c7
AG		 242
243 if (volts > 600) {
244 sr_err("Probed max voltage of %u V is out of spec.", volts);
245 return SR_ERR_BUG;
246 }
247
6ed709fe 248 if (amps > 120) {
9a5185c7
AG		 249 sr_err("Probed max current of %u A is out of spec.", amps);
250 return SR_ERR_BUG;
251 }
252
6ed709fe
AJ		 253 if (watts > 5000) {
254 sr_err("Probed max power of %u W is out of spec.", watts);
255 return SR_ERR_BUG;
256 }
257
9a5185c7
AG		 258 channel = g_malloc0(sizeof(struct channel_spec));
259 channel->name = "1";
6ed709fe 260 channel->voltage[0] = channel->current[0] = channel->power[0] = 0.0;
bcee1299
UH		 261 channel->voltage[1] = volts;
262 channel->current[1] = amps;
263 channel->power[1] = watts;
9a5185c7 264 channel->voltage[2] = channel->current[2] = 0.01;
6ed709fe
AJ		 265 channel->voltage[3] = channel->voltage[4] = 3;
266 channel->current[3] = channel->current[4] = 4;
9a5185c7
AG		 267 *channels = channel;
268 *num_channels = 1;
269
270 *channel_groups = g_malloc(sizeof(struct channel_group_spec));
271 **channel_groups = chroma_62000_cg[0];
272 *num_channel_groups = 1;
273
274 return SR_OK;
275}
276
319fe9ce
UH		 277/* Rigol DP700 series */
278static const uint32_t rigol_dp700_devopts[] = {
279 SR_CONF_CONTINUOUS,
88e4daa9
ML		 280 SR_CONF_LIMIT_SAMPLES | SR_CONF_GET | SR_CONF_SET,
281 SR_CONF_LIMIT_MSEC | SR_CONF_GET | SR_CONF_SET,
319fe9ce
UH		 282};
283
284static const uint32_t rigol_dp700_devopts_cg[] = {
285 SR_CONF_REGULATION | SR_CONF_GET,
286 SR_CONF_OVER_VOLTAGE_PROTECTION_ENABLED | SR_CONF_GET | SR_CONF_SET,
287 SR_CONF_OVER_VOLTAGE_PROTECTION_ACTIVE | SR_CONF_GET,
d828b05e 288 SR_CONF_OVER_VOLTAGE_PROTECTION_THRESHOLD | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
319fe9ce
UH		 289 SR_CONF_OVER_CURRENT_PROTECTION_ENABLED | SR_CONF_GET | SR_CONF_SET,
290 SR_CONF_OVER_CURRENT_PROTECTION_ACTIVE | SR_CONF_GET,
d828b05e 291 SR_CONF_OVER_CURRENT_PROTECTION_THRESHOLD | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
319fe9ce
UH		 292 SR_CONF_VOLTAGE | SR_CONF_GET,
293 SR_CONF_VOLTAGE_TARGET | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
294 SR_CONF_CURRENT | SR_CONF_GET,
295 SR_CONF_CURRENT_LIMIT | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
296 SR_CONF_ENABLED | SR_CONF_GET | SR_CONF_SET,
297};
298
299static const struct channel_spec rigol_dp711_ch[] = {
d828b05e 300 { "1", { 0, 30, 0.01, 3, 3 }, { 0, 5, 0.01, 3, 3 }, { 0, 150, 0, 3, 3 }, FREQ_DC_ONLY, { 0.01, 33, 0.01}, { 0.01, 5.5, 0.01 } },
319fe9ce
UH		 301};
302
303static const struct channel_spec rigol_dp712_ch[] = {
d828b05e 304 { "1", { 0, 50, 0.01, 3, 3 }, { 0, 3, 0.01, 3, 3 }, { 0, 150, 0, 3, 3 }, FREQ_DC_ONLY, { 0.01, 55, 0.01}, { 0.01, 3.3, 0.01 } },
319fe9ce
UH		 305};
306
307static const struct channel_group_spec rigol_dp700_cg[] = {
f2bbcc33 308 { "1", CH_IDX(0), PPS_OVP | PPS_OCP, SR_MQFLAG_DC },
319fe9ce
UH		 309};
310
311/* Same as the DP800 series, except for the missing :SYST:OTP* commands. */
312static const struct scpi_command rigol_dp700_cmd[] = {
313 { SCPI_CMD_REMOTE, "SYST:REMOTE" },
314 { SCPI_CMD_LOCAL, "SYST:LOCAL" },
315 { SCPI_CMD_BEEPER, "SYST:BEEP:STAT?" },
316 { SCPI_CMD_BEEPER_ENABLE, "SYST:BEEP:STAT ON" },
317 { SCPI_CMD_BEEPER_DISABLE, "SYST:BEEP:STAT OFF" },
318 { SCPI_CMD_SELECT_CHANNEL, ":INST:NSEL %s" },
319 { SCPI_CMD_GET_MEAS_VOLTAGE, ":MEAS:VOLT?" },
320 { SCPI_CMD_GET_MEAS_CURRENT, ":MEAS:CURR?" },
321 { SCPI_CMD_GET_MEAS_POWER, ":MEAS:POWE?" },
322 { SCPI_CMD_GET_VOLTAGE_TARGET, ":SOUR:VOLT?" },
323 { SCPI_CMD_SET_VOLTAGE_TARGET, ":SOUR:VOLT %.6f" },
324 { SCPI_CMD_GET_CURRENT_LIMIT, ":SOUR:CURR?" },
325 { SCPI_CMD_SET_CURRENT_LIMIT, ":SOUR:CURR %.6f" },
326 { SCPI_CMD_GET_OUTPUT_ENABLED, ":OUTP?" },
327 { SCPI_CMD_SET_OUTPUT_ENABLE, ":OUTP ON" },
328 { SCPI_CMD_SET_OUTPUT_DISABLE, ":OUTP OFF" },
329 { SCPI_CMD_GET_OUTPUT_REGULATION, ":OUTP:MODE?" },
330 { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_ENABLED, ":OUTP:OVP?" },
331 { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_ENABLE, ":OUTP:OVP ON" },
332 { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_DISABLE, ":OUTP:OVP OFF" },
333 { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_ACTIVE, ":OUTP:OVP:QUES?" },
334 { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_THRESHOLD, ":OUTP:OVP:VAL?" },
335 { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_THRESHOLD, ":OUTP:OVP:VAL %.6f" },
336 { SCPI_CMD_GET_OVER_CURRENT_PROTECTION_ENABLED, ":OUTP:OCP?" },
337 { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_ENABLE, ":OUTP:OCP:STAT ON" },
338 { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_DISABLE, ":OUTP:OCP:STAT OFF" },
339 { SCPI_CMD_GET_OVER_CURRENT_PROTECTION_ACTIVE, ":OUTP:OCP:QUES?" },
340 { SCPI_CMD_GET_OVER_CURRENT_PROTECTION_THRESHOLD, ":OUTP:OCP:VAL?" },
341 { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_THRESHOLD, ":OUTP:OCP:VAL %.6f" },
342 ALL_ZERO
343};
344
d4eabea8 345/* Rigol DP800 series */
584560f1 346static const uint32_t rigol_dp800_devopts[] = {
e91bb0a6 347 SR_CONF_CONTINUOUS,
5827f61b 348 SR_CONF_OVER_TEMPERATURE_PROTECTION | SR_CONF_GET | SR_CONF_SET,
88e4daa9
ML		 349 SR_CONF_LIMIT_SAMPLES | SR_CONF_GET | SR_CONF_SET,
350 SR_CONF_LIMIT_MSEC | SR_CONF_GET | SR_CONF_SET,
d4eabea8
BV		 351};
352
584560f1 353static const uint32_t rigol_dp800_devopts_cg[] = {
7a0b98b5 354 SR_CONF_REGULATION | SR_CONF_GET,
5827f61b
BV		 355 SR_CONF_OVER_VOLTAGE_PROTECTION_ENABLED | SR_CONF_GET | SR_CONF_SET,
356 SR_CONF_OVER_VOLTAGE_PROTECTION_ACTIVE | SR_CONF_GET,
357 SR_CONF_OVER_VOLTAGE_PROTECTION_THRESHOLD | SR_CONF_GET | SR_CONF_SET,
358 SR_CONF_OVER_CURRENT_PROTECTION_ENABLED | SR_CONF_GET | SR_CONF_SET,
359 SR_CONF_OVER_CURRENT_PROTECTION_ACTIVE | SR_CONF_GET,
360 SR_CONF_OVER_CURRENT_PROTECTION_THRESHOLD | SR_CONF_GET | SR_CONF_SET,
7a0b98b5
AJ		 361 SR_CONF_VOLTAGE | SR_CONF_GET,
362 SR_CONF_VOLTAGE_TARGET | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
363 SR_CONF_CURRENT | SR_CONF_GET,
364 SR_CONF_CURRENT_LIMIT | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
365 SR_CONF_ENABLED | SR_CONF_GET | SR_CONF_SET,
d4eabea8
BV		 366};
367
8cb5affe 368static const struct channel_spec rigol_dp821a_ch[] = {
49a468ed
FS		 369 { "1", { 0, 60, 0.001, 3, 3 }, { 0, 1, 0.0001, 4, 4 }, { 0, 60, 0, 3, 4 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS },
370 { "2", { 0, 8, 0.001, 3, 3 }, { 0, 10, 0.001, 3, 3 }, { 0, 80, 0, 3, 3 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS },
cfcdf576
ML		 371};
372
8cb5affe 373static const struct channel_spec rigol_dp831_ch[] = {
49a468ed
FS		 374 { "1", { 0, 8, 0.001, 3, 4 }, { 0, 5, 0.0003, 3, 4 }, { 0, 40, 0, 3, 4 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS },
375 { "2", { 0, 30, 0.001, 3, 4 }, { 0, 2, 0.0001, 3, 4 }, { 0, 60, 0, 3, 4 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS },
376 { "3", { 0, -30, 0.001, 3, 4 }, { 0, 2, 0.0001, 3, 4 }, { 0, 60, 0, 3, 4 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS },
d4eabea8
BV		 377};
378
8cb5affe 379static const struct channel_spec rigol_dp832_ch[] = {
49a468ed
FS		 380 { "1", { 0, 30, 0.001, 3, 4 }, { 0, 3, 0.001, 3, 4 }, { 0, 90, 0, 3, 4 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS },
381 { "2", { 0, 30, 0.001, 3, 4 }, { 0, 3, 0.001, 3, 4 }, { 0, 90, 0, 3, 4 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS },
382 { "3", { 0, 5, 0.001, 3, 4 }, { 0, 3, 0.001, 3, 4 }, { 0, 90, 0, 3, 4 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS },
3222ee10
BV		 383};
384
8cb5affe 385static const struct channel_group_spec rigol_dp820_cg[] = {
f2bbcc33
FS		 386 { "1", CH_IDX(0), PPS_OVP | PPS_OCP, SR_MQFLAG_DC },
387 { "2", CH_IDX(1), PPS_OVP | PPS_OCP, SR_MQFLAG_DC },
cfcdf576
ML		 388};
389
8cb5affe 390static const struct channel_group_spec rigol_dp830_cg[] = {
f2bbcc33
FS		 391 { "1", CH_IDX(0), PPS_OVP | PPS_OCP, SR_MQFLAG_DC },
392 { "2", CH_IDX(1), PPS_OVP | PPS_OCP, SR_MQFLAG_DC },
393 { "3", CH_IDX(2), PPS_OVP | PPS_OCP, SR_MQFLAG_DC },
d4eabea8
BV		 394};
395
8cb5affe 396static const struct scpi_command rigol_dp800_cmd[] = {
60475cd7
BV		 397 { SCPI_CMD_REMOTE, "SYST:REMOTE" },
398 { SCPI_CMD_LOCAL, "SYST:LOCAL" },
ee2860ee
BV		 399 { SCPI_CMD_BEEPER, "SYST:BEEP:STAT?" },
400 { SCPI_CMD_BEEPER_ENABLE, "SYST:BEEP:STAT ON" },
401 { SCPI_CMD_BEEPER_DISABLE, "SYST:BEEP:STAT OFF" },
60475cd7
BV		 402 { SCPI_CMD_SELECT_CHANNEL, ":INST:NSEL %s" },
403 { SCPI_CMD_GET_MEAS_VOLTAGE, ":MEAS:VOLT?" },
404 { SCPI_CMD_GET_MEAS_CURRENT, ":MEAS:CURR?" },
405 { SCPI_CMD_GET_MEAS_POWER, ":MEAS:POWE?" },
406 { SCPI_CMD_GET_VOLTAGE_TARGET, ":SOUR:VOLT?" },
407 { SCPI_CMD_SET_VOLTAGE_TARGET, ":SOUR:VOLT %.6f" },
408 { SCPI_CMD_GET_CURRENT_LIMIT, ":SOUR:CURR?" },
409 { SCPI_CMD_SET_CURRENT_LIMIT, ":SOUR:CURR %.6f" },
410 { SCPI_CMD_GET_OUTPUT_ENABLED, ":OUTP?" },
411 { SCPI_CMD_SET_OUTPUT_ENABLE, ":OUTP ON" },
412 { SCPI_CMD_SET_OUTPUT_DISABLE, ":OUTP OFF" },
413 { SCPI_CMD_GET_OUTPUT_REGULATION, ":OUTP:MODE?" },
d4eabea8 414 { SCPI_CMD_GET_OVER_TEMPERATURE_PROTECTION, ":SYST:OTP?" },
53a81803
BV		 415 { SCPI_CMD_SET_OVER_TEMPERATURE_PROTECTION_ENABLE, ":SYST:OTP ON" },
416 { SCPI_CMD_SET_OVER_TEMPERATURE_PROTECTION_DISABLE, ":SYST:OTP OFF" },
60475cd7
BV		 417 { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_ENABLED, ":OUTP:OVP?" },
418 { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_ENABLE, ":OUTP:OVP ON" },
419 { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_DISABLE, ":OUTP:OVP OFF" },
420 { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_ACTIVE, ":OUTP:OVP:QUES?" },
421 { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_THRESHOLD, ":OUTP:OVP:VAL?" },
422 { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_THRESHOLD, ":OUTP:OVP:VAL %.6f" },
423 { SCPI_CMD_GET_OVER_CURRENT_PROTECTION_ENABLED, ":OUTP:OCP?" },
424 { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_ENABLE, ":OUTP:OCP:STAT ON" },
425 { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_DISABLE, ":OUTP:OCP:STAT OFF" },
426 { SCPI_CMD_GET_OVER_CURRENT_PROTECTION_ACTIVE, ":OUTP:OCP:QUES?" },
427 { SCPI_CMD_GET_OVER_CURRENT_PROTECTION_THRESHOLD, ":OUTP:OCP:VAL?" },
428 { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_THRESHOLD, ":OUTP:OCP:VAL %.6f" },
91ef511d 429 ALL_ZERO
d4eabea8
BV		 430};
431
bfc86799 432/* HP 663xx series */
e76a3575
AG		 433static const uint32_t hp_6630a_devopts[] = {
434 SR_CONF_CONTINUOUS,
88e4daa9
ML		 435 SR_CONF_LIMIT_SAMPLES | SR_CONF_GET | SR_CONF_SET,
436 SR_CONF_LIMIT_MSEC | SR_CONF_GET | SR_CONF_SET,
7c517d02
FS		 437};
438
439static const uint32_t hp_6630a_devopts_cg[] = {
e76a3575
AG		 440 SR_CONF_ENABLED | SR_CONF_SET,
441 SR_CONF_VOLTAGE | SR_CONF_GET,
442 SR_CONF_CURRENT | SR_CONF_GET,
443 SR_CONF_VOLTAGE_TARGET | SR_CONF_SET | SR_CONF_LIST,
444 SR_CONF_CURRENT_LIMIT | SR_CONF_SET | SR_CONF_LIST,
49a468ed 445 SR_CONF_OVER_VOLTAGE_PROTECTION_THRESHOLD | SR_CONF_SET | SR_CONF_LIST,
e76a3575
AG		 446 SR_CONF_OVER_CURRENT_PROTECTION_ENABLED | SR_CONF_SET,
447};
448
a61c8cce 449static const uint32_t hp_6630b_devopts[] = {
e91bb0a6 450 SR_CONF_CONTINUOUS,
88e4daa9
ML		 451 SR_CONF_LIMIT_SAMPLES | SR_CONF_GET | SR_CONF_SET,
452 SR_CONF_LIMIT_MSEC | SR_CONF_GET | SR_CONF_SET,
7c517d02
FS		 453};
454
a61c8cce 455static const uint32_t hp_6630b_devopts_cg[] = {
7a0b98b5
AJ		 456 SR_CONF_ENABLED | SR_CONF_GET | SR_CONF_SET,
457 SR_CONF_VOLTAGE | SR_CONF_GET,
458 SR_CONF_CURRENT | SR_CONF_GET,
459 SR_CONF_VOLTAGE_TARGET | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
460 SR_CONF_CURRENT_LIMIT | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
8b5eadf4 461 SR_CONF_OVER_VOLTAGE_PROTECTION_ACTIVE | SR_CONF_GET,
49a468ed 462 SR_CONF_OVER_VOLTAGE_PROTECTION_THRESHOLD | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
7e381bfc 463 SR_CONF_OVER_CURRENT_PROTECTION_ENABLED | SR_CONF_GET | SR_CONF_SET,
8b5eadf4
FS		 464 SR_CONF_OVER_CURRENT_PROTECTION_ACTIVE | SR_CONF_GET,
465 SR_CONF_OVER_TEMPERATURE_PROTECTION_ACTIVE | SR_CONF_GET,
43ff1110 466 SR_CONF_REGULATION | SR_CONF_GET,
bc4a2a46
BV		 467};
468
e76a3575 469static const struct channel_spec hp_6633a_ch[] = {
49a468ed 470 { "1", { 0, 51.188, 0.0125, 3, 4 }, { 0, 2.0475, 0.0005, 4, 5 }, { 0, 104.80743 }, FREQ_DC_ONLY, { 0, 55, 0.25 }, NO_OCP_LIMITS },
e76a3575
AG		 471};
472
a61c8cce 473static const struct channel_spec hp_6631b_ch[] = {
49a468ed 474 { "1", { 0, 8.19, 0.002, 3, 4 }, { 0, 10.237, 0.00263, 4, 5 }, { 0, 83.84103 }, FREQ_DC_ONLY, { 0, 12, 0.06 }, NO_OCP_LIMITS },
a61c8cce
FS		 475};
476
8cb5affe 477static const struct channel_spec hp_6632b_ch[] = {
49a468ed 478 { "1", { 0, 20.475, 0.005, 3, 4 }, { 0, 5.1188, 0.00132, 4, 5 }, { 0, 104.80743 }, FREQ_DC_ONLY, { 0, 22, 0.1 }, NO_OCP_LIMITS },
bc4a2a46
BV		 479};
480
a61c8cce 481static const struct channel_spec hp_66332a_ch[] = {
49a468ed 482 { "1", { 0, 20.475, 0.005, 3, 4 }, { 0, 5.1188, 0.00132, 4, 5 }, { 0, 104.80743 }, FREQ_DC_ONLY, { 0, 22, 0.1 }, NO_OCP_LIMITS },
a61c8cce
FS		 483};
484
485static const struct channel_spec hp_6633b_ch[] = {
49a468ed 486 { "1", { 0, 51.188, 0.0125, 3, 4 }, { 0, 2.0475, 0.000526, 4, 5 }, { 0, 104.80743 }, FREQ_DC_ONLY, { 0, 55, 0.25 }, NO_OCP_LIMITS },
a61c8cce
FS		 487};
488
489static const struct channel_spec hp_6634b_ch[] = {
49a468ed 490 { "1", { 0, 102.38, 0.025, 3, 4 }, { 0, 1.0238, 0.000263, 4, 5 }, { 0, 104.81664 }, FREQ_DC_ONLY, { 0, 110, 0.5 }, NO_OCP_LIMITS },
a61c8cce
FS		 491};
492
e76a3575 493static const struct channel_group_spec hp_663xx_cg[] = {
f2bbcc33 494 { "1", CH_IDX(0), 0, SR_MQFLAG_DC },
bc4a2a46
BV		 495};
496
e76a3575
AG		 497static const struct scpi_command hp_6630a_cmd[] = {
498 { SCPI_CMD_SET_OUTPUT_ENABLE, "OUT 1" },
499 { SCPI_CMD_SET_OUTPUT_DISABLE, "OUT 0" },
500 { SCPI_CMD_GET_MEAS_VOLTAGE, "VOUT?" },
501 { SCPI_CMD_GET_MEAS_CURRENT, "IOUT?" },
502 { SCPI_CMD_SET_VOLTAGE_TARGET, "VSET %.4f" },
503 { SCPI_CMD_SET_CURRENT_LIMIT, "ISET %.4f" },
504 { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_ENABLE, "OCP 1" },
505 { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_DISABLE, "OCP 0" },
506 { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_THRESHOLD, "OVSET %.4f" },
507 ALL_ZERO
508};
509
a61c8cce 510static const struct scpi_command hp_6630b_cmd[] = {
7e381bfc
FS		 511 { SCPI_CMD_REMOTE, "SYST:REM" },
512 { SCPI_CMD_LOCAL, "SYST:LOC" },
bc4a2a46 513 { SCPI_CMD_GET_OUTPUT_ENABLED, "OUTP:STAT?" },
53a81803
BV		 514 { SCPI_CMD_SET_OUTPUT_ENABLE, "OUTP:STAT ON" },
515 { SCPI_CMD_SET_OUTPUT_DISABLE, "OUTP:STAT OFF" },
bc4a2a46
BV		 516 { SCPI_CMD_GET_MEAS_VOLTAGE, ":MEAS:VOLT?" },
517 { SCPI_CMD_GET_MEAS_CURRENT, ":MEAS:CURR?" },
ca95e90f
BV		 518 { SCPI_CMD_GET_VOLTAGE_TARGET, ":SOUR:VOLT?" },
519 { SCPI_CMD_SET_VOLTAGE_TARGET, ":SOUR:VOLT %.6f" },
520 { SCPI_CMD_GET_CURRENT_LIMIT, ":SOUR:CURR?" },
521 { SCPI_CMD_SET_CURRENT_LIMIT, ":SOUR:CURR %.6f" },
7e381bfc
FS		 522 { SCPI_CMD_GET_OVER_CURRENT_PROTECTION_ENABLED, ":CURR:PROT:STAT?" },
523 { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_ENABLE, ":CURR:PROT:STAT 1" },
524 { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_DISABLE, ":CURR:PROT:STAT 0" },
8b5eadf4
FS		 525 { SCPI_CMD_GET_OVER_CURRENT_PROTECTION_ACTIVE, "STAT:QUES:COND?" },
526 { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_ACTIVE, "STAT:QUES:COND?" },
7e381bfc
FS		 527 { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_THRESHOLD, ":VOLT:PROT?" },
528 { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_THRESHOLD, ":VOLT:PROT %.6f" },
8b5eadf4 529 { SCPI_CMD_GET_OVER_TEMPERATURE_PROTECTION_ACTIVE, "STAT:QUES:COND?" },
43ff1110 530 { SCPI_CMD_GET_OUTPUT_REGULATION, "STAT:OPER:COND?" },
91ef511d 531 ALL_ZERO
bc4a2a46
BV		 532};
533
fe4bb774
FS		 534static int hp_6630b_init_aquisition(const struct sr_dev_inst *sdi)
535{
536 struct sr_scpi_dev_inst *scpi;
537 int ret;
538
539 scpi = sdi->conn;
540
541 /*
542 * Monitor CV (256), CC+ (1024) and CC- (2048) bits of the
543 * Operational Status Register.
544 * Use both positive and negative transitions of the status bits.
545 */
546 ret = sr_scpi_send(scpi, "STAT:OPER:PTR 3328;NTR 3328;ENAB 3328");
547 if (ret != SR_OK)
548 return ret;
549
550 /*
551 * Monitor OVP (1), OCP (2), OTP (16) and Unreg (1024) bits of the
552 * Questionable Status Register.
553 * Use both positive and negative transitions of the status bits.
554 */
555 ret = sr_scpi_send(scpi, "STAT:QUES:PTR 1043;NTR 1043;ENAB 1043");
556 if (ret != SR_OK)
557 return ret;
558
559 /*
560 * Service Request Enable Register set for Operational Status Register
561 * bits (128) and Questionable Status Register bits (8).
562 * This masks the Status Register generating a SRQ/RQS. Not implemented yet!
563 */
564 /*
565 ret = sr_scpi_send(scpi, "*SRE 136");
566 if (ret != SR_OK)
567 return ret;
568 */
569
570 return SR_OK;
571}
572
573static int hp_6630b_update_status(const struct sr_dev_inst *sdi)
574{
575 struct sr_scpi_dev_inst *scpi;
576 int ret;
577 int stb;
578 int ques_even, ques_cond;
579 int oper_even, oper_cond;
580 gboolean output_enabled;
581 gboolean unreg, cv, cc_pos, cc_neg;
582 gboolean regulation_changed;
583 char *regulation;
584
585 scpi = sdi->conn;
586
587 unreg = FALSE;
588 cv = FALSE;
589 cc_pos = FALSE;
590 cc_neg = FALSE;
591 regulation_changed = FALSE;
592
593 /*
594 * Use SPoll when SCPI uses GPIB as transport layer.
595 * SPoll is approx. twice as fast as a normal GPIB write + read would be!
596 */
597#ifdef HAVE_LIBGPIB
598 char spoll_buf;
599
600 if (scpi->transport == SCPI_TRANSPORT_LIBGPIB) {
601 ret = sr_scpi_gpib_spoll(scpi, &spoll_buf);
602 if (ret != SR_OK)
603 return ret;
604 stb = (uint8_t)spoll_buf;
605 }
606 else {
607#endif
608 ret = sr_scpi_get_int(scpi, "*STB?", &stb);
609 if (ret != SR_OK)
610 return ret;
611#ifdef HAVE_LIBGPIB
612 }
613#endif
614
615 /* Questionable status summary bit */
616 if (stb & (1 << 3)) {
617 /* Read the event register to clear it! */
618 ret = sr_scpi_get_int(scpi, "STAT:QUES:EVEN?", &ques_even);
619 if (ret != SR_OK)
620 return ret;
621 /* Now get the values. */
622 ret = sr_scpi_get_int(scpi, "STAT:QUES:COND?", &ques_cond);
623 if (ret != SR_OK)
624 return ret;
625
626 /* OVP */
627 if (ques_even & (1 << 0))
628 sr_session_send_meta(sdi, SR_CONF_OVER_VOLTAGE_PROTECTION_ACTIVE,
629 g_variant_new_boolean(ques_cond & (1 << 0)));
630
631 /* OCP */
632 if (ques_even & (1 << 1))
633 sr_session_send_meta(sdi, SR_CONF_OVER_CURRENT_PROTECTION_ACTIVE,
634 g_variant_new_boolean(ques_cond & (1 << 1)));
635
636 /* OTP */
637 if (ques_even & (1 << 4))
638 sr_session_send_meta(sdi, SR_CONF_OVER_TEMPERATURE_PROTECTION_ACTIVE,
639 g_variant_new_boolean(ques_cond & (1 << 4)));
640
641 /* UNREG */
642 unreg = (ques_cond & (1 << 10));
643 regulation_changed = (ques_even & (1 << 10)) | regulation_changed;
644
645 /*
646 * Check if output state has changed, due to one of the
647 * questionable states changed.
648 * NOTE: The output state is send even if it hasn't changed, but that
649 * only happends rarely.
650 */
651 ret = sr_scpi_get_bool(scpi, "OUTP:STAT?", &output_enabled);
652 if (ret != SR_OK)
653 return ret;
654 sr_session_send_meta(sdi, SR_CONF_ENABLED,
655 g_variant_new_boolean(output_enabled));
656 }
657
658 /* Operation status summary bit */
659 if (stb & (1 << 7)) {
660 /* Read the event register to clear it! */
661 ret = sr_scpi_get_int(scpi, "STAT:OPER:EVEN?", &oper_even);
662 if (ret != SR_OK)
663 return ret;
664 /* Now get the values. */
665 ret = sr_scpi_get_int(scpi, "STAT:OPER:COND?", &oper_cond);
666 if (ret != SR_OK)
667 return ret;
668
669 /* CV */
670 cv = (oper_cond & (1 << 8));
671 regulation_changed = (oper_even & (1 << 8)) | regulation_changed;
672 /* CC+ */
673 cc_pos = (oper_cond & (1 << 10));
674 regulation_changed = (oper_even & (1 << 10)) | regulation_changed;
675 /* CC- */
676 cc_neg = (oper_cond & (1 << 11));
677 regulation_changed = (oper_even & (1 << 11)) | regulation_changed;
678 }
679
680 if (regulation_changed) {
681 if (cv && !cc_pos && !cc_neg &&!unreg)
682 regulation = "CV";
683 else if (cc_pos && !cv && !cc_neg && !unreg)
684 regulation = "CC";
685 else if (cc_neg && !cv && !cc_pos && !unreg)
686 regulation = "CC-";
687 else if (unreg && !cv && !cc_pos && !cc_neg)
688 regulation = "UR";
689 else if (!cv && !cc_pos && !cc_neg &&!unreg)
690 /* This happends in case of OCP active */
691 regulation = "";
692 else {
693 /* This happends from time to time (CV and CC+ active). */
694 sr_dbg("Undefined regulation for HP 66xxB "
695 "(CV=%i, CC+=%i, CC-=%i, UR=%i).",
696 cv, cc_pos, cc_neg, unreg);
697 return FALSE;
698 }
699 sr_session_send_meta(sdi, SR_CONF_REGULATION,
700 g_variant_new_string(regulation));
701 }
702
703 return SR_OK;
704}
705
c3eadb07 706/* Philips/Fluke PM2800 series */
9d9cf1c4 707static const uint32_t philips_pm2800_devopts[] = {
e91bb0a6 708 SR_CONF_CONTINUOUS,
88e4daa9
ML		 709 SR_CONF_LIMIT_SAMPLES | SR_CONF_GET | SR_CONF_SET,
710 SR_CONF_LIMIT_MSEC | SR_CONF_GET | SR_CONF_SET,
9d9cf1c4
BV		 711};
712
c3eadb07 713static const uint32_t philips_pm2800_devopts_cg[] = {
7a0b98b5
AJ		 714 SR_CONF_ENABLED | SR_CONF_GET | SR_CONF_SET,
715 SR_CONF_VOLTAGE | SR_CONF_GET,
716 SR_CONF_VOLTAGE_TARGET | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
717 SR_CONF_CURRENT | SR_CONF_GET,
718 SR_CONF_CURRENT_LIMIT | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
c3eadb07
BV		 719 SR_CONF_OVER_VOLTAGE_PROTECTION_ACTIVE | SR_CONF_GET,
720 SR_CONF_OVER_VOLTAGE_PROTECTION_THRESHOLD | SR_CONF_GET | SR_CONF_SET,
721 SR_CONF_OVER_CURRENT_PROTECTION_ENABLED | SR_CONF_GET | SR_CONF_SET,
722 SR_CONF_OVER_CURRENT_PROTECTION_ACTIVE | SR_CONF_GET,
7a0b98b5 723 SR_CONF_REGULATION | SR_CONF_GET,
c3eadb07
BV		 724};
725
726enum philips_pm2800_modules {
727 PM2800_MOD_30V_10A = 1,
728 PM2800_MOD_60V_5A,
729 PM2800_MOD_60V_10A,
730 PM2800_MOD_8V_15A,
731 PM2800_MOD_60V_2A,
732 PM2800_MOD_120V_1A,
733};
734
329733d9 735static const struct philips_pm2800_module_spec {
c3eadb07 736 /* Min, max, programming resolution. */
bcee1299
UH		 737 double voltage[5];
738 double current[5];
739 double power[5];
c3eadb07
BV		 740} philips_pm2800_module_specs[] = {
741 /* Autoranging modules. */
6ed709fe
AJ		 742 [PM2800_MOD_30V_10A] = { { 0, 30, 0.0075, 2, 4 }, { 0, 10, 0.0025, 2, 4 }, { 0, 60 } },
743 [PM2800_MOD_60V_5A] = { { 0, 60, 0.015, 2, 3 }, { 0, 5, 0.00125, 2, 5 }, { 0, 60 } },
744 [PM2800_MOD_60V_10A] = { { 0, 60, 0.015, 2, 3 }, { 0, 10, 0.0025, 2, 5 }, { 0, 120 } },
c3eadb07 745 /* Linear modules. */
6ed709fe
AJ		 746 [PM2800_MOD_8V_15A] = { { 0, 8, 0.002, 3, 3 }, { -15, 15, 0.00375, 3, 5 }, { 0, 120 } },
747 [PM2800_MOD_60V_2A] = { { 0, 60, 0.015, 2, 3 }, { -2, 2, 0.0005, 3, 4 }, { 0, 120 } },
748 [PM2800_MOD_120V_1A] = { { 0, 120, 0.030, 2, 2 }, { -1, 1, 0.00025, 3, 5 }, { 0, 120 } },
c3eadb07
BV		 749};
750
329733d9 751static const struct philips_pm2800_model {
c3eadb07
BV		 752 unsigned int chassis;
753 unsigned int num_modules;
754 unsigned int set;
755 unsigned int modules[3];
756} philips_pm2800_matrix[] = {
757 /* Autoranging chassis. */
758 { 1, 1, 0, { PM2800_MOD_30V_10A, 0, 0 } },
759 { 1, 1, 1, { PM2800_MOD_60V_5A, 0, 0 } },
760 { 1, 2, 0, { PM2800_MOD_30V_10A, PM2800_MOD_30V_10A, 0 } },
761 { 1, 2, 1, { PM2800_MOD_60V_5A, PM2800_MOD_60V_5A, 0 } },
762 { 1, 2, 2, { PM2800_MOD_30V_10A, PM2800_MOD_60V_5A, 0 } },
763 { 1, 2, 3, { PM2800_MOD_30V_10A, PM2800_MOD_60V_10A, 0 } },
764 { 1, 2, 4, { PM2800_MOD_60V_5A, PM2800_MOD_60V_10A, 0 } },
765 { 1, 3, 0, { PM2800_MOD_30V_10A, PM2800_MOD_30V_10A, PM2800_MOD_30V_10A } },
766 { 1, 3, 1, { PM2800_MOD_60V_5A, PM2800_MOD_60V_5A, PM2800_MOD_60V_5A } },
767 { 1, 3, 2, { PM2800_MOD_30V_10A, PM2800_MOD_30V_10A, PM2800_MOD_60V_5A } },
768 { 1, 3, 3, { PM2800_MOD_30V_10A, PM2800_MOD_60V_5A, PM2800_MOD_60V_5A } },
769 /* Linear chassis. */
770 { 3, 1, 0, { PM2800_MOD_60V_2A, 0, 0 } },
771 { 3, 1, 1, { PM2800_MOD_120V_1A, 0, 0 } },
772 { 3, 1, 2, { PM2800_MOD_8V_15A, 0, 0 } },
773 { 3, 2, 0, { PM2800_MOD_60V_2A, 0, 0 } },
774 { 3, 2, 1, { PM2800_MOD_120V_1A, 0, 0 } },
775 { 3, 2, 2, { PM2800_MOD_60V_2A, PM2800_MOD_120V_1A, 0 } },
776 { 3, 2, 3, { PM2800_MOD_8V_15A, PM2800_MOD_8V_15A, 0 } },
777};
778
329733d9 779static const char *philips_pm2800_names[] = { "1", "2", "3" };
c3eadb07
BV		 780
781static int philips_pm2800_probe_channels(struct sr_dev_inst *sdi,
782 struct sr_scpi_hw_info *hw_info,
783 struct channel_spec **channels, unsigned int *num_channels,
784 struct channel_group_spec **channel_groups, unsigned int *num_channel_groups)
785{
329733d9
UH		 786 const struct philips_pm2800_model *model;
787 const struct philips_pm2800_module_spec *spec;
c3eadb07
BV		 788 unsigned int chassis, num_modules, set, module, m, i;
789
790 (void)sdi;
791
792 /*
793 * The model number as reported by *IDN? looks like e.g. PM2813/11,
794 * Where "PM28" is fixed, followed by the chassis code (1 = autoranging,
795 * 3 = linear series) and the number of modules: 1-3 for autoranging,
796 * 1-2 for linear.
797 * After the slash, the first digit denotes the module set. The
798 * digit after that denotes front (5) or rear (1) binding posts.
799 */
800 chassis = hw_info->model[4] - 0x30;
801 num_modules = hw_info->model[5] - 0x30;
802 set = hw_info->model[7] - 0x30;
803 for (m = 0; m < ARRAY_SIZE(philips_pm2800_matrix); m++) {
804 model = &philips_pm2800_matrix[m];
805 if (model->chassis == chassis && model->num_modules == num_modules
806 && model->set == set)
807 break;
808 }
809 if (m == ARRAY_SIZE(philips_pm2800_matrix)) {
810 sr_dbg("Model %s not found in matrix.", hw_info->model);
811 return SR_ERR;
812 }
813
814 sr_dbg("Found %d output channel%s:", num_modules, num_modules > 1 ? "s" : "");
815 *channels = g_malloc0(sizeof(struct channel_spec) * num_modules);
816 *channel_groups = g_malloc0(sizeof(struct channel_group_spec) * num_modules);
817 for (i = 0; i < num_modules; i++) {
818 module = model->modules[i];
819 spec = &philips_pm2800_module_specs[module];
6ed709fe 820 sr_dbg("output %d: %.0f - %.0fV, %.0f - %.0fA, %.0f - %.0fW", i + 1,
c3eadb07 821 spec->voltage[0], spec->voltage[1],
6ed709fe 822 spec->current[0], spec->current[1],
d9251a2c 823 spec->power[0], spec->power[1]);
329733d9 824 (*channels)[i].name = (char *)philips_pm2800_names[i];
bcee1299 825 memcpy(&((*channels)[i].voltage), spec, sizeof(double) * 15);
329733d9 826 (*channel_groups)[i].name = (char *)philips_pm2800_names[i];
c3eadb07
BV		 827 (*channel_groups)[i].channel_index_mask = 1 << i;
828 (*channel_groups)[i].features = PPS_OTP | PPS_OVP | PPS_OCP;
f2bbcc33 829 (*channel_groups)[i].mqflags = SR_MQFLAG_DC;
c3eadb07
BV		 830 }
831 *num_channels = *num_channel_groups = num_modules;
832
833 return SR_OK;
834}
835
8cb5affe 836static const struct scpi_command philips_pm2800_cmd[] = {
c3eadb07
BV		 837 { SCPI_CMD_SELECT_CHANNEL, ":INST:NSEL %s" },
838 { SCPI_CMD_GET_MEAS_VOLTAGE, ":MEAS:VOLT?" },
839 { SCPI_CMD_GET_MEAS_CURRENT, ":MEAS:CURR?" },
840 { SCPI_CMD_GET_VOLTAGE_TARGET, ":SOUR:VOLT?" },
841 { SCPI_CMD_SET_VOLTAGE_TARGET, ":SOUR:VOLT %.6f" },
842 { SCPI_CMD_GET_CURRENT_LIMIT, ":SOUR:CURR?" },
843 { SCPI_CMD_SET_CURRENT_LIMIT, ":SOUR:CURR %.6f" },
844 { SCPI_CMD_GET_OUTPUT_ENABLED, ":OUTP?" },
845 { SCPI_CMD_SET_OUTPUT_ENABLE, ":OUTP ON" },
846 { SCPI_CMD_SET_OUTPUT_DISABLE, ":OUTP OFF" },
847 { SCPI_CMD_GET_OUTPUT_REGULATION, ":SOUR:FUNC:MODE?" },
848 { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_ACTIVE, ":SOUR:VOLT:PROT:TRIP?" },
849 { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_THRESHOLD, ":SOUR:VOLT:PROT:LEV?" },
850 { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_THRESHOLD, ":SOUR:VOLT:PROT:LEV %.6f" },
851 { SCPI_CMD_GET_OVER_CURRENT_PROTECTION_ENABLED, ":SOUR:CURR:PROT:STAT?" },
852 { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_ENABLE, ":SOUR:CURR:PROT:STAT ON" },
853 { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_DISABLE, ":SOUR:CURR:PROT:STAT OFF" },
854 { SCPI_CMD_GET_OVER_CURRENT_PROTECTION_ACTIVE, ":SOUR:CURR:PROT:TRIP?" },
91ef511d 855 ALL_ZERO
c3eadb07
BV		 856};
857
81eb36d6
MS		 858static const uint32_t rs_hmc8043_devopts[] = {
859 SR_CONF_CONTINUOUS,
88e4daa9
ML		 860 SR_CONF_LIMIT_SAMPLES | SR_CONF_GET | SR_CONF_SET,
861 SR_CONF_LIMIT_MSEC | SR_CONF_GET | SR_CONF_SET,
81eb36d6
MS		 862};
863
864static const uint32_t rs_hmc8043_devopts_cg[] = {
865 SR_CONF_OVER_VOLTAGE_PROTECTION_ENABLED | SR_CONF_GET | SR_CONF_SET,
866 SR_CONF_OVER_VOLTAGE_PROTECTION_ACTIVE | SR_CONF_GET,
867 SR_CONF_OVER_VOLTAGE_PROTECTION_THRESHOLD | SR_CONF_GET | SR_CONF_SET,
868 SR_CONF_VOLTAGE | SR_CONF_GET,
869 SR_CONF_VOLTAGE_TARGET | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
870 SR_CONF_CURRENT | SR_CONF_GET,
871 SR_CONF_CURRENT_LIMIT | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
872 SR_CONF_ENABLED | SR_CONF_GET | SR_CONF_SET,
873};
874
875static const struct channel_spec rs_hmc8043_ch[] = {
49a468ed
FS		 876 { "1", { 0, 32.050, 0.001, 3, 4 }, { 0.001, 3, 0.001, 3, 4 }, { 0, 0, 0, 0, 4 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS },
877 { "2", { 0, 32.050, 0.001, 3, 4 }, { 0.001, 3, 0.001, 3, 4 }, { 0, 0, 0, 0, 4 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS },
878 { "3", { 0, 32.050, 0.001, 3, 4 }, { 0.001, 3, 0.001, 3, 4 }, { 0, 0, 0, 0, 4 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS },
81eb36d6
MS		 879};
880
881static const struct channel_group_spec rs_hmc8043_cg[] = {
f2bbcc33
FS		 882 { "1", CH_IDX(0), PPS_OVP, SR_MQFLAG_DC },
883 { "2", CH_IDX(1), PPS_OVP, SR_MQFLAG_DC },
884 { "3", CH_IDX(2), PPS_OVP, SR_MQFLAG_DC },
81eb36d6
MS		 885};
886
887static const struct scpi_command rs_hmc8043_cmd[] = {
888 { SCPI_CMD_SELECT_CHANNEL, "INST:NSEL %s" },
889 { SCPI_CMD_GET_MEAS_VOLTAGE, "MEAS:VOLT?" },
890 { SCPI_CMD_GET_MEAS_CURRENT, "MEAS:CURR?" },
891 { SCPI_CMD_GET_VOLTAGE_TARGET, "VOLT?" },
892 { SCPI_CMD_SET_VOLTAGE_TARGET, "VOLT %.6f" },
893 { SCPI_CMD_GET_CURRENT_LIMIT, "CURR?" },
894 { SCPI_CMD_SET_CURRENT_LIMIT, "CURR %.6f" },
895 { SCPI_CMD_GET_OUTPUT_ENABLED, "OUTP?" },
896 { SCPI_CMD_SET_OUTPUT_ENABLE, "OUTP ON" },
897 { SCPI_CMD_SET_OUTPUT_DISABLE, "OUTP OFF" },
898 { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_ACTIVE, "VOLT:PROT:TRIP?" },
899 { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_THRESHOLD, "VOLT:PROT:LEV?" },
900 { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_THRESHOLD, "VOLT:PROT:LEV %.6f" },
901 { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_ENABLED, "VOLT:PROT:STAT?" },
902 { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_ENABLE, "VOLT:PROT:STAT ON" },
903 { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_DISABLE, "VOLT:PROT:STAT OFF" },
904 ALL_ZERO
905};
906
d4eabea8 907SR_PRIV const struct scpi_pps pps_profiles[] = {
6cc93128 908 /* Agilent N5763A */
5e7377f4 909 { "Agilent", "N5763A", SCPI_DIALECT_UNKNOWN, 0,
6cc93128
AG		 910 ARRAY_AND_SIZE(agilent_n5700a_devopts),
911 ARRAY_AND_SIZE(agilent_n5700a_devopts_cg),
912 ARRAY_AND_SIZE(agilent_n5763a_ch),
913 ARRAY_AND_SIZE(agilent_n5700a_cg),
914 agilent_n5700a_cmd,
915 .probe_channels = NULL,
7e66bf05
FS		 916 .init_aquisition = NULL,
917 .update_status = NULL,
6cc93128 918 },
ca314e06 919
5c9e56c9 920 /* Agilent N5767A */
5e7377f4 921 { "Agilent", "N5767A", SCPI_DIALECT_UNKNOWN, 0,
5c9e56c9
AG		 922 ARRAY_AND_SIZE(agilent_n5700a_devopts),
923 ARRAY_AND_SIZE(agilent_n5700a_devopts_cg),
924 ARRAY_AND_SIZE(agilent_n5767a_ch),
6cc93128 925 ARRAY_AND_SIZE(agilent_n5700a_cg),
91ef511d 926 agilent_n5700a_cmd,
5c9e56c9 927 .probe_channels = NULL,
7e66bf05
FS		 928 .init_aquisition = NULL,
929 .update_status = NULL,
5c9e56c9 930 },
ca314e06 931
c3bfb959 932 /* BK Precision 9310 */
5e7377f4 933 { "BK", "^9130$", SCPI_DIALECT_UNKNOWN, 0,
c3bfb959
MW		 934 ARRAY_AND_SIZE(bk_9130_devopts),
935 ARRAY_AND_SIZE(bk_9130_devopts_cg),
936 ARRAY_AND_SIZE(bk_9130_ch),
937 ARRAY_AND_SIZE(bk_9130_cg),
938 bk_9130_cmd,
939 .probe_channels = NULL,
7e66bf05
FS		 940 .init_aquisition = NULL,
941 .update_status = NULL,
c3bfb959
MW		 942 },
943
4ee1e2f3 944 /* Chroma 61604 */
5e7377f4 945 { "Chroma", "61604", SCPI_DIALECT_UNKNOWN, 0,
4ee1e2f3
AG		 946 ARRAY_AND_SIZE(chroma_61604_devopts),
947 ARRAY_AND_SIZE(chroma_61604_devopts_cg),
948 ARRAY_AND_SIZE(chroma_61604_ch),
949 ARRAY_AND_SIZE(chroma_61604_cg),
91ef511d 950 chroma_61604_cmd,
4ee1e2f3 951 .probe_channels = NULL,
7e66bf05
FS		 952 .init_aquisition = NULL,
953 .update_status = NULL,
4ee1e2f3 954 },
ca314e06 955
5281993e 956 /* Chroma 62000 series */
5e7377f4 957 { "Chroma", "620[0-9]{2}P-[0-9]{2,3}-[0-9]{1,3}", SCPI_DIALECT_UNKNOWN, 0,
5281993e
AG		 958 ARRAY_AND_SIZE(chroma_62000_devopts),
959 ARRAY_AND_SIZE(chroma_62000_devopts_cg),
9a5185c7
AG		 960 NULL, 0,
961 NULL, 0,
91ef511d 962 chroma_62000_cmd,
9a5185c7 963 .probe_channels = chroma_62000p_probe_channels,
7e66bf05
FS		 964 .init_aquisition = NULL,
965 .update_status = NULL,
5281993e 966 },
ca314e06 967
e76a3575 968 /* HP 6633A */
5e7377f4 969 { "HP", "6633A", SCPI_DIALECT_HP_COMP, 0,
e76a3575 970 ARRAY_AND_SIZE(hp_6630a_devopts),
7c517d02 971 ARRAY_AND_SIZE(hp_6630a_devopts_cg),
e76a3575
AG		 972 ARRAY_AND_SIZE(hp_6633a_ch),
973 ARRAY_AND_SIZE(hp_663xx_cg),
974 hp_6630a_cmd,
975 .probe_channels = NULL,
7e66bf05
FS		 976 .init_aquisition = NULL,
977 .update_status = NULL,
e76a3575
AG		 978 },
979
a61c8cce 980 /* HP 6631B */
5e7377f4 981 { "HP", "6631B", SCPI_DIALECT_HP_66XXB, PPS_OVP | PPS_OCP | PPS_OTP,
a61c8cce
FS		 982 ARRAY_AND_SIZE(hp_6630b_devopts),
983 ARRAY_AND_SIZE(hp_6630b_devopts_cg),
984 ARRAY_AND_SIZE(hp_6631b_ch),
985 ARRAY_AND_SIZE(hp_663xx_cg),
986 hp_6630b_cmd,
987 .probe_channels = NULL,
fe4bb774
FS		 988 hp_6630b_init_aquisition,
989 hp_6630b_update_status,
a61c8cce
FS		 990 },
991
bc4a2a46 992 /* HP 6632B */
5e7377f4 993 { "HP", "6632B", SCPI_DIALECT_HP_66XXB, PPS_OVP | PPS_OCP | PPS_OTP,
a61c8cce
FS		 994 ARRAY_AND_SIZE(hp_6630b_devopts),
995 ARRAY_AND_SIZE(hp_6630b_devopts_cg),
bc4a2a46 996 ARRAY_AND_SIZE(hp_6632b_ch),
e76a3575 997 ARRAY_AND_SIZE(hp_663xx_cg),
a61c8cce
FS		 998 hp_6630b_cmd,
999 .probe_channels = NULL,
fe4bb774
FS		 1000 hp_6630b_init_aquisition,
1001 hp_6630b_update_status,
a61c8cce
FS		 1002 },
1003
1004 /* HP 66332A */
5e7377f4 1005 { "HP", "66332A", SCPI_DIALECT_HP_66XXB, PPS_OVP | PPS_OCP | PPS_OTP,
a61c8cce
FS		 1006 ARRAY_AND_SIZE(hp_6630b_devopts),
1007 ARRAY_AND_SIZE(hp_6630b_devopts_cg),
1008 ARRAY_AND_SIZE(hp_66332a_ch),
1009 ARRAY_AND_SIZE(hp_663xx_cg),
1010 hp_6630b_cmd,
1011 .probe_channels = NULL,
fe4bb774
FS		 1012 hp_6630b_init_aquisition,
1013 hp_6630b_update_status,
a61c8cce
FS		 1014 },
1015
1016 /* HP 6633B */
5e7377f4 1017 { "HP", "6633B", SCPI_DIALECT_HP_66XXB, PPS_OVP | PPS_OCP | PPS_OTP,
a61c8cce
FS		 1018 ARRAY_AND_SIZE(hp_6630b_devopts),
1019 ARRAY_AND_SIZE(hp_6630b_devopts_cg),
1020 ARRAY_AND_SIZE(hp_6633b_ch),
1021 ARRAY_AND_SIZE(hp_663xx_cg),
1022 hp_6630b_cmd,
1023 .probe_channels = NULL,
fe4bb774
FS		 1024 hp_6630b_init_aquisition,
1025 hp_6630b_update_status,
a61c8cce
FS		 1026 },
1027
1028 /* HP 6634B */
5e7377f4 1029 { "HP", "6634B", SCPI_DIALECT_HP_66XXB, PPS_OVP | PPS_OCP | PPS_OTP,
a61c8cce
FS		 1030 ARRAY_AND_SIZE(hp_6630b_devopts),
1031 ARRAY_AND_SIZE(hp_6630b_devopts_cg),
1032 ARRAY_AND_SIZE(hp_6634b_ch),
1033 ARRAY_AND_SIZE(hp_663xx_cg),
1034 hp_6630b_cmd,
c3eadb07 1035 .probe_channels = NULL,
fe4bb774
FS		 1036 hp_6630b_init_aquisition,
1037 hp_6630b_update_status,
bc4a2a46
BV		 1038 },
1039
319fe9ce 1040 /* Rigol DP700 series */
5e7377f4 1041 { "Rigol", "^DP711$", SCPI_DIALECT_UNKNOWN, 0,
319fe9ce
UH		 1042 ARRAY_AND_SIZE(rigol_dp700_devopts),
1043 ARRAY_AND_SIZE(rigol_dp700_devopts_cg),
1044 ARRAY_AND_SIZE(rigol_dp711_ch),
1045 ARRAY_AND_SIZE(rigol_dp700_cg),
1046 rigol_dp700_cmd,
1047 .probe_channels = NULL,
7e66bf05
FS		 1048 .init_aquisition = NULL,
1049 .update_status = NULL,
319fe9ce 1050 },
5e7377f4 1051 { "Rigol", "^DP712$", SCPI_DIALECT_UNKNOWN, 0,
319fe9ce
UH		 1052 ARRAY_AND_SIZE(rigol_dp700_devopts),
1053 ARRAY_AND_SIZE(rigol_dp700_devopts_cg),
1054 ARRAY_AND_SIZE(rigol_dp712_ch),
1055 ARRAY_AND_SIZE(rigol_dp700_cg),
1056 rigol_dp700_cmd,
1057 .probe_channels = NULL,
7e66bf05
FS		 1058 .init_aquisition = NULL,
1059 .update_status = NULL,
319fe9ce
UH		 1060 },
1061
d4eabea8 1062 /* Rigol DP800 series */
5e7377f4 1063 { "Rigol", "^DP821A$", SCPI_DIALECT_UNKNOWN, PPS_OTP,
cfcdf576
ML		 1064 ARRAY_AND_SIZE(rigol_dp800_devopts),
1065 ARRAY_AND_SIZE(rigol_dp800_devopts_cg),
1066 ARRAY_AND_SIZE(rigol_dp821a_ch),
1067 ARRAY_AND_SIZE(rigol_dp820_cg),
91ef511d 1068 rigol_dp800_cmd,
cfcdf576 1069 .probe_channels = NULL,
7e66bf05
FS		 1070 .init_aquisition = NULL,
1071 .update_status = NULL,
cfcdf576 1072 },
5e7377f4 1073 { "Rigol", "^DP831A$", SCPI_DIALECT_UNKNOWN, PPS_OTP,
3222ee10
BV		 1074 ARRAY_AND_SIZE(rigol_dp800_devopts),
1075 ARRAY_AND_SIZE(rigol_dp800_devopts_cg),
1076 ARRAY_AND_SIZE(rigol_dp831_ch),
cfcdf576 1077 ARRAY_AND_SIZE(rigol_dp830_cg),
91ef511d 1078 rigol_dp800_cmd,
c3eadb07 1079 .probe_channels = NULL,
7e66bf05
FS		 1080 .init_aquisition = NULL,
1081 .update_status = NULL,
3222ee10 1082 },
5e7377f4 1083 { "Rigol", "^(DP832|DP832A)$", SCPI_DIALECT_UNKNOWN, PPS_OTP,
3222ee10
BV		 1084 ARRAY_AND_SIZE(rigol_dp800_devopts),
1085 ARRAY_AND_SIZE(rigol_dp800_devopts_cg),
1086 ARRAY_AND_SIZE(rigol_dp832_ch),
cfcdf576 1087 ARRAY_AND_SIZE(rigol_dp830_cg),
91ef511d 1088 rigol_dp800_cmd,
c3eadb07 1089 .probe_channels = NULL,
7e66bf05
FS		 1090 .init_aquisition = NULL,
1091 .update_status = NULL,
c3eadb07
BV		 1092 },
1093
1094 /* Philips/Fluke PM2800 series */
5e7377f4 1095 { "Philips", "^PM28[13][123]/[01234]{1,2}$", SCPI_DIALECT_PHILIPS, 0,
9d9cf1c4 1096 ARRAY_AND_SIZE(philips_pm2800_devopts),
c3eadb07
BV		 1097 ARRAY_AND_SIZE(philips_pm2800_devopts_cg),
1098 NULL, 0,
1099 NULL, 0,
91ef511d 1100 philips_pm2800_cmd,
c3eadb07 1101 philips_pm2800_probe_channels,
7e66bf05
FS		 1102 .init_aquisition = NULL,
1103 .update_status = NULL,
d4eabea8 1104 },
81eb36d6
MS		 1105
1106 /* Rohde & Schwarz HMC8043 */
5e7377f4 1107 { "Rohde&Schwarz", "HMC8043", SCPI_DIALECT_UNKNOWN, 0,
81eb36d6
MS		 1108 ARRAY_AND_SIZE(rs_hmc8043_devopts),
1109 ARRAY_AND_SIZE(rs_hmc8043_devopts_cg),
1110 ARRAY_AND_SIZE(rs_hmc8043_ch),
1111 ARRAY_AND_SIZE(rs_hmc8043_cg),
1112 rs_hmc8043_cmd,
1113 .probe_channels = NULL,
7e66bf05
FS		 1114 .init_aquisition = NULL,
1115 .update_status = NULL,
81eb36d6 1116 },
d4eabea8 1117};
d4eabea8 1118
1beccaed 1119SR_PRIV unsigned int num_pps_profiles = ARRAY_SIZE(pps_profiles);
Hardware access and backend lib