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scpi-pps: Add SR_CONF_REGULATION for HP 66xxB power supplies.
[libsigrok.git] / src / hardware / scpi-pps / profiles.c
CommitLineData
d4eabea8
BV		 1/*
2 * This file is part of the libsigrok project.
3 *
4 * Copyright (C) 2014 Bert Vermeulen <bert@biot.com>
4ee1e2f3
AG		 5 * Copyright (C) 2015 Google, Inc.
6 * (Written by Alexandru Gagniuc <mrnuke@google.com> for Google, Inc.)
7e381bfc 7 * Copyright (C) 2017 Frank Stettner <frank-stettner@gmx.net>
d4eabea8
BV		 8 *
9 * This program is free software: you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation, either version 3 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program. If not, see <http://www.gnu.org/licenses/>.
21 */
22
6ec6c43b 23#include <config.h>
22c18b03 24#include <string.h>
ba464a12 25#include <strings.h>
d4eabea8
BV		 26#include "protocol.h"
27
28#define CH_IDX(x) (1 << x)
6ed709fe 29#define FREQ_DC_ONLY {0, 0, 0, 0, 0}
49a468ed
FS		 30#define NO_OVP_LIMITS {0, 0, 0, 0, 0}
31#define NO_OCP_LIMITS {0, 0, 0, 0, 0}
d4eabea8 32
5c9e56c9
AG		 33/* Agilent/Keysight N5700A series */
34static const uint32_t agilent_n5700a_devopts[] = {
e91bb0a6 35 SR_CONF_CONTINUOUS,
88e4daa9
ML		 36 SR_CONF_LIMIT_SAMPLES | SR_CONF_GET | SR_CONF_SET,
37 SR_CONF_LIMIT_MSEC | SR_CONF_GET | SR_CONF_SET,
5c9e56c9
AG		 38};
39
40static const uint32_t agilent_n5700a_devopts_cg[] = {
41 SR_CONF_OVER_VOLTAGE_PROTECTION_THRESHOLD | SR_CONF_GET | SR_CONF_SET,
42 SR_CONF_OVER_CURRENT_PROTECTION_ENABLED | SR_CONF_GET | SR_CONF_SET,
43 SR_CONF_OVER_CURRENT_PROTECTION_THRESHOLD | SR_CONF_GET | SR_CONF_SET,
da005885
UH		 44 SR_CONF_VOLTAGE | SR_CONF_GET,
45 SR_CONF_VOLTAGE_TARGET | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
46 SR_CONF_CURRENT | SR_CONF_GET,
47 SR_CONF_ENABLED | SR_CONF_GET | SR_CONF_SET,
5c9e56c9
AG		 48};
49
6cc93128
AG		 50static const struct channel_group_spec agilent_n5700a_cg[] = {
51 { "1", CH_IDX(0), PPS_OVP | PPS_OCP },
52};
53
8cb5affe 54static const struct channel_spec agilent_n5767a_ch[] = {
49a468ed 55 { "1", { 0, 60, 0.0072, 3, 4 }, { 0, 25, 0.003, 3, 4 }, { 0, 1500 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS },
5c9e56c9
AG		 56};
57
6cc93128 58static const struct channel_spec agilent_n5763a_ch[] = {
49a468ed 59 { "1", { 0, 12.5, 0.0015, 3, 4 }, { 0, 120, 0.0144, 3, 4 }, { 0, 1500 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS },
5c9e56c9
AG		 60};
61
62/*
63 * TODO: OVER_CURRENT_PROTECTION_ACTIVE status can be determined by the OC bit
562a3490 64 * in STAT:QUES:EVEN?, but this is not implemented.
5c9e56c9 65 */
8cb5affe 66static const struct scpi_command agilent_n5700a_cmd[] = {
5c9e56c9
AG		 67 { SCPI_CMD_REMOTE, "SYST:COMM:RLST REM" },
68 { SCPI_CMD_LOCAL, "SYST:COMM:RLST LOC" },
69 { SCPI_CMD_GET_MEAS_VOLTAGE, ":MEAS:VOLT?" },
70 { SCPI_CMD_GET_MEAS_CURRENT, "MEAS:CURR?" },
71 { SCPI_CMD_GET_VOLTAGE_TARGET, ":SOUR:VOLT?" },
72 { SCPI_CMD_SET_VOLTAGE_TARGET, ":SOUR:VOLT %.6f" },
73 { SCPI_CMD_GET_CURRENT_LIMIT, ":SOUR:CURR?" },
74 { SCPI_CMD_SET_CURRENT_LIMIT, ":SOUR:CURR %.6f" },
75 { SCPI_CMD_GET_OUTPUT_ENABLED, ":OUTP:STAT?" },
76 { SCPI_CMD_SET_OUTPUT_ENABLE, ":OUTP ON" },
77 { SCPI_CMD_SET_OUTPUT_DISABLE, ":OUTP OFF" },
78 { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_THRESHOLD, ":VOLT:PROT?" },
79 { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_THRESHOLD, ":VOLT:PROT %.6f" },
80 { SCPI_CMD_GET_OVER_CURRENT_PROTECTION_ENABLED, ":CURR:PROT:STAT?" },
81 { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_ENABLE, ":CURR:PROT:STAT ON?"},
82 { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_DISABLE, ":CURR:PROT:STAT OFF?"},
562a3490 83 /* Current limit (CC mode) and OCP are set using the same command. */
5c9e56c9
AG		 84 { SCPI_CMD_GET_OVER_CURRENT_PROTECTION_THRESHOLD, ":SOUR:CURR?" },
85 { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_THRESHOLD, ":SOUR:CURR %.6f" },
91ef511d 86 ALL_ZERO
5c9e56c9
AG		 87};
88
c3bfb959
MW		 89/* BK Precision 9130 series */
90static const uint32_t bk_9130_devopts[] = {
91 SR_CONF_CONTINUOUS,
92 SR_CONF_LIMIT_SAMPLES | SR_CONF_GET | SR_CONF_SET,
93 SR_CONF_LIMIT_MSEC | SR_CONF_GET | SR_CONF_SET,
94};
95
96static const uint32_t bk_9130_devopts_cg[] = {
97 SR_CONF_OVER_VOLTAGE_PROTECTION_THRESHOLD | SR_CONF_GET | SR_CONF_SET,
98 SR_CONF_VOLTAGE | SR_CONF_GET,
99 SR_CONF_VOLTAGE_TARGET | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
100 SR_CONF_CURRENT | SR_CONF_GET,
101 SR_CONF_CURRENT_LIMIT | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
102 SR_CONF_ENABLED | SR_CONF_GET | SR_CONF_SET,
103};
104
105static const struct channel_spec bk_9130_ch[] = {
106 { "1", { 0, 30, 0.001, 3, 3 }, { 0, 3, 0.001, 3, 3 }, { 0, 90, 0, 3, 3 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS },
107 { "2", { 0, 30, 0.001, 3, 3 }, { 0, 3, 0.001, 3, 3 }, { 0, 90, 0, 3, 3 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS },
108 { "3", { 0, 5, 0.001, 3, 3 }, { 0, 3, 0.001, 3, 3 }, { 0, 15, 0, 3, 3 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS },
109};
110
111static const struct channel_group_spec bk_9130_cg[] = {
112 { "1", CH_IDX(0), PPS_OVP },
113 { "2", CH_IDX(1), PPS_OVP },
114 { "3", CH_IDX(2), PPS_OVP },
115};
116
117static const struct scpi_command bk_9130_cmd[] = {
118 { SCPI_CMD_REMOTE, "SYST:REMOTE" },
119 { SCPI_CMD_LOCAL, "SYST:LOCAL" },
120 { SCPI_CMD_SELECT_CHANNEL, ":INST:NSEL %s" },
121 { SCPI_CMD_GET_MEAS_VOLTAGE, ":MEAS:VOLT?" },
122 { SCPI_CMD_GET_MEAS_CURRENT, ":MEAS:CURR?" },
123 { SCPI_CMD_GET_MEAS_POWER, ":MEAS:POWER?" },
124 { SCPI_CMD_GET_VOLTAGE_TARGET, ":SOUR:VOLT?" },
125 { SCPI_CMD_SET_VOLTAGE_TARGET, ":SOUR:VOLT %.6f" },
126 { SCPI_CMD_GET_CURRENT_LIMIT, ":SOUR:CURR?" },
127 { SCPI_CMD_SET_CURRENT_LIMIT, ":SOUR:CURR %.6f" },
128 { SCPI_CMD_GET_OUTPUT_ENABLED, ":OUTP?" },
129 { SCPI_CMD_SET_OUTPUT_ENABLE, ":OUTP 1" },
130 { SCPI_CMD_SET_OUTPUT_DISABLE, ":OUTP 0" },
131 { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_THRESHOLD, ":SOUR:VOLT:PROT?" },
132 { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_THRESHOLD, ":SOUR:VOLT:PROT %.6f" },
133 ALL_ZERO
134};
135
4ee1e2f3
AG		 136/* Chroma 61600 series AC source */
137static const uint32_t chroma_61604_devopts[] = {
e91bb0a6 138 SR_CONF_CONTINUOUS,
88e4daa9
ML		 139 SR_CONF_LIMIT_SAMPLES | SR_CONF_GET | SR_CONF_SET,
140 SR_CONF_LIMIT_MSEC | SR_CONF_GET | SR_CONF_SET,
4ee1e2f3
AG		 141};
142
143static const uint32_t chroma_61604_devopts_cg[] = {
144 SR_CONF_OVER_VOLTAGE_PROTECTION_THRESHOLD | SR_CONF_GET | SR_CONF_SET,
145 SR_CONF_OVER_CURRENT_PROTECTION_THRESHOLD | SR_CONF_GET | SR_CONF_SET,
da005885
UH		 146 SR_CONF_VOLTAGE | SR_CONF_GET,
147 SR_CONF_VOLTAGE_TARGET | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
6c0c9dd2
AG		 148 SR_CONF_OUTPUT_FREQUENCY | SR_CONF_GET,
149 SR_CONF_OUTPUT_FREQUENCY_TARGET | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
da005885
UH		 150 SR_CONF_CURRENT | SR_CONF_GET,
151 SR_CONF_ENABLED | SR_CONF_GET | SR_CONF_SET,
4ee1e2f3
AG		 152};
153
8cb5affe 154static const struct channel_spec chroma_61604_ch[] = {
49a468ed 155 { "1", { 0, 300, 0.1, 1, 1 }, { 0, 16, 0.1, 2, 2 }, { 0, 2000, 0, 1, 1 }, { 1.0, 1000.0, 0.01 }, NO_OVP_LIMITS, NO_OCP_LIMITS },
4ee1e2f3
AG		 156};
157
8cb5affe 158static const struct channel_group_spec chroma_61604_cg[] = {
4ee1e2f3
AG		 159 { "1", CH_IDX(0), PPS_OVP | PPS_OCP },
160};
161
8cb5affe 162static const struct scpi_command chroma_61604_cmd[] = {
4ee1e2f3
AG		 163 { SCPI_CMD_REMOTE, "SYST:REM" },
164 { SCPI_CMD_LOCAL, "SYST:LOC" },
165 { SCPI_CMD_GET_MEAS_VOLTAGE, ":FETC:VOLT:ACDC?" },
6c0c9dd2 166 { SCPI_CMD_GET_MEAS_FREQUENCY, ":FETC:FREQ?" },
4ee1e2f3
AG		 167 { SCPI_CMD_GET_MEAS_CURRENT, ":FETC:CURR:AC?" },
168 { SCPI_CMD_GET_MEAS_POWER, ":FETC:POW:AC?" },
169 { SCPI_CMD_GET_VOLTAGE_TARGET, ":SOUR:VOLT:AC?" },
170 { SCPI_CMD_SET_VOLTAGE_TARGET, ":SOUR:VOLT:AC %.1f" },
6c0c9dd2
AG		 171 { SCPI_CMD_GET_FREQUENCY_TARGET, ":SOUR:FREQ?" },
172 { SCPI_CMD_SET_FREQUENCY_TARGET, ":SOUR:FREQ %.2f" },
4ee1e2f3
AG		 173 { SCPI_CMD_GET_OUTPUT_ENABLED, ":OUTP?" },
174 { SCPI_CMD_SET_OUTPUT_ENABLE, ":OUTP ON" },
175 { SCPI_CMD_SET_OUTPUT_DISABLE, ":OUTP OFF" },
176 { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_THRESHOLD, ":SOUR:VOLT:LIM:AC?" },
177 { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_THRESHOLD, ":SOUR:VOLT:LIM:AC %.1f" },
562a3490 178 /* This is not a current limit mode. It is overcurrent protection. */
4ee1e2f3
AG		 179 { SCPI_CMD_GET_OVER_CURRENT_PROTECTION_THRESHOLD, ":SOUR:CURR:LIM?" },
180 { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_THRESHOLD, ":SOUR:CURR:LIM %.2f" },
91ef511d 181 ALL_ZERO
4ee1e2f3
AG		 182};
183
5281993e 184/* Chroma 62000 series DC source */
5281993e 185static const uint32_t chroma_62000_devopts[] = {
e91bb0a6 186 SR_CONF_CONTINUOUS,
88e4daa9
ML		 187 SR_CONF_LIMIT_SAMPLES | SR_CONF_GET | SR_CONF_SET,
188 SR_CONF_LIMIT_MSEC | SR_CONF_GET | SR_CONF_SET,
5281993e
AG		 189};
190
191static const uint32_t chroma_62000_devopts_cg[] = {
192 SR_CONF_OVER_VOLTAGE_PROTECTION_THRESHOLD | SR_CONF_GET | SR_CONF_SET,
193 SR_CONF_OVER_CURRENT_PROTECTION_THRESHOLD | SR_CONF_GET | SR_CONF_SET,
194 SR_CONF_VOLTAGE | SR_CONF_GET,
195 SR_CONF_VOLTAGE_TARGET | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
196 SR_CONF_CURRENT | SR_CONF_GET,
197 SR_CONF_CURRENT_LIMIT | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
198 SR_CONF_ENABLED | SR_CONF_GET | SR_CONF_SET,
199};
200
5281993e
AG		 201static const struct channel_group_spec chroma_62000_cg[] = {
202 { "1", CH_IDX(0), PPS_OVP | PPS_OCP },
203};
204
205static const struct scpi_command chroma_62000_cmd[] = {
206 { SCPI_CMD_REMOTE, ":CONF:REM ON" },
207 { SCPI_CMD_LOCAL, ":CONF:REM OFF" },
208 { SCPI_CMD_BEEPER, ":CONF:BEEP?" },
209 { SCPI_CMD_BEEPER_ENABLE, ":CONF:BEEP ON" },
210 { SCPI_CMD_BEEPER_DISABLE, ":CONF:BEEP OFF" },
211 { SCPI_CMD_GET_MEAS_VOLTAGE, ":MEAS:VOLT?" },
212 { SCPI_CMD_GET_MEAS_CURRENT, ":MEAS:CURR?" },
213 { SCPI_CMD_GET_MEAS_POWER, ":MEAS:POW?" },
214 { SCPI_CMD_GET_VOLTAGE_TARGET, ":SOUR:VOLT?" },
215 { SCPI_CMD_SET_VOLTAGE_TARGET, ":SOUR:VOLT %.2f" },
216 { SCPI_CMD_GET_CURRENT_LIMIT, ":SOUR:CURR?" },
217 { SCPI_CMD_SET_CURRENT_LIMIT, ":SOUR:CURR %.6f" },
218 { SCPI_CMD_GET_OUTPUT_ENABLED, ":CONF:OUTP?" },
219 { SCPI_CMD_SET_OUTPUT_ENABLE, ":CONF:OUTP ON" },
220 { SCPI_CMD_SET_OUTPUT_DISABLE, ":CONF:OUTP OFF" },
221 { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_THRESHOLD, ":SOUR:VOLT:PROT:HIGH?" },
222 { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_THRESHOLD, ":SOUR:VOLT:PROT:HIGH %.6f" },
223 { SCPI_CMD_GET_OVER_CURRENT_PROTECTION_THRESHOLD, ":SOUR:CURR:PROT:HIGH?" },
224 { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_THRESHOLD, ":SOUR:CURR:PROT:HIGH %.6f" },
91ef511d 225 ALL_ZERO
5281993e
AG		 226};
227
9a5185c7
AG		 228static int chroma_62000p_probe_channels(struct sr_dev_inst *sdi,
229 struct sr_scpi_hw_info *hw_info,
230 struct channel_spec **channels, unsigned int *num_channels,
231 struct channel_group_spec **channel_groups,
232 unsigned int *num_channel_groups)
233{
6ed709fe 234 unsigned int volts, amps, watts;
9a5185c7
AG		 235 struct channel_spec *channel;
236
237 (void)sdi;
238
6ed709fe
AJ		 239 sscanf(hw_info->model, "620%uP-%u-%u", &watts, &volts, &amps);
240 watts *= 100;
241 sr_dbg("Found device rated for %d V, %d A and %d W", volts, amps, watts);
9a5185c7
AG		 242
243 if (volts > 600) {
244 sr_err("Probed max voltage of %u V is out of spec.", volts);
245 return SR_ERR_BUG;
246 }
247
6ed709fe 248 if (amps > 120) {
9a5185c7
AG		 249 sr_err("Probed max current of %u A is out of spec.", amps);
250 return SR_ERR_BUG;
251 }
252
6ed709fe
AJ		 253 if (watts > 5000) {
254 sr_err("Probed max power of %u W is out of spec.", watts);
255 return SR_ERR_BUG;
256 }
257
9a5185c7
AG		 258 channel = g_malloc0(sizeof(struct channel_spec));
259 channel->name = "1";
6ed709fe 260 channel->voltage[0] = channel->current[0] = channel->power[0] = 0.0;
bcee1299
UH		 261 channel->voltage[1] = volts;
262 channel->current[1] = amps;
263 channel->power[1] = watts;
9a5185c7 264 channel->voltage[2] = channel->current[2] = 0.01;
6ed709fe
AJ		 265 channel->voltage[3] = channel->voltage[4] = 3;
266 channel->current[3] = channel->current[4] = 4;
9a5185c7
AG		 267 *channels = channel;
268 *num_channels = 1;
269
270 *channel_groups = g_malloc(sizeof(struct channel_group_spec));
271 **channel_groups = chroma_62000_cg[0];
272 *num_channel_groups = 1;
273
274 return SR_OK;
275}
276
319fe9ce
UH		 277/* Rigol DP700 series */
278static const uint32_t rigol_dp700_devopts[] = {
279 SR_CONF_CONTINUOUS,
88e4daa9
ML		 280 SR_CONF_LIMIT_SAMPLES | SR_CONF_GET | SR_CONF_SET,
281 SR_CONF_LIMIT_MSEC | SR_CONF_GET | SR_CONF_SET,
319fe9ce
UH		 282};
283
284static const uint32_t rigol_dp700_devopts_cg[] = {
285 SR_CONF_REGULATION | SR_CONF_GET,
286 SR_CONF_OVER_VOLTAGE_PROTECTION_ENABLED | SR_CONF_GET | SR_CONF_SET,
287 SR_CONF_OVER_VOLTAGE_PROTECTION_ACTIVE | SR_CONF_GET,
d828b05e 288 SR_CONF_OVER_VOLTAGE_PROTECTION_THRESHOLD | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
319fe9ce
UH		 289 SR_CONF_OVER_CURRENT_PROTECTION_ENABLED | SR_CONF_GET | SR_CONF_SET,
290 SR_CONF_OVER_CURRENT_PROTECTION_ACTIVE | SR_CONF_GET,
d828b05e 291 SR_CONF_OVER_CURRENT_PROTECTION_THRESHOLD | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
319fe9ce
UH		 292 SR_CONF_VOLTAGE | SR_CONF_GET,
293 SR_CONF_VOLTAGE_TARGET | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
294 SR_CONF_CURRENT | SR_CONF_GET,
295 SR_CONF_CURRENT_LIMIT | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
296 SR_CONF_ENABLED | SR_CONF_GET | SR_CONF_SET,
297};
298
299static const struct channel_spec rigol_dp711_ch[] = {
d828b05e 300 { "1", { 0, 30, 0.01, 3, 3 }, { 0, 5, 0.01, 3, 3 }, { 0, 150, 0, 3, 3 }, FREQ_DC_ONLY, { 0.01, 33, 0.01}, { 0.01, 5.5, 0.01 } },
319fe9ce
UH		 301};
302
303static const struct channel_spec rigol_dp712_ch[] = {
d828b05e 304 { "1", { 0, 50, 0.01, 3, 3 }, { 0, 3, 0.01, 3, 3 }, { 0, 150, 0, 3, 3 }, FREQ_DC_ONLY, { 0.01, 55, 0.01}, { 0.01, 3.3, 0.01 } },
319fe9ce
UH		 305};
306
307static const struct channel_group_spec rigol_dp700_cg[] = {
308 { "1", CH_IDX(0), PPS_OVP | PPS_OCP },
309};
310
311/* Same as the DP800 series, except for the missing :SYST:OTP* commands. */
312static const struct scpi_command rigol_dp700_cmd[] = {
313 { SCPI_CMD_REMOTE, "SYST:REMOTE" },
314 { SCPI_CMD_LOCAL, "SYST:LOCAL" },
315 { SCPI_CMD_BEEPER, "SYST:BEEP:STAT?" },
316 { SCPI_CMD_BEEPER_ENABLE, "SYST:BEEP:STAT ON" },
317 { SCPI_CMD_BEEPER_DISABLE, "SYST:BEEP:STAT OFF" },
318 { SCPI_CMD_SELECT_CHANNEL, ":INST:NSEL %s" },
319 { SCPI_CMD_GET_MEAS_VOLTAGE, ":MEAS:VOLT?" },
320 { SCPI_CMD_GET_MEAS_CURRENT, ":MEAS:CURR?" },
321 { SCPI_CMD_GET_MEAS_POWER, ":MEAS:POWE?" },
322 { SCPI_CMD_GET_VOLTAGE_TARGET, ":SOUR:VOLT?" },
323 { SCPI_CMD_SET_VOLTAGE_TARGET, ":SOUR:VOLT %.6f" },
324 { SCPI_CMD_GET_CURRENT_LIMIT, ":SOUR:CURR?" },
325 { SCPI_CMD_SET_CURRENT_LIMIT, ":SOUR:CURR %.6f" },
326 { SCPI_CMD_GET_OUTPUT_ENABLED, ":OUTP?" },
327 { SCPI_CMD_SET_OUTPUT_ENABLE, ":OUTP ON" },
328 { SCPI_CMD_SET_OUTPUT_DISABLE, ":OUTP OFF" },
329 { SCPI_CMD_GET_OUTPUT_REGULATION, ":OUTP:MODE?" },
330 { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_ENABLED, ":OUTP:OVP?" },
331 { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_ENABLE, ":OUTP:OVP ON" },
332 { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_DISABLE, ":OUTP:OVP OFF" },
333 { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_ACTIVE, ":OUTP:OVP:QUES?" },
334 { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_THRESHOLD, ":OUTP:OVP:VAL?" },
335 { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_THRESHOLD, ":OUTP:OVP:VAL %.6f" },
336 { SCPI_CMD_GET_OVER_CURRENT_PROTECTION_ENABLED, ":OUTP:OCP?" },
337 { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_ENABLE, ":OUTP:OCP:STAT ON" },
338 { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_DISABLE, ":OUTP:OCP:STAT OFF" },
339 { SCPI_CMD_GET_OVER_CURRENT_PROTECTION_ACTIVE, ":OUTP:OCP:QUES?" },
340 { SCPI_CMD_GET_OVER_CURRENT_PROTECTION_THRESHOLD, ":OUTP:OCP:VAL?" },
341 { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_THRESHOLD, ":OUTP:OCP:VAL %.6f" },
342 ALL_ZERO
343};
344
d4eabea8 345/* Rigol DP800 series */
584560f1 346static const uint32_t rigol_dp800_devopts[] = {
e91bb0a6 347 SR_CONF_CONTINUOUS,
5827f61b 348 SR_CONF_OVER_TEMPERATURE_PROTECTION | SR_CONF_GET | SR_CONF_SET,
88e4daa9
ML		 349 SR_CONF_LIMIT_SAMPLES | SR_CONF_GET | SR_CONF_SET,
350 SR_CONF_LIMIT_MSEC | SR_CONF_GET | SR_CONF_SET,
d4eabea8
BV		 351};
352
584560f1 353static const uint32_t rigol_dp800_devopts_cg[] = {
7a0b98b5 354 SR_CONF_REGULATION | SR_CONF_GET,
5827f61b
BV		 355 SR_CONF_OVER_VOLTAGE_PROTECTION_ENABLED | SR_CONF_GET | SR_CONF_SET,
356 SR_CONF_OVER_VOLTAGE_PROTECTION_ACTIVE | SR_CONF_GET,
357 SR_CONF_OVER_VOLTAGE_PROTECTION_THRESHOLD | SR_CONF_GET | SR_CONF_SET,
358 SR_CONF_OVER_CURRENT_PROTECTION_ENABLED | SR_CONF_GET | SR_CONF_SET,
359 SR_CONF_OVER_CURRENT_PROTECTION_ACTIVE | SR_CONF_GET,
360 SR_CONF_OVER_CURRENT_PROTECTION_THRESHOLD | SR_CONF_GET | SR_CONF_SET,
7a0b98b5
AJ		 361 SR_CONF_VOLTAGE | SR_CONF_GET,
362 SR_CONF_VOLTAGE_TARGET | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
363 SR_CONF_CURRENT | SR_CONF_GET,
364 SR_CONF_CURRENT_LIMIT | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
365 SR_CONF_ENABLED | SR_CONF_GET | SR_CONF_SET,
d4eabea8
BV		 366};
367
8cb5affe 368static const struct channel_spec rigol_dp821a_ch[] = {
49a468ed
FS		 369 { "1", { 0, 60, 0.001, 3, 3 }, { 0, 1, 0.0001, 4, 4 }, { 0, 60, 0, 3, 4 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS },
370 { "2", { 0, 8, 0.001, 3, 3 }, { 0, 10, 0.001, 3, 3 }, { 0, 80, 0, 3, 3 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS },
cfcdf576
ML		 371};
372
8cb5affe 373static const struct channel_spec rigol_dp831_ch[] = {
49a468ed
FS		 374 { "1", { 0, 8, 0.001, 3, 4 }, { 0, 5, 0.0003, 3, 4 }, { 0, 40, 0, 3, 4 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS },
375 { "2", { 0, 30, 0.001, 3, 4 }, { 0, 2, 0.0001, 3, 4 }, { 0, 60, 0, 3, 4 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS },
376 { "3", { 0, -30, 0.001, 3, 4 }, { 0, 2, 0.0001, 3, 4 }, { 0, 60, 0, 3, 4 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS },
d4eabea8
BV		 377};
378
8cb5affe 379static const struct channel_spec rigol_dp832_ch[] = {
49a468ed
FS		 380 { "1", { 0, 30, 0.001, 3, 4 }, { 0, 3, 0.001, 3, 4 }, { 0, 90, 0, 3, 4 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS },
381 { "2", { 0, 30, 0.001, 3, 4 }, { 0, 3, 0.001, 3, 4 }, { 0, 90, 0, 3, 4 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS },
382 { "3", { 0, 5, 0.001, 3, 4 }, { 0, 3, 0.001, 3, 4 }, { 0, 90, 0, 3, 4 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS },
3222ee10
BV		 383};
384
8cb5affe 385static const struct channel_group_spec rigol_dp820_cg[] = {
cfcdf576
ML		 386 { "1", CH_IDX(0), PPS_OVP | PPS_OCP },
387 { "2", CH_IDX(1), PPS_OVP | PPS_OCP },
388};
389
8cb5affe 390static const struct channel_group_spec rigol_dp830_cg[] = {
d4eabea8
BV		 391 { "1", CH_IDX(0), PPS_OVP | PPS_OCP },
392 { "2", CH_IDX(1), PPS_OVP | PPS_OCP },
393 { "3", CH_IDX(2), PPS_OVP | PPS_OCP },
394};
395
8cb5affe 396static const struct scpi_command rigol_dp800_cmd[] = {
60475cd7
BV		 397 { SCPI_CMD_REMOTE, "SYST:REMOTE" },
398 { SCPI_CMD_LOCAL, "SYST:LOCAL" },
ee2860ee
BV		 399 { SCPI_CMD_BEEPER, "SYST:BEEP:STAT?" },
400 { SCPI_CMD_BEEPER_ENABLE, "SYST:BEEP:STAT ON" },
401 { SCPI_CMD_BEEPER_DISABLE, "SYST:BEEP:STAT OFF" },
60475cd7
BV		 402 { SCPI_CMD_SELECT_CHANNEL, ":INST:NSEL %s" },
403 { SCPI_CMD_GET_MEAS_VOLTAGE, ":MEAS:VOLT?" },
404 { SCPI_CMD_GET_MEAS_CURRENT, ":MEAS:CURR?" },
405 { SCPI_CMD_GET_MEAS_POWER, ":MEAS:POWE?" },
406 { SCPI_CMD_GET_VOLTAGE_TARGET, ":SOUR:VOLT?" },
407 { SCPI_CMD_SET_VOLTAGE_TARGET, ":SOUR:VOLT %.6f" },
408 { SCPI_CMD_GET_CURRENT_LIMIT, ":SOUR:CURR?" },
409 { SCPI_CMD_SET_CURRENT_LIMIT, ":SOUR:CURR %.6f" },
410 { SCPI_CMD_GET_OUTPUT_ENABLED, ":OUTP?" },
411 { SCPI_CMD_SET_OUTPUT_ENABLE, ":OUTP ON" },
412 { SCPI_CMD_SET_OUTPUT_DISABLE, ":OUTP OFF" },
413 { SCPI_CMD_GET_OUTPUT_REGULATION, ":OUTP:MODE?" },
d4eabea8 414 { SCPI_CMD_GET_OVER_TEMPERATURE_PROTECTION, ":SYST:OTP?" },
53a81803
BV		 415 { SCPI_CMD_SET_OVER_TEMPERATURE_PROTECTION_ENABLE, ":SYST:OTP ON" },
416 { SCPI_CMD_SET_OVER_TEMPERATURE_PROTECTION_DISABLE, ":SYST:OTP OFF" },
60475cd7
BV		 417 { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_ENABLED, ":OUTP:OVP?" },
418 { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_ENABLE, ":OUTP:OVP ON" },
419 { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_DISABLE, ":OUTP:OVP OFF" },
420 { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_ACTIVE, ":OUTP:OVP:QUES?" },
421 { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_THRESHOLD, ":OUTP:OVP:VAL?" },
422 { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_THRESHOLD, ":OUTP:OVP:VAL %.6f" },
423 { SCPI_CMD_GET_OVER_CURRENT_PROTECTION_ENABLED, ":OUTP:OCP?" },
424 { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_ENABLE, ":OUTP:OCP:STAT ON" },
425 { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_DISABLE, ":OUTP:OCP:STAT OFF" },
426 { SCPI_CMD_GET_OVER_CURRENT_PROTECTION_ACTIVE, ":OUTP:OCP:QUES?" },
427 { SCPI_CMD_GET_OVER_CURRENT_PROTECTION_THRESHOLD, ":OUTP:OCP:VAL?" },
428 { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_THRESHOLD, ":OUTP:OCP:VAL %.6f" },
91ef511d 429 ALL_ZERO
d4eabea8
BV		 430};
431
bfc86799 432/* HP 663xx series */
e76a3575
AG		 433static const uint32_t hp_6630a_devopts[] = {
434 SR_CONF_CONTINUOUS,
88e4daa9
ML		 435 SR_CONF_LIMIT_SAMPLES | SR_CONF_GET | SR_CONF_SET,
436 SR_CONF_LIMIT_MSEC | SR_CONF_GET | SR_CONF_SET,
7c517d02
FS		 437};
438
439static const uint32_t hp_6630a_devopts_cg[] = {
e76a3575
AG		 440 SR_CONF_ENABLED | SR_CONF_SET,
441 SR_CONF_VOLTAGE | SR_CONF_GET,
442 SR_CONF_CURRENT | SR_CONF_GET,
443 SR_CONF_VOLTAGE_TARGET | SR_CONF_SET | SR_CONF_LIST,
444 SR_CONF_CURRENT_LIMIT | SR_CONF_SET | SR_CONF_LIST,
49a468ed 445 SR_CONF_OVER_VOLTAGE_PROTECTION_THRESHOLD | SR_CONF_SET | SR_CONF_LIST,
e76a3575
AG		 446 SR_CONF_OVER_CURRENT_PROTECTION_ENABLED | SR_CONF_SET,
447};
448
a61c8cce 449static const uint32_t hp_6630b_devopts[] = {
e91bb0a6 450 SR_CONF_CONTINUOUS,
88e4daa9
ML		 451 SR_CONF_LIMIT_SAMPLES | SR_CONF_GET | SR_CONF_SET,
452 SR_CONF_LIMIT_MSEC | SR_CONF_GET | SR_CONF_SET,
7c517d02
FS		 453};
454
a61c8cce 455static const uint32_t hp_6630b_devopts_cg[] = {
7a0b98b5
AJ		 456 SR_CONF_ENABLED | SR_CONF_GET | SR_CONF_SET,
457 SR_CONF_VOLTAGE | SR_CONF_GET,
458 SR_CONF_CURRENT | SR_CONF_GET,
459 SR_CONF_VOLTAGE_TARGET | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
460 SR_CONF_CURRENT_LIMIT | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
49a468ed 461 SR_CONF_OVER_VOLTAGE_PROTECTION_THRESHOLD | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
7e381bfc 462 SR_CONF_OVER_CURRENT_PROTECTION_ENABLED | SR_CONF_GET | SR_CONF_SET,
43ff1110 463 SR_CONF_REGULATION | SR_CONF_GET,
bc4a2a46
BV		 464};
465
e76a3575 466static const struct channel_spec hp_6633a_ch[] = {
49a468ed 467 { "1", { 0, 51.188, 0.0125, 3, 4 }, { 0, 2.0475, 0.0005, 4, 5 }, { 0, 104.80743 }, FREQ_DC_ONLY, { 0, 55, 0.25 }, NO_OCP_LIMITS },
e76a3575
AG		 468};
469
a61c8cce 470static const struct channel_spec hp_6631b_ch[] = {
49a468ed 471 { "1", { 0, 8.19, 0.002, 3, 4 }, { 0, 10.237, 0.00263, 4, 5 }, { 0, 83.84103 }, FREQ_DC_ONLY, { 0, 12, 0.06 }, NO_OCP_LIMITS },
a61c8cce
FS		 472};
473
8cb5affe 474static const struct channel_spec hp_6632b_ch[] = {
49a468ed 475 { "1", { 0, 20.475, 0.005, 3, 4 }, { 0, 5.1188, 0.00132, 4, 5 }, { 0, 104.80743 }, FREQ_DC_ONLY, { 0, 22, 0.1 }, NO_OCP_LIMITS },
bc4a2a46
BV		 476};
477
a61c8cce 478static const struct channel_spec hp_66332a_ch[] = {
49a468ed 479 { "1", { 0, 20.475, 0.005, 3, 4 }, { 0, 5.1188, 0.00132, 4, 5 }, { 0, 104.80743 }, FREQ_DC_ONLY, { 0, 22, 0.1 }, NO_OCP_LIMITS },
a61c8cce
FS		 480};
481
482static const struct channel_spec hp_6633b_ch[] = {
49a468ed 483 { "1", { 0, 51.188, 0.0125, 3, 4 }, { 0, 2.0475, 0.000526, 4, 5 }, { 0, 104.80743 }, FREQ_DC_ONLY, { 0, 55, 0.25 }, NO_OCP_LIMITS },
a61c8cce
FS		 484};
485
486static const struct channel_spec hp_6634b_ch[] = {
49a468ed 487 { "1", { 0, 102.38, 0.025, 3, 4 }, { 0, 1.0238, 0.000263, 4, 5 }, { 0, 104.81664 }, FREQ_DC_ONLY, { 0, 110, 0.5 }, NO_OCP_LIMITS },
a61c8cce
FS		 488};
489
e76a3575 490static const struct channel_group_spec hp_663xx_cg[] = {
bc4a2a46
BV		 491 { "1", CH_IDX(0), 0 },
492};
493
e76a3575
AG		 494static const struct scpi_command hp_6630a_cmd[] = {
495 { SCPI_CMD_SET_OUTPUT_ENABLE, "OUT 1" },
496 { SCPI_CMD_SET_OUTPUT_DISABLE, "OUT 0" },
497 { SCPI_CMD_GET_MEAS_VOLTAGE, "VOUT?" },
498 { SCPI_CMD_GET_MEAS_CURRENT, "IOUT?" },
499 { SCPI_CMD_SET_VOLTAGE_TARGET, "VSET %.4f" },
500 { SCPI_CMD_SET_CURRENT_LIMIT, "ISET %.4f" },
501 { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_ENABLE, "OCP 1" },
502 { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_DISABLE, "OCP 0" },
503 { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_THRESHOLD, "OVSET %.4f" },
504 ALL_ZERO
505};
506
a61c8cce 507static const struct scpi_command hp_6630b_cmd[] = {
7e381bfc
FS		 508 { SCPI_CMD_REMOTE, "SYST:REM" },
509 { SCPI_CMD_LOCAL, "SYST:LOC" },
bc4a2a46 510 { SCPI_CMD_GET_OUTPUT_ENABLED, "OUTP:STAT?" },
53a81803
BV		 511 { SCPI_CMD_SET_OUTPUT_ENABLE, "OUTP:STAT ON" },
512 { SCPI_CMD_SET_OUTPUT_DISABLE, "OUTP:STAT OFF" },
bc4a2a46
BV		 513 { SCPI_CMD_GET_MEAS_VOLTAGE, ":MEAS:VOLT?" },
514 { SCPI_CMD_GET_MEAS_CURRENT, ":MEAS:CURR?" },
ca95e90f
BV		 515 { SCPI_CMD_GET_VOLTAGE_TARGET, ":SOUR:VOLT?" },
516 { SCPI_CMD_SET_VOLTAGE_TARGET, ":SOUR:VOLT %.6f" },
517 { SCPI_CMD_GET_CURRENT_LIMIT, ":SOUR:CURR?" },
518 { SCPI_CMD_SET_CURRENT_LIMIT, ":SOUR:CURR %.6f" },
7e381bfc
FS		 519 { SCPI_CMD_GET_OVER_CURRENT_PROTECTION_ENABLED, ":CURR:PROT:STAT?" },
520 { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_ENABLE, ":CURR:PROT:STAT 1" },
521 { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_DISABLE, ":CURR:PROT:STAT 0" },
522 { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_THRESHOLD, ":VOLT:PROT?" },
523 { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_THRESHOLD, ":VOLT:PROT %.6f" },
43ff1110 524 { SCPI_CMD_GET_OUTPUT_REGULATION, "STAT:OPER:COND?" },
91ef511d 525 ALL_ZERO
bc4a2a46
BV		 526};
527
c3eadb07 528/* Philips/Fluke PM2800 series */
9d9cf1c4 529static const uint32_t philips_pm2800_devopts[] = {
e91bb0a6 530 SR_CONF_CONTINUOUS,
88e4daa9
ML		 531 SR_CONF_LIMIT_SAMPLES | SR_CONF_GET | SR_CONF_SET,
532 SR_CONF_LIMIT_MSEC | SR_CONF_GET | SR_CONF_SET,
9d9cf1c4
BV		 533};
534
c3eadb07 535static const uint32_t philips_pm2800_devopts_cg[] = {
7a0b98b5
AJ		 536 SR_CONF_ENABLED | SR_CONF_GET | SR_CONF_SET,
537 SR_CONF_VOLTAGE | SR_CONF_GET,
538 SR_CONF_VOLTAGE_TARGET | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
539 SR_CONF_CURRENT | SR_CONF_GET,
540 SR_CONF_CURRENT_LIMIT | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
c3eadb07
BV		 541 SR_CONF_OVER_VOLTAGE_PROTECTION_ACTIVE | SR_CONF_GET,
542 SR_CONF_OVER_VOLTAGE_PROTECTION_THRESHOLD | SR_CONF_GET | SR_CONF_SET,
543 SR_CONF_OVER_CURRENT_PROTECTION_ENABLED | SR_CONF_GET | SR_CONF_SET,
544 SR_CONF_OVER_CURRENT_PROTECTION_ACTIVE | SR_CONF_GET,
7a0b98b5 545 SR_CONF_REGULATION | SR_CONF_GET,
c3eadb07
BV		 546};
547
548enum philips_pm2800_modules {
549 PM2800_MOD_30V_10A = 1,
550 PM2800_MOD_60V_5A,
551 PM2800_MOD_60V_10A,
552 PM2800_MOD_8V_15A,
553 PM2800_MOD_60V_2A,
554 PM2800_MOD_120V_1A,
555};
556
329733d9 557static const struct philips_pm2800_module_spec {
c3eadb07 558 /* Min, max, programming resolution. */
bcee1299
UH		 559 double voltage[5];
560 double current[5];
561 double power[5];
c3eadb07
BV		 562} philips_pm2800_module_specs[] = {
563 /* Autoranging modules. */
6ed709fe
AJ		 564 [PM2800_MOD_30V_10A] = { { 0, 30, 0.0075, 2, 4 }, { 0, 10, 0.0025, 2, 4 }, { 0, 60 } },
565 [PM2800_MOD_60V_5A] = { { 0, 60, 0.015, 2, 3 }, { 0, 5, 0.00125, 2, 5 }, { 0, 60 } },
566 [PM2800_MOD_60V_10A] = { { 0, 60, 0.015, 2, 3 }, { 0, 10, 0.0025, 2, 5 }, { 0, 120 } },
c3eadb07 567 /* Linear modules. */
6ed709fe
AJ		 568 [PM2800_MOD_8V_15A] = { { 0, 8, 0.002, 3, 3 }, { -15, 15, 0.00375, 3, 5 }, { 0, 120 } },
569 [PM2800_MOD_60V_2A] = { { 0, 60, 0.015, 2, 3 }, { -2, 2, 0.0005, 3, 4 }, { 0, 120 } },
570 [PM2800_MOD_120V_1A] = { { 0, 120, 0.030, 2, 2 }, { -1, 1, 0.00025, 3, 5 }, { 0, 120 } },
c3eadb07
BV		 571};
572
329733d9 573static const struct philips_pm2800_model {
c3eadb07
BV		 574 unsigned int chassis;
575 unsigned int num_modules;
576 unsigned int set;
577 unsigned int modules[3];
578} philips_pm2800_matrix[] = {
579 /* Autoranging chassis. */
580 { 1, 1, 0, { PM2800_MOD_30V_10A, 0, 0 } },
581 { 1, 1, 1, { PM2800_MOD_60V_5A, 0, 0 } },
582 { 1, 2, 0, { PM2800_MOD_30V_10A, PM2800_MOD_30V_10A, 0 } },
583 { 1, 2, 1, { PM2800_MOD_60V_5A, PM2800_MOD_60V_5A, 0 } },
584 { 1, 2, 2, { PM2800_MOD_30V_10A, PM2800_MOD_60V_5A, 0 } },
585 { 1, 2, 3, { PM2800_MOD_30V_10A, PM2800_MOD_60V_10A, 0 } },
586 { 1, 2, 4, { PM2800_MOD_60V_5A, PM2800_MOD_60V_10A, 0 } },
587 { 1, 3, 0, { PM2800_MOD_30V_10A, PM2800_MOD_30V_10A, PM2800_MOD_30V_10A } },
588 { 1, 3, 1, { PM2800_MOD_60V_5A, PM2800_MOD_60V_5A, PM2800_MOD_60V_5A } },
589 { 1, 3, 2, { PM2800_MOD_30V_10A, PM2800_MOD_30V_10A, PM2800_MOD_60V_5A } },
590 { 1, 3, 3, { PM2800_MOD_30V_10A, PM2800_MOD_60V_5A, PM2800_MOD_60V_5A } },
591 /* Linear chassis. */
592 { 3, 1, 0, { PM2800_MOD_60V_2A, 0, 0 } },
593 { 3, 1, 1, { PM2800_MOD_120V_1A, 0, 0 } },
594 { 3, 1, 2, { PM2800_MOD_8V_15A, 0, 0 } },
595 { 3, 2, 0, { PM2800_MOD_60V_2A, 0, 0 } },
596 { 3, 2, 1, { PM2800_MOD_120V_1A, 0, 0 } },
597 { 3, 2, 2, { PM2800_MOD_60V_2A, PM2800_MOD_120V_1A, 0 } },
598 { 3, 2, 3, { PM2800_MOD_8V_15A, PM2800_MOD_8V_15A, 0 } },
599};
600
329733d9 601static const char *philips_pm2800_names[] = { "1", "2", "3" };
c3eadb07
BV		 602
603static int philips_pm2800_probe_channels(struct sr_dev_inst *sdi,
604 struct sr_scpi_hw_info *hw_info,
605 struct channel_spec **channels, unsigned int *num_channels,
606 struct channel_group_spec **channel_groups, unsigned int *num_channel_groups)
607{
329733d9
UH		 608 const struct philips_pm2800_model *model;
609 const struct philips_pm2800_module_spec *spec;
c3eadb07
BV		 610 unsigned int chassis, num_modules, set, module, m, i;
611
612 (void)sdi;
613
614 /*
615 * The model number as reported by *IDN? looks like e.g. PM2813/11,
616 * Where "PM28" is fixed, followed by the chassis code (1 = autoranging,
617 * 3 = linear series) and the number of modules: 1-3 for autoranging,
618 * 1-2 for linear.
619 * After the slash, the first digit denotes the module set. The
620 * digit after that denotes front (5) or rear (1) binding posts.
621 */
622 chassis = hw_info->model[4] - 0x30;
623 num_modules = hw_info->model[5] - 0x30;
624 set = hw_info->model[7] - 0x30;
625 for (m = 0; m < ARRAY_SIZE(philips_pm2800_matrix); m++) {
626 model = &philips_pm2800_matrix[m];
627 if (model->chassis == chassis && model->num_modules == num_modules
628 && model->set == set)
629 break;
630 }
631 if (m == ARRAY_SIZE(philips_pm2800_matrix)) {
632 sr_dbg("Model %s not found in matrix.", hw_info->model);
633 return SR_ERR;
634 }
635
636 sr_dbg("Found %d output channel%s:", num_modules, num_modules > 1 ? "s" : "");
637 *channels = g_malloc0(sizeof(struct channel_spec) * num_modules);
638 *channel_groups = g_malloc0(sizeof(struct channel_group_spec) * num_modules);
639 for (i = 0; i < num_modules; i++) {
640 module = model->modules[i];
641 spec = &philips_pm2800_module_specs[module];
6ed709fe 642 sr_dbg("output %d: %.0f - %.0fV, %.0f - %.0fA, %.0f - %.0fW", i + 1,
c3eadb07 643 spec->voltage[0], spec->voltage[1],
6ed709fe 644 spec->current[0], spec->current[1],
d9251a2c 645 spec->power[0], spec->power[1]);
329733d9 646 (*channels)[i].name = (char *)philips_pm2800_names[i];
bcee1299 647 memcpy(&((*channels)[i].voltage), spec, sizeof(double) * 15);
329733d9 648 (*channel_groups)[i].name = (char *)philips_pm2800_names[i];
c3eadb07
BV		 649 (*channel_groups)[i].channel_index_mask = 1 << i;
650 (*channel_groups)[i].features = PPS_OTP | PPS_OVP | PPS_OCP;
651 }
652 *num_channels = *num_channel_groups = num_modules;
653
654 return SR_OK;
655}
656
8cb5affe 657static const struct scpi_command philips_pm2800_cmd[] = {
c3eadb07
BV		 658 { SCPI_CMD_SELECT_CHANNEL, ":INST:NSEL %s" },
659 { SCPI_CMD_GET_MEAS_VOLTAGE, ":MEAS:VOLT?" },
660 { SCPI_CMD_GET_MEAS_CURRENT, ":MEAS:CURR?" },
661 { SCPI_CMD_GET_VOLTAGE_TARGET, ":SOUR:VOLT?" },
662 { SCPI_CMD_SET_VOLTAGE_TARGET, ":SOUR:VOLT %.6f" },
663 { SCPI_CMD_GET_CURRENT_LIMIT, ":SOUR:CURR?" },
664 { SCPI_CMD_SET_CURRENT_LIMIT, ":SOUR:CURR %.6f" },
665 { SCPI_CMD_GET_OUTPUT_ENABLED, ":OUTP?" },
666 { SCPI_CMD_SET_OUTPUT_ENABLE, ":OUTP ON" },
667 { SCPI_CMD_SET_OUTPUT_DISABLE, ":OUTP OFF" },
668 { SCPI_CMD_GET_OUTPUT_REGULATION, ":SOUR:FUNC:MODE?" },
669 { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_ACTIVE, ":SOUR:VOLT:PROT:TRIP?" },
670 { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_THRESHOLD, ":SOUR:VOLT:PROT:LEV?" },
671 { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_THRESHOLD, ":SOUR:VOLT:PROT:LEV %.6f" },
672 { SCPI_CMD_GET_OVER_CURRENT_PROTECTION_ENABLED, ":SOUR:CURR:PROT:STAT?" },
673 { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_ENABLE, ":SOUR:CURR:PROT:STAT ON" },
674 { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_DISABLE, ":SOUR:CURR:PROT:STAT OFF" },
675 { SCPI_CMD_GET_OVER_CURRENT_PROTECTION_ACTIVE, ":SOUR:CURR:PROT:TRIP?" },
91ef511d 676 ALL_ZERO
c3eadb07
BV		 677};
678
81eb36d6
MS		 679static const uint32_t rs_hmc8043_devopts[] = {
680 SR_CONF_CONTINUOUS,
88e4daa9
ML		 681 SR_CONF_LIMIT_SAMPLES | SR_CONF_GET | SR_CONF_SET,
682 SR_CONF_LIMIT_MSEC | SR_CONF_GET | SR_CONF_SET,
81eb36d6
MS		 683};
684
685static const uint32_t rs_hmc8043_devopts_cg[] = {
686 SR_CONF_OVER_VOLTAGE_PROTECTION_ENABLED | SR_CONF_GET | SR_CONF_SET,
687 SR_CONF_OVER_VOLTAGE_PROTECTION_ACTIVE | SR_CONF_GET,
688 SR_CONF_OVER_VOLTAGE_PROTECTION_THRESHOLD | SR_CONF_GET | SR_CONF_SET,
689 SR_CONF_VOLTAGE | SR_CONF_GET,
690 SR_CONF_VOLTAGE_TARGET | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
691 SR_CONF_CURRENT | SR_CONF_GET,
692 SR_CONF_CURRENT_LIMIT | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
693 SR_CONF_ENABLED | SR_CONF_GET | SR_CONF_SET,
694};
695
696static const struct channel_spec rs_hmc8043_ch[] = {
49a468ed
FS		 697 { "1", { 0, 32.050, 0.001, 3, 4 }, { 0.001, 3, 0.001, 3, 4 }, { 0, 0, 0, 0, 4 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS },
698 { "2", { 0, 32.050, 0.001, 3, 4 }, { 0.001, 3, 0.001, 3, 4 }, { 0, 0, 0, 0, 4 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS },
699 { "3", { 0, 32.050, 0.001, 3, 4 }, { 0.001, 3, 0.001, 3, 4 }, { 0, 0, 0, 0, 4 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS },
81eb36d6
MS		 700};
701
702static const struct channel_group_spec rs_hmc8043_cg[] = {
703 { "1", CH_IDX(0), PPS_OVP },
704 { "2", CH_IDX(1), PPS_OVP },
705 { "3", CH_IDX(2), PPS_OVP },
706};
707
708static const struct scpi_command rs_hmc8043_cmd[] = {
709 { SCPI_CMD_SELECT_CHANNEL, "INST:NSEL %s" },
710 { SCPI_CMD_GET_MEAS_VOLTAGE, "MEAS:VOLT?" },
711 { SCPI_CMD_GET_MEAS_CURRENT, "MEAS:CURR?" },
712 { SCPI_CMD_GET_VOLTAGE_TARGET, "VOLT?" },
713 { SCPI_CMD_SET_VOLTAGE_TARGET, "VOLT %.6f" },
714 { SCPI_CMD_GET_CURRENT_LIMIT, "CURR?" },
715 { SCPI_CMD_SET_CURRENT_LIMIT, "CURR %.6f" },
716 { SCPI_CMD_GET_OUTPUT_ENABLED, "OUTP?" },
717 { SCPI_CMD_SET_OUTPUT_ENABLE, "OUTP ON" },
718 { SCPI_CMD_SET_OUTPUT_DISABLE, "OUTP OFF" },
719 { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_ACTIVE, "VOLT:PROT:TRIP?" },
720 { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_THRESHOLD, "VOLT:PROT:LEV?" },
721 { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_THRESHOLD, "VOLT:PROT:LEV %.6f" },
722 { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_ENABLED, "VOLT:PROT:STAT?" },
723 { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_ENABLE, "VOLT:PROT:STAT ON" },
724 { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_DISABLE, "VOLT:PROT:STAT OFF" },
725 ALL_ZERO
726};
727
d4eabea8 728SR_PRIV const struct scpi_pps pps_profiles[] = {
6cc93128 729 /* Agilent N5763A */
5e7377f4 730 { "Agilent", "N5763A", SCPI_DIALECT_UNKNOWN, 0,
6cc93128
AG		 731 ARRAY_AND_SIZE(agilent_n5700a_devopts),
732 ARRAY_AND_SIZE(agilent_n5700a_devopts_cg),
733 ARRAY_AND_SIZE(agilent_n5763a_ch),
734 ARRAY_AND_SIZE(agilent_n5700a_cg),
735 agilent_n5700a_cmd,
736 .probe_channels = NULL,
737 },
ca314e06 738
5c9e56c9 739 /* Agilent N5767A */
5e7377f4 740 { "Agilent", "N5767A", SCPI_DIALECT_UNKNOWN, 0,
5c9e56c9
AG		 741 ARRAY_AND_SIZE(agilent_n5700a_devopts),
742 ARRAY_AND_SIZE(agilent_n5700a_devopts_cg),
743 ARRAY_AND_SIZE(agilent_n5767a_ch),
6cc93128 744 ARRAY_AND_SIZE(agilent_n5700a_cg),
91ef511d 745 agilent_n5700a_cmd,
5c9e56c9
AG		 746 .probe_channels = NULL,
747 },
ca314e06 748
c3bfb959 749 /* BK Precision 9310 */
5e7377f4 750 { "BK", "^9130$", SCPI_DIALECT_UNKNOWN, 0,
c3bfb959
MW		 751 ARRAY_AND_SIZE(bk_9130_devopts),
752 ARRAY_AND_SIZE(bk_9130_devopts_cg),
753 ARRAY_AND_SIZE(bk_9130_ch),
754 ARRAY_AND_SIZE(bk_9130_cg),
755 bk_9130_cmd,
756 .probe_channels = NULL,
757 },
758
4ee1e2f3 759 /* Chroma 61604 */
5e7377f4 760 { "Chroma", "61604", SCPI_DIALECT_UNKNOWN, 0,
4ee1e2f3
AG		 761 ARRAY_AND_SIZE(chroma_61604_devopts),
762 ARRAY_AND_SIZE(chroma_61604_devopts_cg),
763 ARRAY_AND_SIZE(chroma_61604_ch),
764 ARRAY_AND_SIZE(chroma_61604_cg),
91ef511d 765 chroma_61604_cmd,
4ee1e2f3
AG		 766 .probe_channels = NULL,
767 },
ca314e06 768
5281993e 769 /* Chroma 62000 series */
5e7377f4 770 { "Chroma", "620[0-9]{2}P-[0-9]{2,3}-[0-9]{1,3}", SCPI_DIALECT_UNKNOWN, 0,
5281993e
AG		 771 ARRAY_AND_SIZE(chroma_62000_devopts),
772 ARRAY_AND_SIZE(chroma_62000_devopts_cg),
9a5185c7
AG		 773 NULL, 0,
774 NULL, 0,
91ef511d 775 chroma_62000_cmd,
9a5185c7 776 .probe_channels = chroma_62000p_probe_channels,
5281993e 777 },
ca314e06 778
e76a3575 779 /* HP 6633A */
5e7377f4 780 { "HP", "6633A", SCPI_DIALECT_HP_COMP, 0,
e76a3575 781 ARRAY_AND_SIZE(hp_6630a_devopts),
7c517d02 782 ARRAY_AND_SIZE(hp_6630a_devopts_cg),
e76a3575
AG		 783 ARRAY_AND_SIZE(hp_6633a_ch),
784 ARRAY_AND_SIZE(hp_663xx_cg),
785 hp_6630a_cmd,
786 .probe_channels = NULL,
787 },
788
a61c8cce 789 /* HP 6631B */
5e7377f4 790 { "HP", "6631B", SCPI_DIALECT_HP_66XXB, PPS_OVP | PPS_OCP | PPS_OTP,
a61c8cce
FS		 791 ARRAY_AND_SIZE(hp_6630b_devopts),
792 ARRAY_AND_SIZE(hp_6630b_devopts_cg),
793 ARRAY_AND_SIZE(hp_6631b_ch),
794 ARRAY_AND_SIZE(hp_663xx_cg),
795 hp_6630b_cmd,
796 .probe_channels = NULL,
797 },
798
bc4a2a46 799 /* HP 6632B */
5e7377f4 800 { "HP", "6632B", SCPI_DIALECT_HP_66XXB, PPS_OVP | PPS_OCP | PPS_OTP,
a61c8cce
FS		 801 ARRAY_AND_SIZE(hp_6630b_devopts),
802 ARRAY_AND_SIZE(hp_6630b_devopts_cg),
bc4a2a46 803 ARRAY_AND_SIZE(hp_6632b_ch),
e76a3575 804 ARRAY_AND_SIZE(hp_663xx_cg),
a61c8cce
FS		 805 hp_6630b_cmd,
806 .probe_channels = NULL,
807 },
808
809 /* HP 66332A */
5e7377f4 810 { "HP", "66332A", SCPI_DIALECT_HP_66XXB, PPS_OVP | PPS_OCP | PPS_OTP,
a61c8cce
FS		 811 ARRAY_AND_SIZE(hp_6630b_devopts),
812 ARRAY_AND_SIZE(hp_6630b_devopts_cg),
813 ARRAY_AND_SIZE(hp_66332a_ch),
814 ARRAY_AND_SIZE(hp_663xx_cg),
815 hp_6630b_cmd,
816 .probe_channels = NULL,
817 },
818
819 /* HP 6633B */
5e7377f4 820 { "HP", "6633B", SCPI_DIALECT_HP_66XXB, PPS_OVP | PPS_OCP | PPS_OTP,
a61c8cce
FS		 821 ARRAY_AND_SIZE(hp_6630b_devopts),
822 ARRAY_AND_SIZE(hp_6630b_devopts_cg),
823 ARRAY_AND_SIZE(hp_6633b_ch),
824 ARRAY_AND_SIZE(hp_663xx_cg),
825 hp_6630b_cmd,
826 .probe_channels = NULL,
827 },
828
829 /* HP 6634B */
5e7377f4 830 { "HP", "6634B", SCPI_DIALECT_HP_66XXB, PPS_OVP | PPS_OCP | PPS_OTP,
a61c8cce
FS		 831 ARRAY_AND_SIZE(hp_6630b_devopts),
832 ARRAY_AND_SIZE(hp_6630b_devopts_cg),
833 ARRAY_AND_SIZE(hp_6634b_ch),
834 ARRAY_AND_SIZE(hp_663xx_cg),
835 hp_6630b_cmd,
c3eadb07 836 .probe_channels = NULL,
bc4a2a46
BV		 837 },
838
319fe9ce 839 /* Rigol DP700 series */
5e7377f4 840 { "Rigol", "^DP711$", SCPI_DIALECT_UNKNOWN, 0,
319fe9ce
UH		 841 ARRAY_AND_SIZE(rigol_dp700_devopts),
842 ARRAY_AND_SIZE(rigol_dp700_devopts_cg),
843 ARRAY_AND_SIZE(rigol_dp711_ch),
844 ARRAY_AND_SIZE(rigol_dp700_cg),
845 rigol_dp700_cmd,
846 .probe_channels = NULL,
847 },
5e7377f4 848 { "Rigol", "^DP712$", SCPI_DIALECT_UNKNOWN, 0,
319fe9ce
UH		 849 ARRAY_AND_SIZE(rigol_dp700_devopts),
850 ARRAY_AND_SIZE(rigol_dp700_devopts_cg),
851 ARRAY_AND_SIZE(rigol_dp712_ch),
852 ARRAY_AND_SIZE(rigol_dp700_cg),
853 rigol_dp700_cmd,
854 .probe_channels = NULL,
855 },
856
d4eabea8 857 /* Rigol DP800 series */
5e7377f4 858 { "Rigol", "^DP821A$", SCPI_DIALECT_UNKNOWN, PPS_OTP,
cfcdf576
ML		 859 ARRAY_AND_SIZE(rigol_dp800_devopts),
860 ARRAY_AND_SIZE(rigol_dp800_devopts_cg),
861 ARRAY_AND_SIZE(rigol_dp821a_ch),
862 ARRAY_AND_SIZE(rigol_dp820_cg),
91ef511d 863 rigol_dp800_cmd,
cfcdf576
ML		 864 .probe_channels = NULL,
865 },
5e7377f4 866 { "Rigol", "^DP831A$", SCPI_DIALECT_UNKNOWN, PPS_OTP,
3222ee10
BV		 867 ARRAY_AND_SIZE(rigol_dp800_devopts),
868 ARRAY_AND_SIZE(rigol_dp800_devopts_cg),
869 ARRAY_AND_SIZE(rigol_dp831_ch),
cfcdf576 870 ARRAY_AND_SIZE(rigol_dp830_cg),
91ef511d 871 rigol_dp800_cmd,
c3eadb07 872 .probe_channels = NULL,
3222ee10 873 },
5e7377f4 874 { "Rigol", "^(DP832|DP832A)$", SCPI_DIALECT_UNKNOWN, PPS_OTP,
3222ee10
BV		 875 ARRAY_AND_SIZE(rigol_dp800_devopts),
876 ARRAY_AND_SIZE(rigol_dp800_devopts_cg),
877 ARRAY_AND_SIZE(rigol_dp832_ch),
cfcdf576 878 ARRAY_AND_SIZE(rigol_dp830_cg),
91ef511d 879 rigol_dp800_cmd,
c3eadb07
BV		 880 .probe_channels = NULL,
881 },
882
883 /* Philips/Fluke PM2800 series */
5e7377f4 884 { "Philips", "^PM28[13][123]/[01234]{1,2}$", SCPI_DIALECT_PHILIPS, 0,
9d9cf1c4 885 ARRAY_AND_SIZE(philips_pm2800_devopts),
c3eadb07
BV		 886 ARRAY_AND_SIZE(philips_pm2800_devopts_cg),
887 NULL, 0,
888 NULL, 0,
91ef511d 889 philips_pm2800_cmd,
c3eadb07 890 philips_pm2800_probe_channels,
d4eabea8 891 },
81eb36d6
MS		 892
893 /* Rohde & Schwarz HMC8043 */
5e7377f4 894 { "Rohde&Schwarz", "HMC8043", SCPI_DIALECT_UNKNOWN, 0,
81eb36d6
MS		 895 ARRAY_AND_SIZE(rs_hmc8043_devopts),
896 ARRAY_AND_SIZE(rs_hmc8043_devopts_cg),
897 ARRAY_AND_SIZE(rs_hmc8043_ch),
898 ARRAY_AND_SIZE(rs_hmc8043_cg),
899 rs_hmc8043_cmd,
900 .probe_channels = NULL,
901 },
d4eabea8 902};
d4eabea8 903
1beccaed 904SR_PRIV unsigned int num_pps_profiles = ARRAY_SIZE(pps_profiles);
Hardware access and backend lib