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scpi-pps: Implement init_acquisition() and update_status() for HP 66xxA power supplies.
[libsigrok.git] / src / hardware / scpi-pps / profiles.c
CommitLineData
d4eabea8
BV		 1/*
2 * This file is part of the libsigrok project.
3 *
4 * Copyright (C) 2014 Bert Vermeulen <bert@biot.com>
4ee1e2f3
AG		 5 * Copyright (C) 2015 Google, Inc.
6 * (Written by Alexandru Gagniuc <mrnuke@google.com> for Google, Inc.)
7e66bf05 7 * Copyright (C) 2017,2019 Frank Stettner <frank-stettner@gmx.net>
d4eabea8
BV		 8 *
9 * This program is free software: you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation, either version 3 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program. If not, see <http://www.gnu.org/licenses/>.
21 */
22
6ec6c43b 23#include <config.h>
22c18b03 24#include <string.h>
ba464a12 25#include <strings.h>
d4eabea8
BV		 26#include "protocol.h"
27
28#define CH_IDX(x) (1 << x)
6ed709fe 29#define FREQ_DC_ONLY {0, 0, 0, 0, 0}
49a468ed
FS		 30#define NO_OVP_LIMITS {0, 0, 0, 0, 0}
31#define NO_OCP_LIMITS {0, 0, 0, 0, 0}
d4eabea8 32
5c9e56c9
AG		 33/* Agilent/Keysight N5700A series */
34static const uint32_t agilent_n5700a_devopts[] = {
e91bb0a6 35 SR_CONF_CONTINUOUS,
88e4daa9
ML		 36 SR_CONF_LIMIT_SAMPLES | SR_CONF_GET | SR_CONF_SET,
37 SR_CONF_LIMIT_MSEC | SR_CONF_GET | SR_CONF_SET,
5c9e56c9
AG		 38};
39
40static const uint32_t agilent_n5700a_devopts_cg[] = {
41 SR_CONF_OVER_VOLTAGE_PROTECTION_THRESHOLD | SR_CONF_GET | SR_CONF_SET,
42 SR_CONF_OVER_CURRENT_PROTECTION_ENABLED | SR_CONF_GET | SR_CONF_SET,
43 SR_CONF_OVER_CURRENT_PROTECTION_THRESHOLD | SR_CONF_GET | SR_CONF_SET,
da005885
UH		 44 SR_CONF_VOLTAGE | SR_CONF_GET,
45 SR_CONF_VOLTAGE_TARGET | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
46 SR_CONF_CURRENT | SR_CONF_GET,
47 SR_CONF_ENABLED | SR_CONF_GET | SR_CONF_SET,
5c9e56c9
AG		 48};
49
6cc93128 50static const struct channel_group_spec agilent_n5700a_cg[] = {
f2bbcc33 51 { "1", CH_IDX(0), PPS_OVP | PPS_OCP, SR_MQFLAG_DC },
6cc93128
AG		 52};
53
8cb5affe 54static const struct channel_spec agilent_n5767a_ch[] = {
49a468ed 55 { "1", { 0, 60, 0.0072, 3, 4 }, { 0, 25, 0.003, 3, 4 }, { 0, 1500 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS },
5c9e56c9
AG		 56};
57
6cc93128 58static const struct channel_spec agilent_n5763a_ch[] = {
49a468ed 59 { "1", { 0, 12.5, 0.0015, 3, 4 }, { 0, 120, 0.0144, 3, 4 }, { 0, 1500 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS },
5c9e56c9
AG		 60};
61
62/*
63 * TODO: OVER_CURRENT_PROTECTION_ACTIVE status can be determined by the OC bit
562a3490 64 * in STAT:QUES:EVEN?, but this is not implemented.
5c9e56c9 65 */
8cb5affe 66static const struct scpi_command agilent_n5700a_cmd[] = {
5c9e56c9
AG		 67 { SCPI_CMD_REMOTE, "SYST:COMM:RLST REM" },
68 { SCPI_CMD_LOCAL, "SYST:COMM:RLST LOC" },
69 { SCPI_CMD_GET_MEAS_VOLTAGE, ":MEAS:VOLT?" },
70 { SCPI_CMD_GET_MEAS_CURRENT, "MEAS:CURR?" },
71 { SCPI_CMD_GET_VOLTAGE_TARGET, ":SOUR:VOLT?" },
72 { SCPI_CMD_SET_VOLTAGE_TARGET, ":SOUR:VOLT %.6f" },
73 { SCPI_CMD_GET_CURRENT_LIMIT, ":SOUR:CURR?" },
74 { SCPI_CMD_SET_CURRENT_LIMIT, ":SOUR:CURR %.6f" },
75 { SCPI_CMD_GET_OUTPUT_ENABLED, ":OUTP:STAT?" },
76 { SCPI_CMD_SET_OUTPUT_ENABLE, ":OUTP ON" },
77 { SCPI_CMD_SET_OUTPUT_DISABLE, ":OUTP OFF" },
78 { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_THRESHOLD, ":VOLT:PROT?" },
79 { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_THRESHOLD, ":VOLT:PROT %.6f" },
80 { SCPI_CMD_GET_OVER_CURRENT_PROTECTION_ENABLED, ":CURR:PROT:STAT?" },
81 { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_ENABLE, ":CURR:PROT:STAT ON?"},
82 { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_DISABLE, ":CURR:PROT:STAT OFF?"},
562a3490 83 /* Current limit (CC mode) and OCP are set using the same command. */
5c9e56c9
AG		 84 { SCPI_CMD_GET_OVER_CURRENT_PROTECTION_THRESHOLD, ":SOUR:CURR?" },
85 { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_THRESHOLD, ":SOUR:CURR %.6f" },
91ef511d 86 ALL_ZERO
5c9e56c9
AG		 87};
88
c3bfb959
MW		 89/* BK Precision 9130 series */
90static const uint32_t bk_9130_devopts[] = {
91 SR_CONF_CONTINUOUS,
92 SR_CONF_LIMIT_SAMPLES | SR_CONF_GET | SR_CONF_SET,
93 SR_CONF_LIMIT_MSEC | SR_CONF_GET | SR_CONF_SET,
94};
95
96static const uint32_t bk_9130_devopts_cg[] = {
97 SR_CONF_OVER_VOLTAGE_PROTECTION_THRESHOLD | SR_CONF_GET | SR_CONF_SET,
98 SR_CONF_VOLTAGE | SR_CONF_GET,
99 SR_CONF_VOLTAGE_TARGET | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
100 SR_CONF_CURRENT | SR_CONF_GET,
101 SR_CONF_CURRENT_LIMIT | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
102 SR_CONF_ENABLED | SR_CONF_GET | SR_CONF_SET,
103};
104
105static const struct channel_spec bk_9130_ch[] = {
106 { "1", { 0, 30, 0.001, 3, 3 }, { 0, 3, 0.001, 3, 3 }, { 0, 90, 0, 3, 3 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS },
107 { "2", { 0, 30, 0.001, 3, 3 }, { 0, 3, 0.001, 3, 3 }, { 0, 90, 0, 3, 3 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS },
108 { "3", { 0, 5, 0.001, 3, 3 }, { 0, 3, 0.001, 3, 3 }, { 0, 15, 0, 3, 3 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS },
109};
110
111static const struct channel_group_spec bk_9130_cg[] = {
f2bbcc33
FS		 112 { "1", CH_IDX(0), PPS_OVP, SR_MQFLAG_DC },
113 { "2", CH_IDX(1), PPS_OVP, SR_MQFLAG_DC },
114 { "3", CH_IDX(2), PPS_OVP, SR_MQFLAG_DC },
c3bfb959
MW		 115};
116
117static const struct scpi_command bk_9130_cmd[] = {
118 { SCPI_CMD_REMOTE, "SYST:REMOTE" },
119 { SCPI_CMD_LOCAL, "SYST:LOCAL" },
120 { SCPI_CMD_SELECT_CHANNEL, ":INST:NSEL %s" },
121 { SCPI_CMD_GET_MEAS_VOLTAGE, ":MEAS:VOLT?" },
122 { SCPI_CMD_GET_MEAS_CURRENT, ":MEAS:CURR?" },
123 { SCPI_CMD_GET_MEAS_POWER, ":MEAS:POWER?" },
124 { SCPI_CMD_GET_VOLTAGE_TARGET, ":SOUR:VOLT?" },
125 { SCPI_CMD_SET_VOLTAGE_TARGET, ":SOUR:VOLT %.6f" },
126 { SCPI_CMD_GET_CURRENT_LIMIT, ":SOUR:CURR?" },
127 { SCPI_CMD_SET_CURRENT_LIMIT, ":SOUR:CURR %.6f" },
128 { SCPI_CMD_GET_OUTPUT_ENABLED, ":OUTP?" },
129 { SCPI_CMD_SET_OUTPUT_ENABLE, ":OUTP 1" },
130 { SCPI_CMD_SET_OUTPUT_DISABLE, ":OUTP 0" },
131 { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_THRESHOLD, ":SOUR:VOLT:PROT?" },
132 { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_THRESHOLD, ":SOUR:VOLT:PROT %.6f" },
133 ALL_ZERO
134};
135
4ee1e2f3
AG		 136/* Chroma 61600 series AC source */
137static const uint32_t chroma_61604_devopts[] = {
e91bb0a6 138 SR_CONF_CONTINUOUS,
88e4daa9
ML		 139 SR_CONF_LIMIT_SAMPLES | SR_CONF_GET | SR_CONF_SET,
140 SR_CONF_LIMIT_MSEC | SR_CONF_GET | SR_CONF_SET,
4ee1e2f3
AG		 141};
142
143static const uint32_t chroma_61604_devopts_cg[] = {
144 SR_CONF_OVER_VOLTAGE_PROTECTION_THRESHOLD | SR_CONF_GET | SR_CONF_SET,
145 SR_CONF_OVER_CURRENT_PROTECTION_THRESHOLD | SR_CONF_GET | SR_CONF_SET,
da005885
UH		 146 SR_CONF_VOLTAGE | SR_CONF_GET,
147 SR_CONF_VOLTAGE_TARGET | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
6c0c9dd2
AG		 148 SR_CONF_OUTPUT_FREQUENCY | SR_CONF_GET,
149 SR_CONF_OUTPUT_FREQUENCY_TARGET | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
da005885
UH		 150 SR_CONF_CURRENT | SR_CONF_GET,
151 SR_CONF_ENABLED | SR_CONF_GET | SR_CONF_SET,
4ee1e2f3
AG		 152};
153
8cb5affe 154static const struct channel_spec chroma_61604_ch[] = {
49a468ed 155 { "1", { 0, 300, 0.1, 1, 1 }, { 0, 16, 0.1, 2, 2 }, { 0, 2000, 0, 1, 1 }, { 1.0, 1000.0, 0.01 }, NO_OVP_LIMITS, NO_OCP_LIMITS },
4ee1e2f3
AG		 156};
157
8cb5affe 158static const struct channel_group_spec chroma_61604_cg[] = {
f2bbcc33 159 { "1", CH_IDX(0), PPS_OVP | PPS_OCP, SR_MQFLAG_AC },
4ee1e2f3
AG		 160};
161
8cb5affe 162static const struct scpi_command chroma_61604_cmd[] = {
4ee1e2f3
AG		 163 { SCPI_CMD_REMOTE, "SYST:REM" },
164 { SCPI_CMD_LOCAL, "SYST:LOC" },
165 { SCPI_CMD_GET_MEAS_VOLTAGE, ":FETC:VOLT:ACDC?" },
6c0c9dd2 166 { SCPI_CMD_GET_MEAS_FREQUENCY, ":FETC:FREQ?" },
4ee1e2f3
AG		 167 { SCPI_CMD_GET_MEAS_CURRENT, ":FETC:CURR:AC?" },
168 { SCPI_CMD_GET_MEAS_POWER, ":FETC:POW:AC?" },
169 { SCPI_CMD_GET_VOLTAGE_TARGET, ":SOUR:VOLT:AC?" },
170 { SCPI_CMD_SET_VOLTAGE_TARGET, ":SOUR:VOLT:AC %.1f" },
6c0c9dd2
AG		 171 { SCPI_CMD_GET_FREQUENCY_TARGET, ":SOUR:FREQ?" },
172 { SCPI_CMD_SET_FREQUENCY_TARGET, ":SOUR:FREQ %.2f" },
4ee1e2f3
AG		 173 { SCPI_CMD_GET_OUTPUT_ENABLED, ":OUTP?" },
174 { SCPI_CMD_SET_OUTPUT_ENABLE, ":OUTP ON" },
175 { SCPI_CMD_SET_OUTPUT_DISABLE, ":OUTP OFF" },
176 { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_THRESHOLD, ":SOUR:VOLT:LIM:AC?" },
177 { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_THRESHOLD, ":SOUR:VOLT:LIM:AC %.1f" },
562a3490 178 /* This is not a current limit mode. It is overcurrent protection. */
4ee1e2f3
AG		 179 { SCPI_CMD_GET_OVER_CURRENT_PROTECTION_THRESHOLD, ":SOUR:CURR:LIM?" },
180 { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_THRESHOLD, ":SOUR:CURR:LIM %.2f" },
91ef511d 181 ALL_ZERO
4ee1e2f3
AG		 182};
183
5281993e 184/* Chroma 62000 series DC source */
5281993e 185static const uint32_t chroma_62000_devopts[] = {
e91bb0a6 186 SR_CONF_CONTINUOUS,
88e4daa9
ML		 187 SR_CONF_LIMIT_SAMPLES | SR_CONF_GET | SR_CONF_SET,
188 SR_CONF_LIMIT_MSEC | SR_CONF_GET | SR_CONF_SET,
5281993e
AG		 189};
190
191static const uint32_t chroma_62000_devopts_cg[] = {
192 SR_CONF_OVER_VOLTAGE_PROTECTION_THRESHOLD | SR_CONF_GET | SR_CONF_SET,
193 SR_CONF_OVER_CURRENT_PROTECTION_THRESHOLD | SR_CONF_GET | SR_CONF_SET,
194 SR_CONF_VOLTAGE | SR_CONF_GET,
195 SR_CONF_VOLTAGE_TARGET | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
196 SR_CONF_CURRENT | SR_CONF_GET,
197 SR_CONF_CURRENT_LIMIT | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
198 SR_CONF_ENABLED | SR_CONF_GET | SR_CONF_SET,
199};
200
5281993e 201static const struct channel_group_spec chroma_62000_cg[] = {
f2bbcc33 202 { "1", CH_IDX(0), PPS_OVP | PPS_OCP, SR_MQFLAG_DC },
5281993e
AG		 203};
204
205static const struct scpi_command chroma_62000_cmd[] = {
206 { SCPI_CMD_REMOTE, ":CONF:REM ON" },
207 { SCPI_CMD_LOCAL, ":CONF:REM OFF" },
208 { SCPI_CMD_BEEPER, ":CONF:BEEP?" },
209 { SCPI_CMD_BEEPER_ENABLE, ":CONF:BEEP ON" },
210 { SCPI_CMD_BEEPER_DISABLE, ":CONF:BEEP OFF" },
211 { SCPI_CMD_GET_MEAS_VOLTAGE, ":MEAS:VOLT?" },
212 { SCPI_CMD_GET_MEAS_CURRENT, ":MEAS:CURR?" },
213 { SCPI_CMD_GET_MEAS_POWER, ":MEAS:POW?" },
214 { SCPI_CMD_GET_VOLTAGE_TARGET, ":SOUR:VOLT?" },
215 { SCPI_CMD_SET_VOLTAGE_TARGET, ":SOUR:VOLT %.2f" },
216 { SCPI_CMD_GET_CURRENT_LIMIT, ":SOUR:CURR?" },
217 { SCPI_CMD_SET_CURRENT_LIMIT, ":SOUR:CURR %.6f" },
218 { SCPI_CMD_GET_OUTPUT_ENABLED, ":CONF:OUTP?" },
219 { SCPI_CMD_SET_OUTPUT_ENABLE, ":CONF:OUTP ON" },
220 { SCPI_CMD_SET_OUTPUT_DISABLE, ":CONF:OUTP OFF" },
221 { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_THRESHOLD, ":SOUR:VOLT:PROT:HIGH?" },
222 { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_THRESHOLD, ":SOUR:VOLT:PROT:HIGH %.6f" },
223 { SCPI_CMD_GET_OVER_CURRENT_PROTECTION_THRESHOLD, ":SOUR:CURR:PROT:HIGH?" },
224 { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_THRESHOLD, ":SOUR:CURR:PROT:HIGH %.6f" },
91ef511d 225 ALL_ZERO
5281993e
AG		 226};
227
9a5185c7
AG		 228static int chroma_62000p_probe_channels(struct sr_dev_inst *sdi,
229 struct sr_scpi_hw_info *hw_info,
230 struct channel_spec **channels, unsigned int *num_channels,
231 struct channel_group_spec **channel_groups,
232 unsigned int *num_channel_groups)
233{
6ed709fe 234 unsigned int volts, amps, watts;
9a5185c7
AG		 235 struct channel_spec *channel;
236
237 (void)sdi;
238
6ed709fe
AJ		 239 sscanf(hw_info->model, "620%uP-%u-%u", &watts, &volts, &amps);
240 watts *= 100;
241 sr_dbg("Found device rated for %d V, %d A and %d W", volts, amps, watts);
9a5185c7
AG		 242
243 if (volts > 600) {
244 sr_err("Probed max voltage of %u V is out of spec.", volts);
245 return SR_ERR_BUG;
246 }
247
6ed709fe 248 if (amps > 120) {
9a5185c7
AG		 249 sr_err("Probed max current of %u A is out of spec.", amps);
250 return SR_ERR_BUG;
251 }
252
6ed709fe
AJ		 253 if (watts > 5000) {
254 sr_err("Probed max power of %u W is out of spec.", watts);
255 return SR_ERR_BUG;
256 }
257
9a5185c7
AG		 258 channel = g_malloc0(sizeof(struct channel_spec));
259 channel->name = "1";
6ed709fe 260 channel->voltage[0] = channel->current[0] = channel->power[0] = 0.0;
bcee1299
UH		 261 channel->voltage[1] = volts;
262 channel->current[1] = amps;
263 channel->power[1] = watts;
9a5185c7 264 channel->voltage[2] = channel->current[2] = 0.01;
6ed709fe
AJ		 265 channel->voltage[3] = channel->voltage[4] = 3;
266 channel->current[3] = channel->current[4] = 4;
9a5185c7
AG		 267 *channels = channel;
268 *num_channels = 1;
269
270 *channel_groups = g_malloc(sizeof(struct channel_group_spec));
271 **channel_groups = chroma_62000_cg[0];
272 *num_channel_groups = 1;
273
274 return SR_OK;
275}
276
319fe9ce
UH		 277/* Rigol DP700 series */
278static const uint32_t rigol_dp700_devopts[] = {
279 SR_CONF_CONTINUOUS,
88e4daa9
ML		 280 SR_CONF_LIMIT_SAMPLES | SR_CONF_GET | SR_CONF_SET,
281 SR_CONF_LIMIT_MSEC | SR_CONF_GET | SR_CONF_SET,
319fe9ce
UH		 282};
283
284static const uint32_t rigol_dp700_devopts_cg[] = {
285 SR_CONF_REGULATION | SR_CONF_GET,
286 SR_CONF_OVER_VOLTAGE_PROTECTION_ENABLED | SR_CONF_GET | SR_CONF_SET,
287 SR_CONF_OVER_VOLTAGE_PROTECTION_ACTIVE | SR_CONF_GET,
d828b05e 288 SR_CONF_OVER_VOLTAGE_PROTECTION_THRESHOLD | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
319fe9ce
UH		 289 SR_CONF_OVER_CURRENT_PROTECTION_ENABLED | SR_CONF_GET | SR_CONF_SET,
290 SR_CONF_OVER_CURRENT_PROTECTION_ACTIVE | SR_CONF_GET,
d828b05e 291 SR_CONF_OVER_CURRENT_PROTECTION_THRESHOLD | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
319fe9ce
UH		 292 SR_CONF_VOLTAGE | SR_CONF_GET,
293 SR_CONF_VOLTAGE_TARGET | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
294 SR_CONF_CURRENT | SR_CONF_GET,
295 SR_CONF_CURRENT_LIMIT | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
296 SR_CONF_ENABLED | SR_CONF_GET | SR_CONF_SET,
297};
298
299static const struct channel_spec rigol_dp711_ch[] = {
d828b05e 300 { "1", { 0, 30, 0.01, 3, 3 }, { 0, 5, 0.01, 3, 3 }, { 0, 150, 0, 3, 3 }, FREQ_DC_ONLY, { 0.01, 33, 0.01}, { 0.01, 5.5, 0.01 } },
319fe9ce
UH		 301};
302
303static const struct channel_spec rigol_dp712_ch[] = {
d828b05e 304 { "1", { 0, 50, 0.01, 3, 3 }, { 0, 3, 0.01, 3, 3 }, { 0, 150, 0, 3, 3 }, FREQ_DC_ONLY, { 0.01, 55, 0.01}, { 0.01, 3.3, 0.01 } },
319fe9ce
UH		 305};
306
307static const struct channel_group_spec rigol_dp700_cg[] = {
f2bbcc33 308 { "1", CH_IDX(0), PPS_OVP | PPS_OCP, SR_MQFLAG_DC },
319fe9ce
UH		 309};
310
311/* Same as the DP800 series, except for the missing :SYST:OTP* commands. */
312static const struct scpi_command rigol_dp700_cmd[] = {
313 { SCPI_CMD_REMOTE, "SYST:REMOTE" },
314 { SCPI_CMD_LOCAL, "SYST:LOCAL" },
315 { SCPI_CMD_BEEPER, "SYST:BEEP:STAT?" },
316 { SCPI_CMD_BEEPER_ENABLE, "SYST:BEEP:STAT ON" },
317 { SCPI_CMD_BEEPER_DISABLE, "SYST:BEEP:STAT OFF" },
318 { SCPI_CMD_SELECT_CHANNEL, ":INST:NSEL %s" },
319 { SCPI_CMD_GET_MEAS_VOLTAGE, ":MEAS:VOLT?" },
320 { SCPI_CMD_GET_MEAS_CURRENT, ":MEAS:CURR?" },
321 { SCPI_CMD_GET_MEAS_POWER, ":MEAS:POWE?" },
322 { SCPI_CMD_GET_VOLTAGE_TARGET, ":SOUR:VOLT?" },
323 { SCPI_CMD_SET_VOLTAGE_TARGET, ":SOUR:VOLT %.6f" },
324 { SCPI_CMD_GET_CURRENT_LIMIT, ":SOUR:CURR?" },
325 { SCPI_CMD_SET_CURRENT_LIMIT, ":SOUR:CURR %.6f" },
326 { SCPI_CMD_GET_OUTPUT_ENABLED, ":OUTP?" },
327 { SCPI_CMD_SET_OUTPUT_ENABLE, ":OUTP ON" },
328 { SCPI_CMD_SET_OUTPUT_DISABLE, ":OUTP OFF" },
329 { SCPI_CMD_GET_OUTPUT_REGULATION, ":OUTP:MODE?" },
330 { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_ENABLED, ":OUTP:OVP?" },
331 { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_ENABLE, ":OUTP:OVP ON" },
332 { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_DISABLE, ":OUTP:OVP OFF" },
333 { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_ACTIVE, ":OUTP:OVP:QUES?" },
334 { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_THRESHOLD, ":OUTP:OVP:VAL?" },
335 { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_THRESHOLD, ":OUTP:OVP:VAL %.6f" },
336 { SCPI_CMD_GET_OVER_CURRENT_PROTECTION_ENABLED, ":OUTP:OCP?" },
337 { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_ENABLE, ":OUTP:OCP:STAT ON" },
338 { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_DISABLE, ":OUTP:OCP:STAT OFF" },
339 { SCPI_CMD_GET_OVER_CURRENT_PROTECTION_ACTIVE, ":OUTP:OCP:QUES?" },
340 { SCPI_CMD_GET_OVER_CURRENT_PROTECTION_THRESHOLD, ":OUTP:OCP:VAL?" },
341 { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_THRESHOLD, ":OUTP:OCP:VAL %.6f" },
342 ALL_ZERO
343};
344
d4eabea8 345/* Rigol DP800 series */
584560f1 346static const uint32_t rigol_dp800_devopts[] = {
e91bb0a6 347 SR_CONF_CONTINUOUS,
5827f61b 348 SR_CONF_OVER_TEMPERATURE_PROTECTION | SR_CONF_GET | SR_CONF_SET,
88e4daa9
ML		 349 SR_CONF_LIMIT_SAMPLES | SR_CONF_GET | SR_CONF_SET,
350 SR_CONF_LIMIT_MSEC | SR_CONF_GET | SR_CONF_SET,
d4eabea8
BV		 351};
352
584560f1 353static const uint32_t rigol_dp800_devopts_cg[] = {
7a0b98b5 354 SR_CONF_REGULATION | SR_CONF_GET,
5827f61b
BV		 355 SR_CONF_OVER_VOLTAGE_PROTECTION_ENABLED | SR_CONF_GET | SR_CONF_SET,
356 SR_CONF_OVER_VOLTAGE_PROTECTION_ACTIVE | SR_CONF_GET,
357 SR_CONF_OVER_VOLTAGE_PROTECTION_THRESHOLD | SR_CONF_GET | SR_CONF_SET,
358 SR_CONF_OVER_CURRENT_PROTECTION_ENABLED | SR_CONF_GET | SR_CONF_SET,
359 SR_CONF_OVER_CURRENT_PROTECTION_ACTIVE | SR_CONF_GET,
360 SR_CONF_OVER_CURRENT_PROTECTION_THRESHOLD | SR_CONF_GET | SR_CONF_SET,
7a0b98b5
AJ		 361 SR_CONF_VOLTAGE | SR_CONF_GET,
362 SR_CONF_VOLTAGE_TARGET | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
363 SR_CONF_CURRENT | SR_CONF_GET,
364 SR_CONF_CURRENT_LIMIT | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
365 SR_CONF_ENABLED | SR_CONF_GET | SR_CONF_SET,
d4eabea8
BV		 366};
367
8cb5affe 368static const struct channel_spec rigol_dp821a_ch[] = {
49a468ed
FS		 369 { "1", { 0, 60, 0.001, 3, 3 }, { 0, 1, 0.0001, 4, 4 }, { 0, 60, 0, 3, 4 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS },
370 { "2", { 0, 8, 0.001, 3, 3 }, { 0, 10, 0.001, 3, 3 }, { 0, 80, 0, 3, 3 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS },
cfcdf576
ML		 371};
372
8cb5affe 373static const struct channel_spec rigol_dp831_ch[] = {
49a468ed
FS		 374 { "1", { 0, 8, 0.001, 3, 4 }, { 0, 5, 0.0003, 3, 4 }, { 0, 40, 0, 3, 4 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS },
375 { "2", { 0, 30, 0.001, 3, 4 }, { 0, 2, 0.0001, 3, 4 }, { 0, 60, 0, 3, 4 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS },
376 { "3", { 0, -30, 0.001, 3, 4 }, { 0, 2, 0.0001, 3, 4 }, { 0, 60, 0, 3, 4 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS },
d4eabea8
BV		 377};
378
8cb5affe 379static const struct channel_spec rigol_dp832_ch[] = {
49a468ed
FS		 380 { "1", { 0, 30, 0.001, 3, 4 }, { 0, 3, 0.001, 3, 4 }, { 0, 90, 0, 3, 4 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS },
381 { "2", { 0, 30, 0.001, 3, 4 }, { 0, 3, 0.001, 3, 4 }, { 0, 90, 0, 3, 4 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS },
382 { "3", { 0, 5, 0.001, 3, 4 }, { 0, 3, 0.001, 3, 4 }, { 0, 90, 0, 3, 4 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS },
3222ee10
BV		 383};
384
8cb5affe 385static const struct channel_group_spec rigol_dp820_cg[] = {
f2bbcc33
FS		 386 { "1", CH_IDX(0), PPS_OVP | PPS_OCP, SR_MQFLAG_DC },
387 { "2", CH_IDX(1), PPS_OVP | PPS_OCP, SR_MQFLAG_DC },
cfcdf576
ML		 388};
389
8cb5affe 390static const struct channel_group_spec rigol_dp830_cg[] = {
f2bbcc33
FS		 391 { "1", CH_IDX(0), PPS_OVP | PPS_OCP, SR_MQFLAG_DC },
392 { "2", CH_IDX(1), PPS_OVP | PPS_OCP, SR_MQFLAG_DC },
393 { "3", CH_IDX(2), PPS_OVP | PPS_OCP, SR_MQFLAG_DC },
d4eabea8
BV		 394};
395
8cb5affe 396static const struct scpi_command rigol_dp800_cmd[] = {
60475cd7
BV		 397 { SCPI_CMD_REMOTE, "SYST:REMOTE" },
398 { SCPI_CMD_LOCAL, "SYST:LOCAL" },
ee2860ee
BV		 399 { SCPI_CMD_BEEPER, "SYST:BEEP:STAT?" },
400 { SCPI_CMD_BEEPER_ENABLE, "SYST:BEEP:STAT ON" },
401 { SCPI_CMD_BEEPER_DISABLE, "SYST:BEEP:STAT OFF" },
60475cd7
BV		 402 { SCPI_CMD_SELECT_CHANNEL, ":INST:NSEL %s" },
403 { SCPI_CMD_GET_MEAS_VOLTAGE, ":MEAS:VOLT?" },
404 { SCPI_CMD_GET_MEAS_CURRENT, ":MEAS:CURR?" },
405 { SCPI_CMD_GET_MEAS_POWER, ":MEAS:POWE?" },
406 { SCPI_CMD_GET_VOLTAGE_TARGET, ":SOUR:VOLT?" },
407 { SCPI_CMD_SET_VOLTAGE_TARGET, ":SOUR:VOLT %.6f" },
408 { SCPI_CMD_GET_CURRENT_LIMIT, ":SOUR:CURR?" },
409 { SCPI_CMD_SET_CURRENT_LIMIT, ":SOUR:CURR %.6f" },
410 { SCPI_CMD_GET_OUTPUT_ENABLED, ":OUTP?" },
411 { SCPI_CMD_SET_OUTPUT_ENABLE, ":OUTP ON" },
412 { SCPI_CMD_SET_OUTPUT_DISABLE, ":OUTP OFF" },
413 { SCPI_CMD_GET_OUTPUT_REGULATION, ":OUTP:MODE?" },
d4eabea8 414 { SCPI_CMD_GET_OVER_TEMPERATURE_PROTECTION, ":SYST:OTP?" },
53a81803
BV		 415 { SCPI_CMD_SET_OVER_TEMPERATURE_PROTECTION_ENABLE, ":SYST:OTP ON" },
416 { SCPI_CMD_SET_OVER_TEMPERATURE_PROTECTION_DISABLE, ":SYST:OTP OFF" },
60475cd7
BV		 417 { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_ENABLED, ":OUTP:OVP?" },
418 { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_ENABLE, ":OUTP:OVP ON" },
419 { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_DISABLE, ":OUTP:OVP OFF" },
420 { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_ACTIVE, ":OUTP:OVP:QUES?" },
421 { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_THRESHOLD, ":OUTP:OVP:VAL?" },
422 { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_THRESHOLD, ":OUTP:OVP:VAL %.6f" },
423 { SCPI_CMD_GET_OVER_CURRENT_PROTECTION_ENABLED, ":OUTP:OCP?" },
424 { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_ENABLE, ":OUTP:OCP:STAT ON" },
425 { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_DISABLE, ":OUTP:OCP:STAT OFF" },
426 { SCPI_CMD_GET_OVER_CURRENT_PROTECTION_ACTIVE, ":OUTP:OCP:QUES?" },
427 { SCPI_CMD_GET_OVER_CURRENT_PROTECTION_THRESHOLD, ":OUTP:OCP:VAL?" },
428 { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_THRESHOLD, ":OUTP:OCP:VAL %.6f" },
91ef511d 429 ALL_ZERO
d4eabea8
BV		 430};
431
dbc519f7 432/* HP 663xA series */
e76a3575
AG		 433static const uint32_t hp_6630a_devopts[] = {
434 SR_CONF_CONTINUOUS,
88e4daa9
ML		 435 SR_CONF_LIMIT_SAMPLES | SR_CONF_GET | SR_CONF_SET,
436 SR_CONF_LIMIT_MSEC | SR_CONF_GET | SR_CONF_SET,
7c517d02
FS		 437};
438
439static const uint32_t hp_6630a_devopts_cg[] = {
e76a3575
AG		 440 SR_CONF_ENABLED | SR_CONF_SET,
441 SR_CONF_VOLTAGE | SR_CONF_GET,
442 SR_CONF_CURRENT | SR_CONF_GET,
443 SR_CONF_VOLTAGE_TARGET | SR_CONF_SET | SR_CONF_LIST,
444 SR_CONF_CURRENT_LIMIT | SR_CONF_SET | SR_CONF_LIST,
f083ae63 445 SR_CONF_OVER_VOLTAGE_PROTECTION_ACTIVE | SR_CONF_GET,
49a468ed 446 SR_CONF_OVER_VOLTAGE_PROTECTION_THRESHOLD | SR_CONF_SET | SR_CONF_LIST,
e76a3575 447 SR_CONF_OVER_CURRENT_PROTECTION_ENABLED | SR_CONF_SET,
f083ae63
FS		 448 SR_CONF_OVER_CURRENT_PROTECTION_ACTIVE | SR_CONF_GET,
449 SR_CONF_OVER_TEMPERATURE_PROTECTION_ACTIVE | SR_CONF_GET,
0ad7074c 450 SR_CONF_REGULATION | SR_CONF_GET,
e76a3575
AG		 451};
452
dbc519f7
FS		 453static const struct channel_spec hp_6633a_ch[] = {
454 { "1", { 0, 51.188, 0.0125, 3, 4 }, { 0, 2.0475, 0.0005, 4, 5 }, { 0, 104.80743 }, FREQ_DC_ONLY, { 0, 55, 0.25 }, NO_OCP_LIMITS },
455};
456
457static const struct channel_group_spec hp_6630a_cg[] = {
458 { "1", CH_IDX(0), PPS_OVP | PPS_OCP, SR_MQFLAG_DC },
459};
460
461static const struct scpi_command hp_6630a_cmd[] = {
462 { SCPI_CMD_SET_OUTPUT_ENABLE, "OUT 1" },
463 { SCPI_CMD_SET_OUTPUT_DISABLE, "OUT 0" },
464 { SCPI_CMD_GET_MEAS_VOLTAGE, "VOUT?" },
465 { SCPI_CMD_GET_MEAS_CURRENT, "IOUT?" },
466 { SCPI_CMD_SET_VOLTAGE_TARGET, "VSET %.4f" },
467 { SCPI_CMD_SET_CURRENT_LIMIT, "ISET %.4f" },
f083ae63
FS		 468 { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_ACTIVE, "STS?" },
469 { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_THRESHOLD, "OVSET %.4f" },
dbc519f7
FS		 470 { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_ENABLE, "OCP 1" },
471 { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_DISABLE, "OCP 0" },
f083ae63
FS		 472 { SCPI_CMD_GET_OVER_CURRENT_PROTECTION_ACTIVE, "STS?" },
473 { SCPI_CMD_GET_OVER_TEMPERATURE_PROTECTION_ACTIVE, "STS?" },
0ad7074c 474 { SCPI_CMD_GET_OUTPUT_REGULATION, "STS?" },
dbc519f7
FS		 475 ALL_ZERO
476};
477
fdf03652
FS		 478static int hp_6630a_init_aquisition(const struct sr_dev_inst *sdi)
479{
480 struct sr_scpi_dev_inst *scpi;
481 int ret;
482
483 scpi = sdi->conn;
484
485 /*
486 * Monitor CV (1), CC+ (2), UR (4), OVP (8), OTP (16), OCP (64) and
487 * CC- (256) bits of the Status Register for the FAULT? query.
488 */
489 ret = sr_scpi_send(scpi, "UNMASK 607");
490 if (ret != SR_OK)
491 return ret;
492
493 return SR_OK;
494}
495
496static int hp_6630a_update_status(const struct sr_dev_inst *sdi)
497{
498 struct sr_scpi_dev_inst *scpi;
499 int ret;
500 int fault;
501 gboolean cv, cc_pos, unreg, cc_neg;
502 gboolean regulation_changed;
503 char *regulation;
504
505 scpi = sdi->conn;
506
507 /*
508 * Use the FAULT register (only 0->1 transitions), this way multiple set
509 * regulation bits in the STS/ASTS registers are ignored. In rare cases
510 * we will miss some changes (1->0 transitions, e.g. no regulation at all),
511 * but SPS/ASPS doesn't work either, unless all states are stored and
512 * compared to the states in STS/ASTS.
513 * TODO: Use SPoll or SRQ when SCPI over GPIB is used.
514 */
515 ret = sr_scpi_get_int(scpi, "FAULT?", &fault);
516 if (ret != SR_OK)
517 return ret;
518
519 /* OVP */
520 if (fault & (1 << 3))
521 sr_session_send_meta(sdi, SR_CONF_OVER_VOLTAGE_PROTECTION_ACTIVE,
522 g_variant_new_boolean(fault & (1 << 3)));
523
524 /* OCP */
525 if (fault & (1 << 6))
526 sr_session_send_meta(sdi, SR_CONF_OVER_CURRENT_PROTECTION_ACTIVE,
527 g_variant_new_boolean(fault & (1 << 6)));
528
529 /* OTP */
530 if (fault & (1 << 4))
531 sr_session_send_meta(sdi, SR_CONF_OVER_TEMPERATURE_PROTECTION_ACTIVE,
532 g_variant_new_boolean(fault & (1 << 4)));
533
534 /* CV */
535 cv = (fault & (1 << 0));
536 regulation_changed = (fault & (1 << 0));
537 /* CC+ */
538 cc_pos = (fault & (1 << 1));
539 regulation_changed = (fault & (1 << 1)) | regulation_changed;
540 /* UNREG */
541 unreg = (fault & (1 << 2));
542 regulation_changed = (fault & (1 << 2)) | regulation_changed;
543 /* CC- */
544 cc_neg = (fault & (1 << 9));
545 regulation_changed = (fault & (1 << 9)) | regulation_changed;
546
547 if (regulation_changed) {
548 if (cv && !cc_pos && !cc_neg &&!unreg)
549 regulation = "CV";
550 else if (cc_pos && !cv && !cc_neg && !unreg)
551 regulation = "CC";
552 else if (cc_neg && !cv && !cc_pos && !unreg)
553 regulation = "CC-";
554 else if (unreg && !cv && !cc_pos && !cc_neg)
555 regulation = "UR";
556 else if (!cv && !cc_pos && !cc_neg &&!unreg)
557 regulation = "";
558 else {
559 sr_dbg("Undefined regulation for HP 66xxA "
560 "(CV=%i, CC+=%i, CC-=%i, UR=%i).",
561 cv, cc_pos, cc_neg, unreg);
562 return FALSE;
563 }
564 sr_session_send_meta(sdi, SR_CONF_REGULATION,
565 g_variant_new_string(regulation));
566 }
567
568 return SR_OK;
569}
570
dbc519f7 571/* HP 663xB series */
a61c8cce 572static const uint32_t hp_6630b_devopts[] = {
e91bb0a6 573 SR_CONF_CONTINUOUS,
88e4daa9
ML		 574 SR_CONF_LIMIT_SAMPLES | SR_CONF_GET | SR_CONF_SET,
575 SR_CONF_LIMIT_MSEC | SR_CONF_GET | SR_CONF_SET,
7c517d02
FS		 576};
577
a61c8cce 578static const uint32_t hp_6630b_devopts_cg[] = {
7a0b98b5
AJ		 579 SR_CONF_ENABLED | SR_CONF_GET | SR_CONF_SET,
580 SR_CONF_VOLTAGE | SR_CONF_GET,
581 SR_CONF_CURRENT | SR_CONF_GET,
582 SR_CONF_VOLTAGE_TARGET | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
583 SR_CONF_CURRENT_LIMIT | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
8b5eadf4 584 SR_CONF_OVER_VOLTAGE_PROTECTION_ACTIVE | SR_CONF_GET,
49a468ed 585 SR_CONF_OVER_VOLTAGE_PROTECTION_THRESHOLD | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
7e381bfc 586 SR_CONF_OVER_CURRENT_PROTECTION_ENABLED | SR_CONF_GET | SR_CONF_SET,
8b5eadf4
FS		 587 SR_CONF_OVER_CURRENT_PROTECTION_ACTIVE | SR_CONF_GET,
588 SR_CONF_OVER_TEMPERATURE_PROTECTION_ACTIVE | SR_CONF_GET,
43ff1110 589 SR_CONF_REGULATION | SR_CONF_GET,
bc4a2a46
BV		 590};
591
a61c8cce 592static const struct channel_spec hp_6631b_ch[] = {
49a468ed 593 { "1", { 0, 8.19, 0.002, 3, 4 }, { 0, 10.237, 0.00263, 4, 5 }, { 0, 83.84103 }, FREQ_DC_ONLY, { 0, 12, 0.06 }, NO_OCP_LIMITS },
a61c8cce
FS		 594};
595
8cb5affe 596static const struct channel_spec hp_6632b_ch[] = {
49a468ed 597 { "1", { 0, 20.475, 0.005, 3, 4 }, { 0, 5.1188, 0.00132, 4, 5 }, { 0, 104.80743 }, FREQ_DC_ONLY, { 0, 22, 0.1 }, NO_OCP_LIMITS },
bc4a2a46
BV		 598};
599
a61c8cce 600static const struct channel_spec hp_66332a_ch[] = {
49a468ed 601 { "1", { 0, 20.475, 0.005, 3, 4 }, { 0, 5.1188, 0.00132, 4, 5 }, { 0, 104.80743 }, FREQ_DC_ONLY, { 0, 22, 0.1 }, NO_OCP_LIMITS },
a61c8cce
FS		 602};
603
604static const struct channel_spec hp_6633b_ch[] = {
49a468ed 605 { "1", { 0, 51.188, 0.0125, 3, 4 }, { 0, 2.0475, 0.000526, 4, 5 }, { 0, 104.80743 }, FREQ_DC_ONLY, { 0, 55, 0.25 }, NO_OCP_LIMITS },
a61c8cce
FS		 606};
607
608static const struct channel_spec hp_6634b_ch[] = {
49a468ed 609 { "1", { 0, 102.38, 0.025, 3, 4 }, { 0, 1.0238, 0.000263, 4, 5 }, { 0, 104.81664 }, FREQ_DC_ONLY, { 0, 110, 0.5 }, NO_OCP_LIMITS },
a61c8cce
FS		 610};
611
dbc519f7 612static const struct channel_group_spec hp_6630b_cg[] = {
3d1aa50f 613 { "1", CH_IDX(0), PPS_OVP | PPS_OCP, SR_MQFLAG_DC },
bc4a2a46
BV		 614};
615
a61c8cce 616static const struct scpi_command hp_6630b_cmd[] = {
7e381bfc
FS		 617 { SCPI_CMD_REMOTE, "SYST:REM" },
618 { SCPI_CMD_LOCAL, "SYST:LOC" },
bc4a2a46 619 { SCPI_CMD_GET_OUTPUT_ENABLED, "OUTP:STAT?" },
53a81803
BV		 620 { SCPI_CMD_SET_OUTPUT_ENABLE, "OUTP:STAT ON" },
621 { SCPI_CMD_SET_OUTPUT_DISABLE, "OUTP:STAT OFF" },
bc4a2a46
BV		 622 { SCPI_CMD_GET_MEAS_VOLTAGE, ":MEAS:VOLT?" },
623 { SCPI_CMD_GET_MEAS_CURRENT, ":MEAS:CURR?" },
ca95e90f
BV		 624 { SCPI_CMD_GET_VOLTAGE_TARGET, ":SOUR:VOLT?" },
625 { SCPI_CMD_SET_VOLTAGE_TARGET, ":SOUR:VOLT %.6f" },
626 { SCPI_CMD_GET_CURRENT_LIMIT, ":SOUR:CURR?" },
627 { SCPI_CMD_SET_CURRENT_LIMIT, ":SOUR:CURR %.6f" },
7e381bfc
FS		 628 { SCPI_CMD_GET_OVER_CURRENT_PROTECTION_ENABLED, ":CURR:PROT:STAT?" },
629 { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_ENABLE, ":CURR:PROT:STAT 1" },
630 { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_DISABLE, ":CURR:PROT:STAT 0" },
8b5eadf4
FS		 631 { SCPI_CMD_GET_OVER_CURRENT_PROTECTION_ACTIVE, "STAT:QUES:COND?" },
632 { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_ACTIVE, "STAT:QUES:COND?" },
7e381bfc
FS		 633 { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_THRESHOLD, ":VOLT:PROT?" },
634 { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_THRESHOLD, ":VOLT:PROT %.6f" },
8b5eadf4 635 { SCPI_CMD_GET_OVER_TEMPERATURE_PROTECTION_ACTIVE, "STAT:QUES:COND?" },
43ff1110 636 { SCPI_CMD_GET_OUTPUT_REGULATION, "STAT:OPER:COND?" },
91ef511d 637 ALL_ZERO
bc4a2a46
BV		 638};
639
fe4bb774
FS		 640static int hp_6630b_init_aquisition(const struct sr_dev_inst *sdi)
641{
642 struct sr_scpi_dev_inst *scpi;
643 int ret;
644
645 scpi = sdi->conn;
646
647 /*
648 * Monitor CV (256), CC+ (1024) and CC- (2048) bits of the
649 * Operational Status Register.
650 * Use both positive and negative transitions of the status bits.
651 */
652 ret = sr_scpi_send(scpi, "STAT:OPER:PTR 3328;NTR 3328;ENAB 3328");
653 if (ret != SR_OK)
654 return ret;
655
656 /*
657 * Monitor OVP (1), OCP (2), OTP (16) and Unreg (1024) bits of the
658 * Questionable Status Register.
659 * Use both positive and negative transitions of the status bits.
660 */
661 ret = sr_scpi_send(scpi, "STAT:QUES:PTR 1043;NTR 1043;ENAB 1043");
662 if (ret != SR_OK)
663 return ret;
664
665 /*
666 * Service Request Enable Register set for Operational Status Register
667 * bits (128) and Questionable Status Register bits (8).
668 * This masks the Status Register generating a SRQ/RQS. Not implemented yet!
669 */
670 /*
671 ret = sr_scpi_send(scpi, "*SRE 136");
672 if (ret != SR_OK)
673 return ret;
674 */
675
676 return SR_OK;
677}
678
679static int hp_6630b_update_status(const struct sr_dev_inst *sdi)
680{
681 struct sr_scpi_dev_inst *scpi;
682 int ret;
683 int stb;
684 int ques_even, ques_cond;
685 int oper_even, oper_cond;
686 gboolean output_enabled;
687 gboolean unreg, cv, cc_pos, cc_neg;
688 gboolean regulation_changed;
689 char *regulation;
690
691 scpi = sdi->conn;
692
693 unreg = FALSE;
694 cv = FALSE;
695 cc_pos = FALSE;
696 cc_neg = FALSE;
697 regulation_changed = FALSE;
698
699 /*
700 * Use SPoll when SCPI uses GPIB as transport layer.
701 * SPoll is approx. twice as fast as a normal GPIB write + read would be!
702 */
703#ifdef HAVE_LIBGPIB
704 char spoll_buf;
705
706 if (scpi->transport == SCPI_TRANSPORT_LIBGPIB) {
707 ret = sr_scpi_gpib_spoll(scpi, &spoll_buf);
708 if (ret != SR_OK)
709 return ret;
710 stb = (uint8_t)spoll_buf;
711 }
712 else {
713#endif
714 ret = sr_scpi_get_int(scpi, "*STB?", &stb);
715 if (ret != SR_OK)
716 return ret;
717#ifdef HAVE_LIBGPIB
718 }
719#endif
720
721 /* Questionable status summary bit */
722 if (stb & (1 << 3)) {
723 /* Read the event register to clear it! */
724 ret = sr_scpi_get_int(scpi, "STAT:QUES:EVEN?", &ques_even);
725 if (ret != SR_OK)
726 return ret;
727 /* Now get the values. */
728 ret = sr_scpi_get_int(scpi, "STAT:QUES:COND?", &ques_cond);
729 if (ret != SR_OK)
730 return ret;
731
732 /* OVP */
733 if (ques_even & (1 << 0))
734 sr_session_send_meta(sdi, SR_CONF_OVER_VOLTAGE_PROTECTION_ACTIVE,
735 g_variant_new_boolean(ques_cond & (1 << 0)));
736
737 /* OCP */
738 if (ques_even & (1 << 1))
739 sr_session_send_meta(sdi, SR_CONF_OVER_CURRENT_PROTECTION_ACTIVE,
740 g_variant_new_boolean(ques_cond & (1 << 1)));
741
742 /* OTP */
743 if (ques_even & (1 << 4))
744 sr_session_send_meta(sdi, SR_CONF_OVER_TEMPERATURE_PROTECTION_ACTIVE,
745 g_variant_new_boolean(ques_cond & (1 << 4)));
746
747 /* UNREG */
748 unreg = (ques_cond & (1 << 10));
749 regulation_changed = (ques_even & (1 << 10)) | regulation_changed;
750
751 /*
752 * Check if output state has changed, due to one of the
753 * questionable states changed.
754 * NOTE: The output state is send even if it hasn't changed, but that
755 * only happends rarely.
756 */
757 ret = sr_scpi_get_bool(scpi, "OUTP:STAT?", &output_enabled);
758 if (ret != SR_OK)
759 return ret;
760 sr_session_send_meta(sdi, SR_CONF_ENABLED,
761 g_variant_new_boolean(output_enabled));
762 }
763
764 /* Operation status summary bit */
765 if (stb & (1 << 7)) {
766 /* Read the event register to clear it! */
767 ret = sr_scpi_get_int(scpi, "STAT:OPER:EVEN?", &oper_even);
768 if (ret != SR_OK)
769 return ret;
770 /* Now get the values. */
771 ret = sr_scpi_get_int(scpi, "STAT:OPER:COND?", &oper_cond);
772 if (ret != SR_OK)
773 return ret;
774
775 /* CV */
776 cv = (oper_cond & (1 << 8));
777 regulation_changed = (oper_even & (1 << 8)) | regulation_changed;
778 /* CC+ */
779 cc_pos = (oper_cond & (1 << 10));
780 regulation_changed = (oper_even & (1 << 10)) | regulation_changed;
781 /* CC- */
782 cc_neg = (oper_cond & (1 << 11));
783 regulation_changed = (oper_even & (1 << 11)) | regulation_changed;
784 }
785
786 if (regulation_changed) {
787 if (cv && !cc_pos && !cc_neg &&!unreg)
788 regulation = "CV";
789 else if (cc_pos && !cv && !cc_neg && !unreg)
790 regulation = "CC";
791 else if (cc_neg && !cv && !cc_pos && !unreg)
792 regulation = "CC-";
793 else if (unreg && !cv && !cc_pos && !cc_neg)
794 regulation = "UR";
795 else if (!cv && !cc_pos && !cc_neg &&!unreg)
796 /* This happends in case of OCP active */
797 regulation = "";
798 else {
799 /* This happends from time to time (CV and CC+ active). */
800 sr_dbg("Undefined regulation for HP 66xxB "
801 "(CV=%i, CC+=%i, CC-=%i, UR=%i).",
802 cv, cc_pos, cc_neg, unreg);
803 return FALSE;
804 }
805 sr_session_send_meta(sdi, SR_CONF_REGULATION,
806 g_variant_new_string(regulation));
807 }
808
809 return SR_OK;
810}
811
c3eadb07 812/* Philips/Fluke PM2800 series */
9d9cf1c4 813static const uint32_t philips_pm2800_devopts[] = {
e91bb0a6 814 SR_CONF_CONTINUOUS,
88e4daa9
ML		 815 SR_CONF_LIMIT_SAMPLES | SR_CONF_GET | SR_CONF_SET,
816 SR_CONF_LIMIT_MSEC | SR_CONF_GET | SR_CONF_SET,
9d9cf1c4
BV		 817};
818
c3eadb07 819static const uint32_t philips_pm2800_devopts_cg[] = {
7a0b98b5
AJ		 820 SR_CONF_ENABLED | SR_CONF_GET | SR_CONF_SET,
821 SR_CONF_VOLTAGE | SR_CONF_GET,
822 SR_CONF_VOLTAGE_TARGET | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
823 SR_CONF_CURRENT | SR_CONF_GET,
824 SR_CONF_CURRENT_LIMIT | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
c3eadb07
BV		 825 SR_CONF_OVER_VOLTAGE_PROTECTION_ACTIVE | SR_CONF_GET,
826 SR_CONF_OVER_VOLTAGE_PROTECTION_THRESHOLD | SR_CONF_GET | SR_CONF_SET,
827 SR_CONF_OVER_CURRENT_PROTECTION_ENABLED | SR_CONF_GET | SR_CONF_SET,
828 SR_CONF_OVER_CURRENT_PROTECTION_ACTIVE | SR_CONF_GET,
7a0b98b5 829 SR_CONF_REGULATION | SR_CONF_GET,
c3eadb07
BV		 830};
831
832enum philips_pm2800_modules {
833 PM2800_MOD_30V_10A = 1,
834 PM2800_MOD_60V_5A,
835 PM2800_MOD_60V_10A,
836 PM2800_MOD_8V_15A,
837 PM2800_MOD_60V_2A,
838 PM2800_MOD_120V_1A,
839};
840
329733d9 841static const struct philips_pm2800_module_spec {
c3eadb07 842 /* Min, max, programming resolution. */
bcee1299
UH		 843 double voltage[5];
844 double current[5];
845 double power[5];
c3eadb07
BV		 846} philips_pm2800_module_specs[] = {
847 /* Autoranging modules. */
6ed709fe
AJ		 848 [PM2800_MOD_30V_10A] = { { 0, 30, 0.0075, 2, 4 }, { 0, 10, 0.0025, 2, 4 }, { 0, 60 } },
849 [PM2800_MOD_60V_5A] = { { 0, 60, 0.015, 2, 3 }, { 0, 5, 0.00125, 2, 5 }, { 0, 60 } },
850 [PM2800_MOD_60V_10A] = { { 0, 60, 0.015, 2, 3 }, { 0, 10, 0.0025, 2, 5 }, { 0, 120 } },
c3eadb07 851 /* Linear modules. */
6ed709fe
AJ		 852 [PM2800_MOD_8V_15A] = { { 0, 8, 0.002, 3, 3 }, { -15, 15, 0.00375, 3, 5 }, { 0, 120 } },
853 [PM2800_MOD_60V_2A] = { { 0, 60, 0.015, 2, 3 }, { -2, 2, 0.0005, 3, 4 }, { 0, 120 } },
854 [PM2800_MOD_120V_1A] = { { 0, 120, 0.030, 2, 2 }, { -1, 1, 0.00025, 3, 5 }, { 0, 120 } },
c3eadb07
BV		 855};
856
329733d9 857static const struct philips_pm2800_model {
c3eadb07
BV		 858 unsigned int chassis;
859 unsigned int num_modules;
860 unsigned int set;
861 unsigned int modules[3];
862} philips_pm2800_matrix[] = {
863 /* Autoranging chassis. */
864 { 1, 1, 0, { PM2800_MOD_30V_10A, 0, 0 } },
865 { 1, 1, 1, { PM2800_MOD_60V_5A, 0, 0 } },
866 { 1, 2, 0, { PM2800_MOD_30V_10A, PM2800_MOD_30V_10A, 0 } },
867 { 1, 2, 1, { PM2800_MOD_60V_5A, PM2800_MOD_60V_5A, 0 } },
868 { 1, 2, 2, { PM2800_MOD_30V_10A, PM2800_MOD_60V_5A, 0 } },
869 { 1, 2, 3, { PM2800_MOD_30V_10A, PM2800_MOD_60V_10A, 0 } },
870 { 1, 2, 4, { PM2800_MOD_60V_5A, PM2800_MOD_60V_10A, 0 } },
871 { 1, 3, 0, { PM2800_MOD_30V_10A, PM2800_MOD_30V_10A, PM2800_MOD_30V_10A } },
872 { 1, 3, 1, { PM2800_MOD_60V_5A, PM2800_MOD_60V_5A, PM2800_MOD_60V_5A } },
873 { 1, 3, 2, { PM2800_MOD_30V_10A, PM2800_MOD_30V_10A, PM2800_MOD_60V_5A } },
874 { 1, 3, 3, { PM2800_MOD_30V_10A, PM2800_MOD_60V_5A, PM2800_MOD_60V_5A } },
875 /* Linear chassis. */
876 { 3, 1, 0, { PM2800_MOD_60V_2A, 0, 0 } },
877 { 3, 1, 1, { PM2800_MOD_120V_1A, 0, 0 } },
878 { 3, 1, 2, { PM2800_MOD_8V_15A, 0, 0 } },
879 { 3, 2, 0, { PM2800_MOD_60V_2A, 0, 0 } },
880 { 3, 2, 1, { PM2800_MOD_120V_1A, 0, 0 } },
881 { 3, 2, 2, { PM2800_MOD_60V_2A, PM2800_MOD_120V_1A, 0 } },
882 { 3, 2, 3, { PM2800_MOD_8V_15A, PM2800_MOD_8V_15A, 0 } },
883};
884
329733d9 885static const char *philips_pm2800_names[] = { "1", "2", "3" };
c3eadb07
BV		 886
887static int philips_pm2800_probe_channels(struct sr_dev_inst *sdi,
888 struct sr_scpi_hw_info *hw_info,
889 struct channel_spec **channels, unsigned int *num_channels,
890 struct channel_group_spec **channel_groups, unsigned int *num_channel_groups)
891{
329733d9
UH		 892 const struct philips_pm2800_model *model;
893 const struct philips_pm2800_module_spec *spec;
c3eadb07
BV		 894 unsigned int chassis, num_modules, set, module, m, i;
895
896 (void)sdi;
897
898 /*
899 * The model number as reported by *IDN? looks like e.g. PM2813/11,
900 * Where "PM28" is fixed, followed by the chassis code (1 = autoranging,
901 * 3 = linear series) and the number of modules: 1-3 for autoranging,
902 * 1-2 for linear.
903 * After the slash, the first digit denotes the module set. The
904 * digit after that denotes front (5) or rear (1) binding posts.
905 */
906 chassis = hw_info->model[4] - 0x30;
907 num_modules = hw_info->model[5] - 0x30;
908 set = hw_info->model[7] - 0x30;
909 for (m = 0; m < ARRAY_SIZE(philips_pm2800_matrix); m++) {
910 model = &philips_pm2800_matrix[m];
911 if (model->chassis == chassis && model->num_modules == num_modules
912 && model->set == set)
913 break;
914 }
915 if (m == ARRAY_SIZE(philips_pm2800_matrix)) {
916 sr_dbg("Model %s not found in matrix.", hw_info->model);
917 return SR_ERR;
918 }
919
920 sr_dbg("Found %d output channel%s:", num_modules, num_modules > 1 ? "s" : "");
921 *channels = g_malloc0(sizeof(struct channel_spec) * num_modules);
922 *channel_groups = g_malloc0(sizeof(struct channel_group_spec) * num_modules);
923 for (i = 0; i < num_modules; i++) {
924 module = model->modules[i];
925 spec = &philips_pm2800_module_specs[module];
6ed709fe 926 sr_dbg("output %d: %.0f - %.0fV, %.0f - %.0fA, %.0f - %.0fW", i + 1,
c3eadb07 927 spec->voltage[0], spec->voltage[1],
6ed709fe 928 spec->current[0], spec->current[1],
d9251a2c 929 spec->power[0], spec->power[1]);
329733d9 930 (*channels)[i].name = (char *)philips_pm2800_names[i];
bcee1299 931 memcpy(&((*channels)[i].voltage), spec, sizeof(double) * 15);
329733d9 932 (*channel_groups)[i].name = (char *)philips_pm2800_names[i];
c3eadb07
BV		 933 (*channel_groups)[i].channel_index_mask = 1 << i;
934 (*channel_groups)[i].features = PPS_OTP | PPS_OVP | PPS_OCP;
f2bbcc33 935 (*channel_groups)[i].mqflags = SR_MQFLAG_DC;
c3eadb07
BV		 936 }
937 *num_channels = *num_channel_groups = num_modules;
938
939 return SR_OK;
940}
941
8cb5affe 942static const struct scpi_command philips_pm2800_cmd[] = {
c3eadb07
BV		 943 { SCPI_CMD_SELECT_CHANNEL, ":INST:NSEL %s" },
944 { SCPI_CMD_GET_MEAS_VOLTAGE, ":MEAS:VOLT?" },
945 { SCPI_CMD_GET_MEAS_CURRENT, ":MEAS:CURR?" },
946 { SCPI_CMD_GET_VOLTAGE_TARGET, ":SOUR:VOLT?" },
947 { SCPI_CMD_SET_VOLTAGE_TARGET, ":SOUR:VOLT %.6f" },
948 { SCPI_CMD_GET_CURRENT_LIMIT, ":SOUR:CURR?" },
949 { SCPI_CMD_SET_CURRENT_LIMIT, ":SOUR:CURR %.6f" },
950 { SCPI_CMD_GET_OUTPUT_ENABLED, ":OUTP?" },
951 { SCPI_CMD_SET_OUTPUT_ENABLE, ":OUTP ON" },
952 { SCPI_CMD_SET_OUTPUT_DISABLE, ":OUTP OFF" },
953 { SCPI_CMD_GET_OUTPUT_REGULATION, ":SOUR:FUNC:MODE?" },
954 { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_ACTIVE, ":SOUR:VOLT:PROT:TRIP?" },
955 { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_THRESHOLD, ":SOUR:VOLT:PROT:LEV?" },
956 { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_THRESHOLD, ":SOUR:VOLT:PROT:LEV %.6f" },
957 { SCPI_CMD_GET_OVER_CURRENT_PROTECTION_ENABLED, ":SOUR:CURR:PROT:STAT?" },
958 { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_ENABLE, ":SOUR:CURR:PROT:STAT ON" },
959 { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_DISABLE, ":SOUR:CURR:PROT:STAT OFF" },
960 { SCPI_CMD_GET_OVER_CURRENT_PROTECTION_ACTIVE, ":SOUR:CURR:PROT:TRIP?" },
91ef511d 961 ALL_ZERO
c3eadb07
BV		 962};
963
81eb36d6
MS		 964static const uint32_t rs_hmc8043_devopts[] = {
965 SR_CONF_CONTINUOUS,
88e4daa9
ML		 966 SR_CONF_LIMIT_SAMPLES | SR_CONF_GET | SR_CONF_SET,
967 SR_CONF_LIMIT_MSEC | SR_CONF_GET | SR_CONF_SET,
81eb36d6
MS		 968};
969
970static const uint32_t rs_hmc8043_devopts_cg[] = {
971 SR_CONF_OVER_VOLTAGE_PROTECTION_ENABLED | SR_CONF_GET | SR_CONF_SET,
972 SR_CONF_OVER_VOLTAGE_PROTECTION_ACTIVE | SR_CONF_GET,
973 SR_CONF_OVER_VOLTAGE_PROTECTION_THRESHOLD | SR_CONF_GET | SR_CONF_SET,
974 SR_CONF_VOLTAGE | SR_CONF_GET,
975 SR_CONF_VOLTAGE_TARGET | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
976 SR_CONF_CURRENT | SR_CONF_GET,
977 SR_CONF_CURRENT_LIMIT | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
978 SR_CONF_ENABLED | SR_CONF_GET | SR_CONF_SET,
979};
980
981static const struct channel_spec rs_hmc8043_ch[] = {
49a468ed
FS		 982 { "1", { 0, 32.050, 0.001, 3, 4 }, { 0.001, 3, 0.001, 3, 4 }, { 0, 0, 0, 0, 4 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS },
983 { "2", { 0, 32.050, 0.001, 3, 4 }, { 0.001, 3, 0.001, 3, 4 }, { 0, 0, 0, 0, 4 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS },
984 { "3", { 0, 32.050, 0.001, 3, 4 }, { 0.001, 3, 0.001, 3, 4 }, { 0, 0, 0, 0, 4 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS },
81eb36d6
MS		 985};
986
987static const struct channel_group_spec rs_hmc8043_cg[] = {
f2bbcc33
FS		 988 { "1", CH_IDX(0), PPS_OVP, SR_MQFLAG_DC },
989 { "2", CH_IDX(1), PPS_OVP, SR_MQFLAG_DC },
990 { "3", CH_IDX(2), PPS_OVP, SR_MQFLAG_DC },
81eb36d6
MS		 991};
992
993static const struct scpi_command rs_hmc8043_cmd[] = {
994 { SCPI_CMD_SELECT_CHANNEL, "INST:NSEL %s" },
995 { SCPI_CMD_GET_MEAS_VOLTAGE, "MEAS:VOLT?" },
996 { SCPI_CMD_GET_MEAS_CURRENT, "MEAS:CURR?" },
997 { SCPI_CMD_GET_VOLTAGE_TARGET, "VOLT?" },
998 { SCPI_CMD_SET_VOLTAGE_TARGET, "VOLT %.6f" },
999 { SCPI_CMD_GET_CURRENT_LIMIT, "CURR?" },
1000 { SCPI_CMD_SET_CURRENT_LIMIT, "CURR %.6f" },
1001 { SCPI_CMD_GET_OUTPUT_ENABLED, "OUTP?" },
1002 { SCPI_CMD_SET_OUTPUT_ENABLE, "OUTP ON" },
1003 { SCPI_CMD_SET_OUTPUT_DISABLE, "OUTP OFF" },
1004 { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_ACTIVE, "VOLT:PROT:TRIP?" },
1005 { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_THRESHOLD, "VOLT:PROT:LEV?" },
1006 { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_THRESHOLD, "VOLT:PROT:LEV %.6f" },
1007 { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_ENABLED, "VOLT:PROT:STAT?" },
1008 { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_ENABLE, "VOLT:PROT:STAT ON" },
1009 { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_DISABLE, "VOLT:PROT:STAT OFF" },
1010 ALL_ZERO
1011};
1012
d4eabea8 1013SR_PRIV const struct scpi_pps pps_profiles[] = {
6cc93128 1014 /* Agilent N5763A */
5e7377f4 1015 { "Agilent", "N5763A", SCPI_DIALECT_UNKNOWN, 0,
6cc93128
AG		 1016 ARRAY_AND_SIZE(agilent_n5700a_devopts),
1017 ARRAY_AND_SIZE(agilent_n5700a_devopts_cg),
1018 ARRAY_AND_SIZE(agilent_n5763a_ch),
1019 ARRAY_AND_SIZE(agilent_n5700a_cg),
1020 agilent_n5700a_cmd,
1021 .probe_channels = NULL,
7e66bf05
FS		 1022 .init_aquisition = NULL,
1023 .update_status = NULL,
6cc93128 1024 },
ca314e06 1025
5c9e56c9 1026 /* Agilent N5767A */
5e7377f4 1027 { "Agilent", "N5767A", SCPI_DIALECT_UNKNOWN, 0,
5c9e56c9
AG		 1028 ARRAY_AND_SIZE(agilent_n5700a_devopts),
1029 ARRAY_AND_SIZE(agilent_n5700a_devopts_cg),
1030 ARRAY_AND_SIZE(agilent_n5767a_ch),
6cc93128 1031 ARRAY_AND_SIZE(agilent_n5700a_cg),
91ef511d 1032 agilent_n5700a_cmd,
5c9e56c9 1033 .probe_channels = NULL,
7e66bf05
FS		 1034 .init_aquisition = NULL,
1035 .update_status = NULL,
5c9e56c9 1036 },
ca314e06 1037
c3bfb959 1038 /* BK Precision 9310 */
5e7377f4 1039 { "BK", "^9130$", SCPI_DIALECT_UNKNOWN, 0,
c3bfb959
MW		 1040 ARRAY_AND_SIZE(bk_9130_devopts),
1041 ARRAY_AND_SIZE(bk_9130_devopts_cg),
1042 ARRAY_AND_SIZE(bk_9130_ch),
1043 ARRAY_AND_SIZE(bk_9130_cg),
1044 bk_9130_cmd,
1045 .probe_channels = NULL,
7e66bf05
FS		 1046 .init_aquisition = NULL,
1047 .update_status = NULL,
c3bfb959
MW		 1048 },
1049
4ee1e2f3 1050 /* Chroma 61604 */
5e7377f4 1051 { "Chroma", "61604", SCPI_DIALECT_UNKNOWN, 0,
4ee1e2f3
AG		 1052 ARRAY_AND_SIZE(chroma_61604_devopts),
1053 ARRAY_AND_SIZE(chroma_61604_devopts_cg),
1054 ARRAY_AND_SIZE(chroma_61604_ch),
1055 ARRAY_AND_SIZE(chroma_61604_cg),
91ef511d 1056 chroma_61604_cmd,
4ee1e2f3 1057 .probe_channels = NULL,
7e66bf05
FS		 1058 .init_aquisition = NULL,
1059 .update_status = NULL,
4ee1e2f3 1060 },
ca314e06 1061
5281993e 1062 /* Chroma 62000 series */
5e7377f4 1063 { "Chroma", "620[0-9]{2}P-[0-9]{2,3}-[0-9]{1,3}", SCPI_DIALECT_UNKNOWN, 0,
5281993e
AG		 1064 ARRAY_AND_SIZE(chroma_62000_devopts),
1065 ARRAY_AND_SIZE(chroma_62000_devopts_cg),
9a5185c7
AG		 1066 NULL, 0,
1067 NULL, 0,
91ef511d 1068 chroma_62000_cmd,
9a5185c7 1069 .probe_channels = chroma_62000p_probe_channels,
7e66bf05
FS		 1070 .init_aquisition = NULL,
1071 .update_status = NULL,
5281993e 1072 },
ca314e06 1073
e76a3575 1074 /* HP 6633A */
5e7377f4 1075 { "HP", "6633A", SCPI_DIALECT_HP_COMP, 0,
e76a3575 1076 ARRAY_AND_SIZE(hp_6630a_devopts),
7c517d02 1077 ARRAY_AND_SIZE(hp_6630a_devopts_cg),
e76a3575 1078 ARRAY_AND_SIZE(hp_6633a_ch),
dbc519f7 1079 ARRAY_AND_SIZE(hp_6630a_cg),
e76a3575
AG		 1080 hp_6630a_cmd,
1081 .probe_channels = NULL,
fdf03652
FS		 1082 hp_6630a_init_aquisition,
1083 hp_6630a_update_status,
e76a3575
AG		 1084 },
1085
a61c8cce 1086 /* HP 6631B */
3d1aa50f 1087 { "HP", "6631B", SCPI_DIALECT_HP_66XXB, PPS_OTP,
a61c8cce
FS		 1088 ARRAY_AND_SIZE(hp_6630b_devopts),
1089 ARRAY_AND_SIZE(hp_6630b_devopts_cg),
1090 ARRAY_AND_SIZE(hp_6631b_ch),
dbc519f7 1091 ARRAY_AND_SIZE(hp_6630b_cg),
a61c8cce
FS		 1092 hp_6630b_cmd,
1093 .probe_channels = NULL,
fe4bb774
FS		 1094 hp_6630b_init_aquisition,
1095 hp_6630b_update_status,
a61c8cce
FS		 1096 },
1097
bc4a2a46 1098 /* HP 6632B */
3d1aa50f 1099 { "HP", "6632B", SCPI_DIALECT_HP_66XXB, PPS_OTP,
a61c8cce
FS		 1100 ARRAY_AND_SIZE(hp_6630b_devopts),
1101 ARRAY_AND_SIZE(hp_6630b_devopts_cg),
bc4a2a46 1102 ARRAY_AND_SIZE(hp_6632b_ch),
dbc519f7 1103 ARRAY_AND_SIZE(hp_6630b_cg),
a61c8cce
FS		 1104 hp_6630b_cmd,
1105 .probe_channels = NULL,
fe4bb774
FS		 1106 hp_6630b_init_aquisition,
1107 hp_6630b_update_status,
a61c8cce
FS		 1108 },
1109
1110 /* HP 66332A */
3d1aa50f 1111 { "HP", "66332A", SCPI_DIALECT_HP_66XXB, PPS_OTP,
a61c8cce
FS		 1112 ARRAY_AND_SIZE(hp_6630b_devopts),
1113 ARRAY_AND_SIZE(hp_6630b_devopts_cg),
1114 ARRAY_AND_SIZE(hp_66332a_ch),
dbc519f7 1115 ARRAY_AND_SIZE(hp_6630b_cg),
a61c8cce
FS		 1116 hp_6630b_cmd,
1117 .probe_channels = NULL,
fe4bb774
FS		 1118 hp_6630b_init_aquisition,
1119 hp_6630b_update_status,
a61c8cce
FS		 1120 },
1121
1122 /* HP 6633B */
3d1aa50f 1123 { "HP", "6633B", SCPI_DIALECT_HP_66XXB, PPS_OTP,
a61c8cce
FS		 1124 ARRAY_AND_SIZE(hp_6630b_devopts),
1125 ARRAY_AND_SIZE(hp_6630b_devopts_cg),
1126 ARRAY_AND_SIZE(hp_6633b_ch),
dbc519f7 1127 ARRAY_AND_SIZE(hp_6630b_cg),
a61c8cce
FS		 1128 hp_6630b_cmd,
1129 .probe_channels = NULL,
fe4bb774
FS		 1130 hp_6630b_init_aquisition,
1131 hp_6630b_update_status,
a61c8cce
FS		 1132 },
1133
1134 /* HP 6634B */
3d1aa50f 1135 { "HP", "6634B", SCPI_DIALECT_HP_66XXB, PPS_OTP,
a61c8cce
FS		 1136 ARRAY_AND_SIZE(hp_6630b_devopts),
1137 ARRAY_AND_SIZE(hp_6630b_devopts_cg),
1138 ARRAY_AND_SIZE(hp_6634b_ch),
dbc519f7 1139 ARRAY_AND_SIZE(hp_6630b_cg),
a61c8cce 1140 hp_6630b_cmd,
c3eadb07 1141 .probe_channels = NULL,
fe4bb774
FS		 1142 hp_6630b_init_aquisition,
1143 hp_6630b_update_status,
bc4a2a46
BV		 1144 },
1145
319fe9ce 1146 /* Rigol DP700 series */
5e7377f4 1147 { "Rigol", "^DP711$", SCPI_DIALECT_UNKNOWN, 0,
319fe9ce
UH		 1148 ARRAY_AND_SIZE(rigol_dp700_devopts),
1149 ARRAY_AND_SIZE(rigol_dp700_devopts_cg),
1150 ARRAY_AND_SIZE(rigol_dp711_ch),
1151 ARRAY_AND_SIZE(rigol_dp700_cg),
1152 rigol_dp700_cmd,
1153 .probe_channels = NULL,
7e66bf05
FS		 1154 .init_aquisition = NULL,
1155 .update_status = NULL,
319fe9ce 1156 },
5e7377f4 1157 { "Rigol", "^DP712$", SCPI_DIALECT_UNKNOWN, 0,
319fe9ce
UH		 1158 ARRAY_AND_SIZE(rigol_dp700_devopts),
1159 ARRAY_AND_SIZE(rigol_dp700_devopts_cg),
1160 ARRAY_AND_SIZE(rigol_dp712_ch),
1161 ARRAY_AND_SIZE(rigol_dp700_cg),
1162 rigol_dp700_cmd,
1163 .probe_channels = NULL,
7e66bf05
FS		 1164 .init_aquisition = NULL,
1165 .update_status = NULL,
319fe9ce
UH		 1166 },
1167
d4eabea8 1168 /* Rigol DP800 series */
5e7377f4 1169 { "Rigol", "^DP821A$", SCPI_DIALECT_UNKNOWN, PPS_OTP,
cfcdf576
ML		 1170 ARRAY_AND_SIZE(rigol_dp800_devopts),
1171 ARRAY_AND_SIZE(rigol_dp800_devopts_cg),
1172 ARRAY_AND_SIZE(rigol_dp821a_ch),
1173 ARRAY_AND_SIZE(rigol_dp820_cg),
91ef511d 1174 rigol_dp800_cmd,
cfcdf576 1175 .probe_channels = NULL,
7e66bf05
FS		 1176 .init_aquisition = NULL,
1177 .update_status = NULL,
cfcdf576 1178 },
5e7377f4 1179 { "Rigol", "^DP831A$", SCPI_DIALECT_UNKNOWN, PPS_OTP,
3222ee10
BV		 1180 ARRAY_AND_SIZE(rigol_dp800_devopts),
1181 ARRAY_AND_SIZE(rigol_dp800_devopts_cg),
1182 ARRAY_AND_SIZE(rigol_dp831_ch),
cfcdf576 1183 ARRAY_AND_SIZE(rigol_dp830_cg),
91ef511d 1184 rigol_dp800_cmd,
c3eadb07 1185 .probe_channels = NULL,
7e66bf05
FS		 1186 .init_aquisition = NULL,
1187 .update_status = NULL,
3222ee10 1188 },
5e7377f4 1189 { "Rigol", "^(DP832|DP832A)$", SCPI_DIALECT_UNKNOWN, PPS_OTP,
3222ee10
BV		 1190 ARRAY_AND_SIZE(rigol_dp800_devopts),
1191 ARRAY_AND_SIZE(rigol_dp800_devopts_cg),
1192 ARRAY_AND_SIZE(rigol_dp832_ch),
cfcdf576 1193 ARRAY_AND_SIZE(rigol_dp830_cg),
91ef511d 1194 rigol_dp800_cmd,
c3eadb07 1195 .probe_channels = NULL,
7e66bf05
FS		 1196 .init_aquisition = NULL,
1197 .update_status = NULL,
c3eadb07
BV		 1198 },
1199
1200 /* Philips/Fluke PM2800 series */
5e7377f4 1201 { "Philips", "^PM28[13][123]/[01234]{1,2}$", SCPI_DIALECT_PHILIPS, 0,
9d9cf1c4 1202 ARRAY_AND_SIZE(philips_pm2800_devopts),
c3eadb07
BV		 1203 ARRAY_AND_SIZE(philips_pm2800_devopts_cg),
1204 NULL, 0,
1205 NULL, 0,
91ef511d 1206 philips_pm2800_cmd,
c3eadb07 1207 philips_pm2800_probe_channels,
7e66bf05
FS		 1208 .init_aquisition = NULL,
1209 .update_status = NULL,
d4eabea8 1210 },
81eb36d6
MS		 1211
1212 /* Rohde & Schwarz HMC8043 */
5e7377f4 1213 { "Rohde&Schwarz", "HMC8043", SCPI_DIALECT_UNKNOWN, 0,
81eb36d6
MS		 1214 ARRAY_AND_SIZE(rs_hmc8043_devopts),
1215 ARRAY_AND_SIZE(rs_hmc8043_devopts_cg),
1216 ARRAY_AND_SIZE(rs_hmc8043_ch),
1217 ARRAY_AND_SIZE(rs_hmc8043_cg),
1218 rs_hmc8043_cmd,
1219 .probe_channels = NULL,
7e66bf05
FS		 1220 .init_aquisition = NULL,
1221 .update_status = NULL,
81eb36d6 1222 },
d4eabea8 1223};
d4eabea8 1224
1beccaed 1225SR_PRIV unsigned int num_pps_profiles = ARRAY_SIZE(pps_profiles);
Hardware access and backend lib