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scpi-pps: Add config keys SR_CONF_OVER_VOLTAGE_PROTECTION_ACTIVE,
[libsigrok.git] / src / hardware / scpi-pps / profiles.c
CommitLineData
d4eabea8
BV		 1/*
2 * This file is part of the libsigrok project.
3 *
4 * Copyright (C) 2014 Bert Vermeulen <bert@biot.com>
4ee1e2f3
AG		 5 * Copyright (C) 2015 Google, Inc.
6 * (Written by Alexandru Gagniuc <mrnuke@google.com> for Google, Inc.)
7e66bf05 7 * Copyright (C) 2017,2019 Frank Stettner <frank-stettner@gmx.net>
d4eabea8
BV		 8 *
9 * This program is free software: you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation, either version 3 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program. If not, see <http://www.gnu.org/licenses/>.
21 */
22
6ec6c43b 23#include <config.h>
22c18b03 24#include <string.h>
ba464a12 25#include <strings.h>
d4eabea8
BV		 26#include "protocol.h"
27
28#define CH_IDX(x) (1 << x)
6ed709fe 29#define FREQ_DC_ONLY {0, 0, 0, 0, 0}
49a468ed
FS		 30#define NO_OVP_LIMITS {0, 0, 0, 0, 0}
31#define NO_OCP_LIMITS {0, 0, 0, 0, 0}
d4eabea8 32
5c9e56c9
AG		 33/* Agilent/Keysight N5700A series */
34static const uint32_t agilent_n5700a_devopts[] = {
e91bb0a6 35 SR_CONF_CONTINUOUS,
88e4daa9
ML		 36 SR_CONF_LIMIT_SAMPLES | SR_CONF_GET | SR_CONF_SET,
37 SR_CONF_LIMIT_MSEC | SR_CONF_GET | SR_CONF_SET,
5c9e56c9
AG		 38};
39
40static const uint32_t agilent_n5700a_devopts_cg[] = {
41 SR_CONF_OVER_VOLTAGE_PROTECTION_THRESHOLD | SR_CONF_GET | SR_CONF_SET,
42 SR_CONF_OVER_CURRENT_PROTECTION_ENABLED | SR_CONF_GET | SR_CONF_SET,
43 SR_CONF_OVER_CURRENT_PROTECTION_THRESHOLD | SR_CONF_GET | SR_CONF_SET,
da005885
UH		 44 SR_CONF_VOLTAGE | SR_CONF_GET,
45 SR_CONF_VOLTAGE_TARGET | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
46 SR_CONF_CURRENT | SR_CONF_GET,
47 SR_CONF_ENABLED | SR_CONF_GET | SR_CONF_SET,
5c9e56c9
AG		 48};
49
6cc93128 50static const struct channel_group_spec agilent_n5700a_cg[] = {
f2bbcc33 51 { "1", CH_IDX(0), PPS_OVP | PPS_OCP, SR_MQFLAG_DC },
6cc93128
AG		 52};
53
8cb5affe 54static const struct channel_spec agilent_n5767a_ch[] = {
49a468ed 55 { "1", { 0, 60, 0.0072, 3, 4 }, { 0, 25, 0.003, 3, 4 }, { 0, 1500 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS },
5c9e56c9
AG		 56};
57
6cc93128 58static const struct channel_spec agilent_n5763a_ch[] = {
49a468ed 59 { "1", { 0, 12.5, 0.0015, 3, 4 }, { 0, 120, 0.0144, 3, 4 }, { 0, 1500 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS },
5c9e56c9
AG		 60};
61
62/*
63 * TODO: OVER_CURRENT_PROTECTION_ACTIVE status can be determined by the OC bit
562a3490 64 * in STAT:QUES:EVEN?, but this is not implemented.
5c9e56c9 65 */
8cb5affe 66static const struct scpi_command agilent_n5700a_cmd[] = {
5c9e56c9
AG		 67 { SCPI_CMD_REMOTE, "SYST:COMM:RLST REM" },
68 { SCPI_CMD_LOCAL, "SYST:COMM:RLST LOC" },
69 { SCPI_CMD_GET_MEAS_VOLTAGE, ":MEAS:VOLT?" },
70 { SCPI_CMD_GET_MEAS_CURRENT, "MEAS:CURR?" },
71 { SCPI_CMD_GET_VOLTAGE_TARGET, ":SOUR:VOLT?" },
72 { SCPI_CMD_SET_VOLTAGE_TARGET, ":SOUR:VOLT %.6f" },
73 { SCPI_CMD_GET_CURRENT_LIMIT, ":SOUR:CURR?" },
74 { SCPI_CMD_SET_CURRENT_LIMIT, ":SOUR:CURR %.6f" },
75 { SCPI_CMD_GET_OUTPUT_ENABLED, ":OUTP:STAT?" },
76 { SCPI_CMD_SET_OUTPUT_ENABLE, ":OUTP ON" },
77 { SCPI_CMD_SET_OUTPUT_DISABLE, ":OUTP OFF" },
78 { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_THRESHOLD, ":VOLT:PROT?" },
79 { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_THRESHOLD, ":VOLT:PROT %.6f" },
80 { SCPI_CMD_GET_OVER_CURRENT_PROTECTION_ENABLED, ":CURR:PROT:STAT?" },
81 { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_ENABLE, ":CURR:PROT:STAT ON?"},
82 { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_DISABLE, ":CURR:PROT:STAT OFF?"},
562a3490 83 /* Current limit (CC mode) and OCP are set using the same command. */
5c9e56c9
AG		 84 { SCPI_CMD_GET_OVER_CURRENT_PROTECTION_THRESHOLD, ":SOUR:CURR?" },
85 { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_THRESHOLD, ":SOUR:CURR %.6f" },
91ef511d 86 ALL_ZERO
5c9e56c9
AG		 87};
88
c3bfb959
MW		 89/* BK Precision 9130 series */
90static const uint32_t bk_9130_devopts[] = {
91 SR_CONF_CONTINUOUS,
92 SR_CONF_LIMIT_SAMPLES | SR_CONF_GET | SR_CONF_SET,
93 SR_CONF_LIMIT_MSEC | SR_CONF_GET | SR_CONF_SET,
94};
95
96static const uint32_t bk_9130_devopts_cg[] = {
97 SR_CONF_OVER_VOLTAGE_PROTECTION_THRESHOLD | SR_CONF_GET | SR_CONF_SET,
98 SR_CONF_VOLTAGE | SR_CONF_GET,
99 SR_CONF_VOLTAGE_TARGET | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
100 SR_CONF_CURRENT | SR_CONF_GET,
101 SR_CONF_CURRENT_LIMIT | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
102 SR_CONF_ENABLED | SR_CONF_GET | SR_CONF_SET,
103};
104
105static const struct channel_spec bk_9130_ch[] = {
106 { "1", { 0, 30, 0.001, 3, 3 }, { 0, 3, 0.001, 3, 3 }, { 0, 90, 0, 3, 3 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS },
107 { "2", { 0, 30, 0.001, 3, 3 }, { 0, 3, 0.001, 3, 3 }, { 0, 90, 0, 3, 3 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS },
108 { "3", { 0, 5, 0.001, 3, 3 }, { 0, 3, 0.001, 3, 3 }, { 0, 15, 0, 3, 3 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS },
109};
110
111static const struct channel_group_spec bk_9130_cg[] = {
f2bbcc33
FS		 112 { "1", CH_IDX(0), PPS_OVP, SR_MQFLAG_DC },
113 { "2", CH_IDX(1), PPS_OVP, SR_MQFLAG_DC },
114 { "3", CH_IDX(2), PPS_OVP, SR_MQFLAG_DC },
c3bfb959
MW		 115};
116
117static const struct scpi_command bk_9130_cmd[] = {
118 { SCPI_CMD_REMOTE, "SYST:REMOTE" },
119 { SCPI_CMD_LOCAL, "SYST:LOCAL" },
120 { SCPI_CMD_SELECT_CHANNEL, ":INST:NSEL %s" },
121 { SCPI_CMD_GET_MEAS_VOLTAGE, ":MEAS:VOLT?" },
122 { SCPI_CMD_GET_MEAS_CURRENT, ":MEAS:CURR?" },
123 { SCPI_CMD_GET_MEAS_POWER, ":MEAS:POWER?" },
124 { SCPI_CMD_GET_VOLTAGE_TARGET, ":SOUR:VOLT?" },
125 { SCPI_CMD_SET_VOLTAGE_TARGET, ":SOUR:VOLT %.6f" },
126 { SCPI_CMD_GET_CURRENT_LIMIT, ":SOUR:CURR?" },
127 { SCPI_CMD_SET_CURRENT_LIMIT, ":SOUR:CURR %.6f" },
128 { SCPI_CMD_GET_OUTPUT_ENABLED, ":OUTP?" },
129 { SCPI_CMD_SET_OUTPUT_ENABLE, ":OUTP 1" },
130 { SCPI_CMD_SET_OUTPUT_DISABLE, ":OUTP 0" },
131 { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_THRESHOLD, ":SOUR:VOLT:PROT?" },
132 { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_THRESHOLD, ":SOUR:VOLT:PROT %.6f" },
133 ALL_ZERO
134};
135
4ee1e2f3
AG		 136/* Chroma 61600 series AC source */
137static const uint32_t chroma_61604_devopts[] = {
e91bb0a6 138 SR_CONF_CONTINUOUS,
88e4daa9
ML		 139 SR_CONF_LIMIT_SAMPLES | SR_CONF_GET | SR_CONF_SET,
140 SR_CONF_LIMIT_MSEC | SR_CONF_GET | SR_CONF_SET,
4ee1e2f3
AG		 141};
142
143static const uint32_t chroma_61604_devopts_cg[] = {
144 SR_CONF_OVER_VOLTAGE_PROTECTION_THRESHOLD | SR_CONF_GET | SR_CONF_SET,
145 SR_CONF_OVER_CURRENT_PROTECTION_THRESHOLD | SR_CONF_GET | SR_CONF_SET,
da005885
UH		 146 SR_CONF_VOLTAGE | SR_CONF_GET,
147 SR_CONF_VOLTAGE_TARGET | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
6c0c9dd2
AG		 148 SR_CONF_OUTPUT_FREQUENCY | SR_CONF_GET,
149 SR_CONF_OUTPUT_FREQUENCY_TARGET | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
da005885
UH		 150 SR_CONF_CURRENT | SR_CONF_GET,
151 SR_CONF_ENABLED | SR_CONF_GET | SR_CONF_SET,
4ee1e2f3
AG		 152};
153
8cb5affe 154static const struct channel_spec chroma_61604_ch[] = {
49a468ed 155 { "1", { 0, 300, 0.1, 1, 1 }, { 0, 16, 0.1, 2, 2 }, { 0, 2000, 0, 1, 1 }, { 1.0, 1000.0, 0.01 }, NO_OVP_LIMITS, NO_OCP_LIMITS },
4ee1e2f3
AG		 156};
157
8cb5affe 158static const struct channel_group_spec chroma_61604_cg[] = {
f2bbcc33 159 { "1", CH_IDX(0), PPS_OVP | PPS_OCP, SR_MQFLAG_AC },
4ee1e2f3
AG		 160};
161
8cb5affe 162static const struct scpi_command chroma_61604_cmd[] = {
4ee1e2f3
AG		 163 { SCPI_CMD_REMOTE, "SYST:REM" },
164 { SCPI_CMD_LOCAL, "SYST:LOC" },
165 { SCPI_CMD_GET_MEAS_VOLTAGE, ":FETC:VOLT:ACDC?" },
6c0c9dd2 166 { SCPI_CMD_GET_MEAS_FREQUENCY, ":FETC:FREQ?" },
4ee1e2f3
AG		 167 { SCPI_CMD_GET_MEAS_CURRENT, ":FETC:CURR:AC?" },
168 { SCPI_CMD_GET_MEAS_POWER, ":FETC:POW:AC?" },
169 { SCPI_CMD_GET_VOLTAGE_TARGET, ":SOUR:VOLT:AC?" },
170 { SCPI_CMD_SET_VOLTAGE_TARGET, ":SOUR:VOLT:AC %.1f" },
6c0c9dd2
AG		 171 { SCPI_CMD_GET_FREQUENCY_TARGET, ":SOUR:FREQ?" },
172 { SCPI_CMD_SET_FREQUENCY_TARGET, ":SOUR:FREQ %.2f" },
4ee1e2f3
AG		 173 { SCPI_CMD_GET_OUTPUT_ENABLED, ":OUTP?" },
174 { SCPI_CMD_SET_OUTPUT_ENABLE, ":OUTP ON" },
175 { SCPI_CMD_SET_OUTPUT_DISABLE, ":OUTP OFF" },
176 { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_THRESHOLD, ":SOUR:VOLT:LIM:AC?" },
177 { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_THRESHOLD, ":SOUR:VOLT:LIM:AC %.1f" },
562a3490 178 /* This is not a current limit mode. It is overcurrent protection. */
4ee1e2f3
AG		 179 { SCPI_CMD_GET_OVER_CURRENT_PROTECTION_THRESHOLD, ":SOUR:CURR:LIM?" },
180 { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_THRESHOLD, ":SOUR:CURR:LIM %.2f" },
91ef511d 181 ALL_ZERO
4ee1e2f3
AG		 182};
183
5281993e 184/* Chroma 62000 series DC source */
5281993e 185static const uint32_t chroma_62000_devopts[] = {
e91bb0a6 186 SR_CONF_CONTINUOUS,
88e4daa9
ML		 187 SR_CONF_LIMIT_SAMPLES | SR_CONF_GET | SR_CONF_SET,
188 SR_CONF_LIMIT_MSEC | SR_CONF_GET | SR_CONF_SET,
5281993e
AG		 189};
190
191static const uint32_t chroma_62000_devopts_cg[] = {
192 SR_CONF_OVER_VOLTAGE_PROTECTION_THRESHOLD | SR_CONF_GET | SR_CONF_SET,
193 SR_CONF_OVER_CURRENT_PROTECTION_THRESHOLD | SR_CONF_GET | SR_CONF_SET,
194 SR_CONF_VOLTAGE | SR_CONF_GET,
195 SR_CONF_VOLTAGE_TARGET | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
196 SR_CONF_CURRENT | SR_CONF_GET,
197 SR_CONF_CURRENT_LIMIT | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
198 SR_CONF_ENABLED | SR_CONF_GET | SR_CONF_SET,
199};
200
5281993e 201static const struct channel_group_spec chroma_62000_cg[] = {
f2bbcc33 202 { "1", CH_IDX(0), PPS_OVP | PPS_OCP, SR_MQFLAG_DC },
5281993e
AG		 203};
204
205static const struct scpi_command chroma_62000_cmd[] = {
206 { SCPI_CMD_REMOTE, ":CONF:REM ON" },
207 { SCPI_CMD_LOCAL, ":CONF:REM OFF" },
208 { SCPI_CMD_BEEPER, ":CONF:BEEP?" },
209 { SCPI_CMD_BEEPER_ENABLE, ":CONF:BEEP ON" },
210 { SCPI_CMD_BEEPER_DISABLE, ":CONF:BEEP OFF" },
211 { SCPI_CMD_GET_MEAS_VOLTAGE, ":MEAS:VOLT?" },
212 { SCPI_CMD_GET_MEAS_CURRENT, ":MEAS:CURR?" },
213 { SCPI_CMD_GET_MEAS_POWER, ":MEAS:POW?" },
214 { SCPI_CMD_GET_VOLTAGE_TARGET, ":SOUR:VOLT?" },
215 { SCPI_CMD_SET_VOLTAGE_TARGET, ":SOUR:VOLT %.2f" },
216 { SCPI_CMD_GET_CURRENT_LIMIT, ":SOUR:CURR?" },
217 { SCPI_CMD_SET_CURRENT_LIMIT, ":SOUR:CURR %.6f" },
218 { SCPI_CMD_GET_OUTPUT_ENABLED, ":CONF:OUTP?" },
219 { SCPI_CMD_SET_OUTPUT_ENABLE, ":CONF:OUTP ON" },
220 { SCPI_CMD_SET_OUTPUT_DISABLE, ":CONF:OUTP OFF" },
221 { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_THRESHOLD, ":SOUR:VOLT:PROT:HIGH?" },
222 { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_THRESHOLD, ":SOUR:VOLT:PROT:HIGH %.6f" },
223 { SCPI_CMD_GET_OVER_CURRENT_PROTECTION_THRESHOLD, ":SOUR:CURR:PROT:HIGH?" },
224 { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_THRESHOLD, ":SOUR:CURR:PROT:HIGH %.6f" },
91ef511d 225 ALL_ZERO
5281993e
AG		 226};
227
9a5185c7
AG		 228static int chroma_62000p_probe_channels(struct sr_dev_inst *sdi,
229 struct sr_scpi_hw_info *hw_info,
230 struct channel_spec **channels, unsigned int *num_channels,
231 struct channel_group_spec **channel_groups,
232 unsigned int *num_channel_groups)
233{
6ed709fe 234 unsigned int volts, amps, watts;
9a5185c7
AG		 235 struct channel_spec *channel;
236
237 (void)sdi;
238
6ed709fe
AJ		 239 sscanf(hw_info->model, "620%uP-%u-%u", &watts, &volts, &amps);
240 watts *= 100;
241 sr_dbg("Found device rated for %d V, %d A and %d W", volts, amps, watts);
9a5185c7
AG		 242
243 if (volts > 600) {
244 sr_err("Probed max voltage of %u V is out of spec.", volts);
245 return SR_ERR_BUG;
246 }
247
6ed709fe 248 if (amps > 120) {
9a5185c7
AG		 249 sr_err("Probed max current of %u A is out of spec.", amps);
250 return SR_ERR_BUG;
251 }
252
6ed709fe
AJ		 253 if (watts > 5000) {
254 sr_err("Probed max power of %u W is out of spec.", watts);
255 return SR_ERR_BUG;
256 }
257
9a5185c7
AG		 258 channel = g_malloc0(sizeof(struct channel_spec));
259 channel->name = "1";
6ed709fe 260 channel->voltage[0] = channel->current[0] = channel->power[0] = 0.0;
bcee1299
UH		 261 channel->voltage[1] = volts;
262 channel->current[1] = amps;
263 channel->power[1] = watts;
9a5185c7 264 channel->voltage[2] = channel->current[2] = 0.01;
6ed709fe
AJ		 265 channel->voltage[3] = channel->voltage[4] = 3;
266 channel->current[3] = channel->current[4] = 4;
9a5185c7
AG		 267 *channels = channel;
268 *num_channels = 1;
269
270 *channel_groups = g_malloc(sizeof(struct channel_group_spec));
271 **channel_groups = chroma_62000_cg[0];
272 *num_channel_groups = 1;
273
274 return SR_OK;
275}
276
319fe9ce
UH		 277/* Rigol DP700 series */
278static const uint32_t rigol_dp700_devopts[] = {
279 SR_CONF_CONTINUOUS,
88e4daa9
ML		 280 SR_CONF_LIMIT_SAMPLES | SR_CONF_GET | SR_CONF_SET,
281 SR_CONF_LIMIT_MSEC | SR_CONF_GET | SR_CONF_SET,
319fe9ce
UH		 282};
283
284static const uint32_t rigol_dp700_devopts_cg[] = {
285 SR_CONF_REGULATION | SR_CONF_GET,
286 SR_CONF_OVER_VOLTAGE_PROTECTION_ENABLED | SR_CONF_GET | SR_CONF_SET,
287 SR_CONF_OVER_VOLTAGE_PROTECTION_ACTIVE | SR_CONF_GET,
d828b05e 288 SR_CONF_OVER_VOLTAGE_PROTECTION_THRESHOLD | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
319fe9ce
UH		 289 SR_CONF_OVER_CURRENT_PROTECTION_ENABLED | SR_CONF_GET | SR_CONF_SET,
290 SR_CONF_OVER_CURRENT_PROTECTION_ACTIVE | SR_CONF_GET,
d828b05e 291 SR_CONF_OVER_CURRENT_PROTECTION_THRESHOLD | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
319fe9ce
UH		 292 SR_CONF_VOLTAGE | SR_CONF_GET,
293 SR_CONF_VOLTAGE_TARGET | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
294 SR_CONF_CURRENT | SR_CONF_GET,
295 SR_CONF_CURRENT_LIMIT | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
296 SR_CONF_ENABLED | SR_CONF_GET | SR_CONF_SET,
297};
298
299static const struct channel_spec rigol_dp711_ch[] = {
d828b05e 300 { "1", { 0, 30, 0.01, 3, 3 }, { 0, 5, 0.01, 3, 3 }, { 0, 150, 0, 3, 3 }, FREQ_DC_ONLY, { 0.01, 33, 0.01}, { 0.01, 5.5, 0.01 } },
319fe9ce
UH		 301};
302
303static const struct channel_spec rigol_dp712_ch[] = {
d828b05e 304 { "1", { 0, 50, 0.01, 3, 3 }, { 0, 3, 0.01, 3, 3 }, { 0, 150, 0, 3, 3 }, FREQ_DC_ONLY, { 0.01, 55, 0.01}, { 0.01, 3.3, 0.01 } },
319fe9ce
UH		 305};
306
307static const struct channel_group_spec rigol_dp700_cg[] = {
f2bbcc33 308 { "1", CH_IDX(0), PPS_OVP | PPS_OCP, SR_MQFLAG_DC },
319fe9ce
UH		 309};
310
311/* Same as the DP800 series, except for the missing :SYST:OTP* commands. */
312static const struct scpi_command rigol_dp700_cmd[] = {
313 { SCPI_CMD_REMOTE, "SYST:REMOTE" },
314 { SCPI_CMD_LOCAL, "SYST:LOCAL" },
315 { SCPI_CMD_BEEPER, "SYST:BEEP:STAT?" },
316 { SCPI_CMD_BEEPER_ENABLE, "SYST:BEEP:STAT ON" },
317 { SCPI_CMD_BEEPER_DISABLE, "SYST:BEEP:STAT OFF" },
318 { SCPI_CMD_SELECT_CHANNEL, ":INST:NSEL %s" },
319 { SCPI_CMD_GET_MEAS_VOLTAGE, ":MEAS:VOLT?" },
320 { SCPI_CMD_GET_MEAS_CURRENT, ":MEAS:CURR?" },
321 { SCPI_CMD_GET_MEAS_POWER, ":MEAS:POWE?" },
322 { SCPI_CMD_GET_VOLTAGE_TARGET, ":SOUR:VOLT?" },
323 { SCPI_CMD_SET_VOLTAGE_TARGET, ":SOUR:VOLT %.6f" },
324 { SCPI_CMD_GET_CURRENT_LIMIT, ":SOUR:CURR?" },
325 { SCPI_CMD_SET_CURRENT_LIMIT, ":SOUR:CURR %.6f" },
326 { SCPI_CMD_GET_OUTPUT_ENABLED, ":OUTP?" },
327 { SCPI_CMD_SET_OUTPUT_ENABLE, ":OUTP ON" },
328 { SCPI_CMD_SET_OUTPUT_DISABLE, ":OUTP OFF" },
329 { SCPI_CMD_GET_OUTPUT_REGULATION, ":OUTP:MODE?" },
330 { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_ENABLED, ":OUTP:OVP?" },
331 { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_ENABLE, ":OUTP:OVP ON" },
332 { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_DISABLE, ":OUTP:OVP OFF" },
333 { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_ACTIVE, ":OUTP:OVP:QUES?" },
334 { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_THRESHOLD, ":OUTP:OVP:VAL?" },
335 { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_THRESHOLD, ":OUTP:OVP:VAL %.6f" },
336 { SCPI_CMD_GET_OVER_CURRENT_PROTECTION_ENABLED, ":OUTP:OCP?" },
337 { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_ENABLE, ":OUTP:OCP:STAT ON" },
338 { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_DISABLE, ":OUTP:OCP:STAT OFF" },
339 { SCPI_CMD_GET_OVER_CURRENT_PROTECTION_ACTIVE, ":OUTP:OCP:QUES?" },
340 { SCPI_CMD_GET_OVER_CURRENT_PROTECTION_THRESHOLD, ":OUTP:OCP:VAL?" },
341 { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_THRESHOLD, ":OUTP:OCP:VAL %.6f" },
342 ALL_ZERO
343};
344
d4eabea8 345/* Rigol DP800 series */
584560f1 346static const uint32_t rigol_dp800_devopts[] = {
e91bb0a6 347 SR_CONF_CONTINUOUS,
5827f61b 348 SR_CONF_OVER_TEMPERATURE_PROTECTION | SR_CONF_GET | SR_CONF_SET,
88e4daa9
ML		 349 SR_CONF_LIMIT_SAMPLES | SR_CONF_GET | SR_CONF_SET,
350 SR_CONF_LIMIT_MSEC | SR_CONF_GET | SR_CONF_SET,
d4eabea8
BV		 351};
352
584560f1 353static const uint32_t rigol_dp800_devopts_cg[] = {
7a0b98b5 354 SR_CONF_REGULATION | SR_CONF_GET,
5827f61b
BV		 355 SR_CONF_OVER_VOLTAGE_PROTECTION_ENABLED | SR_CONF_GET | SR_CONF_SET,
356 SR_CONF_OVER_VOLTAGE_PROTECTION_ACTIVE | SR_CONF_GET,
357 SR_CONF_OVER_VOLTAGE_PROTECTION_THRESHOLD | SR_CONF_GET | SR_CONF_SET,
358 SR_CONF_OVER_CURRENT_PROTECTION_ENABLED | SR_CONF_GET | SR_CONF_SET,
359 SR_CONF_OVER_CURRENT_PROTECTION_ACTIVE | SR_CONF_GET,
360 SR_CONF_OVER_CURRENT_PROTECTION_THRESHOLD | SR_CONF_GET | SR_CONF_SET,
7a0b98b5
AJ		 361 SR_CONF_VOLTAGE | SR_CONF_GET,
362 SR_CONF_VOLTAGE_TARGET | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
363 SR_CONF_CURRENT | SR_CONF_GET,
364 SR_CONF_CURRENT_LIMIT | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
365 SR_CONF_ENABLED | SR_CONF_GET | SR_CONF_SET,
d4eabea8
BV		 366};
367
8cb5affe 368static const struct channel_spec rigol_dp821a_ch[] = {
49a468ed
FS		 369 { "1", { 0, 60, 0.001, 3, 3 }, { 0, 1, 0.0001, 4, 4 }, { 0, 60, 0, 3, 4 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS },
370 { "2", { 0, 8, 0.001, 3, 3 }, { 0, 10, 0.001, 3, 3 }, { 0, 80, 0, 3, 3 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS },
cfcdf576
ML		 371};
372
8cb5affe 373static const struct channel_spec rigol_dp831_ch[] = {
49a468ed
FS		 374 { "1", { 0, 8, 0.001, 3, 4 }, { 0, 5, 0.0003, 3, 4 }, { 0, 40, 0, 3, 4 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS },
375 { "2", { 0, 30, 0.001, 3, 4 }, { 0, 2, 0.0001, 3, 4 }, { 0, 60, 0, 3, 4 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS },
376 { "3", { 0, -30, 0.001, 3, 4 }, { 0, 2, 0.0001, 3, 4 }, { 0, 60, 0, 3, 4 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS },
d4eabea8
BV		 377};
378
8cb5affe 379static const struct channel_spec rigol_dp832_ch[] = {
49a468ed
FS		 380 { "1", { 0, 30, 0.001, 3, 4 }, { 0, 3, 0.001, 3, 4 }, { 0, 90, 0, 3, 4 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS },
381 { "2", { 0, 30, 0.001, 3, 4 }, { 0, 3, 0.001, 3, 4 }, { 0, 90, 0, 3, 4 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS },
382 { "3", { 0, 5, 0.001, 3, 4 }, { 0, 3, 0.001, 3, 4 }, { 0, 90, 0, 3, 4 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS },
3222ee10
BV		 383};
384
8cb5affe 385static const struct channel_group_spec rigol_dp820_cg[] = {
f2bbcc33
FS		 386 { "1", CH_IDX(0), PPS_OVP | PPS_OCP, SR_MQFLAG_DC },
387 { "2", CH_IDX(1), PPS_OVP | PPS_OCP, SR_MQFLAG_DC },
cfcdf576
ML		 388};
389
8cb5affe 390static const struct channel_group_spec rigol_dp830_cg[] = {
f2bbcc33
FS		 391 { "1", CH_IDX(0), PPS_OVP | PPS_OCP, SR_MQFLAG_DC },
392 { "2", CH_IDX(1), PPS_OVP | PPS_OCP, SR_MQFLAG_DC },
393 { "3", CH_IDX(2), PPS_OVP | PPS_OCP, SR_MQFLAG_DC },
d4eabea8
BV		 394};
395
8cb5affe 396static const struct scpi_command rigol_dp800_cmd[] = {
60475cd7
BV		 397 { SCPI_CMD_REMOTE, "SYST:REMOTE" },
398 { SCPI_CMD_LOCAL, "SYST:LOCAL" },
ee2860ee
BV		 399 { SCPI_CMD_BEEPER, "SYST:BEEP:STAT?" },
400 { SCPI_CMD_BEEPER_ENABLE, "SYST:BEEP:STAT ON" },
401 { SCPI_CMD_BEEPER_DISABLE, "SYST:BEEP:STAT OFF" },
60475cd7
BV		 402 { SCPI_CMD_SELECT_CHANNEL, ":INST:NSEL %s" },
403 { SCPI_CMD_GET_MEAS_VOLTAGE, ":MEAS:VOLT?" },
404 { SCPI_CMD_GET_MEAS_CURRENT, ":MEAS:CURR?" },
405 { SCPI_CMD_GET_MEAS_POWER, ":MEAS:POWE?" },
406 { SCPI_CMD_GET_VOLTAGE_TARGET, ":SOUR:VOLT?" },
407 { SCPI_CMD_SET_VOLTAGE_TARGET, ":SOUR:VOLT %.6f" },
408 { SCPI_CMD_GET_CURRENT_LIMIT, ":SOUR:CURR?" },
409 { SCPI_CMD_SET_CURRENT_LIMIT, ":SOUR:CURR %.6f" },
410 { SCPI_CMD_GET_OUTPUT_ENABLED, ":OUTP?" },
411 { SCPI_CMD_SET_OUTPUT_ENABLE, ":OUTP ON" },
412 { SCPI_CMD_SET_OUTPUT_DISABLE, ":OUTP OFF" },
413 { SCPI_CMD_GET_OUTPUT_REGULATION, ":OUTP:MODE?" },
d4eabea8 414 { SCPI_CMD_GET_OVER_TEMPERATURE_PROTECTION, ":SYST:OTP?" },
53a81803
BV		 415 { SCPI_CMD_SET_OVER_TEMPERATURE_PROTECTION_ENABLE, ":SYST:OTP ON" },
416 { SCPI_CMD_SET_OVER_TEMPERATURE_PROTECTION_DISABLE, ":SYST:OTP OFF" },
60475cd7
BV		 417 { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_ENABLED, ":OUTP:OVP?" },
418 { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_ENABLE, ":OUTP:OVP ON" },
419 { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_DISABLE, ":OUTP:OVP OFF" },
420 { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_ACTIVE, ":OUTP:OVP:QUES?" },
421 { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_THRESHOLD, ":OUTP:OVP:VAL?" },
422 { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_THRESHOLD, ":OUTP:OVP:VAL %.6f" },
423 { SCPI_CMD_GET_OVER_CURRENT_PROTECTION_ENABLED, ":OUTP:OCP?" },
424 { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_ENABLE, ":OUTP:OCP:STAT ON" },
425 { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_DISABLE, ":OUTP:OCP:STAT OFF" },
426 { SCPI_CMD_GET_OVER_CURRENT_PROTECTION_ACTIVE, ":OUTP:OCP:QUES?" },
427 { SCPI_CMD_GET_OVER_CURRENT_PROTECTION_THRESHOLD, ":OUTP:OCP:VAL?" },
428 { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_THRESHOLD, ":OUTP:OCP:VAL %.6f" },
91ef511d 429 ALL_ZERO
d4eabea8
BV		 430};
431
dbc519f7 432/* HP 663xA series */
e76a3575
AG		 433static const uint32_t hp_6630a_devopts[] = {
434 SR_CONF_CONTINUOUS,
88e4daa9
ML		 435 SR_CONF_LIMIT_SAMPLES | SR_CONF_GET | SR_CONF_SET,
436 SR_CONF_LIMIT_MSEC | SR_CONF_GET | SR_CONF_SET,
7c517d02
FS		 437};
438
439static const uint32_t hp_6630a_devopts_cg[] = {
e76a3575
AG		 440 SR_CONF_ENABLED | SR_CONF_SET,
441 SR_CONF_VOLTAGE | SR_CONF_GET,
442 SR_CONF_CURRENT | SR_CONF_GET,
443 SR_CONF_VOLTAGE_TARGET | SR_CONF_SET | SR_CONF_LIST,
444 SR_CONF_CURRENT_LIMIT | SR_CONF_SET | SR_CONF_LIST,
f083ae63 445 SR_CONF_OVER_VOLTAGE_PROTECTION_ACTIVE | SR_CONF_GET,
49a468ed 446 SR_CONF_OVER_VOLTAGE_PROTECTION_THRESHOLD | SR_CONF_SET | SR_CONF_LIST,
e76a3575 447 SR_CONF_OVER_CURRENT_PROTECTION_ENABLED | SR_CONF_SET,
f083ae63
FS		 448 SR_CONF_OVER_CURRENT_PROTECTION_ACTIVE | SR_CONF_GET,
449 SR_CONF_OVER_TEMPERATURE_PROTECTION_ACTIVE | SR_CONF_GET,
0ad7074c 450 SR_CONF_REGULATION | SR_CONF_GET,
e76a3575
AG		 451};
452
dbc519f7
FS		 453static const struct channel_spec hp_6633a_ch[] = {
454 { "1", { 0, 51.188, 0.0125, 3, 4 }, { 0, 2.0475, 0.0005, 4, 5 }, { 0, 104.80743 }, FREQ_DC_ONLY, { 0, 55, 0.25 }, NO_OCP_LIMITS },
455};
456
457static const struct channel_group_spec hp_6630a_cg[] = {
458 { "1", CH_IDX(0), PPS_OVP | PPS_OCP, SR_MQFLAG_DC },
459};
460
461static const struct scpi_command hp_6630a_cmd[] = {
462 { SCPI_CMD_SET_OUTPUT_ENABLE, "OUT 1" },
463 { SCPI_CMD_SET_OUTPUT_DISABLE, "OUT 0" },
464 { SCPI_CMD_GET_MEAS_VOLTAGE, "VOUT?" },
465 { SCPI_CMD_GET_MEAS_CURRENT, "IOUT?" },
466 { SCPI_CMD_SET_VOLTAGE_TARGET, "VSET %.4f" },
467 { SCPI_CMD_SET_CURRENT_LIMIT, "ISET %.4f" },
f083ae63
FS		 468 { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_ACTIVE, "STS?" },
469 { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_THRESHOLD, "OVSET %.4f" },
dbc519f7
FS		 470 { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_ENABLE, "OCP 1" },
471 { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_DISABLE, "OCP 0" },
f083ae63
FS		 472 { SCPI_CMD_GET_OVER_CURRENT_PROTECTION_ACTIVE, "STS?" },
473 { SCPI_CMD_GET_OVER_TEMPERATURE_PROTECTION_ACTIVE, "STS?" },
0ad7074c 474 { SCPI_CMD_GET_OUTPUT_REGULATION, "STS?" },
dbc519f7
FS		 475 ALL_ZERO
476};
477
478/* HP 663xB series */
a61c8cce 479static const uint32_t hp_6630b_devopts[] = {
e91bb0a6 480 SR_CONF_CONTINUOUS,
88e4daa9
ML		 481 SR_CONF_LIMIT_SAMPLES | SR_CONF_GET | SR_CONF_SET,
482 SR_CONF_LIMIT_MSEC | SR_CONF_GET | SR_CONF_SET,
7c517d02
FS		 483};
484
a61c8cce 485static const uint32_t hp_6630b_devopts_cg[] = {
7a0b98b5
AJ		 486 SR_CONF_ENABLED | SR_CONF_GET | SR_CONF_SET,
487 SR_CONF_VOLTAGE | SR_CONF_GET,
488 SR_CONF_CURRENT | SR_CONF_GET,
489 SR_CONF_VOLTAGE_TARGET | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
490 SR_CONF_CURRENT_LIMIT | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
8b5eadf4 491 SR_CONF_OVER_VOLTAGE_PROTECTION_ACTIVE | SR_CONF_GET,
49a468ed 492 SR_CONF_OVER_VOLTAGE_PROTECTION_THRESHOLD | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
7e381bfc 493 SR_CONF_OVER_CURRENT_PROTECTION_ENABLED | SR_CONF_GET | SR_CONF_SET,
8b5eadf4
FS		 494 SR_CONF_OVER_CURRENT_PROTECTION_ACTIVE | SR_CONF_GET,
495 SR_CONF_OVER_TEMPERATURE_PROTECTION_ACTIVE | SR_CONF_GET,
43ff1110 496 SR_CONF_REGULATION | SR_CONF_GET,
bc4a2a46
BV		 497};
498
a61c8cce 499static const struct channel_spec hp_6631b_ch[] = {
49a468ed 500 { "1", { 0, 8.19, 0.002, 3, 4 }, { 0, 10.237, 0.00263, 4, 5 }, { 0, 83.84103 }, FREQ_DC_ONLY, { 0, 12, 0.06 }, NO_OCP_LIMITS },
a61c8cce
FS		 501};
502
8cb5affe 503static const struct channel_spec hp_6632b_ch[] = {
49a468ed 504 { "1", { 0, 20.475, 0.005, 3, 4 }, { 0, 5.1188, 0.00132, 4, 5 }, { 0, 104.80743 }, FREQ_DC_ONLY, { 0, 22, 0.1 }, NO_OCP_LIMITS },
bc4a2a46
BV		 505};
506
a61c8cce 507static const struct channel_spec hp_66332a_ch[] = {
49a468ed 508 { "1", { 0, 20.475, 0.005, 3, 4 }, { 0, 5.1188, 0.00132, 4, 5 }, { 0, 104.80743 }, FREQ_DC_ONLY, { 0, 22, 0.1 }, NO_OCP_LIMITS },
a61c8cce
FS		 509};
510
511static const struct channel_spec hp_6633b_ch[] = {
49a468ed 512 { "1", { 0, 51.188, 0.0125, 3, 4 }, { 0, 2.0475, 0.000526, 4, 5 }, { 0, 104.80743 }, FREQ_DC_ONLY, { 0, 55, 0.25 }, NO_OCP_LIMITS },
a61c8cce
FS		 513};
514
515static const struct channel_spec hp_6634b_ch[] = {
49a468ed 516 { "1", { 0, 102.38, 0.025, 3, 4 }, { 0, 1.0238, 0.000263, 4, 5 }, { 0, 104.81664 }, FREQ_DC_ONLY, { 0, 110, 0.5 }, NO_OCP_LIMITS },
a61c8cce
FS		 517};
518
dbc519f7 519static const struct channel_group_spec hp_6630b_cg[] = {
3d1aa50f 520 { "1", CH_IDX(0), PPS_OVP | PPS_OCP, SR_MQFLAG_DC },
bc4a2a46
BV		 521};
522
a61c8cce 523static const struct scpi_command hp_6630b_cmd[] = {
7e381bfc
FS		 524 { SCPI_CMD_REMOTE, "SYST:REM" },
525 { SCPI_CMD_LOCAL, "SYST:LOC" },
bc4a2a46 526 { SCPI_CMD_GET_OUTPUT_ENABLED, "OUTP:STAT?" },
53a81803
BV		 527 { SCPI_CMD_SET_OUTPUT_ENABLE, "OUTP:STAT ON" },
528 { SCPI_CMD_SET_OUTPUT_DISABLE, "OUTP:STAT OFF" },
bc4a2a46
BV		 529 { SCPI_CMD_GET_MEAS_VOLTAGE, ":MEAS:VOLT?" },
530 { SCPI_CMD_GET_MEAS_CURRENT, ":MEAS:CURR?" },
ca95e90f
BV		 531 { SCPI_CMD_GET_VOLTAGE_TARGET, ":SOUR:VOLT?" },
532 { SCPI_CMD_SET_VOLTAGE_TARGET, ":SOUR:VOLT %.6f" },
533 { SCPI_CMD_GET_CURRENT_LIMIT, ":SOUR:CURR?" },
534 { SCPI_CMD_SET_CURRENT_LIMIT, ":SOUR:CURR %.6f" },
7e381bfc
FS		 535 { SCPI_CMD_GET_OVER_CURRENT_PROTECTION_ENABLED, ":CURR:PROT:STAT?" },
536 { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_ENABLE, ":CURR:PROT:STAT 1" },
537 { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_DISABLE, ":CURR:PROT:STAT 0" },
8b5eadf4
FS		 538 { SCPI_CMD_GET_OVER_CURRENT_PROTECTION_ACTIVE, "STAT:QUES:COND?" },
539 { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_ACTIVE, "STAT:QUES:COND?" },
7e381bfc
FS		 540 { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_THRESHOLD, ":VOLT:PROT?" },
541 { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_THRESHOLD, ":VOLT:PROT %.6f" },
8b5eadf4 542 { SCPI_CMD_GET_OVER_TEMPERATURE_PROTECTION_ACTIVE, "STAT:QUES:COND?" },
43ff1110 543 { SCPI_CMD_GET_OUTPUT_REGULATION, "STAT:OPER:COND?" },
91ef511d 544 ALL_ZERO
bc4a2a46
BV		 545};
546
fe4bb774
FS		 547static int hp_6630b_init_aquisition(const struct sr_dev_inst *sdi)
548{
549 struct sr_scpi_dev_inst *scpi;
550 int ret;
551
552 scpi = sdi->conn;
553
554 /*
555 * Monitor CV (256), CC+ (1024) and CC- (2048) bits of the
556 * Operational Status Register.
557 * Use both positive and negative transitions of the status bits.
558 */
559 ret = sr_scpi_send(scpi, "STAT:OPER:PTR 3328;NTR 3328;ENAB 3328");
560 if (ret != SR_OK)
561 return ret;
562
563 /*
564 * Monitor OVP (1), OCP (2), OTP (16) and Unreg (1024) bits of the
565 * Questionable Status Register.
566 * Use both positive and negative transitions of the status bits.
567 */
568 ret = sr_scpi_send(scpi, "STAT:QUES:PTR 1043;NTR 1043;ENAB 1043");
569 if (ret != SR_OK)
570 return ret;
571
572 /*
573 * Service Request Enable Register set for Operational Status Register
574 * bits (128) and Questionable Status Register bits (8).
575 * This masks the Status Register generating a SRQ/RQS. Not implemented yet!
576 */
577 /*
578 ret = sr_scpi_send(scpi, "*SRE 136");
579 if (ret != SR_OK)
580 return ret;
581 */
582
583 return SR_OK;
584}
585
586static int hp_6630b_update_status(const struct sr_dev_inst *sdi)
587{
588 struct sr_scpi_dev_inst *scpi;
589 int ret;
590 int stb;
591 int ques_even, ques_cond;
592 int oper_even, oper_cond;
593 gboolean output_enabled;
594 gboolean unreg, cv, cc_pos, cc_neg;
595 gboolean regulation_changed;
596 char *regulation;
597
598 scpi = sdi->conn;
599
600 unreg = FALSE;
601 cv = FALSE;
602 cc_pos = FALSE;
603 cc_neg = FALSE;
604 regulation_changed = FALSE;
605
606 /*
607 * Use SPoll when SCPI uses GPIB as transport layer.
608 * SPoll is approx. twice as fast as a normal GPIB write + read would be!
609 */
610#ifdef HAVE_LIBGPIB
611 char spoll_buf;
612
613 if (scpi->transport == SCPI_TRANSPORT_LIBGPIB) {
614 ret = sr_scpi_gpib_spoll(scpi, &spoll_buf);
615 if (ret != SR_OK)
616 return ret;
617 stb = (uint8_t)spoll_buf;
618 }
619 else {
620#endif
621 ret = sr_scpi_get_int(scpi, "*STB?", &stb);
622 if (ret != SR_OK)
623 return ret;
624#ifdef HAVE_LIBGPIB
625 }
626#endif
627
628 /* Questionable status summary bit */
629 if (stb & (1 << 3)) {
630 /* Read the event register to clear it! */
631 ret = sr_scpi_get_int(scpi, "STAT:QUES:EVEN?", &ques_even);
632 if (ret != SR_OK)
633 return ret;
634 /* Now get the values. */
635 ret = sr_scpi_get_int(scpi, "STAT:QUES:COND?", &ques_cond);
636 if (ret != SR_OK)
637 return ret;
638
639 /* OVP */
640 if (ques_even & (1 << 0))
641 sr_session_send_meta(sdi, SR_CONF_OVER_VOLTAGE_PROTECTION_ACTIVE,
642 g_variant_new_boolean(ques_cond & (1 << 0)));
643
644 /* OCP */
645 if (ques_even & (1 << 1))
646 sr_session_send_meta(sdi, SR_CONF_OVER_CURRENT_PROTECTION_ACTIVE,
647 g_variant_new_boolean(ques_cond & (1 << 1)));
648
649 /* OTP */
650 if (ques_even & (1 << 4))
651 sr_session_send_meta(sdi, SR_CONF_OVER_TEMPERATURE_PROTECTION_ACTIVE,
652 g_variant_new_boolean(ques_cond & (1 << 4)));
653
654 /* UNREG */
655 unreg = (ques_cond & (1 << 10));
656 regulation_changed = (ques_even & (1 << 10)) | regulation_changed;
657
658 /*
659 * Check if output state has changed, due to one of the
660 * questionable states changed.
661 * NOTE: The output state is send even if it hasn't changed, but that
662 * only happends rarely.
663 */
664 ret = sr_scpi_get_bool(scpi, "OUTP:STAT?", &output_enabled);
665 if (ret != SR_OK)
666 return ret;
667 sr_session_send_meta(sdi, SR_CONF_ENABLED,
668 g_variant_new_boolean(output_enabled));
669 }
670
671 /* Operation status summary bit */
672 if (stb & (1 << 7)) {
673 /* Read the event register to clear it! */
674 ret = sr_scpi_get_int(scpi, "STAT:OPER:EVEN?", &oper_even);
675 if (ret != SR_OK)
676 return ret;
677 /* Now get the values. */
678 ret = sr_scpi_get_int(scpi, "STAT:OPER:COND?", &oper_cond);
679 if (ret != SR_OK)
680 return ret;
681
682 /* CV */
683 cv = (oper_cond & (1 << 8));
684 regulation_changed = (oper_even & (1 << 8)) | regulation_changed;
685 /* CC+ */
686 cc_pos = (oper_cond & (1 << 10));
687 regulation_changed = (oper_even & (1 << 10)) | regulation_changed;
688 /* CC- */
689 cc_neg = (oper_cond & (1 << 11));
690 regulation_changed = (oper_even & (1 << 11)) | regulation_changed;
691 }
692
693 if (regulation_changed) {
694 if (cv && !cc_pos && !cc_neg &&!unreg)
695 regulation = "CV";
696 else if (cc_pos && !cv && !cc_neg && !unreg)
697 regulation = "CC";
698 else if (cc_neg && !cv && !cc_pos && !unreg)
699 regulation = "CC-";
700 else if (unreg && !cv && !cc_pos && !cc_neg)
701 regulation = "UR";
702 else if (!cv && !cc_pos && !cc_neg &&!unreg)
703 /* This happends in case of OCP active */
704 regulation = "";
705 else {
706 /* This happends from time to time (CV and CC+ active). */
707 sr_dbg("Undefined regulation for HP 66xxB "
708 "(CV=%i, CC+=%i, CC-=%i, UR=%i).",
709 cv, cc_pos, cc_neg, unreg);
710 return FALSE;
711 }
712 sr_session_send_meta(sdi, SR_CONF_REGULATION,
713 g_variant_new_string(regulation));
714 }
715
716 return SR_OK;
717}
718
c3eadb07 719/* Philips/Fluke PM2800 series */
9d9cf1c4 720static const uint32_t philips_pm2800_devopts[] = {
e91bb0a6 721 SR_CONF_CONTINUOUS,
88e4daa9
ML		 722 SR_CONF_LIMIT_SAMPLES | SR_CONF_GET | SR_CONF_SET,
723 SR_CONF_LIMIT_MSEC | SR_CONF_GET | SR_CONF_SET,
9d9cf1c4
BV		 724};
725
c3eadb07 726static const uint32_t philips_pm2800_devopts_cg[] = {
7a0b98b5
AJ		 727 SR_CONF_ENABLED | SR_CONF_GET | SR_CONF_SET,
728 SR_CONF_VOLTAGE | SR_CONF_GET,
729 SR_CONF_VOLTAGE_TARGET | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
730 SR_CONF_CURRENT | SR_CONF_GET,
731 SR_CONF_CURRENT_LIMIT | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
c3eadb07
BV		 732 SR_CONF_OVER_VOLTAGE_PROTECTION_ACTIVE | SR_CONF_GET,
733 SR_CONF_OVER_VOLTAGE_PROTECTION_THRESHOLD | SR_CONF_GET | SR_CONF_SET,
734 SR_CONF_OVER_CURRENT_PROTECTION_ENABLED | SR_CONF_GET | SR_CONF_SET,
735 SR_CONF_OVER_CURRENT_PROTECTION_ACTIVE | SR_CONF_GET,
7a0b98b5 736 SR_CONF_REGULATION | SR_CONF_GET,
c3eadb07
BV		 737};
738
739enum philips_pm2800_modules {
740 PM2800_MOD_30V_10A = 1,
741 PM2800_MOD_60V_5A,
742 PM2800_MOD_60V_10A,
743 PM2800_MOD_8V_15A,
744 PM2800_MOD_60V_2A,
745 PM2800_MOD_120V_1A,
746};
747
329733d9 748static const struct philips_pm2800_module_spec {
c3eadb07 749 /* Min, max, programming resolution. */
bcee1299
UH		 750 double voltage[5];
751 double current[5];
752 double power[5];
c3eadb07
BV		 753} philips_pm2800_module_specs[] = {
754 /* Autoranging modules. */
6ed709fe
AJ		 755 [PM2800_MOD_30V_10A] = { { 0, 30, 0.0075, 2, 4 }, { 0, 10, 0.0025, 2, 4 }, { 0, 60 } },
756 [PM2800_MOD_60V_5A] = { { 0, 60, 0.015, 2, 3 }, { 0, 5, 0.00125, 2, 5 }, { 0, 60 } },
757 [PM2800_MOD_60V_10A] = { { 0, 60, 0.015, 2, 3 }, { 0, 10, 0.0025, 2, 5 }, { 0, 120 } },
c3eadb07 758 /* Linear modules. */
6ed709fe
AJ		 759 [PM2800_MOD_8V_15A] = { { 0, 8, 0.002, 3, 3 }, { -15, 15, 0.00375, 3, 5 }, { 0, 120 } },
760 [PM2800_MOD_60V_2A] = { { 0, 60, 0.015, 2, 3 }, { -2, 2, 0.0005, 3, 4 }, { 0, 120 } },
761 [PM2800_MOD_120V_1A] = { { 0, 120, 0.030, 2, 2 }, { -1, 1, 0.00025, 3, 5 }, { 0, 120 } },
c3eadb07
BV		 762};
763
329733d9 764static const struct philips_pm2800_model {
c3eadb07
BV		 765 unsigned int chassis;
766 unsigned int num_modules;
767 unsigned int set;
768 unsigned int modules[3];
769} philips_pm2800_matrix[] = {
770 /* Autoranging chassis. */
771 { 1, 1, 0, { PM2800_MOD_30V_10A, 0, 0 } },
772 { 1, 1, 1, { PM2800_MOD_60V_5A, 0, 0 } },
773 { 1, 2, 0, { PM2800_MOD_30V_10A, PM2800_MOD_30V_10A, 0 } },
774 { 1, 2, 1, { PM2800_MOD_60V_5A, PM2800_MOD_60V_5A, 0 } },
775 { 1, 2, 2, { PM2800_MOD_30V_10A, PM2800_MOD_60V_5A, 0 } },
776 { 1, 2, 3, { PM2800_MOD_30V_10A, PM2800_MOD_60V_10A, 0 } },
777 { 1, 2, 4, { PM2800_MOD_60V_5A, PM2800_MOD_60V_10A, 0 } },
778 { 1, 3, 0, { PM2800_MOD_30V_10A, PM2800_MOD_30V_10A, PM2800_MOD_30V_10A } },
779 { 1, 3, 1, { PM2800_MOD_60V_5A, PM2800_MOD_60V_5A, PM2800_MOD_60V_5A } },
780 { 1, 3, 2, { PM2800_MOD_30V_10A, PM2800_MOD_30V_10A, PM2800_MOD_60V_5A } },
781 { 1, 3, 3, { PM2800_MOD_30V_10A, PM2800_MOD_60V_5A, PM2800_MOD_60V_5A } },
782 /* Linear chassis. */
783 { 3, 1, 0, { PM2800_MOD_60V_2A, 0, 0 } },
784 { 3, 1, 1, { PM2800_MOD_120V_1A, 0, 0 } },
785 { 3, 1, 2, { PM2800_MOD_8V_15A, 0, 0 } },
786 { 3, 2, 0, { PM2800_MOD_60V_2A, 0, 0 } },
787 { 3, 2, 1, { PM2800_MOD_120V_1A, 0, 0 } },
788 { 3, 2, 2, { PM2800_MOD_60V_2A, PM2800_MOD_120V_1A, 0 } },
789 { 3, 2, 3, { PM2800_MOD_8V_15A, PM2800_MOD_8V_15A, 0 } },
790};
791
329733d9 792static const char *philips_pm2800_names[] = { "1", "2", "3" };
c3eadb07
BV		 793
794static int philips_pm2800_probe_channels(struct sr_dev_inst *sdi,
795 struct sr_scpi_hw_info *hw_info,
796 struct channel_spec **channels, unsigned int *num_channels,
797 struct channel_group_spec **channel_groups, unsigned int *num_channel_groups)
798{
329733d9
UH		 799 const struct philips_pm2800_model *model;
800 const struct philips_pm2800_module_spec *spec;
c3eadb07
BV		 801 unsigned int chassis, num_modules, set, module, m, i;
802
803 (void)sdi;
804
805 /*
806 * The model number as reported by *IDN? looks like e.g. PM2813/11,
807 * Where "PM28" is fixed, followed by the chassis code (1 = autoranging,
808 * 3 = linear series) and the number of modules: 1-3 for autoranging,
809 * 1-2 for linear.
810 * After the slash, the first digit denotes the module set. The
811 * digit after that denotes front (5) or rear (1) binding posts.
812 */
813 chassis = hw_info->model[4] - 0x30;
814 num_modules = hw_info->model[5] - 0x30;
815 set = hw_info->model[7] - 0x30;
816 for (m = 0; m < ARRAY_SIZE(philips_pm2800_matrix); m++) {
817 model = &philips_pm2800_matrix[m];
818 if (model->chassis == chassis && model->num_modules == num_modules
819 && model->set == set)
820 break;
821 }
822 if (m == ARRAY_SIZE(philips_pm2800_matrix)) {
823 sr_dbg("Model %s not found in matrix.", hw_info->model);
824 return SR_ERR;
825 }
826
827 sr_dbg("Found %d output channel%s:", num_modules, num_modules > 1 ? "s" : "");
828 *channels = g_malloc0(sizeof(struct channel_spec) * num_modules);
829 *channel_groups = g_malloc0(sizeof(struct channel_group_spec) * num_modules);
830 for (i = 0; i < num_modules; i++) {
831 module = model->modules[i];
832 spec = &philips_pm2800_module_specs[module];
6ed709fe 833 sr_dbg("output %d: %.0f - %.0fV, %.0f - %.0fA, %.0f - %.0fW", i + 1,
c3eadb07 834 spec->voltage[0], spec->voltage[1],
6ed709fe 835 spec->current[0], spec->current[1],
d9251a2c 836 spec->power[0], spec->power[1]);
329733d9 837 (*channels)[i].name = (char *)philips_pm2800_names[i];
bcee1299 838 memcpy(&((*channels)[i].voltage), spec, sizeof(double) * 15);
329733d9 839 (*channel_groups)[i].name = (char *)philips_pm2800_names[i];
c3eadb07
BV		 840 (*channel_groups)[i].channel_index_mask = 1 << i;
841 (*channel_groups)[i].features = PPS_OTP | PPS_OVP | PPS_OCP;
f2bbcc33 842 (*channel_groups)[i].mqflags = SR_MQFLAG_DC;
c3eadb07
BV		 843 }
844 *num_channels = *num_channel_groups = num_modules;
845
846 return SR_OK;
847}
848
8cb5affe 849static const struct scpi_command philips_pm2800_cmd[] = {
c3eadb07
BV		 850 { SCPI_CMD_SELECT_CHANNEL, ":INST:NSEL %s" },
851 { SCPI_CMD_GET_MEAS_VOLTAGE, ":MEAS:VOLT?" },
852 { SCPI_CMD_GET_MEAS_CURRENT, ":MEAS:CURR?" },
853 { SCPI_CMD_GET_VOLTAGE_TARGET, ":SOUR:VOLT?" },
854 { SCPI_CMD_SET_VOLTAGE_TARGET, ":SOUR:VOLT %.6f" },
855 { SCPI_CMD_GET_CURRENT_LIMIT, ":SOUR:CURR?" },
856 { SCPI_CMD_SET_CURRENT_LIMIT, ":SOUR:CURR %.6f" },
857 { SCPI_CMD_GET_OUTPUT_ENABLED, ":OUTP?" },
858 { SCPI_CMD_SET_OUTPUT_ENABLE, ":OUTP ON" },
859 { SCPI_CMD_SET_OUTPUT_DISABLE, ":OUTP OFF" },
860 { SCPI_CMD_GET_OUTPUT_REGULATION, ":SOUR:FUNC:MODE?" },
861 { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_ACTIVE, ":SOUR:VOLT:PROT:TRIP?" },
862 { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_THRESHOLD, ":SOUR:VOLT:PROT:LEV?" },
863 { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_THRESHOLD, ":SOUR:VOLT:PROT:LEV %.6f" },
864 { SCPI_CMD_GET_OVER_CURRENT_PROTECTION_ENABLED, ":SOUR:CURR:PROT:STAT?" },
865 { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_ENABLE, ":SOUR:CURR:PROT:STAT ON" },
866 { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_DISABLE, ":SOUR:CURR:PROT:STAT OFF" },
867 { SCPI_CMD_GET_OVER_CURRENT_PROTECTION_ACTIVE, ":SOUR:CURR:PROT:TRIP?" },
91ef511d 868 ALL_ZERO
c3eadb07
BV		 869};
870
81eb36d6
MS		 871static const uint32_t rs_hmc8043_devopts[] = {
872 SR_CONF_CONTINUOUS,
88e4daa9
ML		 873 SR_CONF_LIMIT_SAMPLES | SR_CONF_GET | SR_CONF_SET,
874 SR_CONF_LIMIT_MSEC | SR_CONF_GET | SR_CONF_SET,
81eb36d6
MS		 875};
876
877static const uint32_t rs_hmc8043_devopts_cg[] = {
878 SR_CONF_OVER_VOLTAGE_PROTECTION_ENABLED | SR_CONF_GET | SR_CONF_SET,
879 SR_CONF_OVER_VOLTAGE_PROTECTION_ACTIVE | SR_CONF_GET,
880 SR_CONF_OVER_VOLTAGE_PROTECTION_THRESHOLD | SR_CONF_GET | SR_CONF_SET,
881 SR_CONF_VOLTAGE | SR_CONF_GET,
882 SR_CONF_VOLTAGE_TARGET | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
883 SR_CONF_CURRENT | SR_CONF_GET,
884 SR_CONF_CURRENT_LIMIT | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
885 SR_CONF_ENABLED | SR_CONF_GET | SR_CONF_SET,
886};
887
888static const struct channel_spec rs_hmc8043_ch[] = {
49a468ed
FS		 889 { "1", { 0, 32.050, 0.001, 3, 4 }, { 0.001, 3, 0.001, 3, 4 }, { 0, 0, 0, 0, 4 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS },
890 { "2", { 0, 32.050, 0.001, 3, 4 }, { 0.001, 3, 0.001, 3, 4 }, { 0, 0, 0, 0, 4 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS },
891 { "3", { 0, 32.050, 0.001, 3, 4 }, { 0.001, 3, 0.001, 3, 4 }, { 0, 0, 0, 0, 4 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS },
81eb36d6
MS		 892};
893
894static const struct channel_group_spec rs_hmc8043_cg[] = {
f2bbcc33
FS		 895 { "1", CH_IDX(0), PPS_OVP, SR_MQFLAG_DC },
896 { "2", CH_IDX(1), PPS_OVP, SR_MQFLAG_DC },
897 { "3", CH_IDX(2), PPS_OVP, SR_MQFLAG_DC },
81eb36d6
MS		 898};
899
900static const struct scpi_command rs_hmc8043_cmd[] = {
901 { SCPI_CMD_SELECT_CHANNEL, "INST:NSEL %s" },
902 { SCPI_CMD_GET_MEAS_VOLTAGE, "MEAS:VOLT?" },
903 { SCPI_CMD_GET_MEAS_CURRENT, "MEAS:CURR?" },
904 { SCPI_CMD_GET_VOLTAGE_TARGET, "VOLT?" },
905 { SCPI_CMD_SET_VOLTAGE_TARGET, "VOLT %.6f" },
906 { SCPI_CMD_GET_CURRENT_LIMIT, "CURR?" },
907 { SCPI_CMD_SET_CURRENT_LIMIT, "CURR %.6f" },
908 { SCPI_CMD_GET_OUTPUT_ENABLED, "OUTP?" },
909 { SCPI_CMD_SET_OUTPUT_ENABLE, "OUTP ON" },
910 { SCPI_CMD_SET_OUTPUT_DISABLE, "OUTP OFF" },
911 { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_ACTIVE, "VOLT:PROT:TRIP?" },
912 { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_THRESHOLD, "VOLT:PROT:LEV?" },
913 { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_THRESHOLD, "VOLT:PROT:LEV %.6f" },
914 { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_ENABLED, "VOLT:PROT:STAT?" },
915 { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_ENABLE, "VOLT:PROT:STAT ON" },
916 { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_DISABLE, "VOLT:PROT:STAT OFF" },
917 ALL_ZERO
918};
919
d4eabea8 920SR_PRIV const struct scpi_pps pps_profiles[] = {
6cc93128 921 /* Agilent N5763A */
5e7377f4 922 { "Agilent", "N5763A", SCPI_DIALECT_UNKNOWN, 0,
6cc93128
AG		 923 ARRAY_AND_SIZE(agilent_n5700a_devopts),
924 ARRAY_AND_SIZE(agilent_n5700a_devopts_cg),
925 ARRAY_AND_SIZE(agilent_n5763a_ch),
926 ARRAY_AND_SIZE(agilent_n5700a_cg),
927 agilent_n5700a_cmd,
928 .probe_channels = NULL,
7e66bf05
FS		 929 .init_aquisition = NULL,
930 .update_status = NULL,
6cc93128 931 },
ca314e06 932
5c9e56c9 933 /* Agilent N5767A */
5e7377f4 934 { "Agilent", "N5767A", SCPI_DIALECT_UNKNOWN, 0,
5c9e56c9
AG		 935 ARRAY_AND_SIZE(agilent_n5700a_devopts),
936 ARRAY_AND_SIZE(agilent_n5700a_devopts_cg),
937 ARRAY_AND_SIZE(agilent_n5767a_ch),
6cc93128 938 ARRAY_AND_SIZE(agilent_n5700a_cg),
91ef511d 939 agilent_n5700a_cmd,
5c9e56c9 940 .probe_channels = NULL,
7e66bf05
FS		 941 .init_aquisition = NULL,
942 .update_status = NULL,
5c9e56c9 943 },
ca314e06 944
c3bfb959 945 /* BK Precision 9310 */
5e7377f4 946 { "BK", "^9130$", SCPI_DIALECT_UNKNOWN, 0,
c3bfb959
MW		 947 ARRAY_AND_SIZE(bk_9130_devopts),
948 ARRAY_AND_SIZE(bk_9130_devopts_cg),
949 ARRAY_AND_SIZE(bk_9130_ch),
950 ARRAY_AND_SIZE(bk_9130_cg),
951 bk_9130_cmd,
952 .probe_channels = NULL,
7e66bf05
FS		 953 .init_aquisition = NULL,
954 .update_status = NULL,
c3bfb959
MW		 955 },
956
4ee1e2f3 957 /* Chroma 61604 */
5e7377f4 958 { "Chroma", "61604", SCPI_DIALECT_UNKNOWN, 0,
4ee1e2f3
AG		 959 ARRAY_AND_SIZE(chroma_61604_devopts),
960 ARRAY_AND_SIZE(chroma_61604_devopts_cg),
961 ARRAY_AND_SIZE(chroma_61604_ch),
962 ARRAY_AND_SIZE(chroma_61604_cg),
91ef511d 963 chroma_61604_cmd,
4ee1e2f3 964 .probe_channels = NULL,
7e66bf05
FS		 965 .init_aquisition = NULL,
966 .update_status = NULL,
4ee1e2f3 967 },
ca314e06 968
5281993e 969 /* Chroma 62000 series */
5e7377f4 970 { "Chroma", "620[0-9]{2}P-[0-9]{2,3}-[0-9]{1,3}", SCPI_DIALECT_UNKNOWN, 0,
5281993e
AG		 971 ARRAY_AND_SIZE(chroma_62000_devopts),
972 ARRAY_AND_SIZE(chroma_62000_devopts_cg),
9a5185c7
AG		 973 NULL, 0,
974 NULL, 0,
91ef511d 975 chroma_62000_cmd,
9a5185c7 976 .probe_channels = chroma_62000p_probe_channels,
7e66bf05
FS		 977 .init_aquisition = NULL,
978 .update_status = NULL,
5281993e 979 },
ca314e06 980
e76a3575 981 /* HP 6633A */
5e7377f4 982 { "HP", "6633A", SCPI_DIALECT_HP_COMP, 0,
e76a3575 983 ARRAY_AND_SIZE(hp_6630a_devopts),
7c517d02 984 ARRAY_AND_SIZE(hp_6630a_devopts_cg),
e76a3575 985 ARRAY_AND_SIZE(hp_6633a_ch),
dbc519f7 986 ARRAY_AND_SIZE(hp_6630a_cg),
e76a3575
AG		 987 hp_6630a_cmd,
988 .probe_channels = NULL,
7e66bf05
FS		 989 .init_aquisition = NULL,
990 .update_status = NULL,
e76a3575
AG		 991 },
992
a61c8cce 993 /* HP 6631B */
3d1aa50f 994 { "HP", "6631B", SCPI_DIALECT_HP_66XXB, PPS_OTP,
a61c8cce
FS		 995 ARRAY_AND_SIZE(hp_6630b_devopts),
996 ARRAY_AND_SIZE(hp_6630b_devopts_cg),
997 ARRAY_AND_SIZE(hp_6631b_ch),
dbc519f7 998 ARRAY_AND_SIZE(hp_6630b_cg),
a61c8cce
FS		 999 hp_6630b_cmd,
1000 .probe_channels = NULL,
fe4bb774
FS		 1001 hp_6630b_init_aquisition,
1002 hp_6630b_update_status,
a61c8cce
FS		 1003 },
1004
bc4a2a46 1005 /* HP 6632B */
3d1aa50f 1006 { "HP", "6632B", SCPI_DIALECT_HP_66XXB, PPS_OTP,
a61c8cce
FS		 1007 ARRAY_AND_SIZE(hp_6630b_devopts),
1008 ARRAY_AND_SIZE(hp_6630b_devopts_cg),
bc4a2a46 1009 ARRAY_AND_SIZE(hp_6632b_ch),
dbc519f7 1010 ARRAY_AND_SIZE(hp_6630b_cg),
a61c8cce
FS		 1011 hp_6630b_cmd,
1012 .probe_channels = NULL,
fe4bb774
FS		 1013 hp_6630b_init_aquisition,
1014 hp_6630b_update_status,
a61c8cce
FS		 1015 },
1016
1017 /* HP 66332A */
3d1aa50f 1018 { "HP", "66332A", SCPI_DIALECT_HP_66XXB, PPS_OTP,
a61c8cce
FS		 1019 ARRAY_AND_SIZE(hp_6630b_devopts),
1020 ARRAY_AND_SIZE(hp_6630b_devopts_cg),
1021 ARRAY_AND_SIZE(hp_66332a_ch),
dbc519f7 1022 ARRAY_AND_SIZE(hp_6630b_cg),
a61c8cce
FS		 1023 hp_6630b_cmd,
1024 .probe_channels = NULL,
fe4bb774
FS		 1025 hp_6630b_init_aquisition,
1026 hp_6630b_update_status,
a61c8cce
FS		 1027 },
1028
1029 /* HP 6633B */
3d1aa50f 1030 { "HP", "6633B", SCPI_DIALECT_HP_66XXB, PPS_OTP,
a61c8cce
FS		 1031 ARRAY_AND_SIZE(hp_6630b_devopts),
1032 ARRAY_AND_SIZE(hp_6630b_devopts_cg),
1033 ARRAY_AND_SIZE(hp_6633b_ch),
dbc519f7 1034 ARRAY_AND_SIZE(hp_6630b_cg),
a61c8cce
FS		 1035 hp_6630b_cmd,
1036 .probe_channels = NULL,
fe4bb774
FS		 1037 hp_6630b_init_aquisition,
1038 hp_6630b_update_status,
a61c8cce
FS		 1039 },
1040
1041 /* HP 6634B */
3d1aa50f 1042 { "HP", "6634B", SCPI_DIALECT_HP_66XXB, PPS_OTP,
a61c8cce
FS		 1043 ARRAY_AND_SIZE(hp_6630b_devopts),
1044 ARRAY_AND_SIZE(hp_6630b_devopts_cg),
1045 ARRAY_AND_SIZE(hp_6634b_ch),
dbc519f7 1046 ARRAY_AND_SIZE(hp_6630b_cg),
a61c8cce 1047 hp_6630b_cmd,
c3eadb07 1048 .probe_channels = NULL,
fe4bb774
FS		 1049 hp_6630b_init_aquisition,
1050 hp_6630b_update_status,
bc4a2a46
BV		 1051 },
1052
319fe9ce 1053 /* Rigol DP700 series */
5e7377f4 1054 { "Rigol", "^DP711$", SCPI_DIALECT_UNKNOWN, 0,
319fe9ce
UH		 1055 ARRAY_AND_SIZE(rigol_dp700_devopts),
1056 ARRAY_AND_SIZE(rigol_dp700_devopts_cg),
1057 ARRAY_AND_SIZE(rigol_dp711_ch),
1058 ARRAY_AND_SIZE(rigol_dp700_cg),
1059 rigol_dp700_cmd,
1060 .probe_channels = NULL,
7e66bf05
FS		 1061 .init_aquisition = NULL,
1062 .update_status = NULL,
319fe9ce 1063 },
5e7377f4 1064 { "Rigol", "^DP712$", SCPI_DIALECT_UNKNOWN, 0,
319fe9ce
UH		 1065 ARRAY_AND_SIZE(rigol_dp700_devopts),
1066 ARRAY_AND_SIZE(rigol_dp700_devopts_cg),
1067 ARRAY_AND_SIZE(rigol_dp712_ch),
1068 ARRAY_AND_SIZE(rigol_dp700_cg),
1069 rigol_dp700_cmd,
1070 .probe_channels = NULL,
7e66bf05
FS		 1071 .init_aquisition = NULL,
1072 .update_status = NULL,
319fe9ce
UH		 1073 },
1074
d4eabea8 1075 /* Rigol DP800 series */
5e7377f4 1076 { "Rigol", "^DP821A$", SCPI_DIALECT_UNKNOWN, PPS_OTP,
cfcdf576
ML		 1077 ARRAY_AND_SIZE(rigol_dp800_devopts),
1078 ARRAY_AND_SIZE(rigol_dp800_devopts_cg),
1079 ARRAY_AND_SIZE(rigol_dp821a_ch),
1080 ARRAY_AND_SIZE(rigol_dp820_cg),
91ef511d 1081 rigol_dp800_cmd,
cfcdf576 1082 .probe_channels = NULL,
7e66bf05
FS		 1083 .init_aquisition = NULL,
1084 .update_status = NULL,
cfcdf576 1085 },
5e7377f4 1086 { "Rigol", "^DP831A$", SCPI_DIALECT_UNKNOWN, PPS_OTP,
3222ee10
BV		 1087 ARRAY_AND_SIZE(rigol_dp800_devopts),
1088 ARRAY_AND_SIZE(rigol_dp800_devopts_cg),
1089 ARRAY_AND_SIZE(rigol_dp831_ch),
cfcdf576 1090 ARRAY_AND_SIZE(rigol_dp830_cg),
91ef511d 1091 rigol_dp800_cmd,
c3eadb07 1092 .probe_channels = NULL,
7e66bf05
FS		 1093 .init_aquisition = NULL,
1094 .update_status = NULL,
3222ee10 1095 },
5e7377f4 1096 { "Rigol", "^(DP832|DP832A)$", SCPI_DIALECT_UNKNOWN, PPS_OTP,
3222ee10
BV		 1097 ARRAY_AND_SIZE(rigol_dp800_devopts),
1098 ARRAY_AND_SIZE(rigol_dp800_devopts_cg),
1099 ARRAY_AND_SIZE(rigol_dp832_ch),
cfcdf576 1100 ARRAY_AND_SIZE(rigol_dp830_cg),
91ef511d 1101 rigol_dp800_cmd,
c3eadb07 1102 .probe_channels = NULL,
7e66bf05
FS		 1103 .init_aquisition = NULL,
1104 .update_status = NULL,
c3eadb07
BV		 1105 },
1106
1107 /* Philips/Fluke PM2800 series */
5e7377f4 1108 { "Philips", "^PM28[13][123]/[01234]{1,2}$", SCPI_DIALECT_PHILIPS, 0,
9d9cf1c4 1109 ARRAY_AND_SIZE(philips_pm2800_devopts),
c3eadb07
BV		 1110 ARRAY_AND_SIZE(philips_pm2800_devopts_cg),
1111 NULL, 0,
1112 NULL, 0,
91ef511d 1113 philips_pm2800_cmd,
c3eadb07 1114 philips_pm2800_probe_channels,
7e66bf05
FS		 1115 .init_aquisition = NULL,
1116 .update_status = NULL,
d4eabea8 1117 },
81eb36d6
MS		 1118
1119 /* Rohde & Schwarz HMC8043 */
5e7377f4 1120 { "Rohde&Schwarz", "HMC8043", SCPI_DIALECT_UNKNOWN, 0,
81eb36d6
MS		 1121 ARRAY_AND_SIZE(rs_hmc8043_devopts),
1122 ARRAY_AND_SIZE(rs_hmc8043_devopts_cg),
1123 ARRAY_AND_SIZE(rs_hmc8043_ch),
1124 ARRAY_AND_SIZE(rs_hmc8043_cg),
1125 rs_hmc8043_cmd,
1126 .probe_channels = NULL,
7e66bf05
FS		 1127 .init_aquisition = NULL,
1128 .update_status = NULL,
81eb36d6 1129 },
d4eabea8 1130};
d4eabea8 1131
1beccaed 1132SR_PRIV unsigned int num_pps_profiles = ARRAY_SIZE(pps_profiles);
Hardware access and backend lib