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chronovu-la8: use new scan API + fixes
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1/*
2 * This file is part of the sigrok project.
3 *
4 * Copyright (C) 2010-2012 Håvard Espeland <gus@ping.uio.no>,
5 * Copyright (C) 2010 Martin Stensgård <mastensg@ping.uio.no>
6 * Copyright (C) 2010 Carl Henrik Lunde <chlunde@ping.uio.no>
7 *
8 * This program is free software: you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation, either version 3 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program. If not, see <http://www.gnu.org/licenses/>.
20 */
21
22/*
23 * ASIX SIGMA/SIGMA2 logic analyzer driver
24 */
25
26#include <glib.h>
27#include <glib/gstdio.h>
28#include <ftdi.h>
29#include <string.h>
30#include "libsigrok.h"
31#include "libsigrok-internal.h"
32#include "asix-sigma.h"
33
34#define USB_VENDOR 0xa600
35#define USB_PRODUCT 0xa000
36#define USB_DESCRIPTION "ASIX SIGMA"
37#define USB_VENDOR_NAME "ASIX"
38#define USB_MODEL_NAME "SIGMA"
39#define USB_MODEL_VERSION ""
40#define TRIGGER_TYPES "rf10"
41#define NUM_PROBES 16
42
43SR_PRIV struct sr_dev_driver asix_sigma_driver_info;
44static struct sr_dev_driver *adi = &asix_sigma_driver_info;
45
46static const uint64_t supported_samplerates[] = {
47 SR_KHZ(200),
48 SR_KHZ(250),
49 SR_KHZ(500),
50 SR_MHZ(1),
51 SR_MHZ(5),
52 SR_MHZ(10),
53 SR_MHZ(25),
54 SR_MHZ(50),
55 SR_MHZ(100),
56 SR_MHZ(200),
57 0,
58};
59
60/*
61 * Probe numbers seem to go from 1-16, according to this image:
62 * http://tools.asix.net/img/sigma_sigmacab_pins_720.jpg
63 * (the cable has two additional GND pins, and a TI and TO pin)
64 */
65static const char *probe_names[NUM_PROBES + 1] = {
66 "1",
67 "2",
68 "3",
69 "4",
70 "5",
71 "6",
72 "7",
73 "8",
74 "9",
75 "10",
76 "11",
77 "12",
78 "13",
79 "14",
80 "15",
81 "16",
82 NULL,
83};
84
85static const struct sr_samplerates samplerates = {
86 0,
87 0,
88 0,
89 supported_samplerates,
90};
91
92static const int hwcaps[] = {
93 SR_HWCAP_LOGIC_ANALYZER,
94 SR_HWCAP_SAMPLERATE,
95 SR_HWCAP_CAPTURE_RATIO,
96 SR_HWCAP_PROBECONFIG,
97
98 SR_HWCAP_LIMIT_MSEC,
99 0,
100};
101
102/* Force the FPGA to reboot. */
103static uint8_t suicide[] = {
104 0x84, 0x84, 0x88, 0x84, 0x88, 0x84, 0x88, 0x84,
105};
106
107/* Prepare to upload firmware (FPGA specific). */
108static uint8_t init[] = {
109 0x03, 0x03, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
110};
111
112/* Initialize the logic analyzer mode. */
113static uint8_t logic_mode_start[] = {
114 0x00, 0x40, 0x0f, 0x25, 0x35, 0x40,
115 0x2a, 0x3a, 0x40, 0x03, 0x20, 0x38,
116};
117
118static const char *firmware_files[] = {
119 "asix-sigma-50.fw", /* 50 MHz, supports 8 bit fractions */
120 "asix-sigma-100.fw", /* 100 MHz */
121 "asix-sigma-200.fw", /* 200 MHz */
122 "asix-sigma-50sync.fw", /* Synchronous clock from pin */
123 "asix-sigma-phasor.fw", /* Frequency counter */
124};
125
126static int hw_dev_acquisition_stop(int dev_index, void *cb_data);
127
128static int sigma_read(void *buf, size_t size, struct context *ctx)
129{
130 int ret;
131
132 ret = ftdi_read_data(&ctx->ftdic, (unsigned char *)buf, size);
133 if (ret < 0) {
134 sr_err("sigma: ftdi_read_data failed: %s",
135 ftdi_get_error_string(&ctx->ftdic));
136 }
137
138 return ret;
139}
140
141static int sigma_write(void *buf, size_t size, struct context *ctx)
142{
143 int ret;
144
145 ret = ftdi_write_data(&ctx->ftdic, (unsigned char *)buf, size);
146 if (ret < 0) {
147 sr_err("sigma: ftdi_write_data failed: %s",
148 ftdi_get_error_string(&ctx->ftdic));
149 } else if ((size_t) ret != size) {
150 sr_err("sigma: ftdi_write_data did not complete write.");
151 }
152
153 return ret;
154}
155
156static int sigma_write_register(uint8_t reg, uint8_t *data, size_t len,
157 struct context *ctx)
158{
159 size_t i;
160 uint8_t buf[len + 2];
161 int idx = 0;
162
163 buf[idx++] = REG_ADDR_LOW | (reg & 0xf);
164 buf[idx++] = REG_ADDR_HIGH | (reg >> 4);
165
166 for (i = 0; i < len; ++i) {
167 buf[idx++] = REG_DATA_LOW | (data[i] & 0xf);
168 buf[idx++] = REG_DATA_HIGH_WRITE | (data[i] >> 4);
169 }
170
171 return sigma_write(buf, idx, ctx);
172}
173
174static int sigma_set_register(uint8_t reg, uint8_t value, struct context *ctx)
175{
176 return sigma_write_register(reg, &value, 1, ctx);
177}
178
179static int sigma_read_register(uint8_t reg, uint8_t *data, size_t len,
180 struct context *ctx)
181{
182 uint8_t buf[3];
183
184 buf[0] = REG_ADDR_LOW | (reg & 0xf);
185 buf[1] = REG_ADDR_HIGH | (reg >> 4);
186 buf[2] = REG_READ_ADDR;
187
188 sigma_write(buf, sizeof(buf), ctx);
189
190 return sigma_read(data, len, ctx);
191}
192
193static uint8_t sigma_get_register(uint8_t reg, struct context *ctx)
194{
195 uint8_t value;
196
197 if (1 != sigma_read_register(reg, &value, 1, ctx)) {
198 sr_err("sigma: sigma_get_register: 1 byte expected");
199 return 0;
200 }
201
202 return value;
203}
204
205static int sigma_read_pos(uint32_t *stoppos, uint32_t *triggerpos,
206 struct context *ctx)
207{
208 uint8_t buf[] = {
209 REG_ADDR_LOW | READ_TRIGGER_POS_LOW,
210
211 REG_READ_ADDR | NEXT_REG,
212 REG_READ_ADDR | NEXT_REG,
213 REG_READ_ADDR | NEXT_REG,
214 REG_READ_ADDR | NEXT_REG,
215 REG_READ_ADDR | NEXT_REG,
216 REG_READ_ADDR | NEXT_REG,
217 };
218 uint8_t result[6];
219
220 sigma_write(buf, sizeof(buf), ctx);
221
222 sigma_read(result, sizeof(result), ctx);
223
224 *triggerpos = result[0] | (result[1] << 8) | (result[2] << 16);
225 *stoppos = result[3] | (result[4] << 8) | (result[5] << 16);
226
227 /* Not really sure why this must be done, but according to spec. */
228 if ((--*stoppos & 0x1ff) == 0x1ff)
229 stoppos -= 64;
230
231 if ((*--triggerpos & 0x1ff) == 0x1ff)
232 triggerpos -= 64;
233
234 return 1;
235}
236
237static int sigma_read_dram(uint16_t startchunk, size_t numchunks,
238 uint8_t *data, struct context *ctx)
239{
240 size_t i;
241 uint8_t buf[4096];
242 int idx = 0;
243
244 /* Send the startchunk. Index start with 1. */
245 buf[0] = startchunk >> 8;
246 buf[1] = startchunk & 0xff;
247 sigma_write_register(WRITE_MEMROW, buf, 2, ctx);
248
249 /* Read the DRAM. */
250 buf[idx++] = REG_DRAM_BLOCK;
251 buf[idx++] = REG_DRAM_WAIT_ACK;
252
253 for (i = 0; i < numchunks; ++i) {
254 /* Alternate bit to copy from DRAM to cache. */
255 if (i != (numchunks - 1))
256 buf[idx++] = REG_DRAM_BLOCK | (((i + 1) % 2) << 4);
257
258 buf[idx++] = REG_DRAM_BLOCK_DATA | ((i % 2) << 4);
259
260 if (i != (numchunks - 1))
261 buf[idx++] = REG_DRAM_WAIT_ACK;
262 }
263
264 sigma_write(buf, idx, ctx);
265
266 return sigma_read(data, numchunks * CHUNK_SIZE, ctx);
267}
268
269/* Upload trigger look-up tables to Sigma. */
270static int sigma_write_trigger_lut(struct triggerlut *lut, struct context *ctx)
271{
272 int i;
273 uint8_t tmp[2];
274 uint16_t bit;
275
276 /* Transpose the table and send to Sigma. */
277 for (i = 0; i < 16; ++i) {
278 bit = 1 << i;
279
280 tmp[0] = tmp[1] = 0;
281
282 if (lut->m2d[0] & bit)
283 tmp[0] |= 0x01;
284 if (lut->m2d[1] & bit)
285 tmp[0] |= 0x02;
286 if (lut->m2d[2] & bit)
287 tmp[0] |= 0x04;
288 if (lut->m2d[3] & bit)
289 tmp[0] |= 0x08;
290
291 if (lut->m3 & bit)
292 tmp[0] |= 0x10;
293 if (lut->m3s & bit)
294 tmp[0] |= 0x20;
295 if (lut->m4 & bit)
296 tmp[0] |= 0x40;
297
298 if (lut->m0d[0] & bit)
299 tmp[1] |= 0x01;
300 if (lut->m0d[1] & bit)
301 tmp[1] |= 0x02;
302 if (lut->m0d[2] & bit)
303 tmp[1] |= 0x04;
304 if (lut->m0d[3] & bit)
305 tmp[1] |= 0x08;
306
307 if (lut->m1d[0] & bit)
308 tmp[1] |= 0x10;
309 if (lut->m1d[1] & bit)
310 tmp[1] |= 0x20;
311 if (lut->m1d[2] & bit)
312 tmp[1] |= 0x40;
313 if (lut->m1d[3] & bit)
314 tmp[1] |= 0x80;
315
316 sigma_write_register(WRITE_TRIGGER_SELECT0, tmp, sizeof(tmp),
317 ctx);
318 sigma_set_register(WRITE_TRIGGER_SELECT1, 0x30 | i, ctx);
319 }
320
321 /* Send the parameters */
322 sigma_write_register(WRITE_TRIGGER_SELECT0, (uint8_t *) &lut->params,
323 sizeof(lut->params), ctx);
324
325 return SR_OK;
326}
327
328/* Generate the bitbang stream for programming the FPGA. */
329static int bin2bitbang(const char *filename,
330 unsigned char **buf, size_t *buf_size)
331{
332 FILE *f;
333 unsigned long file_size;
334 unsigned long offset = 0;
335 unsigned char *p;
336 uint8_t *firmware;
337 unsigned long fwsize = 0;
338 const int buffer_size = 65536;
339 size_t i;
340 int c, bit, v;
341 uint32_t imm = 0x3f6df2ab;
342
343 f = g_fopen(filename, "rb");
344 if (!f) {
345 sr_err("sigma: g_fopen(\"%s\", \"rb\")", filename);
346 return SR_ERR;
347 }
348
349 if (-1 == fseek(f, 0, SEEK_END)) {
350 sr_err("sigma: fseek on %s failed", filename);
351 fclose(f);
352 return SR_ERR;
353 }
354
355 file_size = ftell(f);
356
357 fseek(f, 0, SEEK_SET);
358
359 if (!(firmware = g_try_malloc(buffer_size))) {
360 sr_err("sigma: %s: firmware malloc failed", __func__);
361 fclose(f);
362 return SR_ERR_MALLOC;
363 }
364
365 while ((c = getc(f)) != EOF) {
366 imm = (imm + 0xa853753) % 177 + (imm * 0x8034052);
367 firmware[fwsize++] = c ^ imm;
368 }
369 fclose(f);
370
371 if(fwsize != file_size) {
372 sr_err("sigma: %s: Error reading firmware", filename);
373 fclose(f);
374 g_free(firmware);
375 return SR_ERR;
376 }
377
378 *buf_size = fwsize * 2 * 8;
379
380 *buf = p = (unsigned char *)g_try_malloc(*buf_size);
381 if (!p) {
382 sr_err("sigma: %s: buf/p malloc failed", __func__);
383 g_free(firmware);
384 return SR_ERR_MALLOC;
385 }
386
387 for (i = 0; i < fwsize; ++i) {
388 for (bit = 7; bit >= 0; --bit) {
389 v = firmware[i] & 1 << bit ? 0x40 : 0x00;
390 p[offset++] = v | 0x01;
391 p[offset++] = v;
392 }
393 }
394
395 g_free(firmware);
396
397 if (offset != *buf_size) {
398 g_free(*buf);
399 sr_err("sigma: Error reading firmware %s "
400 "offset=%ld, file_size=%ld, buf_size=%zd.",
401 filename, offset, file_size, *buf_size);
402
403 return SR_ERR;
404 }
405
406 return SR_OK;
407}
408
409static int hw_init(void)
410{
411
412 /* Nothing to do. */
413
414 return SR_OK;
415}
416
417static int hw_scan(void)
418{
419 struct sr_dev_inst *sdi;
420 struct context *ctx;
421 struct ftdi_device_list *devlist;
422 char serial_txt[10];
423 uint32_t serial;
424
425 if (!(ctx = g_try_malloc(sizeof(struct context)))) {
426 sr_err("sigma: %s: ctx malloc failed", __func__);
427 return SR_ERR_MALLOC;
428 }
429
430 ftdi_init(&ctx->ftdic);
431
432 /* Look for SIGMAs. */
433
434 if (ftdi_usb_find_all(&ctx->ftdic, &devlist,
435 USB_VENDOR, USB_PRODUCT) <= 0)
436 goto free;
437
438 /* Make sure it's a version 1 or 2 SIGMA. */
439 ftdi_usb_get_strings(&ctx->ftdic, devlist->dev, NULL, 0, NULL, 0,
440 serial_txt, sizeof(serial_txt));
441 sscanf(serial_txt, "%x", &serial);
442
443 if (serial < 0xa6010000 || serial > 0xa602ffff) {
444 sr_err("sigma: Only SIGMA and SIGMA2 are supported "
445 "in this version of sigrok.");
446 goto free;
447 }
448
449 sr_info("Found ASIX SIGMA - Serial: %s", serial_txt);
450
451 ctx->cur_samplerate = 0;
452 ctx->period_ps = 0;
453 ctx->limit_msec = 0;
454 ctx->cur_firmware = -1;
455 ctx->num_probes = 0;
456 ctx->samples_per_event = 0;
457 ctx->capture_ratio = 50;
458 ctx->use_triggers = 0;
459
460 /* Register SIGMA device. */
461 if (!(sdi = sr_dev_inst_new(0, SR_ST_INITIALIZING, USB_VENDOR_NAME,
462 USB_MODEL_NAME, USB_MODEL_VERSION))) {
463 sr_err("sigma: %s: sdi was NULL", __func__);
464 goto free;
465 }
466
467 sdi->priv = ctx;
468
469 adi->instances = g_slist_append(adi->instances, sdi);
470
471 /* We will open the device again when we need it. */
472 ftdi_list_free(&devlist);
473
474 return 1;
475
476free:
477 g_free(ctx);
478 return 0;
479}
480
481static int upload_firmware(int firmware_idx, struct context *ctx)
482{
483 int ret;
484 unsigned char *buf;
485 unsigned char pins;
486 size_t buf_size;
487 unsigned char result[32];
488 char firmware_path[128];
489
490 /* Make sure it's an ASIX SIGMA. */
491 if ((ret = ftdi_usb_open_desc(&ctx->ftdic,
492 USB_VENDOR, USB_PRODUCT, USB_DESCRIPTION, NULL)) < 0) {
493 sr_err("sigma: ftdi_usb_open failed: %s",
494 ftdi_get_error_string(&ctx->ftdic));
495 return 0;
496 }
497
498 if ((ret = ftdi_set_bitmode(&ctx->ftdic, 0xdf, BITMODE_BITBANG)) < 0) {
499 sr_err("sigma: ftdi_set_bitmode failed: %s",
500 ftdi_get_error_string(&ctx->ftdic));
501 return 0;
502 }
503
504 /* Four times the speed of sigmalogan - Works well. */
505 if ((ret = ftdi_set_baudrate(&ctx->ftdic, 750000)) < 0) {
506 sr_err("sigma: ftdi_set_baudrate failed: %s",
507 ftdi_get_error_string(&ctx->ftdic));
508 return 0;
509 }
510
511 /* Force the FPGA to reboot. */
512 sigma_write(suicide, sizeof(suicide), ctx);
513 sigma_write(suicide, sizeof(suicide), ctx);
514 sigma_write(suicide, sizeof(suicide), ctx);
515 sigma_write(suicide, sizeof(suicide), ctx);
516
517 /* Prepare to upload firmware (FPGA specific). */
518 sigma_write(init, sizeof(init), ctx);
519
520 ftdi_usb_purge_buffers(&ctx->ftdic);
521
522 /* Wait until the FPGA asserts INIT_B. */
523 while (1) {
524 ret = sigma_read(result, 1, ctx);
525 if (result[0] & 0x20)
526 break;
527 }
528
529 /* Prepare firmware. */
530 snprintf(firmware_path, sizeof(firmware_path), "%s/%s", FIRMWARE_DIR,
531 firmware_files[firmware_idx]);
532
533 if ((ret = bin2bitbang(firmware_path, &buf, &buf_size)) != SR_OK) {
534 sr_err("sigma: An error occured while reading the firmware: %s",
535 firmware_path);
536 return ret;
537 }
538
539 /* Upload firmare. */
540 sr_info("sigma: Uploading firmware %s", firmware_files[firmware_idx]);
541 sigma_write(buf, buf_size, ctx);
542
543 g_free(buf);
544
545 if ((ret = ftdi_set_bitmode(&ctx->ftdic, 0x00, BITMODE_RESET)) < 0) {
546 sr_err("sigma: ftdi_set_bitmode failed: %s",
547 ftdi_get_error_string(&ctx->ftdic));
548 return SR_ERR;
549 }
550
551 ftdi_usb_purge_buffers(&ctx->ftdic);
552
553 /* Discard garbage. */
554 while (1 == sigma_read(&pins, 1, ctx))
555 ;
556
557 /* Initialize the logic analyzer mode. */
558 sigma_write(logic_mode_start, sizeof(logic_mode_start), ctx);
559
560 /* Expect a 3 byte reply. */
561 ret = sigma_read(result, 3, ctx);
562 if (ret != 3 ||
563 result[0] != 0xa6 || result[1] != 0x55 || result[2] != 0xaa) {
564 sr_err("sigma: Configuration failed. Invalid reply received.");
565 return SR_ERR;
566 }
567
568 ctx->cur_firmware = firmware_idx;
569
570 sr_info("sigma: Firmware uploaded");
571
572 return SR_OK;
573}
574
575static int hw_dev_open(int dev_index)
576{
577 struct sr_dev_inst *sdi;
578 struct context *ctx;
579 int ret;
580
581 if (!(sdi = sr_dev_inst_get(adi->instances, dev_index)))
582 return SR_ERR;
583
584 ctx = sdi->priv;
585
586 /* Make sure it's an ASIX SIGMA. */
587 if ((ret = ftdi_usb_open_desc(&ctx->ftdic,
588 USB_VENDOR, USB_PRODUCT, USB_DESCRIPTION, NULL)) < 0) {
589
590 sr_err("sigma: ftdi_usb_open failed: %s",
591 ftdi_get_error_string(&ctx->ftdic));
592
593 return 0;
594 }
595
596 sdi->status = SR_ST_ACTIVE;
597
598 return SR_OK;
599}
600
601static int set_samplerate(struct sr_dev_inst *sdi, uint64_t samplerate)
602{
603 int i, ret;
604 struct context *ctx = sdi->priv;
605
606 for (i = 0; supported_samplerates[i]; i++) {
607 if (supported_samplerates[i] == samplerate)
608 break;
609 }
610 if (supported_samplerates[i] == 0)
611 return SR_ERR_SAMPLERATE;
612
613 if (samplerate <= SR_MHZ(50)) {
614 ret = upload_firmware(0, ctx);
615 ctx->num_probes = 16;
616 }
617 if (samplerate == SR_MHZ(100)) {
618 ret = upload_firmware(1, ctx);
619 ctx->num_probes = 8;
620 }
621 else if (samplerate == SR_MHZ(200)) {
622 ret = upload_firmware(2, ctx);
623 ctx->num_probes = 4;
624 }
625
626 ctx->cur_samplerate = samplerate;
627 ctx->period_ps = 1000000000000 / samplerate;
628 ctx->samples_per_event = 16 / ctx->num_probes;
629 ctx->state.state = SIGMA_IDLE;
630
631 return ret;
632}
633
634/*
635 * In 100 and 200 MHz mode, only a single pin rising/falling can be
636 * set as trigger. In other modes, two rising/falling triggers can be set,
637 * in addition to value/mask trigger for any number of probes.
638 *
639 * The Sigma supports complex triggers using boolean expressions, but this
640 * has not been implemented yet.
641 */
642static int configure_probes(struct sr_dev_inst *sdi, const GSList *probes)
643{
644 struct context *ctx = sdi->priv;
645 const struct sr_probe *probe;
646 const GSList *l;
647 int trigger_set = 0;
648 int probebit;
649
650 memset(&ctx->trigger, 0, sizeof(struct sigma_trigger));
651
652 for (l = probes; l; l = l->next) {
653 probe = (struct sr_probe *)l->data;
654 probebit = 1 << (probe->index - 1);
655
656 if (!probe->enabled || !probe->trigger)
657 continue;
658
659 if (ctx->cur_samplerate >= SR_MHZ(100)) {
660 /* Fast trigger support. */
661 if (trigger_set) {
662 sr_err("sigma: ASIX SIGMA only supports a single "
663 "pin trigger in 100 and 200MHz mode.");
664 return SR_ERR;
665 }
666 if (probe->trigger[0] == 'f')
667 ctx->trigger.fallingmask |= probebit;
668 else if (probe->trigger[0] == 'r')
669 ctx->trigger.risingmask |= probebit;
670 else {
671 sr_err("sigma: ASIX SIGMA only supports "
672 "rising/falling trigger in 100 "
673 "and 200MHz mode.");
674 return SR_ERR;
675 }
676
677 ++trigger_set;
678 } else {
679 /* Simple trigger support (event). */
680 if (probe->trigger[0] == '1') {
681 ctx->trigger.simplevalue |= probebit;
682 ctx->trigger.simplemask |= probebit;
683 }
684 else if (probe->trigger[0] == '0') {
685 ctx->trigger.simplevalue &= ~probebit;
686 ctx->trigger.simplemask |= probebit;
687 }
688 else if (probe->trigger[0] == 'f') {
689 ctx->trigger.fallingmask |= probebit;
690 ++trigger_set;
691 }
692 else if (probe->trigger[0] == 'r') {
693 ctx->trigger.risingmask |= probebit;
694 ++trigger_set;
695 }
696
697 /*
698 * Actually, Sigma supports 2 rising/falling triggers,
699 * but they are ORed and the current trigger syntax
700 * does not permit ORed triggers.
701 */
702 if (trigger_set > 1) {
703 sr_err("sigma: ASIX SIGMA only supports 1 "
704 "rising/falling triggers.");
705 return SR_ERR;
706 }
707 }
708
709 if (trigger_set)
710 ctx->use_triggers = 1;
711 }
712
713 return SR_OK;
714}
715
716static int hw_dev_close(int dev_index)
717{
718 struct sr_dev_inst *sdi;
719 struct context *ctx;
720
721 if (!(sdi = sr_dev_inst_get(adi->instances, dev_index))) {
722 sr_err("sigma: %s: sdi was NULL", __func__);
723 return SR_ERR_BUG;
724 }
725
726 if (!(ctx = sdi->priv)) {
727 sr_err("sigma: %s: sdi->priv was NULL", __func__);
728 return SR_ERR_BUG;
729 }
730
731 /* TODO */
732 if (sdi->status == SR_ST_ACTIVE)
733 ftdi_usb_close(&ctx->ftdic);
734
735 sdi->status = SR_ST_INACTIVE;
736
737 return SR_OK;
738}
739
740static int hw_cleanup(void)
741{
742 GSList *l;
743 struct sr_dev_inst *sdi;
744 int ret = SR_OK;
745
746 /* Properly close all devices. */
747 for (l = adi->instances; l; l = l->next) {
748 if (!(sdi = l->data)) {
749 /* Log error, but continue cleaning up the rest. */
750 sr_err("sigma: %s: sdi was NULL, continuing", __func__);
751 ret = SR_ERR_BUG;
752 continue;
753 }
754 sr_dev_inst_free(sdi);
755 }
756 g_slist_free(adi->instances);
757 adi->instances = NULL;
758
759 return ret;
760}
761
762static const void *hw_dev_info_get(int dev_index, int dev_info_id)
763{
764 struct sr_dev_inst *sdi;
765 struct context *ctx;
766 const void *info = NULL;
767
768 if (!(sdi = sr_dev_inst_get(adi->instances, dev_index))) {
769 sr_err("sigma: %s: sdi was NULL", __func__);
770 return NULL;
771 }
772
773 ctx = sdi->priv;
774
775 switch (dev_info_id) {
776 case SR_DI_INST:
777 info = sdi;
778 break;
779 case SR_DI_NUM_PROBES:
780 info = GINT_TO_POINTER(NUM_PROBES);
781 break;
782 case SR_DI_PROBE_NAMES:
783 info = probe_names;
784 break;
785 case SR_DI_SAMPLERATES:
786 info = &samplerates;
787 break;
788 case SR_DI_TRIGGER_TYPES:
789 info = (char *)TRIGGER_TYPES;
790 break;
791 case SR_DI_CUR_SAMPLERATE:
792 info = &ctx->cur_samplerate;
793 break;
794 }
795
796 return info;
797}
798
799static int hw_dev_status_get(int dev_index)
800{
801 struct sr_dev_inst *sdi;
802
803 sdi = sr_dev_inst_get(adi->instances, dev_index);
804 if (sdi)
805 return sdi->status;
806 else
807 return SR_ST_NOT_FOUND;
808}
809
810static const int *hw_hwcap_get_all(void)
811{
812 return hwcaps;
813}
814
815static int hw_dev_config_set(int dev_index, int hwcap, const void *value)
816{
817 struct sr_dev_inst *sdi;
818 struct context *ctx;
819 int ret;
820
821 if (!(sdi = sr_dev_inst_get(adi->instances, dev_index)))
822 return SR_ERR;
823
824 ctx = sdi->priv;
825
826 if (hwcap == SR_HWCAP_SAMPLERATE) {
827 ret = set_samplerate(sdi, *(const uint64_t *)value);
828 } else if (hwcap == SR_HWCAP_PROBECONFIG) {
829 ret = configure_probes(sdi, value);
830 } else if (hwcap == SR_HWCAP_LIMIT_MSEC) {
831 ctx->limit_msec = *(const uint64_t *)value;
832 if (ctx->limit_msec > 0)
833 ret = SR_OK;
834 else
835 ret = SR_ERR;
836 } else if (hwcap == SR_HWCAP_CAPTURE_RATIO) {
837 ctx->capture_ratio = *(const uint64_t *)value;
838 if (ctx->capture_ratio < 0 || ctx->capture_ratio > 100)
839 ret = SR_ERR;
840 else
841 ret = SR_OK;
842 } else {
843 ret = SR_ERR;
844 }
845
846 return ret;
847}
848
849/* Software trigger to determine exact trigger position. */
850static int get_trigger_offset(uint16_t *samples, uint16_t last_sample,
851 struct sigma_trigger *t)
852{
853 int i;
854
855 for (i = 0; i < 8; ++i) {
856 if (i > 0)
857 last_sample = samples[i-1];
858
859 /* Simple triggers. */
860 if ((samples[i] & t->simplemask) != t->simplevalue)
861 continue;
862
863 /* Rising edge. */
864 if ((last_sample & t->risingmask) != 0 || (samples[i] &
865 t->risingmask) != t->risingmask)
866 continue;
867
868 /* Falling edge. */
869 if ((last_sample & t->fallingmask) != t->fallingmask ||
870 (samples[i] & t->fallingmask) != 0)
871 continue;
872
873 break;
874 }
875
876 /* If we did not match, return original trigger pos. */
877 return i & 0x7;
878}
879
880/*
881 * Decode chunk of 1024 bytes, 64 clusters, 7 events per cluster.
882 * Each event is 20ns apart, and can contain multiple samples.
883 *
884 * For 200 MHz, events contain 4 samples for each channel, spread 5 ns apart.
885 * For 100 MHz, events contain 2 samples for each channel, spread 10 ns apart.
886 * For 50 MHz and below, events contain one sample for each channel,
887 * spread 20 ns apart.
888 */
889static int decode_chunk_ts(uint8_t *buf, uint16_t *lastts,
890 uint16_t *lastsample, int triggerpos,
891 uint16_t limit_chunk, void *cb_data)
892{
893 struct sr_dev_inst *sdi = cb_data;
894 struct context *ctx = sdi->priv;
895 uint16_t tsdiff, ts;
896 uint16_t samples[65536 * ctx->samples_per_event];
897 struct sr_datafeed_packet packet;
898 struct sr_datafeed_logic logic;
899 int i, j, k, l, numpad, tosend;
900 size_t n = 0, sent = 0;
901 int clustersize = EVENTS_PER_CLUSTER * ctx->samples_per_event;
902 uint16_t *event;
903 uint16_t cur_sample;
904 int triggerts = -1;
905
906 /* Check if trigger is in this chunk. */
907 if (triggerpos != -1) {
908 if (ctx->cur_samplerate <= SR_MHZ(50))
909 triggerpos -= EVENTS_PER_CLUSTER - 1;
910
911 if (triggerpos < 0)
912 triggerpos = 0;
913
914 /* Find in which cluster the trigger occured. */
915 triggerts = triggerpos / 7;
916 }
917
918 /* For each ts. */
919 for (i = 0; i < 64; ++i) {
920 ts = *(uint16_t *) &buf[i * 16];
921 tsdiff = ts - *lastts;
922 *lastts = ts;
923
924 /* Decode partial chunk. */
925 if (limit_chunk && ts > limit_chunk)
926 return SR_OK;
927
928 /* Pad last sample up to current point. */
929 numpad = tsdiff * ctx->samples_per_event - clustersize;
930 if (numpad > 0) {
931 for (j = 0; j < numpad; ++j)
932 samples[j] = *lastsample;
933
934 n = numpad;
935 }
936
937 /* Send samples between previous and this timestamp to sigrok. */
938 sent = 0;
939 while (sent < n) {
940 tosend = MIN(2048, n - sent);
941
942 packet.type = SR_DF_LOGIC;
943 packet.payload = &logic;
944 logic.length = tosend * sizeof(uint16_t);
945 logic.unitsize = 2;
946 logic.data = samples + sent;
947 sr_session_send(ctx->session_dev_id, &packet);
948
949 sent += tosend;
950 }
951 n = 0;
952
953 event = (uint16_t *) &buf[i * 16 + 2];
954 cur_sample = 0;
955
956 /* For each event in cluster. */
957 for (j = 0; j < 7; ++j) {
958
959 /* For each sample in event. */
960 for (k = 0; k < ctx->samples_per_event; ++k) {
961 cur_sample = 0;
962
963 /* For each probe. */
964 for (l = 0; l < ctx->num_probes; ++l)
965 cur_sample |= (!!(event[j] & (1 << (l *
966 ctx->samples_per_event + k)))) << l;
967
968 samples[n++] = cur_sample;
969 }
970 }
971
972 /* Send data up to trigger point (if triggered). */
973 sent = 0;
974 if (i == triggerts) {
975 /*
976 * Trigger is not always accurate to sample because of
977 * pipeline delay. However, it always triggers before
978 * the actual event. We therefore look at the next
979 * samples to pinpoint the exact position of the trigger.
980 */
981 tosend = get_trigger_offset(samples, *lastsample,
982 &ctx->trigger);
983
984 if (tosend > 0) {
985 packet.type = SR_DF_LOGIC;
986 packet.payload = &logic;
987 logic.length = tosend * sizeof(uint16_t);
988 logic.unitsize = 2;
989 logic.data = samples;
990 sr_session_send(ctx->session_dev_id, &packet);
991
992 sent += tosend;
993 }
994
995 /* Only send trigger if explicitly enabled. */
996 if (ctx->use_triggers) {
997 packet.type = SR_DF_TRIGGER;
998 sr_session_send(ctx->session_dev_id, &packet);
999 }
1000 }
1001
1002 /* Send rest of the chunk to sigrok. */
1003 tosend = n - sent;
1004
1005 if (tosend > 0) {
1006 packet.type = SR_DF_LOGIC;
1007 packet.payload = &logic;
1008 logic.length = tosend * sizeof(uint16_t);
1009 logic.unitsize = 2;
1010 logic.data = samples + sent;
1011 sr_session_send(ctx->session_dev_id, &packet);
1012 }
1013
1014 *lastsample = samples[n - 1];
1015 }
1016
1017 return SR_OK;
1018}
1019
1020static int receive_data(int fd, int revents, void *cb_data)
1021{
1022 struct sr_dev_inst *sdi = cb_data;
1023 struct context *ctx = sdi->priv;
1024 struct sr_datafeed_packet packet;
1025 const int chunks_per_read = 32;
1026 unsigned char buf[chunks_per_read * CHUNK_SIZE];
1027 int bufsz, numchunks, i, newchunks;
1028 uint64_t running_msec;
1029 struct timeval tv;
1030
1031 /* Avoid compiler warnings. */
1032 (void)fd;
1033 (void)revents;
1034
1035 /* Get the current position. */
1036 sigma_read_pos(&ctx->state.stoppos, &ctx->state.triggerpos, ctx);
1037
1038 numchunks = (ctx->state.stoppos + 511) / 512;
1039
1040 if (ctx->state.state == SIGMA_IDLE)
1041 return TRUE;
1042
1043 if (ctx->state.state == SIGMA_CAPTURE) {
1044 /* Check if the timer has expired, or memory is full. */
1045 gettimeofday(&tv, 0);
1046 running_msec = (tv.tv_sec - ctx->start_tv.tv_sec) * 1000 +
1047 (tv.tv_usec - ctx->start_tv.tv_usec) / 1000;
1048
1049 if (running_msec < ctx->limit_msec && numchunks < 32767)
1050 return TRUE; /* While capturing... */
1051 else
1052 hw_dev_acquisition_stop(sdi->index, sdi);
1053
1054 } else if (ctx->state.state == SIGMA_DOWNLOAD) {
1055 if (ctx->state.chunks_downloaded >= numchunks) {
1056 /* End of samples. */
1057 packet.type = SR_DF_END;
1058 sr_session_send(ctx->session_dev_id, &packet);
1059
1060 ctx->state.state = SIGMA_IDLE;
1061
1062 return TRUE;
1063 }
1064
1065 newchunks = MIN(chunks_per_read,
1066 numchunks - ctx->state.chunks_downloaded);
1067
1068 sr_info("sigma: Downloading sample data: %.0f %%",
1069 100.0 * ctx->state.chunks_downloaded / numchunks);
1070
1071 bufsz = sigma_read_dram(ctx->state.chunks_downloaded,
1072 newchunks, buf, ctx);
1073 /* TODO: Check bufsz. For now, just avoid compiler warnings. */
1074 (void)bufsz;
1075
1076 /* Find first ts. */
1077 if (ctx->state.chunks_downloaded == 0) {
1078 ctx->state.lastts = *(uint16_t *) buf - 1;
1079 ctx->state.lastsample = 0;
1080 }
1081
1082 /* Decode chunks and send them to sigrok. */
1083 for (i = 0; i < newchunks; ++i) {
1084 int limit_chunk = 0;
1085
1086 /* The last chunk may potentially be only in part. */
1087 if (ctx->state.chunks_downloaded == numchunks - 1) {
1088 /* Find the last valid timestamp */
1089 limit_chunk = ctx->state.stoppos % 512 + ctx->state.lastts;
1090 }
1091
1092 if (ctx->state.chunks_downloaded + i == ctx->state.triggerchunk)
1093 decode_chunk_ts(buf + (i * CHUNK_SIZE),
1094 &ctx->state.lastts,
1095 &ctx->state.lastsample,
1096 ctx->state.triggerpos & 0x1ff,
1097 limit_chunk, sdi);
1098 else
1099 decode_chunk_ts(buf + (i * CHUNK_SIZE),
1100 &ctx->state.lastts,
1101 &ctx->state.lastsample,
1102 -1, limit_chunk, sdi);
1103
1104 ++ctx->state.chunks_downloaded;
1105 }
1106 }
1107
1108 return TRUE;
1109}
1110
1111/* Build a LUT entry used by the trigger functions. */
1112static void build_lut_entry(uint16_t value, uint16_t mask, uint16_t *entry)
1113{
1114 int i, j, k, bit;
1115
1116 /* For each quad probe. */
1117 for (i = 0; i < 4; ++i) {
1118 entry[i] = 0xffff;
1119
1120 /* For each bit in LUT. */
1121 for (j = 0; j < 16; ++j)
1122
1123 /* For each probe in quad. */
1124 for (k = 0; k < 4; ++k) {
1125 bit = 1 << (i * 4 + k);
1126
1127 /* Set bit in entry */
1128 if ((mask & bit) &&
1129 ((!(value & bit)) !=
1130 (!(j & (1 << k)))))
1131 entry[i] &= ~(1 << j);
1132 }
1133 }
1134}
1135
1136/* Add a logical function to LUT mask. */
1137static void add_trigger_function(enum triggerop oper, enum triggerfunc func,
1138 int index, int neg, uint16_t *mask)
1139{
1140 int i, j;
1141 int x[2][2], tmp, a, b, aset, bset, rset;
1142
1143 memset(x, 0, 4 * sizeof(int));
1144
1145 /* Trigger detect condition. */
1146 switch (oper) {
1147 case OP_LEVEL:
1148 x[0][1] = 1;
1149 x[1][1] = 1;
1150 break;
1151 case OP_NOT:
1152 x[0][0] = 1;
1153 x[1][0] = 1;
1154 break;
1155 case OP_RISE:
1156 x[0][1] = 1;
1157 break;
1158 case OP_FALL:
1159 x[1][0] = 1;
1160 break;
1161 case OP_RISEFALL:
1162 x[0][1] = 1;
1163 x[1][0] = 1;
1164 break;
1165 case OP_NOTRISE:
1166 x[1][1] = 1;
1167 x[0][0] = 1;
1168 x[1][0] = 1;
1169 break;
1170 case OP_NOTFALL:
1171 x[1][1] = 1;
1172 x[0][0] = 1;
1173 x[0][1] = 1;
1174 break;
1175 case OP_NOTRISEFALL:
1176 x[1][1] = 1;
1177 x[0][0] = 1;
1178 break;
1179 }
1180
1181 /* Transpose if neg is set. */
1182 if (neg) {
1183 for (i = 0; i < 2; ++i) {
1184 for (j = 0; j < 2; ++j) {
1185 tmp = x[i][j];
1186 x[i][j] = x[1-i][1-j];
1187 x[1-i][1-j] = tmp;
1188 }
1189 }
1190 }
1191
1192 /* Update mask with function. */
1193 for (i = 0; i < 16; ++i) {
1194 a = (i >> (2 * index + 0)) & 1;
1195 b = (i >> (2 * index + 1)) & 1;
1196
1197 aset = (*mask >> i) & 1;
1198 bset = x[b][a];
1199
1200 if (func == FUNC_AND || func == FUNC_NAND)
1201 rset = aset & bset;
1202 else if (func == FUNC_OR || func == FUNC_NOR)
1203 rset = aset | bset;
1204 else if (func == FUNC_XOR || func == FUNC_NXOR)
1205 rset = aset ^ bset;
1206
1207 if (func == FUNC_NAND || func == FUNC_NOR || func == FUNC_NXOR)
1208 rset = !rset;
1209
1210 *mask &= ~(1 << i);
1211
1212 if (rset)
1213 *mask |= 1 << i;
1214 }
1215}
1216
1217/*
1218 * Build trigger LUTs used by 50 MHz and lower sample rates for supporting
1219 * simple pin change and state triggers. Only two transitions (rise/fall) can be
1220 * set at any time, but a full mask and value can be set (0/1).
1221 */
1222static int build_basic_trigger(struct triggerlut *lut, struct context *ctx)
1223{
1224 int i,j;
1225 uint16_t masks[2] = { 0, 0 };
1226
1227 memset(lut, 0, sizeof(struct triggerlut));
1228
1229 /* Contant for simple triggers. */
1230 lut->m4 = 0xa000;
1231
1232 /* Value/mask trigger support. */
1233 build_lut_entry(ctx->trigger.simplevalue, ctx->trigger.simplemask,
1234 lut->m2d);
1235
1236 /* Rise/fall trigger support. */
1237 for (i = 0, j = 0; i < 16; ++i) {
1238 if (ctx->trigger.risingmask & (1 << i) ||
1239 ctx->trigger.fallingmask & (1 << i))
1240 masks[j++] = 1 << i;
1241 }
1242
1243 build_lut_entry(masks[0], masks[0], lut->m0d);
1244 build_lut_entry(masks[1], masks[1], lut->m1d);
1245
1246 /* Add glue logic */
1247 if (masks[0] || masks[1]) {
1248 /* Transition trigger. */
1249 if (masks[0] & ctx->trigger.risingmask)
1250 add_trigger_function(OP_RISE, FUNC_OR, 0, 0, &lut->m3);
1251 if (masks[0] & ctx->trigger.fallingmask)
1252 add_trigger_function(OP_FALL, FUNC_OR, 0, 0, &lut->m3);
1253 if (masks[1] & ctx->trigger.risingmask)
1254 add_trigger_function(OP_RISE, FUNC_OR, 1, 0, &lut->m3);
1255 if (masks[1] & ctx->trigger.fallingmask)
1256 add_trigger_function(OP_FALL, FUNC_OR, 1, 0, &lut->m3);
1257 } else {
1258 /* Only value/mask trigger. */
1259 lut->m3 = 0xffff;
1260 }
1261
1262 /* Triggertype: event. */
1263 lut->params.selres = 3;
1264
1265 return SR_OK;
1266}
1267
1268static int hw_dev_acquisition_start(int dev_index, void *cb_data)
1269{
1270 struct sr_dev_inst *sdi;
1271 struct context *ctx;
1272 struct sr_datafeed_packet *packet;
1273 struct sr_datafeed_header *header;
1274 struct sr_datafeed_meta_logic meta;
1275 struct clockselect_50 clockselect;
1276 int frac, triggerpin, ret;
1277 uint8_t triggerselect;
1278 struct triggerinout triggerinout_conf;
1279 struct triggerlut lut;
1280
1281 if (!(sdi = sr_dev_inst_get(adi->instances, dev_index)))
1282 return SR_ERR;
1283
1284 ctx = sdi->priv;
1285
1286 /* If the samplerate has not been set, default to 200 kHz. */
1287 if (ctx->cur_firmware == -1) {
1288 if ((ret = set_samplerate(sdi, SR_KHZ(200))) != SR_OK)
1289 return ret;
1290 }
1291
1292 /* Enter trigger programming mode. */
1293 sigma_set_register(WRITE_TRIGGER_SELECT1, 0x20, ctx);
1294
1295 /* 100 and 200 MHz mode. */
1296 if (ctx->cur_samplerate >= SR_MHZ(100)) {
1297 sigma_set_register(WRITE_TRIGGER_SELECT1, 0x81, ctx);
1298
1299 /* Find which pin to trigger on from mask. */
1300 for (triggerpin = 0; triggerpin < 8; ++triggerpin)
1301 if ((ctx->trigger.risingmask | ctx->trigger.fallingmask) &
1302 (1 << triggerpin))
1303 break;
1304
1305 /* Set trigger pin and light LED on trigger. */
1306 triggerselect = (1 << LEDSEL1) | (triggerpin & 0x7);
1307
1308 /* Default rising edge. */
1309 if (ctx->trigger.fallingmask)
1310 triggerselect |= 1 << 3;
1311
1312 /* All other modes. */
1313 } else if (ctx->cur_samplerate <= SR_MHZ(50)) {
1314 build_basic_trigger(&lut, ctx);
1315
1316 sigma_write_trigger_lut(&lut, ctx);
1317
1318 triggerselect = (1 << LEDSEL1) | (1 << LEDSEL0);
1319 }
1320
1321 /* Setup trigger in and out pins to default values. */
1322 memset(&triggerinout_conf, 0, sizeof(struct triggerinout));
1323 triggerinout_conf.trgout_bytrigger = 1;
1324 triggerinout_conf.trgout_enable = 1;
1325
1326 sigma_write_register(WRITE_TRIGGER_OPTION,
1327 (uint8_t *) &triggerinout_conf,
1328 sizeof(struct triggerinout), ctx);
1329
1330 /* Go back to normal mode. */
1331 sigma_set_register(WRITE_TRIGGER_SELECT1, triggerselect, ctx);
1332
1333 /* Set clock select register. */
1334 if (ctx->cur_samplerate == SR_MHZ(200))
1335 /* Enable 4 probes. */
1336 sigma_set_register(WRITE_CLOCK_SELECT, 0xf0, ctx);
1337 else if (ctx->cur_samplerate == SR_MHZ(100))
1338 /* Enable 8 probes. */
1339 sigma_set_register(WRITE_CLOCK_SELECT, 0x00, ctx);
1340 else {
1341 /*
1342 * 50 MHz mode (or fraction thereof). Any fraction down to
1343 * 50 MHz / 256 can be used, but is not supported by sigrok API.
1344 */
1345 frac = SR_MHZ(50) / ctx->cur_samplerate - 1;
1346
1347 clockselect.async = 0;
1348 clockselect.fraction = frac;
1349 clockselect.disabled_probes = 0;
1350
1351 sigma_write_register(WRITE_CLOCK_SELECT,
1352 (uint8_t *) &clockselect,
1353 sizeof(clockselect), ctx);
1354 }
1355
1356 /* Setup maximum post trigger time. */
1357 sigma_set_register(WRITE_POST_TRIGGER,
1358 (ctx->capture_ratio * 255) / 100, ctx);
1359
1360 /* Start acqusition. */
1361 gettimeofday(&ctx->start_tv, 0);
1362 sigma_set_register(WRITE_MODE, 0x0d, ctx);
1363
1364 ctx->session_dev_id = cb_data;
1365
1366 if (!(packet = g_try_malloc(sizeof(struct sr_datafeed_packet)))) {
1367 sr_err("sigma: %s: packet malloc failed.", __func__);
1368 return SR_ERR_MALLOC;
1369 }
1370
1371 if (!(header = g_try_malloc(sizeof(struct sr_datafeed_header)))) {
1372 sr_err("sigma: %s: header malloc failed.", __func__);
1373 return SR_ERR_MALLOC;
1374 }
1375
1376 /* Send header packet to the session bus. */
1377 packet->type = SR_DF_HEADER;
1378 packet->payload = header;
1379 header->feed_version = 1;
1380 gettimeofday(&header->starttime, NULL);
1381 sr_session_send(ctx->session_dev_id, packet);
1382
1383 /* Send metadata about the SR_DF_LOGIC packets to come. */
1384 packet->type = SR_DF_META_LOGIC;
1385 packet->payload = &meta;
1386 meta.samplerate = ctx->cur_samplerate;
1387 meta.num_probes = ctx->num_probes;
1388 sr_session_send(ctx->session_dev_id, packet);
1389
1390 /* Add capture source. */
1391 sr_source_add(0, G_IO_IN, 10, receive_data, sdi);
1392
1393 g_free(header);
1394 g_free(packet);
1395
1396 ctx->state.state = SIGMA_CAPTURE;
1397
1398 return SR_OK;
1399}
1400
1401static int hw_dev_acquisition_stop(int dev_index, void *cb_data)
1402{
1403 struct sr_dev_inst *sdi;
1404 struct context *ctx;
1405 uint8_t modestatus;
1406
1407 /* Avoid compiler warnings. */
1408 (void)cb_data;
1409
1410 if (!(sdi = sr_dev_inst_get(adi->instances, dev_index))) {
1411 sr_err("sigma: %s: sdi was NULL", __func__);
1412 return SR_ERR_BUG;
1413 }
1414
1415 if (!(ctx = sdi->priv)) {
1416 sr_err("sigma: %s: sdi->priv was NULL", __func__);
1417 return SR_ERR_BUG;
1418 }
1419
1420 /* Stop acquisition. */
1421 sigma_set_register(WRITE_MODE, 0x11, ctx);
1422
1423 /* Set SDRAM Read Enable. */
1424 sigma_set_register(WRITE_MODE, 0x02, ctx);
1425
1426 /* Get the current position. */
1427 sigma_read_pos(&ctx->state.stoppos, &ctx->state.triggerpos, ctx);
1428
1429 /* Check if trigger has fired. */
1430 modestatus = sigma_get_register(READ_MODE, ctx);
1431 if (modestatus & 0x20)
1432 ctx->state.triggerchunk = ctx->state.triggerpos / 512;
1433 else
1434 ctx->state.triggerchunk = -1;
1435
1436 ctx->state.chunks_downloaded = 0;
1437
1438 ctx->state.state = SIGMA_DOWNLOAD;
1439
1440 return SR_OK;
1441}
1442
1443SR_PRIV struct sr_dev_driver asix_sigma_driver_info = {
1444 .name = "asix-sigma",
1445 .longname = "ASIX SIGMA/SIGMA2",
1446 .api_version = 1,
1447 .init = hw_init,
1448 .cleanup = hw_cleanup,
1449 .scan = hw_scan,
1450 .dev_open = hw_dev_open,
1451 .dev_close = hw_dev_close,
1452 .dev_info_get = hw_dev_info_get,
1453 .dev_status_get = hw_dev_status_get,
1454 .hwcap_get_all = hw_hwcap_get_all,
1455 .dev_config_set = hw_dev_config_set,
1456 .dev_acquisition_start = hw_dev_acquisition_start,
1457 .dev_acquisition_stop = hw_dev_acquisition_stop,
1458 .instances = NULL,
1459};
Hardware access and backend lib