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Commit | Line | Data |
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28a35d8a HE |
1 | /* |
2 | * This file is part of the sigrok project. | |
3 | * | |
868501fa | 4 | * Copyright (C) 2010-2012 Håvard Espeland <gus@ping.uio.no>, |
911f1834 UH |
5 | * Copyright (C) 2010 Martin Stensgård <mastensg@ping.uio.no> |
6 | * Copyright (C) 2010 Carl Henrik Lunde <chlunde@ping.uio.no> | |
28a35d8a HE |
7 | * |
8 | * This program is free software: you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation, either version 3 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
20 | */ | |
21 | ||
911f1834 | 22 | /* |
6352d030 | 23 | * ASIX SIGMA/SIGMA2 logic analyzer driver |
911f1834 UH |
24 | */ |
25 | ||
3bbd9849 UH |
26 | #include <glib.h> |
27 | #include <glib/gstdio.h> | |
28a35d8a HE |
28 | #include <ftdi.h> |
29 | #include <string.h> | |
45c59c8b BV |
30 | #include "libsigrok.h" |
31 | #include "libsigrok-internal.h" | |
28a35d8a HE |
32 | #include "asix-sigma.h" |
33 | ||
34 | #define USB_VENDOR 0xa600 | |
35 | #define USB_PRODUCT 0xa000 | |
36 | #define USB_DESCRIPTION "ASIX SIGMA" | |
37 | #define USB_VENDOR_NAME "ASIX" | |
38 | #define USB_MODEL_NAME "SIGMA" | |
39 | #define USB_MODEL_VERSION "" | |
ee492173 | 40 | #define TRIGGER_TYPES "rf10" |
464d12c7 | 41 | #define NUM_PROBES 16 |
28a35d8a | 42 | |
d68e2d1a | 43 | static GSList *dev_insts = NULL; |
28a35d8a | 44 | |
a533743d | 45 | static const uint64_t supported_samplerates[] = { |
59df0c77 UH |
46 | SR_KHZ(200), |
47 | SR_KHZ(250), | |
48 | SR_KHZ(500), | |
49 | SR_MHZ(1), | |
50 | SR_MHZ(5), | |
51 | SR_MHZ(10), | |
52 | SR_MHZ(25), | |
53 | SR_MHZ(50), | |
54 | SR_MHZ(100), | |
55 | SR_MHZ(200), | |
28a35d8a HE |
56 | 0, |
57 | }; | |
58 | ||
d261dbbf UH |
59 | /* |
60 | * Probe numbers seem to go from 1-16, according to this image: | |
61 | * http://tools.asix.net/img/sigma_sigmacab_pins_720.jpg | |
62 | * (the cable has two additional GND pins, and a TI and TO pin) | |
63 | */ | |
c37d2b1b | 64 | static const char *probe_names[NUM_PROBES + 1] = { |
464d12c7 KS |
65 | "1", |
66 | "2", | |
67 | "3", | |
68 | "4", | |
69 | "5", | |
70 | "6", | |
71 | "7", | |
72 | "8", | |
73 | "9", | |
74 | "10", | |
75 | "11", | |
76 | "12", | |
77 | "13", | |
78 | "14", | |
79 | "15", | |
d261dbbf | 80 | "16", |
464d12c7 KS |
81 | NULL, |
82 | }; | |
83 | ||
a533743d | 84 | static const struct sr_samplerates samplerates = { |
590b9f9a UH |
85 | 0, |
86 | 0, | |
87 | 0, | |
28a35d8a HE |
88 | supported_samplerates, |
89 | }; | |
90 | ||
915f7cc8 | 91 | static const int hwcaps[] = { |
5a2326a7 UH |
92 | SR_HWCAP_LOGIC_ANALYZER, |
93 | SR_HWCAP_SAMPLERATE, | |
94 | SR_HWCAP_CAPTURE_RATIO, | |
95 | SR_HWCAP_PROBECONFIG, | |
28a35d8a | 96 | |
5a2326a7 | 97 | SR_HWCAP_LIMIT_MSEC, |
28a35d8a HE |
98 | 0, |
99 | }; | |
100 | ||
fefa1800 UH |
101 | /* Force the FPGA to reboot. */ |
102 | static uint8_t suicide[] = { | |
103 | 0x84, 0x84, 0x88, 0x84, 0x88, 0x84, 0x88, 0x84, | |
104 | }; | |
105 | ||
106 | /* Prepare to upload firmware (FPGA specific). */ | |
107 | static uint8_t init[] = { | |
108 | 0x03, 0x03, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, | |
109 | }; | |
110 | ||
111 | /* Initialize the logic analyzer mode. */ | |
112 | static uint8_t logic_mode_start[] = { | |
113 | 0x00, 0x40, 0x0f, 0x25, 0x35, 0x40, | |
114 | 0x2a, 0x3a, 0x40, 0x03, 0x20, 0x38, | |
115 | }; | |
116 | ||
eec5275e | 117 | static const char *firmware_files[] = { |
a8116d76 HE |
118 | "asix-sigma-50.fw", /* 50 MHz, supports 8 bit fractions */ |
119 | "asix-sigma-100.fw", /* 100 MHz */ | |
120 | "asix-sigma-200.fw", /* 200 MHz */ | |
ed09fd07 | 121 | "asix-sigma-50sync.fw", /* Synchronous clock from pin */ |
a8116d76 | 122 | "asix-sigma-phasor.fw", /* Frequency counter */ |
f6564c8d HE |
123 | }; |
124 | ||
3cd3a20b | 125 | static int hw_dev_acquisition_stop(int dev_index, void *cb_data); |
6aac7737 | 126 | |
ea9cfed7 | 127 | static int sigma_read(void *buf, size_t size, struct context *ctx) |
28a35d8a HE |
128 | { |
129 | int ret; | |
fefa1800 | 130 | |
ea9cfed7 | 131 | ret = ftdi_read_data(&ctx->ftdic, (unsigned char *)buf, size); |
28a35d8a | 132 | if (ret < 0) { |
7b48d6e1 | 133 | sr_err("sigma: ftdi_read_data failed: %s", |
ea9cfed7 | 134 | ftdi_get_error_string(&ctx->ftdic)); |
28a35d8a HE |
135 | } |
136 | ||
137 | return ret; | |
138 | } | |
139 | ||
ea9cfed7 | 140 | static int sigma_write(void *buf, size_t size, struct context *ctx) |
28a35d8a HE |
141 | { |
142 | int ret; | |
fefa1800 | 143 | |
ea9cfed7 | 144 | ret = ftdi_write_data(&ctx->ftdic, (unsigned char *)buf, size); |
28a35d8a | 145 | if (ret < 0) { |
7b48d6e1 | 146 | sr_err("sigma: ftdi_write_data failed: %s", |
ea9cfed7 | 147 | ftdi_get_error_string(&ctx->ftdic)); |
fefa1800 | 148 | } else if ((size_t) ret != size) { |
0aeb0ccd | 149 | sr_err("sigma: ftdi_write_data did not complete write."); |
28a35d8a HE |
150 | } |
151 | ||
152 | return ret; | |
153 | } | |
154 | ||
99965709 | 155 | static int sigma_write_register(uint8_t reg, uint8_t *data, size_t len, |
ea9cfed7 | 156 | struct context *ctx) |
28a35d8a HE |
157 | { |
158 | size_t i; | |
159 | uint8_t buf[len + 2]; | |
160 | int idx = 0; | |
161 | ||
162 | buf[idx++] = REG_ADDR_LOW | (reg & 0xf); | |
163 | buf[idx++] = REG_ADDR_HIGH | (reg >> 4); | |
164 | ||
fefa1800 | 165 | for (i = 0; i < len; ++i) { |
28a35d8a HE |
166 | buf[idx++] = REG_DATA_LOW | (data[i] & 0xf); |
167 | buf[idx++] = REG_DATA_HIGH_WRITE | (data[i] >> 4); | |
168 | } | |
169 | ||
ea9cfed7 | 170 | return sigma_write(buf, idx, ctx); |
28a35d8a HE |
171 | } |
172 | ||
ea9cfed7 | 173 | static int sigma_set_register(uint8_t reg, uint8_t value, struct context *ctx) |
28a35d8a | 174 | { |
ea9cfed7 | 175 | return sigma_write_register(reg, &value, 1, ctx); |
28a35d8a HE |
176 | } |
177 | ||
99965709 | 178 | static int sigma_read_register(uint8_t reg, uint8_t *data, size_t len, |
ea9cfed7 | 179 | struct context *ctx) |
28a35d8a HE |
180 | { |
181 | uint8_t buf[3]; | |
fefa1800 | 182 | |
28a35d8a HE |
183 | buf[0] = REG_ADDR_LOW | (reg & 0xf); |
184 | buf[1] = REG_ADDR_HIGH | (reg >> 4); | |
28a35d8a HE |
185 | buf[2] = REG_READ_ADDR; |
186 | ||
ea9cfed7 | 187 | sigma_write(buf, sizeof(buf), ctx); |
28a35d8a | 188 | |
ea9cfed7 | 189 | return sigma_read(data, len, ctx); |
28a35d8a HE |
190 | } |
191 | ||
ea9cfed7 | 192 | static uint8_t sigma_get_register(uint8_t reg, struct context *ctx) |
28a35d8a HE |
193 | { |
194 | uint8_t value; | |
fefa1800 | 195 | |
ea9cfed7 | 196 | if (1 != sigma_read_register(reg, &value, 1, ctx)) { |
7b48d6e1 | 197 | sr_err("sigma: sigma_get_register: 1 byte expected"); |
28a35d8a HE |
198 | return 0; |
199 | } | |
200 | ||
201 | return value; | |
202 | } | |
203 | ||
99965709 | 204 | static int sigma_read_pos(uint32_t *stoppos, uint32_t *triggerpos, |
ea9cfed7 | 205 | struct context *ctx) |
28a35d8a HE |
206 | { |
207 | uint8_t buf[] = { | |
208 | REG_ADDR_LOW | READ_TRIGGER_POS_LOW, | |
209 | ||
210 | REG_READ_ADDR | NEXT_REG, | |
211 | REG_READ_ADDR | NEXT_REG, | |
212 | REG_READ_ADDR | NEXT_REG, | |
213 | REG_READ_ADDR | NEXT_REG, | |
214 | REG_READ_ADDR | NEXT_REG, | |
215 | REG_READ_ADDR | NEXT_REG, | |
216 | }; | |
28a35d8a HE |
217 | uint8_t result[6]; |
218 | ||
ea9cfed7 | 219 | sigma_write(buf, sizeof(buf), ctx); |
28a35d8a | 220 | |
ea9cfed7 | 221 | sigma_read(result, sizeof(result), ctx); |
28a35d8a HE |
222 | |
223 | *triggerpos = result[0] | (result[1] << 8) | (result[2] << 16); | |
224 | *stoppos = result[3] | (result[4] << 8) | (result[5] << 16); | |
225 | ||
57bbf56b HE |
226 | /* Not really sure why this must be done, but according to spec. */ |
227 | if ((--*stoppos & 0x1ff) == 0x1ff) | |
228 | stoppos -= 64; | |
229 | ||
230 | if ((*--triggerpos & 0x1ff) == 0x1ff) | |
231 | triggerpos -= 64; | |
232 | ||
28a35d8a HE |
233 | return 1; |
234 | } | |
235 | ||
99965709 | 236 | static int sigma_read_dram(uint16_t startchunk, size_t numchunks, |
ea9cfed7 | 237 | uint8_t *data, struct context *ctx) |
28a35d8a HE |
238 | { |
239 | size_t i; | |
240 | uint8_t buf[4096]; | |
241 | int idx = 0; | |
242 | ||
fefa1800 | 243 | /* Send the startchunk. Index start with 1. */ |
28a35d8a HE |
244 | buf[0] = startchunk >> 8; |
245 | buf[1] = startchunk & 0xff; | |
ea9cfed7 | 246 | sigma_write_register(WRITE_MEMROW, buf, 2, ctx); |
28a35d8a | 247 | |
fefa1800 | 248 | /* Read the DRAM. */ |
28a35d8a HE |
249 | buf[idx++] = REG_DRAM_BLOCK; |
250 | buf[idx++] = REG_DRAM_WAIT_ACK; | |
251 | ||
252 | for (i = 0; i < numchunks; ++i) { | |
fefa1800 UH |
253 | /* Alternate bit to copy from DRAM to cache. */ |
254 | if (i != (numchunks - 1)) | |
255 | buf[idx++] = REG_DRAM_BLOCK | (((i + 1) % 2) << 4); | |
28a35d8a HE |
256 | |
257 | buf[idx++] = REG_DRAM_BLOCK_DATA | ((i % 2) << 4); | |
258 | ||
fefa1800 | 259 | if (i != (numchunks - 1)) |
28a35d8a HE |
260 | buf[idx++] = REG_DRAM_WAIT_ACK; |
261 | } | |
262 | ||
ea9cfed7 | 263 | sigma_write(buf, idx, ctx); |
28a35d8a | 264 | |
ea9cfed7 | 265 | return sigma_read(data, numchunks * CHUNK_SIZE, ctx); |
28a35d8a HE |
266 | } |
267 | ||
4ae1f451 | 268 | /* Upload trigger look-up tables to Sigma. */ |
ea9cfed7 | 269 | static int sigma_write_trigger_lut(struct triggerlut *lut, struct context *ctx) |
ee492173 HE |
270 | { |
271 | int i; | |
272 | uint8_t tmp[2]; | |
273 | uint16_t bit; | |
274 | ||
275 | /* Transpose the table and send to Sigma. */ | |
276 | for (i = 0; i < 16; ++i) { | |
277 | bit = 1 << i; | |
278 | ||
279 | tmp[0] = tmp[1] = 0; | |
280 | ||
281 | if (lut->m2d[0] & bit) | |
282 | tmp[0] |= 0x01; | |
283 | if (lut->m2d[1] & bit) | |
284 | tmp[0] |= 0x02; | |
285 | if (lut->m2d[2] & bit) | |
286 | tmp[0] |= 0x04; | |
287 | if (lut->m2d[3] & bit) | |
288 | tmp[0] |= 0x08; | |
289 | ||
290 | if (lut->m3 & bit) | |
291 | tmp[0] |= 0x10; | |
292 | if (lut->m3s & bit) | |
293 | tmp[0] |= 0x20; | |
294 | if (lut->m4 & bit) | |
295 | tmp[0] |= 0x40; | |
296 | ||
297 | if (lut->m0d[0] & bit) | |
298 | tmp[1] |= 0x01; | |
299 | if (lut->m0d[1] & bit) | |
300 | tmp[1] |= 0x02; | |
301 | if (lut->m0d[2] & bit) | |
302 | tmp[1] |= 0x04; | |
303 | if (lut->m0d[3] & bit) | |
304 | tmp[1] |= 0x08; | |
305 | ||
306 | if (lut->m1d[0] & bit) | |
307 | tmp[1] |= 0x10; | |
308 | if (lut->m1d[1] & bit) | |
309 | tmp[1] |= 0x20; | |
310 | if (lut->m1d[2] & bit) | |
311 | tmp[1] |= 0x40; | |
312 | if (lut->m1d[3] & bit) | |
313 | tmp[1] |= 0x80; | |
314 | ||
99965709 | 315 | sigma_write_register(WRITE_TRIGGER_SELECT0, tmp, sizeof(tmp), |
ea9cfed7 UH |
316 | ctx); |
317 | sigma_set_register(WRITE_TRIGGER_SELECT1, 0x30 | i, ctx); | |
ee492173 HE |
318 | } |
319 | ||
320 | /* Send the parameters */ | |
321 | sigma_write_register(WRITE_TRIGGER_SELECT0, (uint8_t *) &lut->params, | |
ea9cfed7 | 322 | sizeof(lut->params), ctx); |
ee492173 | 323 | |
e46b8fb1 | 324 | return SR_OK; |
ee492173 HE |
325 | } |
326 | ||
fefa1800 | 327 | /* Generate the bitbang stream for programming the FPGA. */ |
28a35d8a | 328 | static int bin2bitbang(const char *filename, |
fefa1800 | 329 | unsigned char **buf, size_t *buf_size) |
28a35d8a | 330 | { |
fefa1800 | 331 | FILE *f; |
e3fff420 | 332 | unsigned long file_size; |
28a35d8a HE |
333 | unsigned long offset = 0; |
334 | unsigned char *p; | |
e3fff420 HE |
335 | uint8_t *firmware; |
336 | unsigned long fwsize = 0; | |
28a35d8a HE |
337 | const int buffer_size = 65536; |
338 | size_t i; | |
e3fff420 | 339 | int c, bit, v; |
fefa1800 | 340 | uint32_t imm = 0x3f6df2ab; |
28a35d8a | 341 | |
868d8cef | 342 | f = g_fopen(filename, "rb"); |
28a35d8a | 343 | if (!f) { |
7b48d6e1 | 344 | sr_err("sigma: g_fopen(\"%s\", \"rb\")", filename); |
b53738ba | 345 | return SR_ERR; |
28a35d8a HE |
346 | } |
347 | ||
348 | if (-1 == fseek(f, 0, SEEK_END)) { | |
7b48d6e1 | 349 | sr_err("sigma: fseek on %s failed", filename); |
28a35d8a | 350 | fclose(f); |
b53738ba | 351 | return SR_ERR; |
28a35d8a HE |
352 | } |
353 | ||
354 | file_size = ftell(f); | |
355 | ||
356 | fseek(f, 0, SEEK_SET); | |
357 | ||
b53738ba | 358 | if (!(firmware = g_try_malloc(buffer_size))) { |
340cfac0 | 359 | sr_err("sigma: %s: firmware malloc failed", __func__); |
12ad53f5 | 360 | fclose(f); |
b53738ba | 361 | return SR_ERR_MALLOC; |
28a35d8a HE |
362 | } |
363 | ||
28a35d8a HE |
364 | while ((c = getc(f)) != EOF) { |
365 | imm = (imm + 0xa853753) % 177 + (imm * 0x8034052); | |
e3fff420 | 366 | firmware[fwsize++] = c ^ imm; |
28a35d8a HE |
367 | } |
368 | fclose(f); | |
369 | ||
e3fff420 HE |
370 | if(fwsize != file_size) { |
371 | sr_err("sigma: %s: Error reading firmware", filename); | |
372 | fclose(f); | |
373 | g_free(firmware); | |
374 | return SR_ERR; | |
28a35d8a HE |
375 | } |
376 | ||
28a35d8a HE |
377 | *buf_size = fwsize * 2 * 8; |
378 | ||
b53738ba | 379 | *buf = p = (unsigned char *)g_try_malloc(*buf_size); |
28a35d8a | 380 | if (!p) { |
340cfac0 | 381 | sr_err("sigma: %s: buf/p malloc failed", __func__); |
12ad53f5 | 382 | g_free(firmware); |
b53738ba | 383 | return SR_ERR_MALLOC; |
28a35d8a HE |
384 | } |
385 | ||
386 | for (i = 0; i < fwsize; ++i) { | |
28a35d8a | 387 | for (bit = 7; bit >= 0; --bit) { |
fefa1800 | 388 | v = firmware[i] & 1 << bit ? 0x40 : 0x00; |
28a35d8a HE |
389 | p[offset++] = v | 0x01; |
390 | p[offset++] = v; | |
391 | } | |
392 | } | |
393 | ||
394 | g_free(firmware); | |
395 | ||
396 | if (offset != *buf_size) { | |
397 | g_free(*buf); | |
7b48d6e1 | 398 | sr_err("sigma: Error reading firmware %s " |
0aeb0ccd | 399 | "offset=%ld, file_size=%ld, buf_size=%zd.", |
133a37bf | 400 | filename, offset, file_size, *buf_size); |
28a35d8a | 401 | |
b53738ba | 402 | return SR_ERR; |
28a35d8a HE |
403 | } |
404 | ||
b53738ba | 405 | return SR_OK; |
28a35d8a HE |
406 | } |
407 | ||
40dda2c3 | 408 | static int hw_init(void) |
61136ea6 BV |
409 | { |
410 | ||
411 | /* Nothing to do. */ | |
412 | ||
413 | return SR_OK; | |
414 | } | |
415 | ||
416 | static int hw_scan(void) | |
28a35d8a | 417 | { |
d68e2d1a | 418 | struct sr_dev_inst *sdi; |
ea9cfed7 | 419 | struct context *ctx; |
e3fff420 HE |
420 | struct ftdi_device_list *devlist; |
421 | char serial_txt[10]; | |
422 | uint32_t serial; | |
28a35d8a | 423 | |
ea9cfed7 UH |
424 | if (!(ctx = g_try_malloc(sizeof(struct context)))) { |
425 | sr_err("sigma: %s: ctx malloc failed", __func__); | |
e3fff420 | 426 | return SR_ERR_MALLOC; |
b53738ba | 427 | } |
99965709 | 428 | |
ea9cfed7 | 429 | ftdi_init(&ctx->ftdic); |
28a35d8a | 430 | |
fefa1800 | 431 | /* Look for SIGMAs. */ |
e3fff420 HE |
432 | |
433 | if (ftdi_usb_find_all(&ctx->ftdic, &devlist, | |
6352d030 | 434 | USB_VENDOR, USB_PRODUCT) <= 0) |
99965709 HE |
435 | goto free; |
436 | ||
e3fff420 HE |
437 | /* Make sure it's a version 1 or 2 SIGMA. */ |
438 | ftdi_usb_get_strings(&ctx->ftdic, devlist->dev, NULL, 0, NULL, 0, | |
6352d030 | 439 | serial_txt, sizeof(serial_txt)); |
e3fff420 HE |
440 | sscanf(serial_txt, "%x", &serial); |
441 | ||
6352d030 | 442 | if (serial < 0xa6010000 || serial > 0xa602ffff) { |
e3fff420 | 443 | sr_err("sigma: Only SIGMA and SIGMA2 are supported " |
6352d030 | 444 | "in this version of sigrok."); |
e3fff420 HE |
445 | goto free; |
446 | } | |
447 | ||
448 | sr_info("Found ASIX SIGMA - Serial: %s", serial_txt); | |
449 | ||
ea9cfed7 UH |
450 | ctx->cur_samplerate = 0; |
451 | ctx->period_ps = 0; | |
452 | ctx->limit_msec = 0; | |
453 | ctx->cur_firmware = -1; | |
454 | ctx->num_probes = 0; | |
455 | ctx->samples_per_event = 0; | |
456 | ctx->capture_ratio = 50; | |
457 | ctx->use_triggers = 0; | |
28a35d8a | 458 | |
fefa1800 | 459 | /* Register SIGMA device. */ |
d68e2d1a UH |
460 | if (!(sdi = sr_dev_inst_new(0, SR_ST_INITIALIZING, USB_VENDOR_NAME, |
461 | USB_MODEL_NAME, USB_MODEL_VERSION))) { | |
462 | sr_err("sigma: %s: sdi was NULL", __func__); | |
99965709 | 463 | goto free; |
d68e2d1a | 464 | } |
99965709 | 465 | |
ea9cfed7 | 466 | sdi->priv = ctx; |
28a35d8a | 467 | |
d68e2d1a | 468 | dev_insts = g_slist_append(dev_insts, sdi); |
28a35d8a | 469 | |
fefa1800 | 470 | /* We will open the device again when we need it. */ |
e3fff420 | 471 | ftdi_list_free(&devlist); |
28a35d8a HE |
472 | |
473 | return 1; | |
ea9cfed7 | 474 | |
99965709 | 475 | free: |
ea9cfed7 | 476 | g_free(ctx); |
99965709 | 477 | return 0; |
28a35d8a HE |
478 | } |
479 | ||
ea9cfed7 | 480 | static int upload_firmware(int firmware_idx, struct context *ctx) |
28a35d8a HE |
481 | { |
482 | int ret; | |
483 | unsigned char *buf; | |
484 | unsigned char pins; | |
485 | size_t buf_size; | |
28a35d8a | 486 | unsigned char result[32]; |
e8397563 | 487 | char firmware_path[128]; |
28a35d8a | 488 | |
fefa1800 | 489 | /* Make sure it's an ASIX SIGMA. */ |
ea9cfed7 | 490 | if ((ret = ftdi_usb_open_desc(&ctx->ftdic, |
28a35d8a | 491 | USB_VENDOR, USB_PRODUCT, USB_DESCRIPTION, NULL)) < 0) { |
7b48d6e1 | 492 | sr_err("sigma: ftdi_usb_open failed: %s", |
ea9cfed7 | 493 | ftdi_get_error_string(&ctx->ftdic)); |
28a35d8a HE |
494 | return 0; |
495 | } | |
496 | ||
ea9cfed7 | 497 | if ((ret = ftdi_set_bitmode(&ctx->ftdic, 0xdf, BITMODE_BITBANG)) < 0) { |
7b48d6e1 | 498 | sr_err("sigma: ftdi_set_bitmode failed: %s", |
ea9cfed7 | 499 | ftdi_get_error_string(&ctx->ftdic)); |
28a35d8a HE |
500 | return 0; |
501 | } | |
502 | ||
fefa1800 | 503 | /* Four times the speed of sigmalogan - Works well. */ |
ea9cfed7 | 504 | if ((ret = ftdi_set_baudrate(&ctx->ftdic, 750000)) < 0) { |
7b48d6e1 | 505 | sr_err("sigma: ftdi_set_baudrate failed: %s", |
ea9cfed7 | 506 | ftdi_get_error_string(&ctx->ftdic)); |
28a35d8a HE |
507 | return 0; |
508 | } | |
509 | ||
fefa1800 | 510 | /* Force the FPGA to reboot. */ |
ea9cfed7 UH |
511 | sigma_write(suicide, sizeof(suicide), ctx); |
512 | sigma_write(suicide, sizeof(suicide), ctx); | |
513 | sigma_write(suicide, sizeof(suicide), ctx); | |
514 | sigma_write(suicide, sizeof(suicide), ctx); | |
28a35d8a | 515 | |
fefa1800 | 516 | /* Prepare to upload firmware (FPGA specific). */ |
ea9cfed7 | 517 | sigma_write(init, sizeof(init), ctx); |
28a35d8a | 518 | |
ea9cfed7 | 519 | ftdi_usb_purge_buffers(&ctx->ftdic); |
28a35d8a | 520 | |
fefa1800 | 521 | /* Wait until the FPGA asserts INIT_B. */ |
28a35d8a | 522 | while (1) { |
ea9cfed7 | 523 | ret = sigma_read(result, 1, ctx); |
28a35d8a HE |
524 | if (result[0] & 0x20) |
525 | break; | |
526 | } | |
527 | ||
9ddb2a12 | 528 | /* Prepare firmware. */ |
e8397563 | 529 | snprintf(firmware_path, sizeof(firmware_path), "%s/%s", FIRMWARE_DIR, |
f6564c8d HE |
530 | firmware_files[firmware_idx]); |
531 | ||
b53738ba | 532 | if ((ret = bin2bitbang(firmware_path, &buf, &buf_size)) != SR_OK) { |
7b48d6e1 | 533 | sr_err("sigma: An error occured while reading the firmware: %s", |
133a37bf | 534 | firmware_path); |
b53738ba | 535 | return ret; |
28a35d8a HE |
536 | } |
537 | ||
fefa1800 | 538 | /* Upload firmare. */ |
e3fff420 | 539 | sr_info("sigma: Uploading firmware %s", firmware_files[firmware_idx]); |
ea9cfed7 | 540 | sigma_write(buf, buf_size, ctx); |
28a35d8a HE |
541 | |
542 | g_free(buf); | |
543 | ||
ea9cfed7 | 544 | if ((ret = ftdi_set_bitmode(&ctx->ftdic, 0x00, BITMODE_RESET)) < 0) { |
7b48d6e1 | 545 | sr_err("sigma: ftdi_set_bitmode failed: %s", |
ea9cfed7 | 546 | ftdi_get_error_string(&ctx->ftdic)); |
e46b8fb1 | 547 | return SR_ERR; |
28a35d8a HE |
548 | } |
549 | ||
ea9cfed7 | 550 | ftdi_usb_purge_buffers(&ctx->ftdic); |
28a35d8a | 551 | |
fefa1800 | 552 | /* Discard garbage. */ |
ea9cfed7 | 553 | while (1 == sigma_read(&pins, 1, ctx)) |
28a35d8a HE |
554 | ; |
555 | ||
fefa1800 | 556 | /* Initialize the logic analyzer mode. */ |
ea9cfed7 | 557 | sigma_write(logic_mode_start, sizeof(logic_mode_start), ctx); |
28a35d8a | 558 | |
fefa1800 | 559 | /* Expect a 3 byte reply. */ |
ea9cfed7 | 560 | ret = sigma_read(result, 3, ctx); |
28a35d8a HE |
561 | if (ret != 3 || |
562 | result[0] != 0xa6 || result[1] != 0x55 || result[2] != 0xaa) { | |
7b48d6e1 | 563 | sr_err("sigma: Configuration failed. Invalid reply received."); |
e46b8fb1 | 564 | return SR_ERR; |
28a35d8a HE |
565 | } |
566 | ||
ea9cfed7 | 567 | ctx->cur_firmware = firmware_idx; |
f6564c8d | 568 | |
e3fff420 HE |
569 | sr_info("sigma: Firmware uploaded"); |
570 | ||
e46b8fb1 | 571 | return SR_OK; |
f6564c8d HE |
572 | } |
573 | ||
e7eb703f | 574 | static int hw_dev_open(int dev_index) |
f6564c8d | 575 | { |
d68e2d1a | 576 | struct sr_dev_inst *sdi; |
ea9cfed7 | 577 | struct context *ctx; |
f6564c8d HE |
578 | int ret; |
579 | ||
bb7ef793 | 580 | if (!(sdi = sr_dev_inst_get(dev_insts, dev_index))) |
e46b8fb1 | 581 | return SR_ERR; |
99965709 | 582 | |
ea9cfed7 | 583 | ctx = sdi->priv; |
99965709 | 584 | |
9ddb2a12 | 585 | /* Make sure it's an ASIX SIGMA. */ |
ea9cfed7 | 586 | if ((ret = ftdi_usb_open_desc(&ctx->ftdic, |
f6564c8d HE |
587 | USB_VENDOR, USB_PRODUCT, USB_DESCRIPTION, NULL)) < 0) { |
588 | ||
7b48d6e1 | 589 | sr_err("sigma: ftdi_usb_open failed: %s", |
ea9cfed7 | 590 | ftdi_get_error_string(&ctx->ftdic)); |
f6564c8d HE |
591 | |
592 | return 0; | |
593 | } | |
28a35d8a | 594 | |
5a2326a7 | 595 | sdi->status = SR_ST_ACTIVE; |
28a35d8a | 596 | |
e46b8fb1 | 597 | return SR_OK; |
f6564c8d HE |
598 | } |
599 | ||
d68e2d1a | 600 | static int set_samplerate(struct sr_dev_inst *sdi, uint64_t samplerate) |
f6564c8d | 601 | { |
e8397563 | 602 | int i, ret; |
ea9cfed7 | 603 | struct context *ctx = sdi->priv; |
f6564c8d HE |
604 | |
605 | for (i = 0; supported_samplerates[i]; i++) { | |
606 | if (supported_samplerates[i] == samplerate) | |
607 | break; | |
608 | } | |
609 | if (supported_samplerates[i] == 0) | |
e46b8fb1 | 610 | return SR_ERR_SAMPLERATE; |
f6564c8d | 611 | |
59df0c77 | 612 | if (samplerate <= SR_MHZ(50)) { |
ea9cfed7 UH |
613 | ret = upload_firmware(0, ctx); |
614 | ctx->num_probes = 16; | |
e8397563 | 615 | } |
59df0c77 | 616 | if (samplerate == SR_MHZ(100)) { |
ea9cfed7 UH |
617 | ret = upload_firmware(1, ctx); |
618 | ctx->num_probes = 8; | |
f78898e9 | 619 | } |
59df0c77 | 620 | else if (samplerate == SR_MHZ(200)) { |
ea9cfed7 UH |
621 | ret = upload_firmware(2, ctx); |
622 | ctx->num_probes = 4; | |
f78898e9 | 623 | } |
f6564c8d | 624 | |
ea9cfed7 UH |
625 | ctx->cur_samplerate = samplerate; |
626 | ctx->period_ps = 1000000000000 / samplerate; | |
627 | ctx->samples_per_event = 16 / ctx->num_probes; | |
628 | ctx->state.state = SIGMA_IDLE; | |
f6564c8d | 629 | |
e8397563 | 630 | return ret; |
28a35d8a HE |
631 | } |
632 | ||
c53d793f HE |
633 | /* |
634 | * In 100 and 200 MHz mode, only a single pin rising/falling can be | |
635 | * set as trigger. In other modes, two rising/falling triggers can be set, | |
636 | * in addition to value/mask trigger for any number of probes. | |
637 | * | |
638 | * The Sigma supports complex triggers using boolean expressions, but this | |
639 | * has not been implemented yet. | |
640 | */ | |
1b79df2f | 641 | static int configure_probes(struct sr_dev_inst *sdi, const GSList *probes) |
57bbf56b | 642 | { |
ea9cfed7 | 643 | struct context *ctx = sdi->priv; |
1b79df2f JH |
644 | const struct sr_probe *probe; |
645 | const GSList *l; | |
57bbf56b | 646 | int trigger_set = 0; |
a42aec7f | 647 | int probebit; |
57bbf56b | 648 | |
ea9cfed7 | 649 | memset(&ctx->trigger, 0, sizeof(struct sigma_trigger)); |
eec5275e | 650 | |
57bbf56b | 651 | for (l = probes; l; l = l->next) { |
1afe8989 | 652 | probe = (struct sr_probe *)l->data; |
a42aec7f | 653 | probebit = 1 << (probe->index - 1); |
57bbf56b HE |
654 | |
655 | if (!probe->enabled || !probe->trigger) | |
656 | continue; | |
657 | ||
ea9cfed7 | 658 | if (ctx->cur_samplerate >= SR_MHZ(100)) { |
c53d793f | 659 | /* Fast trigger support. */ |
ee492173 | 660 | if (trigger_set) { |
7b48d6e1 | 661 | sr_err("sigma: ASIX SIGMA only supports a single " |
133a37bf | 662 | "pin trigger in 100 and 200MHz mode."); |
e46b8fb1 | 663 | return SR_ERR; |
ee492173 HE |
664 | } |
665 | if (probe->trigger[0] == 'f') | |
ea9cfed7 | 666 | ctx->trigger.fallingmask |= probebit; |
ee492173 | 667 | else if (probe->trigger[0] == 'r') |
ea9cfed7 | 668 | ctx->trigger.risingmask |= probebit; |
ee492173 | 669 | else { |
7b48d6e1 | 670 | sr_err("sigma: ASIX SIGMA only supports " |
133a37bf UH |
671 | "rising/falling trigger in 100 " |
672 | "and 200MHz mode."); | |
e46b8fb1 | 673 | return SR_ERR; |
ee492173 | 674 | } |
57bbf56b | 675 | |
c53d793f | 676 | ++trigger_set; |
ee492173 | 677 | } else { |
c53d793f HE |
678 | /* Simple trigger support (event). */ |
679 | if (probe->trigger[0] == '1') { | |
ea9cfed7 UH |
680 | ctx->trigger.simplevalue |= probebit; |
681 | ctx->trigger.simplemask |= probebit; | |
c53d793f HE |
682 | } |
683 | else if (probe->trigger[0] == '0') { | |
ea9cfed7 UH |
684 | ctx->trigger.simplevalue &= ~probebit; |
685 | ctx->trigger.simplemask |= probebit; | |
c53d793f HE |
686 | } |
687 | else if (probe->trigger[0] == 'f') { | |
ea9cfed7 | 688 | ctx->trigger.fallingmask |= probebit; |
c53d793f HE |
689 | ++trigger_set; |
690 | } | |
691 | else if (probe->trigger[0] == 'r') { | |
ea9cfed7 | 692 | ctx->trigger.risingmask |= probebit; |
c53d793f HE |
693 | ++trigger_set; |
694 | } | |
ee492173 | 695 | |
ea9cfed7 UH |
696 | /* |
697 | * Actually, Sigma supports 2 rising/falling triggers, | |
698 | * but they are ORed and the current trigger syntax | |
699 | * does not permit ORed triggers. | |
700 | */ | |
98b8cbc1 | 701 | if (trigger_set > 1) { |
7b48d6e1 UH |
702 | sr_err("sigma: ASIX SIGMA only supports 1 " |
703 | "rising/falling triggers."); | |
e46b8fb1 | 704 | return SR_ERR; |
ee492173 | 705 | } |
ee492173 | 706 | } |
5b5ea7c6 HE |
707 | |
708 | if (trigger_set) | |
ea9cfed7 | 709 | ctx->use_triggers = 1; |
57bbf56b HE |
710 | } |
711 | ||
e46b8fb1 | 712 | return SR_OK; |
57bbf56b HE |
713 | } |
714 | ||
e7eb703f | 715 | static int hw_dev_close(int dev_index) |
28a35d8a | 716 | { |
d68e2d1a | 717 | struct sr_dev_inst *sdi; |
ea9cfed7 | 718 | struct context *ctx; |
28a35d8a | 719 | |
bb7ef793 | 720 | if (!(sdi = sr_dev_inst_get(dev_insts, dev_index))) { |
340cfac0 | 721 | sr_err("sigma: %s: sdi was NULL", __func__); |
0abee507 | 722 | return SR_ERR_BUG; |
697785d1 | 723 | } |
9be9893e | 724 | |
ea9cfed7 | 725 | if (!(ctx = sdi->priv)) { |
340cfac0 | 726 | sr_err("sigma: %s: sdi->priv was NULL", __func__); |
0abee507 | 727 | return SR_ERR_BUG; |
9be9893e | 728 | } |
697785d1 UH |
729 | |
730 | /* TODO */ | |
731 | if (sdi->status == SR_ST_ACTIVE) | |
ea9cfed7 | 732 | ftdi_usb_close(&ctx->ftdic); |
697785d1 UH |
733 | |
734 | sdi->status = SR_ST_INACTIVE; | |
735 | ||
736 | return SR_OK; | |
28a35d8a HE |
737 | } |
738 | ||
57ab7d9f | 739 | static int hw_cleanup(void) |
28a35d8a | 740 | { |
99965709 | 741 | GSList *l; |
d68e2d1a | 742 | struct sr_dev_inst *sdi; |
57ab7d9f | 743 | int ret = SR_OK; |
99965709 HE |
744 | |
745 | /* Properly close all devices. */ | |
d68e2d1a | 746 | for (l = dev_insts; l; l = l->next) { |
57ab7d9f UH |
747 | if (!(sdi = l->data)) { |
748 | /* Log error, but continue cleaning up the rest. */ | |
7b48d6e1 | 749 | sr_err("sigma: %s: sdi was NULL, continuing", __func__); |
57ab7d9f UH |
750 | ret = SR_ERR_BUG; |
751 | continue; | |
752 | } | |
d3683c42 | 753 | sr_dev_inst_free(sdi); |
99965709 | 754 | } |
d68e2d1a UH |
755 | g_slist_free(dev_insts); |
756 | dev_insts = NULL; | |
57ab7d9f UH |
757 | |
758 | return ret; | |
28a35d8a HE |
759 | } |
760 | ||
b7f578be | 761 | static const void *hw_dev_info_get(int dev_index, int dev_info_id) |
28a35d8a | 762 | { |
d68e2d1a | 763 | struct sr_dev_inst *sdi; |
ea9cfed7 | 764 | struct context *ctx; |
b7f578be | 765 | const void *info = NULL; |
28a35d8a | 766 | |
bb7ef793 | 767 | if (!(sdi = sr_dev_inst_get(dev_insts, dev_index))) { |
7b48d6e1 | 768 | sr_err("sigma: %s: sdi was NULL", __func__); |
28a35d8a HE |
769 | return NULL; |
770 | } | |
771 | ||
ea9cfed7 | 772 | ctx = sdi->priv; |
99965709 | 773 | |
bb7ef793 | 774 | switch (dev_info_id) { |
1d9a8a5f | 775 | case SR_DI_INST: |
28a35d8a HE |
776 | info = sdi; |
777 | break; | |
5a2326a7 | 778 | case SR_DI_NUM_PROBES: |
464d12c7 KS |
779 | info = GINT_TO_POINTER(NUM_PROBES); |
780 | break; | |
781 | case SR_DI_PROBE_NAMES: | |
782 | info = probe_names; | |
28a35d8a | 783 | break; |
5a2326a7 | 784 | case SR_DI_SAMPLERATES: |
28a35d8a HE |
785 | info = &samplerates; |
786 | break; | |
5a2326a7 | 787 | case SR_DI_TRIGGER_TYPES: |
57bbf56b | 788 | info = (char *)TRIGGER_TYPES; |
28a35d8a | 789 | break; |
5a2326a7 | 790 | case SR_DI_CUR_SAMPLERATE: |
ea9cfed7 | 791 | info = &ctx->cur_samplerate; |
28a35d8a HE |
792 | break; |
793 | } | |
794 | ||
795 | return info; | |
796 | } | |
797 | ||
e7eb703f | 798 | static int hw_dev_status_get(int dev_index) |
28a35d8a | 799 | { |
d68e2d1a | 800 | struct sr_dev_inst *sdi; |
28a35d8a | 801 | |
bb7ef793 | 802 | sdi = sr_dev_inst_get(dev_insts, dev_index); |
28a35d8a HE |
803 | if (sdi) |
804 | return sdi->status; | |
805 | else | |
5a2326a7 | 806 | return SR_ST_NOT_FOUND; |
28a35d8a HE |
807 | } |
808 | ||
915f7cc8 | 809 | static const int *hw_hwcap_get_all(void) |
28a35d8a | 810 | { |
ffedd0bf | 811 | return hwcaps; |
28a35d8a HE |
812 | } |
813 | ||
1b79df2f | 814 | static int hw_dev_config_set(int dev_index, int hwcap, const void *value) |
28a35d8a | 815 | { |
d68e2d1a | 816 | struct sr_dev_inst *sdi; |
ea9cfed7 | 817 | struct context *ctx; |
28a35d8a | 818 | int ret; |
f6564c8d | 819 | |
bb7ef793 | 820 | if (!(sdi = sr_dev_inst_get(dev_insts, dev_index))) |
e46b8fb1 | 821 | return SR_ERR; |
28a35d8a | 822 | |
ea9cfed7 | 823 | ctx = sdi->priv; |
99965709 | 824 | |
ffedd0bf | 825 | if (hwcap == SR_HWCAP_SAMPLERATE) { |
1b79df2f | 826 | ret = set_samplerate(sdi, *(const uint64_t *)value); |
ffedd0bf | 827 | } else if (hwcap == SR_HWCAP_PROBECONFIG) { |
99965709 | 828 | ret = configure_probes(sdi, value); |
ffedd0bf | 829 | } else if (hwcap == SR_HWCAP_LIMIT_MSEC) { |
1b79df2f | 830 | ctx->limit_msec = *(const uint64_t *)value; |
ea9cfed7 | 831 | if (ctx->limit_msec > 0) |
e46b8fb1 | 832 | ret = SR_OK; |
94ba4bd6 | 833 | else |
e46b8fb1 | 834 | ret = SR_ERR; |
ffedd0bf | 835 | } else if (hwcap == SR_HWCAP_CAPTURE_RATIO) { |
1b79df2f | 836 | ctx->capture_ratio = *(const uint64_t *)value; |
ea9cfed7 | 837 | if (ctx->capture_ratio < 0 || ctx->capture_ratio > 100) |
e46b8fb1 | 838 | ret = SR_ERR; |
94ba4bd6 | 839 | else |
e46b8fb1 | 840 | ret = SR_OK; |
28a35d8a | 841 | } else { |
e46b8fb1 | 842 | ret = SR_ERR; |
28a35d8a HE |
843 | } |
844 | ||
845 | return ret; | |
846 | } | |
847 | ||
36b1c8e6 HE |
848 | /* Software trigger to determine exact trigger position. */ |
849 | static int get_trigger_offset(uint16_t *samples, uint16_t last_sample, | |
850 | struct sigma_trigger *t) | |
851 | { | |
852 | int i; | |
853 | ||
854 | for (i = 0; i < 8; ++i) { | |
855 | if (i > 0) | |
856 | last_sample = samples[i-1]; | |
857 | ||
858 | /* Simple triggers. */ | |
859 | if ((samples[i] & t->simplemask) != t->simplevalue) | |
860 | continue; | |
861 | ||
862 | /* Rising edge. */ | |
863 | if ((last_sample & t->risingmask) != 0 || (samples[i] & | |
864 | t->risingmask) != t->risingmask) | |
865 | continue; | |
866 | ||
867 | /* Falling edge. */ | |
bdfc7a89 HE |
868 | if ((last_sample & t->fallingmask) != t->fallingmask || |
869 | (samples[i] & t->fallingmask) != 0) | |
36b1c8e6 HE |
870 | continue; |
871 | ||
872 | break; | |
873 | } | |
874 | ||
875 | /* If we did not match, return original trigger pos. */ | |
876 | return i & 0x7; | |
877 | } | |
878 | ||
28a35d8a | 879 | /* |
fefa1800 UH |
880 | * Decode chunk of 1024 bytes, 64 clusters, 7 events per cluster. |
881 | * Each event is 20ns apart, and can contain multiple samples. | |
f78898e9 HE |
882 | * |
883 | * For 200 MHz, events contain 4 samples for each channel, spread 5 ns apart. | |
884 | * For 100 MHz, events contain 2 samples for each channel, spread 10 ns apart. | |
885 | * For 50 MHz and below, events contain one sample for each channel, | |
886 | * spread 20 ns apart. | |
28a35d8a HE |
887 | */ |
888 | static int decode_chunk_ts(uint8_t *buf, uint16_t *lastts, | |
88c51afe | 889 | uint16_t *lastsample, int triggerpos, |
3cd3a20b | 890 | uint16_t limit_chunk, void *cb_data) |
28a35d8a | 891 | { |
3cd3a20b | 892 | struct sr_dev_inst *sdi = cb_data; |
ea9cfed7 | 893 | struct context *ctx = sdi->priv; |
fefa1800 | 894 | uint16_t tsdiff, ts; |
ea9cfed7 | 895 | uint16_t samples[65536 * ctx->samples_per_event]; |
b9c735a2 | 896 | struct sr_datafeed_packet packet; |
9c939c51 | 897 | struct sr_datafeed_logic logic; |
f78898e9 | 898 | int i, j, k, l, numpad, tosend; |
fefa1800 | 899 | size_t n = 0, sent = 0; |
ea9cfed7 | 900 | int clustersize = EVENTS_PER_CLUSTER * ctx->samples_per_event; |
fefa1800 | 901 | uint16_t *event; |
f78898e9 | 902 | uint16_t cur_sample; |
57bbf56b | 903 | int triggerts = -1; |
ee492173 | 904 | |
4ae1f451 | 905 | /* Check if trigger is in this chunk. */ |
ee492173 | 906 | if (triggerpos != -1) { |
ea9cfed7 | 907 | if (ctx->cur_samplerate <= SR_MHZ(50)) |
36b1c8e6 | 908 | triggerpos -= EVENTS_PER_CLUSTER - 1; |
ee492173 HE |
909 | |
910 | if (triggerpos < 0) | |
911 | triggerpos = 0; | |
57bbf56b | 912 | |
ee492173 HE |
913 | /* Find in which cluster the trigger occured. */ |
914 | triggerts = triggerpos / 7; | |
915 | } | |
28a35d8a | 916 | |
eec5275e | 917 | /* For each ts. */ |
28a35d8a | 918 | for (i = 0; i < 64; ++i) { |
fefa1800 | 919 | ts = *(uint16_t *) &buf[i * 16]; |
28a35d8a HE |
920 | tsdiff = ts - *lastts; |
921 | *lastts = ts; | |
922 | ||
88c51afe HE |
923 | /* Decode partial chunk. */ |
924 | if (limit_chunk && ts > limit_chunk) | |
e46b8fb1 | 925 | return SR_OK; |
88c51afe | 926 | |
fefa1800 | 927 | /* Pad last sample up to current point. */ |
ea9cfed7 | 928 | numpad = tsdiff * ctx->samples_per_event - clustersize; |
28a35d8a | 929 | if (numpad > 0) { |
f78898e9 HE |
930 | for (j = 0; j < numpad; ++j) |
931 | samples[j] = *lastsample; | |
932 | ||
933 | n = numpad; | |
28a35d8a HE |
934 | } |
935 | ||
57bbf56b HE |
936 | /* Send samples between previous and this timestamp to sigrok. */ |
937 | sent = 0; | |
938 | while (sent < n) { | |
939 | tosend = MIN(2048, n - sent); | |
940 | ||
5a2326a7 | 941 | packet.type = SR_DF_LOGIC; |
9c939c51 BV |
942 | packet.payload = &logic; |
943 | logic.length = tosend * sizeof(uint16_t); | |
944 | logic.unitsize = 2; | |
945 | logic.data = samples + sent; | |
3cd3a20b | 946 | sr_session_send(ctx->session_dev_id, &packet); |
28a35d8a | 947 | |
57bbf56b HE |
948 | sent += tosend; |
949 | } | |
950 | n = 0; | |
951 | ||
952 | event = (uint16_t *) &buf[i * 16 + 2]; | |
f78898e9 HE |
953 | cur_sample = 0; |
954 | ||
955 | /* For each event in cluster. */ | |
28a35d8a | 956 | for (j = 0; j < 7; ++j) { |
f78898e9 HE |
957 | |
958 | /* For each sample in event. */ | |
ea9cfed7 | 959 | for (k = 0; k < ctx->samples_per_event; ++k) { |
f78898e9 HE |
960 | cur_sample = 0; |
961 | ||
962 | /* For each probe. */ | |
ea9cfed7 | 963 | for (l = 0; l < ctx->num_probes; ++l) |
edca2c5c | 964 | cur_sample |= (!!(event[j] & (1 << (l * |
ea9cfed7 | 965 | ctx->samples_per_event + k)))) << l; |
f78898e9 HE |
966 | |
967 | samples[n++] = cur_sample; | |
28a35d8a HE |
968 | } |
969 | } | |
970 | ||
eec5275e | 971 | /* Send data up to trigger point (if triggered). */ |
fefa1800 | 972 | sent = 0; |
57bbf56b HE |
973 | if (i == triggerts) { |
974 | /* | |
36b1c8e6 HE |
975 | * Trigger is not always accurate to sample because of |
976 | * pipeline delay. However, it always triggers before | |
977 | * the actual event. We therefore look at the next | |
978 | * samples to pinpoint the exact position of the trigger. | |
57bbf56b | 979 | */ |
bdfc7a89 | 980 | tosend = get_trigger_offset(samples, *lastsample, |
ea9cfed7 | 981 | &ctx->trigger); |
57bbf56b HE |
982 | |
983 | if (tosend > 0) { | |
5a2326a7 | 984 | packet.type = SR_DF_LOGIC; |
9c939c51 BV |
985 | packet.payload = &logic; |
986 | logic.length = tosend * sizeof(uint16_t); | |
987 | logic.unitsize = 2; | |
988 | logic.data = samples; | |
3cd3a20b | 989 | sr_session_send(ctx->session_dev_id, &packet); |
57bbf56b HE |
990 | |
991 | sent += tosend; | |
992 | } | |
28a35d8a | 993 | |
5b5ea7c6 | 994 | /* Only send trigger if explicitly enabled. */ |
ea9cfed7 | 995 | if (ctx->use_triggers) { |
5a2326a7 | 996 | packet.type = SR_DF_TRIGGER; |
3cd3a20b | 997 | sr_session_send(ctx->session_dev_id, &packet); |
5b5ea7c6 | 998 | } |
28a35d8a | 999 | } |
57bbf56b | 1000 | |
eec5275e | 1001 | /* Send rest of the chunk to sigrok. */ |
57bbf56b HE |
1002 | tosend = n - sent; |
1003 | ||
abda62ce | 1004 | if (tosend > 0) { |
5a2326a7 | 1005 | packet.type = SR_DF_LOGIC; |
9c939c51 BV |
1006 | packet.payload = &logic; |
1007 | logic.length = tosend * sizeof(uint16_t); | |
1008 | logic.unitsize = 2; | |
1009 | logic.data = samples + sent; | |
3cd3a20b | 1010 | sr_session_send(ctx->session_dev_id, &packet); |
abda62ce | 1011 | } |
ee492173 HE |
1012 | |
1013 | *lastsample = samples[n - 1]; | |
28a35d8a HE |
1014 | } |
1015 | ||
e46b8fb1 | 1016 | return SR_OK; |
28a35d8a HE |
1017 | } |
1018 | ||
1f9813eb | 1019 | static int receive_data(int fd, int revents, void *cb_data) |
28a35d8a | 1020 | { |
1f9813eb | 1021 | struct sr_dev_inst *sdi = cb_data; |
ea9cfed7 | 1022 | struct context *ctx = sdi->priv; |
b9c735a2 | 1023 | struct sr_datafeed_packet packet; |
28a35d8a HE |
1024 | const int chunks_per_read = 32; |
1025 | unsigned char buf[chunks_per_read * CHUNK_SIZE]; | |
6aac7737 | 1026 | int bufsz, numchunks, i, newchunks; |
94ba4bd6 | 1027 | uint64_t running_msec; |
28a35d8a | 1028 | struct timeval tv; |
28a35d8a | 1029 | |
cb93f8a9 UH |
1030 | /* Avoid compiler warnings. */ |
1031 | (void)fd; | |
1032 | (void)revents; | |
28a35d8a | 1033 | |
805919b0 HE |
1034 | /* Get the current position. */ |
1035 | sigma_read_pos(&ctx->state.stoppos, &ctx->state.triggerpos, ctx); | |
1036 | ||
ea9cfed7 | 1037 | numchunks = (ctx->state.stoppos + 511) / 512; |
28a35d8a | 1038 | |
ea9cfed7 | 1039 | if (ctx->state.state == SIGMA_IDLE) |
805919b0 | 1040 | return TRUE; |
28a35d8a | 1041 | |
ea9cfed7 | 1042 | if (ctx->state.state == SIGMA_CAPTURE) { |
6aac7737 HE |
1043 | /* Check if the timer has expired, or memory is full. */ |
1044 | gettimeofday(&tv, 0); | |
ea9cfed7 UH |
1045 | running_msec = (tv.tv_sec - ctx->start_tv.tv_sec) * 1000 + |
1046 | (tv.tv_usec - ctx->start_tv.tv_usec) / 1000; | |
28a35d8a | 1047 | |
ea9cfed7 | 1048 | if (running_msec < ctx->limit_msec && numchunks < 32767) |
805919b0 | 1049 | return TRUE; /* While capturing... */ |
e3fff420 HE |
1050 | else |
1051 | hw_dev_acquisition_stop(sdi->index, sdi); | |
6aac7737 | 1052 | |
ea9cfed7 UH |
1053 | } else if (ctx->state.state == SIGMA_DOWNLOAD) { |
1054 | if (ctx->state.chunks_downloaded >= numchunks) { | |
6aac7737 | 1055 | /* End of samples. */ |
5a2326a7 | 1056 | packet.type = SR_DF_END; |
3cd3a20b | 1057 | sr_session_send(ctx->session_dev_id, &packet); |
6aac7737 | 1058 | |
ea9cfed7 | 1059 | ctx->state.state = SIGMA_IDLE; |
f78898e9 | 1060 | |
6aac7737 HE |
1061 | return TRUE; |
1062 | } | |
1063 | ||
1064 | newchunks = MIN(chunks_per_read, | |
ea9cfed7 | 1065 | numchunks - ctx->state.chunks_downloaded); |
28a35d8a | 1066 | |
7b48d6e1 | 1067 | sr_info("sigma: Downloading sample data: %.0f %%", |
ea9cfed7 | 1068 | 100.0 * ctx->state.chunks_downloaded / numchunks); |
28a35d8a | 1069 | |
ea9cfed7 UH |
1070 | bufsz = sigma_read_dram(ctx->state.chunks_downloaded, |
1071 | newchunks, buf, ctx); | |
719c5a93 UH |
1072 | /* TODO: Check bufsz. For now, just avoid compiler warnings. */ |
1073 | (void)bufsz; | |
28a35d8a | 1074 | |
fefa1800 | 1075 | /* Find first ts. */ |
ea9cfed7 UH |
1076 | if (ctx->state.chunks_downloaded == 0) { |
1077 | ctx->state.lastts = *(uint16_t *) buf - 1; | |
1078 | ctx->state.lastsample = 0; | |
6aac7737 | 1079 | } |
28a35d8a | 1080 | |
fefa1800 | 1081 | /* Decode chunks and send them to sigrok. */ |
28a35d8a | 1082 | for (i = 0; i < newchunks; ++i) { |
88c51afe HE |
1083 | int limit_chunk = 0; |
1084 | ||
1085 | /* The last chunk may potentially be only in part. */ | |
ea9cfed7 | 1086 | if (ctx->state.chunks_downloaded == numchunks - 1) { |
88c51afe | 1087 | /* Find the last valid timestamp */ |
ea9cfed7 | 1088 | limit_chunk = ctx->state.stoppos % 512 + ctx->state.lastts; |
88c51afe HE |
1089 | } |
1090 | ||
ea9cfed7 | 1091 | if (ctx->state.chunks_downloaded + i == ctx->state.triggerchunk) |
57bbf56b | 1092 | decode_chunk_ts(buf + (i * CHUNK_SIZE), |
ea9cfed7 UH |
1093 | &ctx->state.lastts, |
1094 | &ctx->state.lastsample, | |
1095 | ctx->state.triggerpos & 0x1ff, | |
1f9813eb | 1096 | limit_chunk, sdi); |
57bbf56b HE |
1097 | else |
1098 | decode_chunk_ts(buf + (i * CHUNK_SIZE), | |
ea9cfed7 UH |
1099 | &ctx->state.lastts, |
1100 | &ctx->state.lastsample, | |
1f9813eb | 1101 | -1, limit_chunk, sdi); |
28a35d8a | 1102 | |
ea9cfed7 | 1103 | ++ctx->state.chunks_downloaded; |
88c51afe | 1104 | } |
28a35d8a HE |
1105 | } |
1106 | ||
28a35d8a HE |
1107 | return TRUE; |
1108 | } | |
1109 | ||
c53d793f HE |
1110 | /* Build a LUT entry used by the trigger functions. */ |
1111 | static void build_lut_entry(uint16_t value, uint16_t mask, uint16_t *entry) | |
ee492173 HE |
1112 | { |
1113 | int i, j, k, bit; | |
1114 | ||
f758d074 | 1115 | /* For each quad probe. */ |
ee492173 | 1116 | for (i = 0; i < 4; ++i) { |
c53d793f | 1117 | entry[i] = 0xffff; |
ee492173 | 1118 | |
f758d074 | 1119 | /* For each bit in LUT. */ |
ee492173 HE |
1120 | for (j = 0; j < 16; ++j) |
1121 | ||
f758d074 | 1122 | /* For each probe in quad. */ |
ee492173 HE |
1123 | for (k = 0; k < 4; ++k) { |
1124 | bit = 1 << (i * 4 + k); | |
1125 | ||
c53d793f HE |
1126 | /* Set bit in entry */ |
1127 | if ((mask & bit) && | |
1128 | ((!(value & bit)) != | |
4ae1f451 | 1129 | (!(j & (1 << k))))) |
c53d793f | 1130 | entry[i] &= ~(1 << j); |
ee492173 HE |
1131 | } |
1132 | } | |
c53d793f | 1133 | } |
ee492173 | 1134 | |
c53d793f HE |
1135 | /* Add a logical function to LUT mask. */ |
1136 | static void add_trigger_function(enum triggerop oper, enum triggerfunc func, | |
1137 | int index, int neg, uint16_t *mask) | |
1138 | { | |
1139 | int i, j; | |
1140 | int x[2][2], tmp, a, b, aset, bset, rset; | |
1141 | ||
1142 | memset(x, 0, 4 * sizeof(int)); | |
1143 | ||
1144 | /* Trigger detect condition. */ | |
1145 | switch (oper) { | |
1146 | case OP_LEVEL: | |
1147 | x[0][1] = 1; | |
1148 | x[1][1] = 1; | |
1149 | break; | |
1150 | case OP_NOT: | |
1151 | x[0][0] = 1; | |
1152 | x[1][0] = 1; | |
1153 | break; | |
1154 | case OP_RISE: | |
1155 | x[0][1] = 1; | |
1156 | break; | |
1157 | case OP_FALL: | |
1158 | x[1][0] = 1; | |
1159 | break; | |
1160 | case OP_RISEFALL: | |
1161 | x[0][1] = 1; | |
1162 | x[1][0] = 1; | |
1163 | break; | |
1164 | case OP_NOTRISE: | |
1165 | x[1][1] = 1; | |
1166 | x[0][0] = 1; | |
1167 | x[1][0] = 1; | |
1168 | break; | |
1169 | case OP_NOTFALL: | |
1170 | x[1][1] = 1; | |
1171 | x[0][0] = 1; | |
1172 | x[0][1] = 1; | |
1173 | break; | |
1174 | case OP_NOTRISEFALL: | |
1175 | x[1][1] = 1; | |
1176 | x[0][0] = 1; | |
1177 | break; | |
1178 | } | |
1179 | ||
1180 | /* Transpose if neg is set. */ | |
1181 | if (neg) { | |
ea9cfed7 | 1182 | for (i = 0; i < 2; ++i) { |
c53d793f HE |
1183 | for (j = 0; j < 2; ++j) { |
1184 | tmp = x[i][j]; | |
1185 | x[i][j] = x[1-i][1-j]; | |
1186 | x[1-i][1-j] = tmp; | |
1187 | } | |
ea9cfed7 | 1188 | } |
c53d793f HE |
1189 | } |
1190 | ||
1191 | /* Update mask with function. */ | |
1192 | for (i = 0; i < 16; ++i) { | |
1193 | a = (i >> (2 * index + 0)) & 1; | |
1194 | b = (i >> (2 * index + 1)) & 1; | |
1195 | ||
1196 | aset = (*mask >> i) & 1; | |
1197 | bset = x[b][a]; | |
1198 | ||
1199 | if (func == FUNC_AND || func == FUNC_NAND) | |
1200 | rset = aset & bset; | |
1201 | else if (func == FUNC_OR || func == FUNC_NOR) | |
1202 | rset = aset | bset; | |
1203 | else if (func == FUNC_XOR || func == FUNC_NXOR) | |
1204 | rset = aset ^ bset; | |
1205 | ||
1206 | if (func == FUNC_NAND || func == FUNC_NOR || func == FUNC_NXOR) | |
1207 | rset = !rset; | |
1208 | ||
1209 | *mask &= ~(1 << i); | |
1210 | ||
1211 | if (rset) | |
1212 | *mask |= 1 << i; | |
1213 | } | |
1214 | } | |
1215 | ||
1216 | /* | |
1217 | * Build trigger LUTs used by 50 MHz and lower sample rates for supporting | |
1218 | * simple pin change and state triggers. Only two transitions (rise/fall) can be | |
1219 | * set at any time, but a full mask and value can be set (0/1). | |
1220 | */ | |
ea9cfed7 | 1221 | static int build_basic_trigger(struct triggerlut *lut, struct context *ctx) |
c53d793f HE |
1222 | { |
1223 | int i,j; | |
4ae1f451 | 1224 | uint16_t masks[2] = { 0, 0 }; |
c53d793f HE |
1225 | |
1226 | memset(lut, 0, sizeof(struct triggerlut)); | |
1227 | ||
1228 | /* Contant for simple triggers. */ | |
1229 | lut->m4 = 0xa000; | |
1230 | ||
1231 | /* Value/mask trigger support. */ | |
ea9cfed7 | 1232 | build_lut_entry(ctx->trigger.simplevalue, ctx->trigger.simplemask, |
99965709 | 1233 | lut->m2d); |
c53d793f HE |
1234 | |
1235 | /* Rise/fall trigger support. */ | |
1236 | for (i = 0, j = 0; i < 16; ++i) { | |
ea9cfed7 UH |
1237 | if (ctx->trigger.risingmask & (1 << i) || |
1238 | ctx->trigger.fallingmask & (1 << i)) | |
c53d793f HE |
1239 | masks[j++] = 1 << i; |
1240 | } | |
1241 | ||
1242 | build_lut_entry(masks[0], masks[0], lut->m0d); | |
1243 | build_lut_entry(masks[1], masks[1], lut->m1d); | |
1244 | ||
1245 | /* Add glue logic */ | |
1246 | if (masks[0] || masks[1]) { | |
1247 | /* Transition trigger. */ | |
ea9cfed7 | 1248 | if (masks[0] & ctx->trigger.risingmask) |
c53d793f | 1249 | add_trigger_function(OP_RISE, FUNC_OR, 0, 0, &lut->m3); |
ea9cfed7 | 1250 | if (masks[0] & ctx->trigger.fallingmask) |
c53d793f | 1251 | add_trigger_function(OP_FALL, FUNC_OR, 0, 0, &lut->m3); |
ea9cfed7 | 1252 | if (masks[1] & ctx->trigger.risingmask) |
c53d793f | 1253 | add_trigger_function(OP_RISE, FUNC_OR, 1, 0, &lut->m3); |
ea9cfed7 | 1254 | if (masks[1] & ctx->trigger.fallingmask) |
c53d793f HE |
1255 | add_trigger_function(OP_FALL, FUNC_OR, 1, 0, &lut->m3); |
1256 | } else { | |
1257 | /* Only value/mask trigger. */ | |
1258 | lut->m3 = 0xffff; | |
1259 | } | |
ee492173 | 1260 | |
c53d793f | 1261 | /* Triggertype: event. */ |
ee492173 HE |
1262 | lut->params.selres = 3; |
1263 | ||
e46b8fb1 | 1264 | return SR_OK; |
ee492173 HE |
1265 | } |
1266 | ||
3cd3a20b | 1267 | static int hw_dev_acquisition_start(int dev_index, void *cb_data) |
28a35d8a | 1268 | { |
d68e2d1a | 1269 | struct sr_dev_inst *sdi; |
ea9cfed7 | 1270 | struct context *ctx; |
3c36c403 HE |
1271 | struct sr_datafeed_packet *packet; |
1272 | struct sr_datafeed_header *header; | |
f366e86c | 1273 | struct sr_datafeed_meta_logic meta; |
9ddb2a12 | 1274 | struct clockselect_50 clockselect; |
82957b65 | 1275 | int frac, triggerpin, ret; |
57bbf56b HE |
1276 | uint8_t triggerselect; |
1277 | struct triggerinout triggerinout_conf; | |
ee492173 | 1278 | struct triggerlut lut; |
28a35d8a | 1279 | |
bb7ef793 | 1280 | if (!(sdi = sr_dev_inst_get(dev_insts, dev_index))) |
e46b8fb1 | 1281 | return SR_ERR; |
28a35d8a | 1282 | |
ea9cfed7 | 1283 | ctx = sdi->priv; |
28a35d8a | 1284 | |
ea9cfed7 UH |
1285 | /* If the samplerate has not been set, default to 200 kHz. */ |
1286 | if (ctx->cur_firmware == -1) { | |
82957b65 UH |
1287 | if ((ret = set_samplerate(sdi, SR_KHZ(200))) != SR_OK) |
1288 | return ret; | |
1289 | } | |
e8397563 | 1290 | |
eec5275e | 1291 | /* Enter trigger programming mode. */ |
ea9cfed7 | 1292 | sigma_set_register(WRITE_TRIGGER_SELECT1, 0x20, ctx); |
28a35d8a | 1293 | |
eec5275e | 1294 | /* 100 and 200 MHz mode. */ |
ea9cfed7 UH |
1295 | if (ctx->cur_samplerate >= SR_MHZ(100)) { |
1296 | sigma_set_register(WRITE_TRIGGER_SELECT1, 0x81, ctx); | |
57bbf56b | 1297 | |
a42aec7f HE |
1298 | /* Find which pin to trigger on from mask. */ |
1299 | for (triggerpin = 0; triggerpin < 8; ++triggerpin) | |
ea9cfed7 | 1300 | if ((ctx->trigger.risingmask | ctx->trigger.fallingmask) & |
a42aec7f HE |
1301 | (1 << triggerpin)) |
1302 | break; | |
1303 | ||
1304 | /* Set trigger pin and light LED on trigger. */ | |
1305 | triggerselect = (1 << LEDSEL1) | (triggerpin & 0x7); | |
1306 | ||
1307 | /* Default rising edge. */ | |
ea9cfed7 | 1308 | if (ctx->trigger.fallingmask) |
a42aec7f | 1309 | triggerselect |= 1 << 3; |
57bbf56b | 1310 | |
eec5275e | 1311 | /* All other modes. */ |
ea9cfed7 UH |
1312 | } else if (ctx->cur_samplerate <= SR_MHZ(50)) { |
1313 | build_basic_trigger(&lut, ctx); | |
ee492173 | 1314 | |
ea9cfed7 | 1315 | sigma_write_trigger_lut(&lut, ctx); |
57bbf56b HE |
1316 | |
1317 | triggerselect = (1 << LEDSEL1) | (1 << LEDSEL0); | |
1318 | } | |
1319 | ||
eec5275e | 1320 | /* Setup trigger in and out pins to default values. */ |
57bbf56b HE |
1321 | memset(&triggerinout_conf, 0, sizeof(struct triggerinout)); |
1322 | triggerinout_conf.trgout_bytrigger = 1; | |
1323 | triggerinout_conf.trgout_enable = 1; | |
1324 | ||
28a35d8a | 1325 | sigma_write_register(WRITE_TRIGGER_OPTION, |
57bbf56b | 1326 | (uint8_t *) &triggerinout_conf, |
ea9cfed7 | 1327 | sizeof(struct triggerinout), ctx); |
28a35d8a | 1328 | |
eec5275e | 1329 | /* Go back to normal mode. */ |
ea9cfed7 | 1330 | sigma_set_register(WRITE_TRIGGER_SELECT1, triggerselect, ctx); |
28a35d8a | 1331 | |
edca2c5c | 1332 | /* Set clock select register. */ |
ea9cfed7 | 1333 | if (ctx->cur_samplerate == SR_MHZ(200)) |
edca2c5c | 1334 | /* Enable 4 probes. */ |
ea9cfed7 UH |
1335 | sigma_set_register(WRITE_CLOCK_SELECT, 0xf0, ctx); |
1336 | else if (ctx->cur_samplerate == SR_MHZ(100)) | |
edca2c5c | 1337 | /* Enable 8 probes. */ |
ea9cfed7 | 1338 | sigma_set_register(WRITE_CLOCK_SELECT, 0x00, ctx); |
edca2c5c HE |
1339 | else { |
1340 | /* | |
9ddb2a12 | 1341 | * 50 MHz mode (or fraction thereof). Any fraction down to |
eec5275e | 1342 | * 50 MHz / 256 can be used, but is not supported by sigrok API. |
edca2c5c | 1343 | */ |
ea9cfed7 | 1344 | frac = SR_MHZ(50) / ctx->cur_samplerate - 1; |
edca2c5c | 1345 | |
9ddb2a12 UH |
1346 | clockselect.async = 0; |
1347 | clockselect.fraction = frac; | |
1348 | clockselect.disabled_probes = 0; | |
edca2c5c HE |
1349 | |
1350 | sigma_write_register(WRITE_CLOCK_SELECT, | |
9ddb2a12 | 1351 | (uint8_t *) &clockselect, |
ea9cfed7 | 1352 | sizeof(clockselect), ctx); |
edca2c5c HE |
1353 | } |
1354 | ||
fefa1800 | 1355 | /* Setup maximum post trigger time. */ |
99965709 | 1356 | sigma_set_register(WRITE_POST_TRIGGER, |
6352d030 | 1357 | (ctx->capture_ratio * 255) / 100, ctx); |
28a35d8a | 1358 | |
eec5275e | 1359 | /* Start acqusition. */ |
ea9cfed7 UH |
1360 | gettimeofday(&ctx->start_tv, 0); |
1361 | sigma_set_register(WRITE_MODE, 0x0d, ctx); | |
99965709 | 1362 | |
3cd3a20b | 1363 | ctx->session_dev_id = cb_data; |
28a35d8a | 1364 | |
3c36c403 HE |
1365 | if (!(packet = g_try_malloc(sizeof(struct sr_datafeed_packet)))) { |
1366 | sr_err("sigma: %s: packet malloc failed.", __func__); | |
1367 | return SR_ERR_MALLOC; | |
1368 | } | |
1369 | ||
1370 | if (!(header = g_try_malloc(sizeof(struct sr_datafeed_header)))) { | |
1371 | sr_err("sigma: %s: header malloc failed.", __func__); | |
1372 | return SR_ERR_MALLOC; | |
1373 | } | |
28a35d8a | 1374 | |
3c36c403 HE |
1375 | /* Send header packet to the session bus. */ |
1376 | packet->type = SR_DF_HEADER; | |
1377 | packet->payload = header; | |
1378 | header->feed_version = 1; | |
1379 | gettimeofday(&header->starttime, NULL); | |
3c36c403 | 1380 | sr_session_send(ctx->session_dev_id, packet); |
f366e86c BV |
1381 | |
1382 | /* Send metadata about the SR_DF_LOGIC packets to come. */ | |
1383 | packet->type = SR_DF_META_LOGIC; | |
1384 | packet->payload = &meta; | |
1385 | meta.samplerate = ctx->cur_samplerate; | |
1386 | meta.num_probes = ctx->num_probes; | |
1387 | sr_session_send(ctx->session_dev_id, packet); | |
1388 | ||
1389 | /* Add capture source. */ | |
1390 | sr_source_add(0, G_IO_IN, 10, receive_data, sdi); | |
1391 | ||
3c36c403 HE |
1392 | g_free(header); |
1393 | g_free(packet); | |
1394 | ||
ea9cfed7 | 1395 | ctx->state.state = SIGMA_CAPTURE; |
6aac7737 | 1396 | |
e46b8fb1 | 1397 | return SR_OK; |
28a35d8a HE |
1398 | } |
1399 | ||
3cd3a20b | 1400 | static int hw_dev_acquisition_stop(int dev_index, void *cb_data) |
28a35d8a | 1401 | { |
d68e2d1a | 1402 | struct sr_dev_inst *sdi; |
ea9cfed7 | 1403 | struct context *ctx; |
6aac7737 HE |
1404 | uint8_t modestatus; |
1405 | ||
cb93f8a9 | 1406 | /* Avoid compiler warnings. */ |
3cd3a20b | 1407 | (void)cb_data; |
28a35d8a | 1408 | |
bb7ef793 | 1409 | if (!(sdi = sr_dev_inst_get(dev_insts, dev_index))) { |
7b48d6e1 | 1410 | sr_err("sigma: %s: sdi was NULL", __func__); |
3010f21c UH |
1411 | return SR_ERR_BUG; |
1412 | } | |
1413 | ||
ea9cfed7 | 1414 | if (!(ctx = sdi->priv)) { |
7b48d6e1 | 1415 | sr_err("sigma: %s: sdi->priv was NULL", __func__); |
3010f21c UH |
1416 | return SR_ERR_BUG; |
1417 | } | |
1418 | ||
fefa1800 | 1419 | /* Stop acquisition. */ |
ea9cfed7 | 1420 | sigma_set_register(WRITE_MODE, 0x11, ctx); |
28a35d8a | 1421 | |
6aac7737 | 1422 | /* Set SDRAM Read Enable. */ |
ea9cfed7 | 1423 | sigma_set_register(WRITE_MODE, 0x02, ctx); |
6aac7737 HE |
1424 | |
1425 | /* Get the current position. */ | |
ea9cfed7 | 1426 | sigma_read_pos(&ctx->state.stoppos, &ctx->state.triggerpos, ctx); |
6aac7737 HE |
1427 | |
1428 | /* Check if trigger has fired. */ | |
ea9cfed7 | 1429 | modestatus = sigma_get_register(READ_MODE, ctx); |
3010f21c | 1430 | if (modestatus & 0x20) |
ea9cfed7 | 1431 | ctx->state.triggerchunk = ctx->state.triggerpos / 512; |
3010f21c | 1432 | else |
ea9cfed7 | 1433 | ctx->state.triggerchunk = -1; |
6aac7737 | 1434 | |
ea9cfed7 | 1435 | ctx->state.chunks_downloaded = 0; |
6aac7737 | 1436 | |
ea9cfed7 | 1437 | ctx->state.state = SIGMA_DOWNLOAD; |
3010f21c UH |
1438 | |
1439 | return SR_OK; | |
28a35d8a HE |
1440 | } |
1441 | ||
c09f0b57 | 1442 | SR_PRIV struct sr_dev_driver asix_sigma_driver_info = { |
e519ba86 | 1443 | .name = "asix-sigma", |
6352d030 | 1444 | .longname = "ASIX SIGMA/SIGMA2", |
e519ba86 UH |
1445 | .api_version = 1, |
1446 | .init = hw_init, | |
1447 | .cleanup = hw_cleanup, | |
61136ea6 | 1448 | .scan = hw_scan, |
e7eb703f UH |
1449 | .dev_open = hw_dev_open, |
1450 | .dev_close = hw_dev_close, | |
5097b0d0 | 1451 | .dev_info_get = hw_dev_info_get, |
e7eb703f | 1452 | .dev_status_get = hw_dev_status_get, |
ffedd0bf | 1453 | .hwcap_get_all = hw_hwcap_get_all, |
a9a245b4 | 1454 | .dev_config_set = hw_dev_config_set, |
6b3dfec8 UH |
1455 | .dev_acquisition_start = hw_dev_acquisition_start, |
1456 | .dev_acquisition_stop = hw_dev_acquisition_stop, | |
28a35d8a | 1457 | }; |