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scpi-pps: Don't use SCPI_CMD_REMOTE and SCPI_CMD_LOCAL for HP 66xxB devices when...
[libsigrok.git] / src / hardware / scpi-pps / profiles.c
CommitLineData
d4eabea8
BV		 1/*
2 * This file is part of the libsigrok project.
3 *
4 * Copyright (C) 2014 Bert Vermeulen <bert@biot.com>
4ee1e2f3
AG		 5 * Copyright (C) 2015 Google, Inc.
6 * (Written by Alexandru Gagniuc <mrnuke@google.com> for Google, Inc.)
7e66bf05 7 * Copyright (C) 2017,2019 Frank Stettner <frank-stettner@gmx.net>
d4eabea8
BV		 8 *
9 * This program is free software: you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation, either version 3 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program. If not, see <http://www.gnu.org/licenses/>.
21 */
22
6ec6c43b 23#include <config.h>
22c18b03 24#include <string.h>
ba464a12 25#include <strings.h>
d4eabea8
BV		 26#include "protocol.h"
27
28#define CH_IDX(x) (1 << x)
6ed709fe 29#define FREQ_DC_ONLY {0, 0, 0, 0, 0}
49a468ed
FS		 30#define NO_OVP_LIMITS {0, 0, 0, 0, 0}
31#define NO_OCP_LIMITS {0, 0, 0, 0, 0}
d4eabea8 32
5c9e56c9
AG		 33/* Agilent/Keysight N5700A series */
34static const uint32_t agilent_n5700a_devopts[] = {
e91bb0a6 35 SR_CONF_CONTINUOUS,
88e4daa9
ML		 36 SR_CONF_LIMIT_SAMPLES | SR_CONF_GET | SR_CONF_SET,
37 SR_CONF_LIMIT_MSEC | SR_CONF_GET | SR_CONF_SET,
5c9e56c9
AG		 38};
39
40static const uint32_t agilent_n5700a_devopts_cg[] = {
41 SR_CONF_OVER_VOLTAGE_PROTECTION_THRESHOLD | SR_CONF_GET | SR_CONF_SET,
42 SR_CONF_OVER_CURRENT_PROTECTION_ENABLED | SR_CONF_GET | SR_CONF_SET,
43 SR_CONF_OVER_CURRENT_PROTECTION_THRESHOLD | SR_CONF_GET | SR_CONF_SET,
da005885
UH		 44 SR_CONF_VOLTAGE | SR_CONF_GET,
45 SR_CONF_VOLTAGE_TARGET | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
46 SR_CONF_CURRENT | SR_CONF_GET,
47 SR_CONF_ENABLED | SR_CONF_GET | SR_CONF_SET,
5c9e56c9
AG		 48};
49
6cc93128 50static const struct channel_group_spec agilent_n5700a_cg[] = {
f2bbcc33 51 { "1", CH_IDX(0), PPS_OVP | PPS_OCP, SR_MQFLAG_DC },
6cc93128
AG		 52};
53
8cb5affe 54static const struct channel_spec agilent_n5767a_ch[] = {
49a468ed 55 { "1", { 0, 60, 0.0072, 3, 4 }, { 0, 25, 0.003, 3, 4 }, { 0, 1500 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS },
5c9e56c9
AG		 56};
57
6cc93128 58static const struct channel_spec agilent_n5763a_ch[] = {
49a468ed 59 { "1", { 0, 12.5, 0.0015, 3, 4 }, { 0, 120, 0.0144, 3, 4 }, { 0, 1500 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS },
5c9e56c9
AG		 60};
61
62/*
63 * TODO: OVER_CURRENT_PROTECTION_ACTIVE status can be determined by the OC bit
562a3490 64 * in STAT:QUES:EVEN?, but this is not implemented.
5c9e56c9 65 */
8cb5affe 66static const struct scpi_command agilent_n5700a_cmd[] = {
5c9e56c9
AG		 67 { SCPI_CMD_REMOTE, "SYST:COMM:RLST REM" },
68 { SCPI_CMD_LOCAL, "SYST:COMM:RLST LOC" },
69 { SCPI_CMD_GET_MEAS_VOLTAGE, ":MEAS:VOLT?" },
70 { SCPI_CMD_GET_MEAS_CURRENT, "MEAS:CURR?" },
71 { SCPI_CMD_GET_VOLTAGE_TARGET, ":SOUR:VOLT?" },
72 { SCPI_CMD_SET_VOLTAGE_TARGET, ":SOUR:VOLT %.6f" },
73 { SCPI_CMD_GET_CURRENT_LIMIT, ":SOUR:CURR?" },
74 { SCPI_CMD_SET_CURRENT_LIMIT, ":SOUR:CURR %.6f" },
75 { SCPI_CMD_GET_OUTPUT_ENABLED, ":OUTP:STAT?" },
76 { SCPI_CMD_SET_OUTPUT_ENABLE, ":OUTP ON" },
77 { SCPI_CMD_SET_OUTPUT_DISABLE, ":OUTP OFF" },
78 { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_THRESHOLD, ":VOLT:PROT?" },
79 { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_THRESHOLD, ":VOLT:PROT %.6f" },
80 { SCPI_CMD_GET_OVER_CURRENT_PROTECTION_ENABLED, ":CURR:PROT:STAT?" },
81 { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_ENABLE, ":CURR:PROT:STAT ON?"},
82 { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_DISABLE, ":CURR:PROT:STAT OFF?"},
562a3490 83 /* Current limit (CC mode) and OCP are set using the same command. */
5c9e56c9
AG		 84 { SCPI_CMD_GET_OVER_CURRENT_PROTECTION_THRESHOLD, ":SOUR:CURR?" },
85 { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_THRESHOLD, ":SOUR:CURR %.6f" },
91ef511d 86 ALL_ZERO
5c9e56c9
AG		 87};
88
c3bfb959
MW		 89/* BK Precision 9130 series */
90static const uint32_t bk_9130_devopts[] = {
91 SR_CONF_CONTINUOUS,
92 SR_CONF_LIMIT_SAMPLES | SR_CONF_GET | SR_CONF_SET,
93 SR_CONF_LIMIT_MSEC | SR_CONF_GET | SR_CONF_SET,
94};
95
96static const uint32_t bk_9130_devopts_cg[] = {
97 SR_CONF_OVER_VOLTAGE_PROTECTION_THRESHOLD | SR_CONF_GET | SR_CONF_SET,
98 SR_CONF_VOLTAGE | SR_CONF_GET,
99 SR_CONF_VOLTAGE_TARGET | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
100 SR_CONF_CURRENT | SR_CONF_GET,
101 SR_CONF_CURRENT_LIMIT | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
102 SR_CONF_ENABLED | SR_CONF_GET | SR_CONF_SET,
103};
104
105static const struct channel_spec bk_9130_ch[] = {
106 { "1", { 0, 30, 0.001, 3, 3 }, { 0, 3, 0.001, 3, 3 }, { 0, 90, 0, 3, 3 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS },
107 { "2", { 0, 30, 0.001, 3, 3 }, { 0, 3, 0.001, 3, 3 }, { 0, 90, 0, 3, 3 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS },
108 { "3", { 0, 5, 0.001, 3, 3 }, { 0, 3, 0.001, 3, 3 }, { 0, 15, 0, 3, 3 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS },
109};
110
111static const struct channel_group_spec bk_9130_cg[] = {
f2bbcc33
FS		 112 { "1", CH_IDX(0), PPS_OVP, SR_MQFLAG_DC },
113 { "2", CH_IDX(1), PPS_OVP, SR_MQFLAG_DC },
114 { "3", CH_IDX(2), PPS_OVP, SR_MQFLAG_DC },
c3bfb959
MW		 115};
116
117static const struct scpi_command bk_9130_cmd[] = {
118 { SCPI_CMD_REMOTE, "SYST:REMOTE" },
119 { SCPI_CMD_LOCAL, "SYST:LOCAL" },
120 { SCPI_CMD_SELECT_CHANNEL, ":INST:NSEL %s" },
121 { SCPI_CMD_GET_MEAS_VOLTAGE, ":MEAS:VOLT?" },
122 { SCPI_CMD_GET_MEAS_CURRENT, ":MEAS:CURR?" },
123 { SCPI_CMD_GET_MEAS_POWER, ":MEAS:POWER?" },
124 { SCPI_CMD_GET_VOLTAGE_TARGET, ":SOUR:VOLT?" },
125 { SCPI_CMD_SET_VOLTAGE_TARGET, ":SOUR:VOLT %.6f" },
126 { SCPI_CMD_GET_CURRENT_LIMIT, ":SOUR:CURR?" },
127 { SCPI_CMD_SET_CURRENT_LIMIT, ":SOUR:CURR %.6f" },
128 { SCPI_CMD_GET_OUTPUT_ENABLED, ":OUTP?" },
129 { SCPI_CMD_SET_OUTPUT_ENABLE, ":OUTP 1" },
130 { SCPI_CMD_SET_OUTPUT_DISABLE, ":OUTP 0" },
131 { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_THRESHOLD, ":SOUR:VOLT:PROT?" },
132 { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_THRESHOLD, ":SOUR:VOLT:PROT %.6f" },
133 ALL_ZERO
134};
135
4ee1e2f3
AG		 136/* Chroma 61600 series AC source */
137static const uint32_t chroma_61604_devopts[] = {
e91bb0a6 138 SR_CONF_CONTINUOUS,
88e4daa9
ML		 139 SR_CONF_LIMIT_SAMPLES | SR_CONF_GET | SR_CONF_SET,
140 SR_CONF_LIMIT_MSEC | SR_CONF_GET | SR_CONF_SET,
4ee1e2f3
AG		 141};
142
143static const uint32_t chroma_61604_devopts_cg[] = {
144 SR_CONF_OVER_VOLTAGE_PROTECTION_THRESHOLD | SR_CONF_GET | SR_CONF_SET,
145 SR_CONF_OVER_CURRENT_PROTECTION_THRESHOLD | SR_CONF_GET | SR_CONF_SET,
da005885
UH		 146 SR_CONF_VOLTAGE | SR_CONF_GET,
147 SR_CONF_VOLTAGE_TARGET | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
6c0c9dd2
AG		 148 SR_CONF_OUTPUT_FREQUENCY | SR_CONF_GET,
149 SR_CONF_OUTPUT_FREQUENCY_TARGET | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
da005885
UH		 150 SR_CONF_CURRENT | SR_CONF_GET,
151 SR_CONF_ENABLED | SR_CONF_GET | SR_CONF_SET,
4ee1e2f3
AG		 152};
153
8cb5affe 154static const struct channel_spec chroma_61604_ch[] = {
49a468ed 155 { "1", { 0, 300, 0.1, 1, 1 }, { 0, 16, 0.1, 2, 2 }, { 0, 2000, 0, 1, 1 }, { 1.0, 1000.0, 0.01 }, NO_OVP_LIMITS, NO_OCP_LIMITS },
4ee1e2f3
AG		 156};
157
8cb5affe 158static const struct channel_group_spec chroma_61604_cg[] = {
f2bbcc33 159 { "1", CH_IDX(0), PPS_OVP | PPS_OCP, SR_MQFLAG_AC },
4ee1e2f3
AG		 160};
161
8cb5affe 162static const struct scpi_command chroma_61604_cmd[] = {
4ee1e2f3
AG		 163 { SCPI_CMD_REMOTE, "SYST:REM" },
164 { SCPI_CMD_LOCAL, "SYST:LOC" },
165 { SCPI_CMD_GET_MEAS_VOLTAGE, ":FETC:VOLT:ACDC?" },
6c0c9dd2 166 { SCPI_CMD_GET_MEAS_FREQUENCY, ":FETC:FREQ?" },
4ee1e2f3
AG		 167 { SCPI_CMD_GET_MEAS_CURRENT, ":FETC:CURR:AC?" },
168 { SCPI_CMD_GET_MEAS_POWER, ":FETC:POW:AC?" },
169 { SCPI_CMD_GET_VOLTAGE_TARGET, ":SOUR:VOLT:AC?" },
170 { SCPI_CMD_SET_VOLTAGE_TARGET, ":SOUR:VOLT:AC %.1f" },
6c0c9dd2
AG		 171 { SCPI_CMD_GET_FREQUENCY_TARGET, ":SOUR:FREQ?" },
172 { SCPI_CMD_SET_FREQUENCY_TARGET, ":SOUR:FREQ %.2f" },
4ee1e2f3
AG		 173 { SCPI_CMD_GET_OUTPUT_ENABLED, ":OUTP?" },
174 { SCPI_CMD_SET_OUTPUT_ENABLE, ":OUTP ON" },
175 { SCPI_CMD_SET_OUTPUT_DISABLE, ":OUTP OFF" },
176 { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_THRESHOLD, ":SOUR:VOLT:LIM:AC?" },
177 { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_THRESHOLD, ":SOUR:VOLT:LIM:AC %.1f" },
562a3490 178 /* This is not a current limit mode. It is overcurrent protection. */
4ee1e2f3
AG		 179 { SCPI_CMD_GET_OVER_CURRENT_PROTECTION_THRESHOLD, ":SOUR:CURR:LIM?" },
180 { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_THRESHOLD, ":SOUR:CURR:LIM %.2f" },
91ef511d 181 ALL_ZERO
4ee1e2f3
AG		 182};
183
5281993e 184/* Chroma 62000 series DC source */
5281993e 185static const uint32_t chroma_62000_devopts[] = {
e91bb0a6 186 SR_CONF_CONTINUOUS,
88e4daa9
ML		 187 SR_CONF_LIMIT_SAMPLES | SR_CONF_GET | SR_CONF_SET,
188 SR_CONF_LIMIT_MSEC | SR_CONF_GET | SR_CONF_SET,
5281993e
AG		 189};
190
191static const uint32_t chroma_62000_devopts_cg[] = {
192 SR_CONF_OVER_VOLTAGE_PROTECTION_THRESHOLD | SR_CONF_GET | SR_CONF_SET,
193 SR_CONF_OVER_CURRENT_PROTECTION_THRESHOLD | SR_CONF_GET | SR_CONF_SET,
194 SR_CONF_VOLTAGE | SR_CONF_GET,
195 SR_CONF_VOLTAGE_TARGET | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
196 SR_CONF_CURRENT | SR_CONF_GET,
197 SR_CONF_CURRENT_LIMIT | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
198 SR_CONF_ENABLED | SR_CONF_GET | SR_CONF_SET,
199};
200
5281993e 201static const struct channel_group_spec chroma_62000_cg[] = {
f2bbcc33 202 { "1", CH_IDX(0), PPS_OVP | PPS_OCP, SR_MQFLAG_DC },
5281993e
AG		 203};
204
205static const struct scpi_command chroma_62000_cmd[] = {
206 { SCPI_CMD_REMOTE, ":CONF:REM ON" },
207 { SCPI_CMD_LOCAL, ":CONF:REM OFF" },
208 { SCPI_CMD_BEEPER, ":CONF:BEEP?" },
209 { SCPI_CMD_BEEPER_ENABLE, ":CONF:BEEP ON" },
210 { SCPI_CMD_BEEPER_DISABLE, ":CONF:BEEP OFF" },
211 { SCPI_CMD_GET_MEAS_VOLTAGE, ":MEAS:VOLT?" },
212 { SCPI_CMD_GET_MEAS_CURRENT, ":MEAS:CURR?" },
213 { SCPI_CMD_GET_MEAS_POWER, ":MEAS:POW?" },
214 { SCPI_CMD_GET_VOLTAGE_TARGET, ":SOUR:VOLT?" },
215 { SCPI_CMD_SET_VOLTAGE_TARGET, ":SOUR:VOLT %.2f" },
216 { SCPI_CMD_GET_CURRENT_LIMIT, ":SOUR:CURR?" },
217 { SCPI_CMD_SET_CURRENT_LIMIT, ":SOUR:CURR %.6f" },
218 { SCPI_CMD_GET_OUTPUT_ENABLED, ":CONF:OUTP?" },
219 { SCPI_CMD_SET_OUTPUT_ENABLE, ":CONF:OUTP ON" },
220 { SCPI_CMD_SET_OUTPUT_DISABLE, ":CONF:OUTP OFF" },
221 { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_THRESHOLD, ":SOUR:VOLT:PROT:HIGH?" },
222 { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_THRESHOLD, ":SOUR:VOLT:PROT:HIGH %.6f" },
223 { SCPI_CMD_GET_OVER_CURRENT_PROTECTION_THRESHOLD, ":SOUR:CURR:PROT:HIGH?" },
224 { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_THRESHOLD, ":SOUR:CURR:PROT:HIGH %.6f" },
91ef511d 225 ALL_ZERO
5281993e
AG		 226};
227
9a5185c7
AG		 228static int chroma_62000p_probe_channels(struct sr_dev_inst *sdi,
229 struct sr_scpi_hw_info *hw_info,
230 struct channel_spec **channels, unsigned int *num_channels,
231 struct channel_group_spec **channel_groups,
232 unsigned int *num_channel_groups)
233{
6ed709fe 234 unsigned int volts, amps, watts;
9a5185c7
AG		 235 struct channel_spec *channel;
236
237 (void)sdi;
238
6ed709fe
AJ		 239 sscanf(hw_info->model, "620%uP-%u-%u", &watts, &volts, &amps);
240 watts *= 100;
241 sr_dbg("Found device rated for %d V, %d A and %d W", volts, amps, watts);
9a5185c7
AG		 242
243 if (volts > 600) {
244 sr_err("Probed max voltage of %u V is out of spec.", volts);
245 return SR_ERR_BUG;
246 }
247
6ed709fe 248 if (amps > 120) {
9a5185c7
AG		 249 sr_err("Probed max current of %u A is out of spec.", amps);
250 return SR_ERR_BUG;
251 }
252
6ed709fe
AJ		 253 if (watts > 5000) {
254 sr_err("Probed max power of %u W is out of spec.", watts);
255 return SR_ERR_BUG;
256 }
257
9a5185c7
AG		 258 channel = g_malloc0(sizeof(struct channel_spec));
259 channel->name = "1";
6ed709fe 260 channel->voltage[0] = channel->current[0] = channel->power[0] = 0.0;
bcee1299
UH		 261 channel->voltage[1] = volts;
262 channel->current[1] = amps;
263 channel->power[1] = watts;
9a5185c7 264 channel->voltage[2] = channel->current[2] = 0.01;
6ed709fe
AJ		 265 channel->voltage[3] = channel->voltage[4] = 3;
266 channel->current[3] = channel->current[4] = 4;
9a5185c7
AG		 267 *channels = channel;
268 *num_channels = 1;
269
270 *channel_groups = g_malloc(sizeof(struct channel_group_spec));
271 **channel_groups = chroma_62000_cg[0];
272 *num_channel_groups = 1;
273
274 return SR_OK;
275}
276
319fe9ce
UH		 277/* Rigol DP700 series */
278static const uint32_t rigol_dp700_devopts[] = {
279 SR_CONF_CONTINUOUS,
88e4daa9
ML		 280 SR_CONF_LIMIT_SAMPLES | SR_CONF_GET | SR_CONF_SET,
281 SR_CONF_LIMIT_MSEC | SR_CONF_GET | SR_CONF_SET,
319fe9ce
UH		 282};
283
284static const uint32_t rigol_dp700_devopts_cg[] = {
285 SR_CONF_REGULATION | SR_CONF_GET,
286 SR_CONF_OVER_VOLTAGE_PROTECTION_ENABLED | SR_CONF_GET | SR_CONF_SET,
287 SR_CONF_OVER_VOLTAGE_PROTECTION_ACTIVE | SR_CONF_GET,
d828b05e 288 SR_CONF_OVER_VOLTAGE_PROTECTION_THRESHOLD | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
319fe9ce
UH		 289 SR_CONF_OVER_CURRENT_PROTECTION_ENABLED | SR_CONF_GET | SR_CONF_SET,
290 SR_CONF_OVER_CURRENT_PROTECTION_ACTIVE | SR_CONF_GET,
d828b05e 291 SR_CONF_OVER_CURRENT_PROTECTION_THRESHOLD | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
319fe9ce
UH		 292 SR_CONF_VOLTAGE | SR_CONF_GET,
293 SR_CONF_VOLTAGE_TARGET | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
294 SR_CONF_CURRENT | SR_CONF_GET,
295 SR_CONF_CURRENT_LIMIT | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
296 SR_CONF_ENABLED | SR_CONF_GET | SR_CONF_SET,
297};
298
299static const struct channel_spec rigol_dp711_ch[] = {
d828b05e 300 { "1", { 0, 30, 0.01, 3, 3 }, { 0, 5, 0.01, 3, 3 }, { 0, 150, 0, 3, 3 }, FREQ_DC_ONLY, { 0.01, 33, 0.01}, { 0.01, 5.5, 0.01 } },
319fe9ce
UH		 301};
302
303static const struct channel_spec rigol_dp712_ch[] = {
d828b05e 304 { "1", { 0, 50, 0.01, 3, 3 }, { 0, 3, 0.01, 3, 3 }, { 0, 150, 0, 3, 3 }, FREQ_DC_ONLY, { 0.01, 55, 0.01}, { 0.01, 3.3, 0.01 } },
319fe9ce
UH		 305};
306
307static const struct channel_group_spec rigol_dp700_cg[] = {
f2bbcc33 308 { "1", CH_IDX(0), PPS_OVP | PPS_OCP, SR_MQFLAG_DC },
319fe9ce
UH		 309};
310
311/* Same as the DP800 series, except for the missing :SYST:OTP* commands. */
312static const struct scpi_command rigol_dp700_cmd[] = {
313 { SCPI_CMD_REMOTE, "SYST:REMOTE" },
314 { SCPI_CMD_LOCAL, "SYST:LOCAL" },
315 { SCPI_CMD_BEEPER, "SYST:BEEP:STAT?" },
316 { SCPI_CMD_BEEPER_ENABLE, "SYST:BEEP:STAT ON" },
317 { SCPI_CMD_BEEPER_DISABLE, "SYST:BEEP:STAT OFF" },
318 { SCPI_CMD_SELECT_CHANNEL, ":INST:NSEL %s" },
319 { SCPI_CMD_GET_MEAS_VOLTAGE, ":MEAS:VOLT?" },
320 { SCPI_CMD_GET_MEAS_CURRENT, ":MEAS:CURR?" },
321 { SCPI_CMD_GET_MEAS_POWER, ":MEAS:POWE?" },
322 { SCPI_CMD_GET_VOLTAGE_TARGET, ":SOUR:VOLT?" },
323 { SCPI_CMD_SET_VOLTAGE_TARGET, ":SOUR:VOLT %.6f" },
324 { SCPI_CMD_GET_CURRENT_LIMIT, ":SOUR:CURR?" },
325 { SCPI_CMD_SET_CURRENT_LIMIT, ":SOUR:CURR %.6f" },
326 { SCPI_CMD_GET_OUTPUT_ENABLED, ":OUTP?" },
327 { SCPI_CMD_SET_OUTPUT_ENABLE, ":OUTP ON" },
328 { SCPI_CMD_SET_OUTPUT_DISABLE, ":OUTP OFF" },
329 { SCPI_CMD_GET_OUTPUT_REGULATION, ":OUTP:MODE?" },
330 { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_ENABLED, ":OUTP:OVP?" },
331 { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_ENABLE, ":OUTP:OVP ON" },
332 { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_DISABLE, ":OUTP:OVP OFF" },
333 { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_ACTIVE, ":OUTP:OVP:QUES?" },
334 { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_THRESHOLD, ":OUTP:OVP:VAL?" },
335 { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_THRESHOLD, ":OUTP:OVP:VAL %.6f" },
336 { SCPI_CMD_GET_OVER_CURRENT_PROTECTION_ENABLED, ":OUTP:OCP?" },
337 { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_ENABLE, ":OUTP:OCP:STAT ON" },
338 { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_DISABLE, ":OUTP:OCP:STAT OFF" },
339 { SCPI_CMD_GET_OVER_CURRENT_PROTECTION_ACTIVE, ":OUTP:OCP:QUES?" },
340 { SCPI_CMD_GET_OVER_CURRENT_PROTECTION_THRESHOLD, ":OUTP:OCP:VAL?" },
341 { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_THRESHOLD, ":OUTP:OCP:VAL %.6f" },
342 ALL_ZERO
343};
344
d4eabea8 345/* Rigol DP800 series */
584560f1 346static const uint32_t rigol_dp800_devopts[] = {
e91bb0a6 347 SR_CONF_CONTINUOUS,
5827f61b 348 SR_CONF_OVER_TEMPERATURE_PROTECTION | SR_CONF_GET | SR_CONF_SET,
88e4daa9
ML		 349 SR_CONF_LIMIT_SAMPLES | SR_CONF_GET | SR_CONF_SET,
350 SR_CONF_LIMIT_MSEC | SR_CONF_GET | SR_CONF_SET,
d4eabea8
BV		 351};
352
584560f1 353static const uint32_t rigol_dp800_devopts_cg[] = {
7a0b98b5 354 SR_CONF_REGULATION | SR_CONF_GET,
5827f61b
BV		 355 SR_CONF_OVER_VOLTAGE_PROTECTION_ENABLED | SR_CONF_GET | SR_CONF_SET,
356 SR_CONF_OVER_VOLTAGE_PROTECTION_ACTIVE | SR_CONF_GET,
357 SR_CONF_OVER_VOLTAGE_PROTECTION_THRESHOLD | SR_CONF_GET | SR_CONF_SET,
358 SR_CONF_OVER_CURRENT_PROTECTION_ENABLED | SR_CONF_GET | SR_CONF_SET,
359 SR_CONF_OVER_CURRENT_PROTECTION_ACTIVE | SR_CONF_GET,
360 SR_CONF_OVER_CURRENT_PROTECTION_THRESHOLD | SR_CONF_GET | SR_CONF_SET,
7a0b98b5
AJ		 361 SR_CONF_VOLTAGE | SR_CONF_GET,
362 SR_CONF_VOLTAGE_TARGET | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
363 SR_CONF_CURRENT | SR_CONF_GET,
364 SR_CONF_CURRENT_LIMIT | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
365 SR_CONF_ENABLED | SR_CONF_GET | SR_CONF_SET,
d4eabea8
BV		 366};
367
8cb5affe 368static const struct channel_spec rigol_dp821a_ch[] = {
49a468ed
FS		 369 { "1", { 0, 60, 0.001, 3, 3 }, { 0, 1, 0.0001, 4, 4 }, { 0, 60, 0, 3, 4 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS },
370 { "2", { 0, 8, 0.001, 3, 3 }, { 0, 10, 0.001, 3, 3 }, { 0, 80, 0, 3, 3 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS },
cfcdf576
ML		 371};
372
8cb5affe 373static const struct channel_spec rigol_dp831_ch[] = {
49a468ed
FS		 374 { "1", { 0, 8, 0.001, 3, 4 }, { 0, 5, 0.0003, 3, 4 }, { 0, 40, 0, 3, 4 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS },
375 { "2", { 0, 30, 0.001, 3, 4 }, { 0, 2, 0.0001, 3, 4 }, { 0, 60, 0, 3, 4 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS },
376 { "3", { 0, -30, 0.001, 3, 4 }, { 0, 2, 0.0001, 3, 4 }, { 0, 60, 0, 3, 4 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS },
d4eabea8
BV		 377};
378
8cb5affe 379static const struct channel_spec rigol_dp832_ch[] = {
49a468ed
FS		 380 { "1", { 0, 30, 0.001, 3, 4 }, { 0, 3, 0.001, 3, 4 }, { 0, 90, 0, 3, 4 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS },
381 { "2", { 0, 30, 0.001, 3, 4 }, { 0, 3, 0.001, 3, 4 }, { 0, 90, 0, 3, 4 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS },
382 { "3", { 0, 5, 0.001, 3, 4 }, { 0, 3, 0.001, 3, 4 }, { 0, 90, 0, 3, 4 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS },
3222ee10
BV		 383};
384
8cb5affe 385static const struct channel_group_spec rigol_dp820_cg[] = {
f2bbcc33
FS		 386 { "1", CH_IDX(0), PPS_OVP | PPS_OCP, SR_MQFLAG_DC },
387 { "2", CH_IDX(1), PPS_OVP | PPS_OCP, SR_MQFLAG_DC },
cfcdf576
ML		 388};
389
8cb5affe 390static const struct channel_group_spec rigol_dp830_cg[] = {
f2bbcc33
FS		 391 { "1", CH_IDX(0), PPS_OVP | PPS_OCP, SR_MQFLAG_DC },
392 { "2", CH_IDX(1), PPS_OVP | PPS_OCP, SR_MQFLAG_DC },
393 { "3", CH_IDX(2), PPS_OVP | PPS_OCP, SR_MQFLAG_DC },
d4eabea8
BV		 394};
395
8cb5affe 396static const struct scpi_command rigol_dp800_cmd[] = {
60475cd7
BV		 397 { SCPI_CMD_REMOTE, "SYST:REMOTE" },
398 { SCPI_CMD_LOCAL, "SYST:LOCAL" },
ee2860ee
BV		 399 { SCPI_CMD_BEEPER, "SYST:BEEP:STAT?" },
400 { SCPI_CMD_BEEPER_ENABLE, "SYST:BEEP:STAT ON" },
401 { SCPI_CMD_BEEPER_DISABLE, "SYST:BEEP:STAT OFF" },
60475cd7
BV		 402 { SCPI_CMD_SELECT_CHANNEL, ":INST:NSEL %s" },
403 { SCPI_CMD_GET_MEAS_VOLTAGE, ":MEAS:VOLT?" },
404 { SCPI_CMD_GET_MEAS_CURRENT, ":MEAS:CURR?" },
405 { SCPI_CMD_GET_MEAS_POWER, ":MEAS:POWE?" },
406 { SCPI_CMD_GET_VOLTAGE_TARGET, ":SOUR:VOLT?" },
407 { SCPI_CMD_SET_VOLTAGE_TARGET, ":SOUR:VOLT %.6f" },
408 { SCPI_CMD_GET_CURRENT_LIMIT, ":SOUR:CURR?" },
409 { SCPI_CMD_SET_CURRENT_LIMIT, ":SOUR:CURR %.6f" },
410 { SCPI_CMD_GET_OUTPUT_ENABLED, ":OUTP?" },
411 { SCPI_CMD_SET_OUTPUT_ENABLE, ":OUTP ON" },
412 { SCPI_CMD_SET_OUTPUT_DISABLE, ":OUTP OFF" },
413 { SCPI_CMD_GET_OUTPUT_REGULATION, ":OUTP:MODE?" },
d4eabea8 414 { SCPI_CMD_GET_OVER_TEMPERATURE_PROTECTION, ":SYST:OTP?" },
53a81803
BV		 415 { SCPI_CMD_SET_OVER_TEMPERATURE_PROTECTION_ENABLE, ":SYST:OTP ON" },
416 { SCPI_CMD_SET_OVER_TEMPERATURE_PROTECTION_DISABLE, ":SYST:OTP OFF" },
60475cd7
BV		 417 { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_ENABLED, ":OUTP:OVP?" },
418 { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_ENABLE, ":OUTP:OVP ON" },
419 { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_DISABLE, ":OUTP:OVP OFF" },
420 { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_ACTIVE, ":OUTP:OVP:QUES?" },
421 { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_THRESHOLD, ":OUTP:OVP:VAL?" },
422 { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_THRESHOLD, ":OUTP:OVP:VAL %.6f" },
423 { SCPI_CMD_GET_OVER_CURRENT_PROTECTION_ENABLED, ":OUTP:OCP?" },
424 { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_ENABLE, ":OUTP:OCP:STAT ON" },
425 { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_DISABLE, ":OUTP:OCP:STAT OFF" },
426 { SCPI_CMD_GET_OVER_CURRENT_PROTECTION_ACTIVE, ":OUTP:OCP:QUES?" },
427 { SCPI_CMD_GET_OVER_CURRENT_PROTECTION_THRESHOLD, ":OUTP:OCP:VAL?" },
428 { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_THRESHOLD, ":OUTP:OCP:VAL %.6f" },
91ef511d 429 ALL_ZERO
d4eabea8
BV		 430};
431
dbc519f7 432/* HP 663xA series */
e76a3575
AG		 433static const uint32_t hp_6630a_devopts[] = {
434 SR_CONF_CONTINUOUS,
88e4daa9
ML		 435 SR_CONF_LIMIT_SAMPLES | SR_CONF_GET | SR_CONF_SET,
436 SR_CONF_LIMIT_MSEC | SR_CONF_GET | SR_CONF_SET,
7c517d02
FS		 437};
438
439static const uint32_t hp_6630a_devopts_cg[] = {
e76a3575
AG		 440 SR_CONF_ENABLED | SR_CONF_SET,
441 SR_CONF_VOLTAGE | SR_CONF_GET,
442 SR_CONF_CURRENT | SR_CONF_GET,
443 SR_CONF_VOLTAGE_TARGET | SR_CONF_SET | SR_CONF_LIST,
444 SR_CONF_CURRENT_LIMIT | SR_CONF_SET | SR_CONF_LIST,
f083ae63 445 SR_CONF_OVER_VOLTAGE_PROTECTION_ACTIVE | SR_CONF_GET,
49a468ed 446 SR_CONF_OVER_VOLTAGE_PROTECTION_THRESHOLD | SR_CONF_SET | SR_CONF_LIST,
e76a3575 447 SR_CONF_OVER_CURRENT_PROTECTION_ENABLED | SR_CONF_SET,
f083ae63
FS		 448 SR_CONF_OVER_CURRENT_PROTECTION_ACTIVE | SR_CONF_GET,
449 SR_CONF_OVER_TEMPERATURE_PROTECTION_ACTIVE | SR_CONF_GET,
0ad7074c 450 SR_CONF_REGULATION | SR_CONF_GET,
e76a3575
AG		 451};
452
5ce427c7
FS		 453static const struct channel_spec hp_6632a_ch[] = {
454 { "1", { 0, 20.475, 0.005, 3, 4 }, { 0, 5.1188, 0.00125, 4, 5 }, { 0, 104.80743 }, FREQ_DC_ONLY, { 0, 22, 0.1 }, NO_OCP_LIMITS },
455};
456
dbc519f7
FS		 457static const struct channel_spec hp_6633a_ch[] = {
458 { "1", { 0, 51.188, 0.0125, 3, 4 }, { 0, 2.0475, 0.0005, 4, 5 }, { 0, 104.80743 }, FREQ_DC_ONLY, { 0, 55, 0.25 }, NO_OCP_LIMITS },
459};
460
5ce427c7
FS		 461static const struct channel_spec hp_6634a_ch[] = {
462 { "1", { 0, 102.38, 0.025, 3, 4 }, { 0, 1.0238, 0.00025, 4, 5 }, { 0, 104.81664 }, FREQ_DC_ONLY, { 0, 110, 0.5 }, NO_OCP_LIMITS },
463};
464
dbc519f7
FS		 465static const struct channel_group_spec hp_6630a_cg[] = {
466 { "1", CH_IDX(0), PPS_OVP | PPS_OCP, SR_MQFLAG_DC },
467};
468
469static const struct scpi_command hp_6630a_cmd[] = {
470 { SCPI_CMD_SET_OUTPUT_ENABLE, "OUT 1" },
471 { SCPI_CMD_SET_OUTPUT_DISABLE, "OUT 0" },
472 { SCPI_CMD_GET_MEAS_VOLTAGE, "VOUT?" },
473 { SCPI_CMD_GET_MEAS_CURRENT, "IOUT?" },
474 { SCPI_CMD_SET_VOLTAGE_TARGET, "VSET %.4f" },
475 { SCPI_CMD_SET_CURRENT_LIMIT, "ISET %.4f" },
f083ae63
FS		 476 { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_ACTIVE, "STS?" },
477 { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_THRESHOLD, "OVSET %.4f" },
dbc519f7
FS		 478 { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_ENABLE, "OCP 1" },
479 { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_DISABLE, "OCP 0" },
f083ae63
FS		 480 { SCPI_CMD_GET_OVER_CURRENT_PROTECTION_ACTIVE, "STS?" },
481 { SCPI_CMD_GET_OVER_TEMPERATURE_PROTECTION_ACTIVE, "STS?" },
0ad7074c 482 { SCPI_CMD_GET_OUTPUT_REGULATION, "STS?" },
dbc519f7
FS		 483 ALL_ZERO
484};
485
fdf03652
FS		 486static int hp_6630a_init_aquisition(const struct sr_dev_inst *sdi)
487{
488 struct sr_scpi_dev_inst *scpi;
489 int ret;
490
491 scpi = sdi->conn;
492
493 /*
494 * Monitor CV (1), CC+ (2), UR (4), OVP (8), OTP (16), OCP (64) and
495 * CC- (256) bits of the Status Register for the FAULT? query.
496 */
497 ret = sr_scpi_send(scpi, "UNMASK 607");
498 if (ret != SR_OK)
499 return ret;
500
501 return SR_OK;
502}
503
504static int hp_6630a_update_status(const struct sr_dev_inst *sdi)
505{
506 struct sr_scpi_dev_inst *scpi;
507 int ret;
508 int fault;
509 gboolean cv, cc_pos, unreg, cc_neg;
510 gboolean regulation_changed;
511 char *regulation;
512
513 scpi = sdi->conn;
514
515 /*
516 * Use the FAULT register (only 0->1 transitions), this way multiple set
517 * regulation bits in the STS/ASTS registers are ignored. In rare cases
518 * we will miss some changes (1->0 transitions, e.g. no regulation at all),
519 * but SPS/ASPS doesn't work either, unless all states are stored and
520 * compared to the states in STS/ASTS.
521 * TODO: Use SPoll or SRQ when SCPI over GPIB is used.
522 */
523 ret = sr_scpi_get_int(scpi, "FAULT?", &fault);
524 if (ret != SR_OK)
525 return ret;
526
527 /* OVP */
528 if (fault & (1 << 3))
529 sr_session_send_meta(sdi, SR_CONF_OVER_VOLTAGE_PROTECTION_ACTIVE,
530 g_variant_new_boolean(fault & (1 << 3)));
531
532 /* OCP */
533 if (fault & (1 << 6))
534 sr_session_send_meta(sdi, SR_CONF_OVER_CURRENT_PROTECTION_ACTIVE,
535 g_variant_new_boolean(fault & (1 << 6)));
536
537 /* OTP */
538 if (fault & (1 << 4))
539 sr_session_send_meta(sdi, SR_CONF_OVER_TEMPERATURE_PROTECTION_ACTIVE,
540 g_variant_new_boolean(fault & (1 << 4)));
541
542 /* CV */
543 cv = (fault & (1 << 0));
544 regulation_changed = (fault & (1 << 0));
545 /* CC+ */
546 cc_pos = (fault & (1 << 1));
547 regulation_changed = (fault & (1 << 1)) | regulation_changed;
548 /* UNREG */
549 unreg = (fault & (1 << 2));
550 regulation_changed = (fault & (1 << 2)) | regulation_changed;
551 /* CC- */
552 cc_neg = (fault & (1 << 9));
553 regulation_changed = (fault & (1 << 9)) | regulation_changed;
554
555 if (regulation_changed) {
556 if (cv && !cc_pos && !cc_neg &&!unreg)
557 regulation = "CV";
558 else if (cc_pos && !cv && !cc_neg && !unreg)
559 regulation = "CC";
560 else if (cc_neg && !cv && !cc_pos && !unreg)
561 regulation = "CC-";
562 else if (unreg && !cv && !cc_pos && !cc_neg)
563 regulation = "UR";
564 else if (!cv && !cc_pos && !cc_neg &&!unreg)
565 regulation = "";
566 else {
567 sr_dbg("Undefined regulation for HP 66xxA "
568 "(CV=%i, CC+=%i, CC-=%i, UR=%i).",
569 cv, cc_pos, cc_neg, unreg);
570 return FALSE;
571 }
572 sr_session_send_meta(sdi, SR_CONF_REGULATION,
573 g_variant_new_string(regulation));
574 }
575
576 return SR_OK;
577}
578
dbc519f7 579/* HP 663xB series */
a61c8cce 580static const uint32_t hp_6630b_devopts[] = {
e91bb0a6 581 SR_CONF_CONTINUOUS,
88e4daa9
ML		 582 SR_CONF_LIMIT_SAMPLES | SR_CONF_GET | SR_CONF_SET,
583 SR_CONF_LIMIT_MSEC | SR_CONF_GET | SR_CONF_SET,
7c517d02
FS		 584};
585
a61c8cce 586static const uint32_t hp_6630b_devopts_cg[] = {
7a0b98b5
AJ		 587 SR_CONF_ENABLED | SR_CONF_GET | SR_CONF_SET,
588 SR_CONF_VOLTAGE | SR_CONF_GET,
589 SR_CONF_CURRENT | SR_CONF_GET,
590 SR_CONF_VOLTAGE_TARGET | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
591 SR_CONF_CURRENT_LIMIT | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
8b5eadf4 592 SR_CONF_OVER_VOLTAGE_PROTECTION_ACTIVE | SR_CONF_GET,
49a468ed 593 SR_CONF_OVER_VOLTAGE_PROTECTION_THRESHOLD | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
7e381bfc 594 SR_CONF_OVER_CURRENT_PROTECTION_ENABLED | SR_CONF_GET | SR_CONF_SET,
8b5eadf4
FS		 595 SR_CONF_OVER_CURRENT_PROTECTION_ACTIVE | SR_CONF_GET,
596 SR_CONF_OVER_TEMPERATURE_PROTECTION_ACTIVE | SR_CONF_GET,
43ff1110 597 SR_CONF_REGULATION | SR_CONF_GET,
bc4a2a46
BV		 598};
599
5ce427c7
FS		 600static const struct channel_spec hp_6611c_ch[] = {
601 { "1", { 0, 8.19, 0.002, 3, 4 }, { 0, 5.1188, 0.00125, 4, 5 }, { 0, 41.92297 }, FREQ_DC_ONLY, { 0, 12, 0.06 }, NO_OCP_LIMITS },
602};
603
604static const struct channel_spec hp_6612c_ch[] = {
605 { "1", { 0, 20.475, 0.005, 3, 4 }, { 0, 2.0475, 0.0005, 4, 5 }, { 0, 41.92256 }, FREQ_DC_ONLY, { 0, 22, 0.1 }, NO_OCP_LIMITS },
606};
607
608static const struct channel_spec hp_6613c_ch[] = {
609 { "1", { 0, 51.188, 0.0125, 3, 4 }, { 0, 1.0238, 0.00025, 4, 5 }, { 0, 52.40627 }, FREQ_DC_ONLY, { 0, 55, 0.25 }, NO_OCP_LIMITS },
610};
611
612static const struct channel_spec hp_6614c_ch[] = {
613 { "1", { 0, 102.38, 0.025, 3, 4 }, { 0, 0.5118, 0.000125, 4, 5 }, { 0, 52.39808 }, FREQ_DC_ONLY, { 0, 110, 0.5 }, NO_OCP_LIMITS },
614};
615
a61c8cce 616static const struct channel_spec hp_6631b_ch[] = {
49a468ed 617 { "1", { 0, 8.19, 0.002, 3, 4 }, { 0, 10.237, 0.00263, 4, 5 }, { 0, 83.84103 }, FREQ_DC_ONLY, { 0, 12, 0.06 }, NO_OCP_LIMITS },
a61c8cce
FS		 618};
619
8cb5affe 620static const struct channel_spec hp_6632b_ch[] = {
49a468ed 621 { "1", { 0, 20.475, 0.005, 3, 4 }, { 0, 5.1188, 0.00132, 4, 5 }, { 0, 104.80743 }, FREQ_DC_ONLY, { 0, 22, 0.1 }, NO_OCP_LIMITS },
bc4a2a46
BV		 622};
623
a61c8cce 624static const struct channel_spec hp_66332a_ch[] = {
49a468ed 625 { "1", { 0, 20.475, 0.005, 3, 4 }, { 0, 5.1188, 0.00132, 4, 5 }, { 0, 104.80743 }, FREQ_DC_ONLY, { 0, 22, 0.1 }, NO_OCP_LIMITS },
a61c8cce
FS		 626};
627
628static const struct channel_spec hp_6633b_ch[] = {
49a468ed 629 { "1", { 0, 51.188, 0.0125, 3, 4 }, { 0, 2.0475, 0.000526, 4, 5 }, { 0, 104.80743 }, FREQ_DC_ONLY, { 0, 55, 0.25 }, NO_OCP_LIMITS },
a61c8cce
FS		 630};
631
632static const struct channel_spec hp_6634b_ch[] = {
49a468ed 633 { "1", { 0, 102.38, 0.025, 3, 4 }, { 0, 1.0238, 0.000263, 4, 5 }, { 0, 104.81664 }, FREQ_DC_ONLY, { 0, 110, 0.5 }, NO_OCP_LIMITS },
a61c8cce
FS		 634};
635
dbc519f7 636static const struct channel_group_spec hp_6630b_cg[] = {
3d1aa50f 637 { "1", CH_IDX(0), PPS_OVP | PPS_OCP, SR_MQFLAG_DC },
bc4a2a46
BV		 638};
639
a61c8cce 640static const struct scpi_command hp_6630b_cmd[] = {
26e96658
FS		 641 /*
642 * SCPI_CMD_REMOTE and SCPI_CMD_LOCAL are not used when GPIB is used,
643 * otherwise the device will report (non critical) error 602.
644 */
7e381bfc
FS		 645 { SCPI_CMD_REMOTE, "SYST:REM" },
646 { SCPI_CMD_LOCAL, "SYST:LOC" },
bc4a2a46 647 { SCPI_CMD_GET_OUTPUT_ENABLED, "OUTP:STAT?" },
53a81803
BV		 648 { SCPI_CMD_SET_OUTPUT_ENABLE, "OUTP:STAT ON" },
649 { SCPI_CMD_SET_OUTPUT_DISABLE, "OUTP:STAT OFF" },
bc4a2a46
BV		 650 { SCPI_CMD_GET_MEAS_VOLTAGE, ":MEAS:VOLT?" },
651 { SCPI_CMD_GET_MEAS_CURRENT, ":MEAS:CURR?" },
ca95e90f
BV		 652 { SCPI_CMD_GET_VOLTAGE_TARGET, ":SOUR:VOLT?" },
653 { SCPI_CMD_SET_VOLTAGE_TARGET, ":SOUR:VOLT %.6f" },
654 { SCPI_CMD_GET_CURRENT_LIMIT, ":SOUR:CURR?" },
655 { SCPI_CMD_SET_CURRENT_LIMIT, ":SOUR:CURR %.6f" },
7e381bfc
FS		 656 { SCPI_CMD_GET_OVER_CURRENT_PROTECTION_ENABLED, ":CURR:PROT:STAT?" },
657 { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_ENABLE, ":CURR:PROT:STAT 1" },
658 { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_DISABLE, ":CURR:PROT:STAT 0" },
8b5eadf4
FS		 659 { SCPI_CMD_GET_OVER_CURRENT_PROTECTION_ACTIVE, "STAT:QUES:COND?" },
660 { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_ACTIVE, "STAT:QUES:COND?" },
7e381bfc
FS		 661 { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_THRESHOLD, ":VOLT:PROT?" },
662 { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_THRESHOLD, ":VOLT:PROT %.6f" },
8b5eadf4 663 { SCPI_CMD_GET_OVER_TEMPERATURE_PROTECTION_ACTIVE, "STAT:QUES:COND?" },
43ff1110 664 { SCPI_CMD_GET_OUTPUT_REGULATION, "STAT:OPER:COND?" },
91ef511d 665 ALL_ZERO
bc4a2a46
BV		 666};
667
fe4bb774
FS		 668static int hp_6630b_init_aquisition(const struct sr_dev_inst *sdi)
669{
670 struct sr_scpi_dev_inst *scpi;
671 int ret;
672
673 scpi = sdi->conn;
674
675 /*
676 * Monitor CV (256), CC+ (1024) and CC- (2048) bits of the
677 * Operational Status Register.
678 * Use both positive and negative transitions of the status bits.
679 */
680 ret = sr_scpi_send(scpi, "STAT:OPER:PTR 3328;NTR 3328;ENAB 3328");
681 if (ret != SR_OK)
682 return ret;
683
684 /*
685 * Monitor OVP (1), OCP (2), OTP (16) and Unreg (1024) bits of the
686 * Questionable Status Register.
687 * Use both positive and negative transitions of the status bits.
688 */
689 ret = sr_scpi_send(scpi, "STAT:QUES:PTR 1043;NTR 1043;ENAB 1043");
690 if (ret != SR_OK)
691 return ret;
692
693 /*
694 * Service Request Enable Register set for Operational Status Register
695 * bits (128) and Questionable Status Register bits (8).
696 * This masks the Status Register generating a SRQ/RQS. Not implemented yet!
697 */
698 /*
699 ret = sr_scpi_send(scpi, "*SRE 136");
700 if (ret != SR_OK)
701 return ret;
702 */
703
704 return SR_OK;
705}
706
707static int hp_6630b_update_status(const struct sr_dev_inst *sdi)
708{
709 struct sr_scpi_dev_inst *scpi;
710 int ret;
711 int stb;
712 int ques_even, ques_cond;
713 int oper_even, oper_cond;
714 gboolean output_enabled;
715 gboolean unreg, cv, cc_pos, cc_neg;
716 gboolean regulation_changed;
717 char *regulation;
718
719 scpi = sdi->conn;
720
721 unreg = FALSE;
722 cv = FALSE;
723 cc_pos = FALSE;
724 cc_neg = FALSE;
725 regulation_changed = FALSE;
726
727 /*
728 * Use SPoll when SCPI uses GPIB as transport layer.
729 * SPoll is approx. twice as fast as a normal GPIB write + read would be!
730 */
731#ifdef HAVE_LIBGPIB
732 char spoll_buf;
733
734 if (scpi->transport == SCPI_TRANSPORT_LIBGPIB) {
735 ret = sr_scpi_gpib_spoll(scpi, &spoll_buf);
736 if (ret != SR_OK)
737 return ret;
738 stb = (uint8_t)spoll_buf;
739 }
740 else {
741#endif
742 ret = sr_scpi_get_int(scpi, "*STB?", &stb);
743 if (ret != SR_OK)
744 return ret;
745#ifdef HAVE_LIBGPIB
746 }
747#endif
748
749 /* Questionable status summary bit */
750 if (stb & (1 << 3)) {
751 /* Read the event register to clear it! */
752 ret = sr_scpi_get_int(scpi, "STAT:QUES:EVEN?", &ques_even);
753 if (ret != SR_OK)
754 return ret;
755 /* Now get the values. */
756 ret = sr_scpi_get_int(scpi, "STAT:QUES:COND?", &ques_cond);
757 if (ret != SR_OK)
758 return ret;
759
760 /* OVP */
761 if (ques_even & (1 << 0))
762 sr_session_send_meta(sdi, SR_CONF_OVER_VOLTAGE_PROTECTION_ACTIVE,
763 g_variant_new_boolean(ques_cond & (1 << 0)));
764
765 /* OCP */
766 if (ques_even & (1 << 1))
767 sr_session_send_meta(sdi, SR_CONF_OVER_CURRENT_PROTECTION_ACTIVE,
768 g_variant_new_boolean(ques_cond & (1 << 1)));
769
770 /* OTP */
771 if (ques_even & (1 << 4))
772 sr_session_send_meta(sdi, SR_CONF_OVER_TEMPERATURE_PROTECTION_ACTIVE,
773 g_variant_new_boolean(ques_cond & (1 << 4)));
774
775 /* UNREG */
776 unreg = (ques_cond & (1 << 10));
777 regulation_changed = (ques_even & (1 << 10)) | regulation_changed;
778
779 /*
780 * Check if output state has changed, due to one of the
781 * questionable states changed.
782 * NOTE: The output state is send even if it hasn't changed, but that
783 * only happends rarely.
784 */
785 ret = sr_scpi_get_bool(scpi, "OUTP:STAT?", &output_enabled);
786 if (ret != SR_OK)
787 return ret;
788 sr_session_send_meta(sdi, SR_CONF_ENABLED,
789 g_variant_new_boolean(output_enabled));
790 }
791
792 /* Operation status summary bit */
793 if (stb & (1 << 7)) {
794 /* Read the event register to clear it! */
795 ret = sr_scpi_get_int(scpi, "STAT:OPER:EVEN?", &oper_even);
796 if (ret != SR_OK)
797 return ret;
798 /* Now get the values. */
799 ret = sr_scpi_get_int(scpi, "STAT:OPER:COND?", &oper_cond);
800 if (ret != SR_OK)
801 return ret;
802
803 /* CV */
804 cv = (oper_cond & (1 << 8));
805 regulation_changed = (oper_even & (1 << 8)) | regulation_changed;
806 /* CC+ */
807 cc_pos = (oper_cond & (1 << 10));
808 regulation_changed = (oper_even & (1 << 10)) | regulation_changed;
809 /* CC- */
810 cc_neg = (oper_cond & (1 << 11));
811 regulation_changed = (oper_even & (1 << 11)) | regulation_changed;
812 }
813
814 if (regulation_changed) {
815 if (cv && !cc_pos && !cc_neg &&!unreg)
816 regulation = "CV";
817 else if (cc_pos && !cv && !cc_neg && !unreg)
818 regulation = "CC";
819 else if (cc_neg && !cv && !cc_pos && !unreg)
820 regulation = "CC-";
821 else if (unreg && !cv && !cc_pos && !cc_neg)
822 regulation = "UR";
823 else if (!cv && !cc_pos && !cc_neg &&!unreg)
824 /* This happends in case of OCP active */
825 regulation = "";
826 else {
827 /* This happends from time to time (CV and CC+ active). */
828 sr_dbg("Undefined regulation for HP 66xxB "
829 "(CV=%i, CC+=%i, CC-=%i, UR=%i).",
830 cv, cc_pos, cc_neg, unreg);
831 return FALSE;
832 }
833 sr_session_send_meta(sdi, SR_CONF_REGULATION,
834 g_variant_new_string(regulation));
835 }
836
837 return SR_OK;
838}
839
c3eadb07 840/* Philips/Fluke PM2800 series */
9d9cf1c4 841static const uint32_t philips_pm2800_devopts[] = {
e91bb0a6 842 SR_CONF_CONTINUOUS,
88e4daa9
ML		 843 SR_CONF_LIMIT_SAMPLES | SR_CONF_GET | SR_CONF_SET,
844 SR_CONF_LIMIT_MSEC | SR_CONF_GET | SR_CONF_SET,
9d9cf1c4
BV		 845};
846
c3eadb07 847static const uint32_t philips_pm2800_devopts_cg[] = {
7a0b98b5
AJ		 848 SR_CONF_ENABLED | SR_CONF_GET | SR_CONF_SET,
849 SR_CONF_VOLTAGE | SR_CONF_GET,
850 SR_CONF_VOLTAGE_TARGET | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
851 SR_CONF_CURRENT | SR_CONF_GET,
852 SR_CONF_CURRENT_LIMIT | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
c3eadb07
BV		 853 SR_CONF_OVER_VOLTAGE_PROTECTION_ACTIVE | SR_CONF_GET,
854 SR_CONF_OVER_VOLTAGE_PROTECTION_THRESHOLD | SR_CONF_GET | SR_CONF_SET,
855 SR_CONF_OVER_CURRENT_PROTECTION_ENABLED | SR_CONF_GET | SR_CONF_SET,
856 SR_CONF_OVER_CURRENT_PROTECTION_ACTIVE | SR_CONF_GET,
7a0b98b5 857 SR_CONF_REGULATION | SR_CONF_GET,
c3eadb07
BV		 858};
859
860enum philips_pm2800_modules {
861 PM2800_MOD_30V_10A = 1,
862 PM2800_MOD_60V_5A,
863 PM2800_MOD_60V_10A,
864 PM2800_MOD_8V_15A,
865 PM2800_MOD_60V_2A,
866 PM2800_MOD_120V_1A,
867};
868
329733d9 869static const struct philips_pm2800_module_spec {
c3eadb07 870 /* Min, max, programming resolution. */
bcee1299
UH		 871 double voltage[5];
872 double current[5];
873 double power[5];
c3eadb07
BV		 874} philips_pm2800_module_specs[] = {
875 /* Autoranging modules. */
6ed709fe
AJ		 876 [PM2800_MOD_30V_10A] = { { 0, 30, 0.0075, 2, 4 }, { 0, 10, 0.0025, 2, 4 }, { 0, 60 } },
877 [PM2800_MOD_60V_5A] = { { 0, 60, 0.015, 2, 3 }, { 0, 5, 0.00125, 2, 5 }, { 0, 60 } },
878 [PM2800_MOD_60V_10A] = { { 0, 60, 0.015, 2, 3 }, { 0, 10, 0.0025, 2, 5 }, { 0, 120 } },
c3eadb07 879 /* Linear modules. */
6ed709fe
AJ		 880 [PM2800_MOD_8V_15A] = { { 0, 8, 0.002, 3, 3 }, { -15, 15, 0.00375, 3, 5 }, { 0, 120 } },
881 [PM2800_MOD_60V_2A] = { { 0, 60, 0.015, 2, 3 }, { -2, 2, 0.0005, 3, 4 }, { 0, 120 } },
882 [PM2800_MOD_120V_1A] = { { 0, 120, 0.030, 2, 2 }, { -1, 1, 0.00025, 3, 5 }, { 0, 120 } },
c3eadb07
BV		 883};
884
329733d9 885static const struct philips_pm2800_model {
c3eadb07
BV		 886 unsigned int chassis;
887 unsigned int num_modules;
888 unsigned int set;
889 unsigned int modules[3];
890} philips_pm2800_matrix[] = {
891 /* Autoranging chassis. */
892 { 1, 1, 0, { PM2800_MOD_30V_10A, 0, 0 } },
893 { 1, 1, 1, { PM2800_MOD_60V_5A, 0, 0 } },
894 { 1, 2, 0, { PM2800_MOD_30V_10A, PM2800_MOD_30V_10A, 0 } },
895 { 1, 2, 1, { PM2800_MOD_60V_5A, PM2800_MOD_60V_5A, 0 } },
896 { 1, 2, 2, { PM2800_MOD_30V_10A, PM2800_MOD_60V_5A, 0 } },
897 { 1, 2, 3, { PM2800_MOD_30V_10A, PM2800_MOD_60V_10A, 0 } },
898 { 1, 2, 4, { PM2800_MOD_60V_5A, PM2800_MOD_60V_10A, 0 } },
899 { 1, 3, 0, { PM2800_MOD_30V_10A, PM2800_MOD_30V_10A, PM2800_MOD_30V_10A } },
900 { 1, 3, 1, { PM2800_MOD_60V_5A, PM2800_MOD_60V_5A, PM2800_MOD_60V_5A } },
901 { 1, 3, 2, { PM2800_MOD_30V_10A, PM2800_MOD_30V_10A, PM2800_MOD_60V_5A } },
902 { 1, 3, 3, { PM2800_MOD_30V_10A, PM2800_MOD_60V_5A, PM2800_MOD_60V_5A } },
903 /* Linear chassis. */
904 { 3, 1, 0, { PM2800_MOD_60V_2A, 0, 0 } },
905 { 3, 1, 1, { PM2800_MOD_120V_1A, 0, 0 } },
906 { 3, 1, 2, { PM2800_MOD_8V_15A, 0, 0 } },
907 { 3, 2, 0, { PM2800_MOD_60V_2A, 0, 0 } },
908 { 3, 2, 1, { PM2800_MOD_120V_1A, 0, 0 } },
909 { 3, 2, 2, { PM2800_MOD_60V_2A, PM2800_MOD_120V_1A, 0 } },
910 { 3, 2, 3, { PM2800_MOD_8V_15A, PM2800_MOD_8V_15A, 0 } },
911};
912
329733d9 913static const char *philips_pm2800_names[] = { "1", "2", "3" };
c3eadb07
BV		 914
915static int philips_pm2800_probe_channels(struct sr_dev_inst *sdi,
916 struct sr_scpi_hw_info *hw_info,
917 struct channel_spec **channels, unsigned int *num_channels,
918 struct channel_group_spec **channel_groups, unsigned int *num_channel_groups)
919{
329733d9
UH		 920 const struct philips_pm2800_model *model;
921 const struct philips_pm2800_module_spec *spec;
c3eadb07
BV		 922 unsigned int chassis, num_modules, set, module, m, i;
923
924 (void)sdi;
925
926 /*
927 * The model number as reported by *IDN? looks like e.g. PM2813/11,
928 * Where "PM28" is fixed, followed by the chassis code (1 = autoranging,
929 * 3 = linear series) and the number of modules: 1-3 for autoranging,
930 * 1-2 for linear.
931 * After the slash, the first digit denotes the module set. The
932 * digit after that denotes front (5) or rear (1) binding posts.
933 */
934 chassis = hw_info->model[4] - 0x30;
935 num_modules = hw_info->model[5] - 0x30;
936 set = hw_info->model[7] - 0x30;
937 for (m = 0; m < ARRAY_SIZE(philips_pm2800_matrix); m++) {
938 model = &philips_pm2800_matrix[m];
939 if (model->chassis == chassis && model->num_modules == num_modules
940 && model->set == set)
941 break;
942 }
943 if (m == ARRAY_SIZE(philips_pm2800_matrix)) {
944 sr_dbg("Model %s not found in matrix.", hw_info->model);
945 return SR_ERR;
946 }
947
948 sr_dbg("Found %d output channel%s:", num_modules, num_modules > 1 ? "s" : "");
949 *channels = g_malloc0(sizeof(struct channel_spec) * num_modules);
950 *channel_groups = g_malloc0(sizeof(struct channel_group_spec) * num_modules);
951 for (i = 0; i < num_modules; i++) {
952 module = model->modules[i];
953 spec = &philips_pm2800_module_specs[module];
6ed709fe 954 sr_dbg("output %d: %.0f - %.0fV, %.0f - %.0fA, %.0f - %.0fW", i + 1,
c3eadb07 955 spec->voltage[0], spec->voltage[1],
6ed709fe 956 spec->current[0], spec->current[1],
d9251a2c 957 spec->power[0], spec->power[1]);
329733d9 958 (*channels)[i].name = (char *)philips_pm2800_names[i];
bcee1299 959 memcpy(&((*channels)[i].voltage), spec, sizeof(double) * 15);
329733d9 960 (*channel_groups)[i].name = (char *)philips_pm2800_names[i];
c3eadb07
BV		 961 (*channel_groups)[i].channel_index_mask = 1 << i;
962 (*channel_groups)[i].features = PPS_OTP | PPS_OVP | PPS_OCP;
f2bbcc33 963 (*channel_groups)[i].mqflags = SR_MQFLAG_DC;
c3eadb07
BV		 964 }
965 *num_channels = *num_channel_groups = num_modules;
966
967 return SR_OK;
968}
969
8cb5affe 970static const struct scpi_command philips_pm2800_cmd[] = {
c3eadb07
BV		 971 { SCPI_CMD_SELECT_CHANNEL, ":INST:NSEL %s" },
972 { SCPI_CMD_GET_MEAS_VOLTAGE, ":MEAS:VOLT?" },
973 { SCPI_CMD_GET_MEAS_CURRENT, ":MEAS:CURR?" },
974 { SCPI_CMD_GET_VOLTAGE_TARGET, ":SOUR:VOLT?" },
975 { SCPI_CMD_SET_VOLTAGE_TARGET, ":SOUR:VOLT %.6f" },
976 { SCPI_CMD_GET_CURRENT_LIMIT, ":SOUR:CURR?" },
977 { SCPI_CMD_SET_CURRENT_LIMIT, ":SOUR:CURR %.6f" },
978 { SCPI_CMD_GET_OUTPUT_ENABLED, ":OUTP?" },
979 { SCPI_CMD_SET_OUTPUT_ENABLE, ":OUTP ON" },
980 { SCPI_CMD_SET_OUTPUT_DISABLE, ":OUTP OFF" },
981 { SCPI_CMD_GET_OUTPUT_REGULATION, ":SOUR:FUNC:MODE?" },
982 { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_ACTIVE, ":SOUR:VOLT:PROT:TRIP?" },
983 { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_THRESHOLD, ":SOUR:VOLT:PROT:LEV?" },
984 { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_THRESHOLD, ":SOUR:VOLT:PROT:LEV %.6f" },
985 { SCPI_CMD_GET_OVER_CURRENT_PROTECTION_ENABLED, ":SOUR:CURR:PROT:STAT?" },
986 { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_ENABLE, ":SOUR:CURR:PROT:STAT ON" },
987 { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_DISABLE, ":SOUR:CURR:PROT:STAT OFF" },
988 { SCPI_CMD_GET_OVER_CURRENT_PROTECTION_ACTIVE, ":SOUR:CURR:PROT:TRIP?" },
91ef511d 989 ALL_ZERO
c3eadb07
BV		 990};
991
81eb36d6
MS		 992static const uint32_t rs_hmc8043_devopts[] = {
993 SR_CONF_CONTINUOUS,
88e4daa9
ML		 994 SR_CONF_LIMIT_SAMPLES | SR_CONF_GET | SR_CONF_SET,
995 SR_CONF_LIMIT_MSEC | SR_CONF_GET | SR_CONF_SET,
81eb36d6
MS		 996};
997
998static const uint32_t rs_hmc8043_devopts_cg[] = {
999 SR_CONF_OVER_VOLTAGE_PROTECTION_ENABLED | SR_CONF_GET | SR_CONF_SET,
1000 SR_CONF_OVER_VOLTAGE_PROTECTION_ACTIVE | SR_CONF_GET,
1001 SR_CONF_OVER_VOLTAGE_PROTECTION_THRESHOLD | SR_CONF_GET | SR_CONF_SET,
1002 SR_CONF_VOLTAGE | SR_CONF_GET,
1003 SR_CONF_VOLTAGE_TARGET | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
1004 SR_CONF_CURRENT | SR_CONF_GET,
1005 SR_CONF_CURRENT_LIMIT | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
1006 SR_CONF_ENABLED | SR_CONF_GET | SR_CONF_SET,
1007};
1008
1009static const struct channel_spec rs_hmc8043_ch[] = {
49a468ed
FS		 1010 { "1", { 0, 32.050, 0.001, 3, 4 }, { 0.001, 3, 0.001, 3, 4 }, { 0, 0, 0, 0, 4 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS },
1011 { "2", { 0, 32.050, 0.001, 3, 4 }, { 0.001, 3, 0.001, 3, 4 }, { 0, 0, 0, 0, 4 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS },
1012 { "3", { 0, 32.050, 0.001, 3, 4 }, { 0.001, 3, 0.001, 3, 4 }, { 0, 0, 0, 0, 4 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS },
81eb36d6
MS		 1013};
1014
1015static const struct channel_group_spec rs_hmc8043_cg[] = {
f2bbcc33
FS		 1016 { "1", CH_IDX(0), PPS_OVP, SR_MQFLAG_DC },
1017 { "2", CH_IDX(1), PPS_OVP, SR_MQFLAG_DC },
1018 { "3", CH_IDX(2), PPS_OVP, SR_MQFLAG_DC },
81eb36d6
MS		 1019};
1020
1021static const struct scpi_command rs_hmc8043_cmd[] = {
1022 { SCPI_CMD_SELECT_CHANNEL, "INST:NSEL %s" },
1023 { SCPI_CMD_GET_MEAS_VOLTAGE, "MEAS:VOLT?" },
1024 { SCPI_CMD_GET_MEAS_CURRENT, "MEAS:CURR?" },
1025 { SCPI_CMD_GET_VOLTAGE_TARGET, "VOLT?" },
1026 { SCPI_CMD_SET_VOLTAGE_TARGET, "VOLT %.6f" },
1027 { SCPI_CMD_GET_CURRENT_LIMIT, "CURR?" },
1028 { SCPI_CMD_SET_CURRENT_LIMIT, "CURR %.6f" },
1029 { SCPI_CMD_GET_OUTPUT_ENABLED, "OUTP?" },
1030 { SCPI_CMD_SET_OUTPUT_ENABLE, "OUTP ON" },
1031 { SCPI_CMD_SET_OUTPUT_DISABLE, "OUTP OFF" },
1032 { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_ACTIVE, "VOLT:PROT:TRIP?" },
1033 { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_THRESHOLD, "VOLT:PROT:LEV?" },
1034 { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_THRESHOLD, "VOLT:PROT:LEV %.6f" },
1035 { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_ENABLED, "VOLT:PROT:STAT?" },
1036 { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_ENABLE, "VOLT:PROT:STAT ON" },
1037 { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_DISABLE, "VOLT:PROT:STAT OFF" },
1038 ALL_ZERO
1039};
1040
d4eabea8 1041SR_PRIV const struct scpi_pps pps_profiles[] = {
6cc93128 1042 /* Agilent N5763A */
5e7377f4 1043 { "Agilent", "N5763A", SCPI_DIALECT_UNKNOWN, 0,
6cc93128
AG		 1044 ARRAY_AND_SIZE(agilent_n5700a_devopts),
1045 ARRAY_AND_SIZE(agilent_n5700a_devopts_cg),
1046 ARRAY_AND_SIZE(agilent_n5763a_ch),
1047 ARRAY_AND_SIZE(agilent_n5700a_cg),
1048 agilent_n5700a_cmd,
1049 .probe_channels = NULL,
7e66bf05
FS		 1050 .init_aquisition = NULL,
1051 .update_status = NULL,
6cc93128 1052 },
ca314e06 1053
5c9e56c9 1054 /* Agilent N5767A */
5e7377f4 1055 { "Agilent", "N5767A", SCPI_DIALECT_UNKNOWN, 0,
5c9e56c9
AG		 1056 ARRAY_AND_SIZE(agilent_n5700a_devopts),
1057 ARRAY_AND_SIZE(agilent_n5700a_devopts_cg),
1058 ARRAY_AND_SIZE(agilent_n5767a_ch),
6cc93128 1059 ARRAY_AND_SIZE(agilent_n5700a_cg),
91ef511d 1060 agilent_n5700a_cmd,
5c9e56c9 1061 .probe_channels = NULL,
7e66bf05
FS		 1062 .init_aquisition = NULL,
1063 .update_status = NULL,
5c9e56c9 1064 },
ca314e06 1065
c3bfb959 1066 /* BK Precision 9310 */
5e7377f4 1067 { "BK", "^9130$", SCPI_DIALECT_UNKNOWN, 0,
c3bfb959
MW		 1068 ARRAY_AND_SIZE(bk_9130_devopts),
1069 ARRAY_AND_SIZE(bk_9130_devopts_cg),
1070 ARRAY_AND_SIZE(bk_9130_ch),
1071 ARRAY_AND_SIZE(bk_9130_cg),
1072 bk_9130_cmd,
1073 .probe_channels = NULL,
7e66bf05
FS		 1074 .init_aquisition = NULL,
1075 .update_status = NULL,
c3bfb959
MW		 1076 },
1077
4ee1e2f3 1078 /* Chroma 61604 */
5e7377f4 1079 { "Chroma", "61604", SCPI_DIALECT_UNKNOWN, 0,
4ee1e2f3
AG		 1080 ARRAY_AND_SIZE(chroma_61604_devopts),
1081 ARRAY_AND_SIZE(chroma_61604_devopts_cg),
1082 ARRAY_AND_SIZE(chroma_61604_ch),
1083 ARRAY_AND_SIZE(chroma_61604_cg),
91ef511d 1084 chroma_61604_cmd,
4ee1e2f3 1085 .probe_channels = NULL,
7e66bf05
FS		 1086 .init_aquisition = NULL,
1087 .update_status = NULL,
4ee1e2f3 1088 },
ca314e06 1089
5281993e 1090 /* Chroma 62000 series */
5e7377f4 1091 { "Chroma", "620[0-9]{2}P-[0-9]{2,3}-[0-9]{1,3}", SCPI_DIALECT_UNKNOWN, 0,
5281993e
AG		 1092 ARRAY_AND_SIZE(chroma_62000_devopts),
1093 ARRAY_AND_SIZE(chroma_62000_devopts_cg),
9a5185c7
AG		 1094 NULL, 0,
1095 NULL, 0,
91ef511d 1096 chroma_62000_cmd,
9a5185c7 1097 .probe_channels = chroma_62000p_probe_channels,
7e66bf05
FS		 1098 .init_aquisition = NULL,
1099 .update_status = NULL,
5281993e 1100 },
ca314e06 1101
5ce427c7
FS		 1102 /*
1103 * This entry is for testing the HP COMP language with a HP 6632B power
1104 * supply switched to the COMP language ("SYST:LANG COMP"). When used,
1105 * disable the entry for the HP 6632B below!
1106 */
1107 /*
1108 { "HP", "6632B", SCPI_DIALECT_HP_COMP, 0,
1109 ARRAY_AND_SIZE(hp_6630a_devopts),
1110 ARRAY_AND_SIZE(hp_6630a_devopts_cg),
1111 ARRAY_AND_SIZE(hp_6632a_ch),
1112 ARRAY_AND_SIZE(hp_6630a_cg),
1113 hp_6630a_cmd,
1114 .probe_channels = NULL,
1115 hp_6630a_init_aquisition,
1116 hp_6630a_update_status,
1117 },
1118 */
1119
1120 /* HP 6632A */
1121 { "HP", "6632A", SCPI_DIALECT_HP_COMP, 0,
1122 ARRAY_AND_SIZE(hp_6630a_devopts),
1123 ARRAY_AND_SIZE(hp_6630a_devopts_cg),
1124 ARRAY_AND_SIZE(hp_6632a_ch),
1125 ARRAY_AND_SIZE(hp_6630a_cg),
1126 hp_6630a_cmd,
1127 .probe_channels = NULL,
1128 hp_6630a_init_aquisition,
1129 hp_6630a_update_status,
1130 },
1131
e76a3575 1132 /* HP 6633A */
5e7377f4 1133 { "HP", "6633A", SCPI_DIALECT_HP_COMP, 0,
e76a3575 1134 ARRAY_AND_SIZE(hp_6630a_devopts),
7c517d02 1135 ARRAY_AND_SIZE(hp_6630a_devopts_cg),
e76a3575 1136 ARRAY_AND_SIZE(hp_6633a_ch),
dbc519f7 1137 ARRAY_AND_SIZE(hp_6630a_cg),
e76a3575
AG		 1138 hp_6630a_cmd,
1139 .probe_channels = NULL,
fdf03652
FS		 1140 hp_6630a_init_aquisition,
1141 hp_6630a_update_status,
e76a3575
AG		 1142 },
1143
5ce427c7
FS		 1144 /* HP 6634A */
1145 { "HP", "6634A", SCPI_DIALECT_HP_COMP, 0,
1146 ARRAY_AND_SIZE(hp_6630a_devopts),
1147 ARRAY_AND_SIZE(hp_6630a_devopts_cg),
1148 ARRAY_AND_SIZE(hp_6634a_ch),
1149 ARRAY_AND_SIZE(hp_6630a_cg),
1150 hp_6630a_cmd,
1151 .probe_channels = NULL,
1152 hp_6630a_init_aquisition,
1153 hp_6630a_update_status,
1154 },
1155
1156 /* HP 6611C */
1157 { "HP", "6611C", SCPI_DIALECT_HP_66XXB, PPS_OTP,
1158 ARRAY_AND_SIZE(hp_6630b_devopts),
1159 ARRAY_AND_SIZE(hp_6630b_devopts_cg),
1160 ARRAY_AND_SIZE(hp_6611c_ch),
1161 ARRAY_AND_SIZE(hp_6630b_cg),
1162 hp_6630b_cmd,
1163 .probe_channels = NULL,
1164 hp_6630b_init_aquisition,
1165 hp_6630b_update_status,
1166 },
1167
1168 /* HP 6612C */
1169 { "HP", "6612C", SCPI_DIALECT_HP_66XXB, PPS_OTP,
1170 ARRAY_AND_SIZE(hp_6630b_devopts),
1171 ARRAY_AND_SIZE(hp_6630b_devopts_cg),
1172 ARRAY_AND_SIZE(hp_6612c_ch),
1173 ARRAY_AND_SIZE(hp_6630b_cg),
1174 hp_6630b_cmd,
1175 .probe_channels = NULL,
1176 hp_6630b_init_aquisition,
1177 hp_6630b_update_status,
1178 },
1179
1180 /* HP 6613C */
1181 { "HP", "6613C", SCPI_DIALECT_HP_66XXB, PPS_OTP,
1182 ARRAY_AND_SIZE(hp_6630b_devopts),
1183 ARRAY_AND_SIZE(hp_6630b_devopts_cg),
1184 ARRAY_AND_SIZE(hp_6613c_ch),
1185 ARRAY_AND_SIZE(hp_6630b_cg),
1186 hp_6630b_cmd,
1187 .probe_channels = NULL,
1188 hp_6630b_init_aquisition,
1189 hp_6630b_update_status,
1190 },
1191
1192 /* HP 6614C */
1193 { "HP", "6614C", SCPI_DIALECT_HP_66XXB, PPS_OTP,
1194 ARRAY_AND_SIZE(hp_6630b_devopts),
1195 ARRAY_AND_SIZE(hp_6630b_devopts_cg),
1196 ARRAY_AND_SIZE(hp_6614c_ch),
1197 ARRAY_AND_SIZE(hp_6630b_cg),
1198 hp_6630b_cmd,
1199 .probe_channels = NULL,
1200 hp_6630b_init_aquisition,
1201 hp_6630b_update_status,
1202 },
1203
a61c8cce 1204 /* HP 6631B */
3d1aa50f 1205 { "HP", "6631B", SCPI_DIALECT_HP_66XXB, PPS_OTP,
a61c8cce
FS		 1206 ARRAY_AND_SIZE(hp_6630b_devopts),
1207 ARRAY_AND_SIZE(hp_6630b_devopts_cg),
1208 ARRAY_AND_SIZE(hp_6631b_ch),
dbc519f7 1209 ARRAY_AND_SIZE(hp_6630b_cg),
a61c8cce
FS		 1210 hp_6630b_cmd,
1211 .probe_channels = NULL,
fe4bb774
FS		 1212 hp_6630b_init_aquisition,
1213 hp_6630b_update_status,
a61c8cce
FS		 1214 },
1215
bc4a2a46 1216 /* HP 6632B */
3d1aa50f 1217 { "HP", "6632B", SCPI_DIALECT_HP_66XXB, PPS_OTP,
a61c8cce
FS		 1218 ARRAY_AND_SIZE(hp_6630b_devopts),
1219 ARRAY_AND_SIZE(hp_6630b_devopts_cg),
bc4a2a46 1220 ARRAY_AND_SIZE(hp_6632b_ch),
dbc519f7 1221 ARRAY_AND_SIZE(hp_6630b_cg),
a61c8cce
FS		 1222 hp_6630b_cmd,
1223 .probe_channels = NULL,
fe4bb774
FS		 1224 hp_6630b_init_aquisition,
1225 hp_6630b_update_status,
a61c8cce
FS		 1226 },
1227
1228 /* HP 66332A */
3d1aa50f 1229 { "HP", "66332A", SCPI_DIALECT_HP_66XXB, PPS_OTP,
a61c8cce
FS		 1230 ARRAY_AND_SIZE(hp_6630b_devopts),
1231 ARRAY_AND_SIZE(hp_6630b_devopts_cg),
1232 ARRAY_AND_SIZE(hp_66332a_ch),
dbc519f7 1233 ARRAY_AND_SIZE(hp_6630b_cg),
a61c8cce
FS		 1234 hp_6630b_cmd,
1235 .probe_channels = NULL,
fe4bb774
FS		 1236 hp_6630b_init_aquisition,
1237 hp_6630b_update_status,
a61c8cce
FS		 1238 },
1239
1240 /* HP 6633B */
3d1aa50f 1241 { "HP", "6633B", SCPI_DIALECT_HP_66XXB, PPS_OTP,
a61c8cce
FS		 1242 ARRAY_AND_SIZE(hp_6630b_devopts),
1243 ARRAY_AND_SIZE(hp_6630b_devopts_cg),
1244 ARRAY_AND_SIZE(hp_6633b_ch),
dbc519f7 1245 ARRAY_AND_SIZE(hp_6630b_cg),
a61c8cce
FS		 1246 hp_6630b_cmd,
1247 .probe_channels = NULL,
fe4bb774
FS		 1248 hp_6630b_init_aquisition,
1249 hp_6630b_update_status,
a61c8cce
FS		 1250 },
1251
1252 /* HP 6634B */
3d1aa50f 1253 { "HP", "6634B", SCPI_DIALECT_HP_66XXB, PPS_OTP,
a61c8cce
FS		 1254 ARRAY_AND_SIZE(hp_6630b_devopts),
1255 ARRAY_AND_SIZE(hp_6630b_devopts_cg),
1256 ARRAY_AND_SIZE(hp_6634b_ch),
dbc519f7 1257 ARRAY_AND_SIZE(hp_6630b_cg),
a61c8cce 1258 hp_6630b_cmd,
c3eadb07 1259 .probe_channels = NULL,
fe4bb774
FS		 1260 hp_6630b_init_aquisition,
1261 hp_6630b_update_status,
bc4a2a46
BV		 1262 },
1263
319fe9ce 1264 /* Rigol DP700 series */
5e7377f4 1265 { "Rigol", "^DP711$", SCPI_DIALECT_UNKNOWN, 0,
319fe9ce
UH		 1266 ARRAY_AND_SIZE(rigol_dp700_devopts),
1267 ARRAY_AND_SIZE(rigol_dp700_devopts_cg),
1268 ARRAY_AND_SIZE(rigol_dp711_ch),
1269 ARRAY_AND_SIZE(rigol_dp700_cg),
1270 rigol_dp700_cmd,
1271 .probe_channels = NULL,
7e66bf05
FS		 1272 .init_aquisition = NULL,
1273 .update_status = NULL,
319fe9ce 1274 },
5e7377f4 1275 { "Rigol", "^DP712$", SCPI_DIALECT_UNKNOWN, 0,
319fe9ce
UH		 1276 ARRAY_AND_SIZE(rigol_dp700_devopts),
1277 ARRAY_AND_SIZE(rigol_dp700_devopts_cg),
1278 ARRAY_AND_SIZE(rigol_dp712_ch),
1279 ARRAY_AND_SIZE(rigol_dp700_cg),
1280 rigol_dp700_cmd,
1281 .probe_channels = NULL,
7e66bf05
FS		 1282 .init_aquisition = NULL,
1283 .update_status = NULL,
319fe9ce
UH		 1284 },
1285
d4eabea8 1286 /* Rigol DP800 series */
5e7377f4 1287 { "Rigol", "^DP821A$", SCPI_DIALECT_UNKNOWN, PPS_OTP,
cfcdf576
ML		 1288 ARRAY_AND_SIZE(rigol_dp800_devopts),
1289 ARRAY_AND_SIZE(rigol_dp800_devopts_cg),
1290 ARRAY_AND_SIZE(rigol_dp821a_ch),
1291 ARRAY_AND_SIZE(rigol_dp820_cg),
91ef511d 1292 rigol_dp800_cmd,
cfcdf576 1293 .probe_channels = NULL,
7e66bf05
FS		 1294 .init_aquisition = NULL,
1295 .update_status = NULL,
cfcdf576 1296 },
5e7377f4 1297 { "Rigol", "^DP831A$", SCPI_DIALECT_UNKNOWN, PPS_OTP,
3222ee10
BV		 1298 ARRAY_AND_SIZE(rigol_dp800_devopts),
1299 ARRAY_AND_SIZE(rigol_dp800_devopts_cg),
1300 ARRAY_AND_SIZE(rigol_dp831_ch),
cfcdf576 1301 ARRAY_AND_SIZE(rigol_dp830_cg),
91ef511d 1302 rigol_dp800_cmd,
c3eadb07 1303 .probe_channels = NULL,
7e66bf05
FS		 1304 .init_aquisition = NULL,
1305 .update_status = NULL,
3222ee10 1306 },
5e7377f4 1307 { "Rigol", "^(DP832|DP832A)$", SCPI_DIALECT_UNKNOWN, PPS_OTP,
3222ee10
BV		 1308 ARRAY_AND_SIZE(rigol_dp800_devopts),
1309 ARRAY_AND_SIZE(rigol_dp800_devopts_cg),
1310 ARRAY_AND_SIZE(rigol_dp832_ch),
cfcdf576 1311 ARRAY_AND_SIZE(rigol_dp830_cg),
91ef511d 1312 rigol_dp800_cmd,
c3eadb07 1313 .probe_channels = NULL,
7e66bf05
FS		 1314 .init_aquisition = NULL,
1315 .update_status = NULL,
c3eadb07
BV		 1316 },
1317
1318 /* Philips/Fluke PM2800 series */
5e7377f4 1319 { "Philips", "^PM28[13][123]/[01234]{1,2}$", SCPI_DIALECT_PHILIPS, 0,
9d9cf1c4 1320 ARRAY_AND_SIZE(philips_pm2800_devopts),
c3eadb07
BV		 1321 ARRAY_AND_SIZE(philips_pm2800_devopts_cg),
1322 NULL, 0,
1323 NULL, 0,
91ef511d 1324 philips_pm2800_cmd,
c3eadb07 1325 philips_pm2800_probe_channels,
7e66bf05
FS		 1326 .init_aquisition = NULL,
1327 .update_status = NULL,
d4eabea8 1328 },
81eb36d6
MS		 1329
1330 /* Rohde & Schwarz HMC8043 */
5e7377f4 1331 { "Rohde&Schwarz", "HMC8043", SCPI_DIALECT_UNKNOWN, 0,
81eb36d6
MS		 1332 ARRAY_AND_SIZE(rs_hmc8043_devopts),
1333 ARRAY_AND_SIZE(rs_hmc8043_devopts_cg),
1334 ARRAY_AND_SIZE(rs_hmc8043_ch),
1335 ARRAY_AND_SIZE(rs_hmc8043_cg),
1336 rs_hmc8043_cmd,
1337 .probe_channels = NULL,
7e66bf05
FS		 1338 .init_aquisition = NULL,
1339 .update_status = NULL,
81eb36d6 1340 },
d4eabea8 1341};
d4eabea8 1342
1beccaed 1343SR_PRIV unsigned int num_pps_profiles = ARRAY_SIZE(pps_profiles);
Hardware access and backend lib