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d4eabea8 BV |
1 | /* |
2 | * This file is part of the libsigrok project. | |
3 | * | |
4 | * Copyright (C) 2014 Bert Vermeulen <bert@biot.com> | |
4ee1e2f3 AG |
5 | * Copyright (C) 2015 Google, Inc. |
6 | * (Written by Alexandru Gagniuc <mrnuke@google.com> for Google, Inc.) | |
7e66bf05 | 7 | * Copyright (C) 2017,2019 Frank Stettner <frank-stettner@gmx.net> |
d4eabea8 BV |
8 | * |
9 | * This program is free software: you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License as published by | |
11 | * the Free Software Foundation, either version 3 of the License, or | |
12 | * (at your option) any later version. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
21 | */ | |
22 | ||
6ec6c43b | 23 | #include <config.h> |
22c18b03 | 24 | #include <string.h> |
ba464a12 | 25 | #include <strings.h> |
d4eabea8 BV |
26 | #include "protocol.h" |
27 | ||
28 | #define CH_IDX(x) (1 << x) | |
6ed709fe | 29 | #define FREQ_DC_ONLY {0, 0, 0, 0, 0} |
49a468ed FS |
30 | #define NO_OVP_LIMITS {0, 0, 0, 0, 0} |
31 | #define NO_OCP_LIMITS {0, 0, 0, 0, 0} | |
d4eabea8 | 32 | |
5c9e56c9 AG |
33 | /* Agilent/Keysight N5700A series */ |
34 | static const uint32_t agilent_n5700a_devopts[] = { | |
e91bb0a6 | 35 | SR_CONF_CONTINUOUS, |
88e4daa9 ML |
36 | SR_CONF_LIMIT_SAMPLES | SR_CONF_GET | SR_CONF_SET, |
37 | SR_CONF_LIMIT_MSEC | SR_CONF_GET | SR_CONF_SET, | |
5c9e56c9 AG |
38 | }; |
39 | ||
40 | static const uint32_t agilent_n5700a_devopts_cg[] = { | |
41 | SR_CONF_OVER_VOLTAGE_PROTECTION_THRESHOLD | SR_CONF_GET | SR_CONF_SET, | |
42 | SR_CONF_OVER_CURRENT_PROTECTION_ENABLED | SR_CONF_GET | SR_CONF_SET, | |
43 | SR_CONF_OVER_CURRENT_PROTECTION_THRESHOLD | SR_CONF_GET | SR_CONF_SET, | |
da005885 UH |
44 | SR_CONF_VOLTAGE | SR_CONF_GET, |
45 | SR_CONF_VOLTAGE_TARGET | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST, | |
46 | SR_CONF_CURRENT | SR_CONF_GET, | |
47 | SR_CONF_ENABLED | SR_CONF_GET | SR_CONF_SET, | |
5c9e56c9 AG |
48 | }; |
49 | ||
6cc93128 | 50 | static const struct channel_group_spec agilent_n5700a_cg[] = { |
f2bbcc33 | 51 | { "1", CH_IDX(0), PPS_OVP | PPS_OCP, SR_MQFLAG_DC }, |
6cc93128 AG |
52 | }; |
53 | ||
8cb5affe | 54 | static const struct channel_spec agilent_n5767a_ch[] = { |
49a468ed | 55 | { "1", { 0, 60, 0.0072, 3, 4 }, { 0, 25, 0.003, 3, 4 }, { 0, 1500 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS }, |
5c9e56c9 AG |
56 | }; |
57 | ||
6cc93128 | 58 | static const struct channel_spec agilent_n5763a_ch[] = { |
49a468ed | 59 | { "1", { 0, 12.5, 0.0015, 3, 4 }, { 0, 120, 0.0144, 3, 4 }, { 0, 1500 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS }, |
5c9e56c9 AG |
60 | }; |
61 | ||
62 | /* | |
63 | * TODO: OVER_CURRENT_PROTECTION_ACTIVE status can be determined by the OC bit | |
562a3490 | 64 | * in STAT:QUES:EVEN?, but this is not implemented. |
5c9e56c9 | 65 | */ |
8cb5affe | 66 | static const struct scpi_command agilent_n5700a_cmd[] = { |
5c9e56c9 AG |
67 | { SCPI_CMD_REMOTE, "SYST:COMM:RLST REM" }, |
68 | { SCPI_CMD_LOCAL, "SYST:COMM:RLST LOC" }, | |
69 | { SCPI_CMD_GET_MEAS_VOLTAGE, ":MEAS:VOLT?" }, | |
70 | { SCPI_CMD_GET_MEAS_CURRENT, "MEAS:CURR?" }, | |
71 | { SCPI_CMD_GET_VOLTAGE_TARGET, ":SOUR:VOLT?" }, | |
72 | { SCPI_CMD_SET_VOLTAGE_TARGET, ":SOUR:VOLT %.6f" }, | |
73 | { SCPI_CMD_GET_CURRENT_LIMIT, ":SOUR:CURR?" }, | |
74 | { SCPI_CMD_SET_CURRENT_LIMIT, ":SOUR:CURR %.6f" }, | |
75 | { SCPI_CMD_GET_OUTPUT_ENABLED, ":OUTP:STAT?" }, | |
76 | { SCPI_CMD_SET_OUTPUT_ENABLE, ":OUTP ON" }, | |
77 | { SCPI_CMD_SET_OUTPUT_DISABLE, ":OUTP OFF" }, | |
78 | { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_THRESHOLD, ":VOLT:PROT?" }, | |
79 | { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_THRESHOLD, ":VOLT:PROT %.6f" }, | |
80 | { SCPI_CMD_GET_OVER_CURRENT_PROTECTION_ENABLED, ":CURR:PROT:STAT?" }, | |
81 | { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_ENABLE, ":CURR:PROT:STAT ON?"}, | |
82 | { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_DISABLE, ":CURR:PROT:STAT OFF?"}, | |
562a3490 | 83 | /* Current limit (CC mode) and OCP are set using the same command. */ |
5c9e56c9 AG |
84 | { SCPI_CMD_GET_OVER_CURRENT_PROTECTION_THRESHOLD, ":SOUR:CURR?" }, |
85 | { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_THRESHOLD, ":SOUR:CURR %.6f" }, | |
91ef511d | 86 | ALL_ZERO |
5c9e56c9 AG |
87 | }; |
88 | ||
c3bfb959 MW |
89 | /* BK Precision 9130 series */ |
90 | static const uint32_t bk_9130_devopts[] = { | |
91 | SR_CONF_CONTINUOUS, | |
92 | SR_CONF_LIMIT_SAMPLES | SR_CONF_GET | SR_CONF_SET, | |
93 | SR_CONF_LIMIT_MSEC | SR_CONF_GET | SR_CONF_SET, | |
94 | }; | |
95 | ||
96 | static const uint32_t bk_9130_devopts_cg[] = { | |
97 | SR_CONF_OVER_VOLTAGE_PROTECTION_THRESHOLD | SR_CONF_GET | SR_CONF_SET, | |
98 | SR_CONF_VOLTAGE | SR_CONF_GET, | |
99 | SR_CONF_VOLTAGE_TARGET | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST, | |
100 | SR_CONF_CURRENT | SR_CONF_GET, | |
101 | SR_CONF_CURRENT_LIMIT | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST, | |
102 | SR_CONF_ENABLED | SR_CONF_GET | SR_CONF_SET, | |
103 | }; | |
104 | ||
105 | static const struct channel_spec bk_9130_ch[] = { | |
106 | { "1", { 0, 30, 0.001, 3, 3 }, { 0, 3, 0.001, 3, 3 }, { 0, 90, 0, 3, 3 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS }, | |
107 | { "2", { 0, 30, 0.001, 3, 3 }, { 0, 3, 0.001, 3, 3 }, { 0, 90, 0, 3, 3 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS }, | |
108 | { "3", { 0, 5, 0.001, 3, 3 }, { 0, 3, 0.001, 3, 3 }, { 0, 15, 0, 3, 3 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS }, | |
109 | }; | |
110 | ||
111 | static const struct channel_group_spec bk_9130_cg[] = { | |
f2bbcc33 FS |
112 | { "1", CH_IDX(0), PPS_OVP, SR_MQFLAG_DC }, |
113 | { "2", CH_IDX(1), PPS_OVP, SR_MQFLAG_DC }, | |
114 | { "3", CH_IDX(2), PPS_OVP, SR_MQFLAG_DC }, | |
c3bfb959 MW |
115 | }; |
116 | ||
117 | static const struct scpi_command bk_9130_cmd[] = { | |
118 | { SCPI_CMD_REMOTE, "SYST:REMOTE" }, | |
119 | { SCPI_CMD_LOCAL, "SYST:LOCAL" }, | |
120 | { SCPI_CMD_SELECT_CHANNEL, ":INST:NSEL %s" }, | |
121 | { SCPI_CMD_GET_MEAS_VOLTAGE, ":MEAS:VOLT?" }, | |
122 | { SCPI_CMD_GET_MEAS_CURRENT, ":MEAS:CURR?" }, | |
123 | { SCPI_CMD_GET_MEAS_POWER, ":MEAS:POWER?" }, | |
124 | { SCPI_CMD_GET_VOLTAGE_TARGET, ":SOUR:VOLT?" }, | |
125 | { SCPI_CMD_SET_VOLTAGE_TARGET, ":SOUR:VOLT %.6f" }, | |
126 | { SCPI_CMD_GET_CURRENT_LIMIT, ":SOUR:CURR?" }, | |
127 | { SCPI_CMD_SET_CURRENT_LIMIT, ":SOUR:CURR %.6f" }, | |
128 | { SCPI_CMD_GET_OUTPUT_ENABLED, ":OUTP?" }, | |
129 | { SCPI_CMD_SET_OUTPUT_ENABLE, ":OUTP 1" }, | |
130 | { SCPI_CMD_SET_OUTPUT_DISABLE, ":OUTP 0" }, | |
131 | { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_THRESHOLD, ":SOUR:VOLT:PROT?" }, | |
132 | { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_THRESHOLD, ":SOUR:VOLT:PROT %.6f" }, | |
133 | ALL_ZERO | |
134 | }; | |
135 | ||
4ee1e2f3 AG |
136 | /* Chroma 61600 series AC source */ |
137 | static const uint32_t chroma_61604_devopts[] = { | |
e91bb0a6 | 138 | SR_CONF_CONTINUOUS, |
88e4daa9 ML |
139 | SR_CONF_LIMIT_SAMPLES | SR_CONF_GET | SR_CONF_SET, |
140 | SR_CONF_LIMIT_MSEC | SR_CONF_GET | SR_CONF_SET, | |
4ee1e2f3 AG |
141 | }; |
142 | ||
143 | static const uint32_t chroma_61604_devopts_cg[] = { | |
144 | SR_CONF_OVER_VOLTAGE_PROTECTION_THRESHOLD | SR_CONF_GET | SR_CONF_SET, | |
145 | SR_CONF_OVER_CURRENT_PROTECTION_THRESHOLD | SR_CONF_GET | SR_CONF_SET, | |
da005885 UH |
146 | SR_CONF_VOLTAGE | SR_CONF_GET, |
147 | SR_CONF_VOLTAGE_TARGET | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST, | |
6c0c9dd2 AG |
148 | SR_CONF_OUTPUT_FREQUENCY | SR_CONF_GET, |
149 | SR_CONF_OUTPUT_FREQUENCY_TARGET | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST, | |
da005885 UH |
150 | SR_CONF_CURRENT | SR_CONF_GET, |
151 | SR_CONF_ENABLED | SR_CONF_GET | SR_CONF_SET, | |
4ee1e2f3 AG |
152 | }; |
153 | ||
8cb5affe | 154 | static const struct channel_spec chroma_61604_ch[] = { |
49a468ed | 155 | { "1", { 0, 300, 0.1, 1, 1 }, { 0, 16, 0.1, 2, 2 }, { 0, 2000, 0, 1, 1 }, { 1.0, 1000.0, 0.01 }, NO_OVP_LIMITS, NO_OCP_LIMITS }, |
4ee1e2f3 AG |
156 | }; |
157 | ||
8cb5affe | 158 | static const struct channel_group_spec chroma_61604_cg[] = { |
f2bbcc33 | 159 | { "1", CH_IDX(0), PPS_OVP | PPS_OCP, SR_MQFLAG_AC }, |
4ee1e2f3 AG |
160 | }; |
161 | ||
8cb5affe | 162 | static const struct scpi_command chroma_61604_cmd[] = { |
4ee1e2f3 AG |
163 | { SCPI_CMD_REMOTE, "SYST:REM" }, |
164 | { SCPI_CMD_LOCAL, "SYST:LOC" }, | |
165 | { SCPI_CMD_GET_MEAS_VOLTAGE, ":FETC:VOLT:ACDC?" }, | |
6c0c9dd2 | 166 | { SCPI_CMD_GET_MEAS_FREQUENCY, ":FETC:FREQ?" }, |
4ee1e2f3 AG |
167 | { SCPI_CMD_GET_MEAS_CURRENT, ":FETC:CURR:AC?" }, |
168 | { SCPI_CMD_GET_MEAS_POWER, ":FETC:POW:AC?" }, | |
169 | { SCPI_CMD_GET_VOLTAGE_TARGET, ":SOUR:VOLT:AC?" }, | |
170 | { SCPI_CMD_SET_VOLTAGE_TARGET, ":SOUR:VOLT:AC %.1f" }, | |
6c0c9dd2 AG |
171 | { SCPI_CMD_GET_FREQUENCY_TARGET, ":SOUR:FREQ?" }, |
172 | { SCPI_CMD_SET_FREQUENCY_TARGET, ":SOUR:FREQ %.2f" }, | |
4ee1e2f3 AG |
173 | { SCPI_CMD_GET_OUTPUT_ENABLED, ":OUTP?" }, |
174 | { SCPI_CMD_SET_OUTPUT_ENABLE, ":OUTP ON" }, | |
175 | { SCPI_CMD_SET_OUTPUT_DISABLE, ":OUTP OFF" }, | |
176 | { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_THRESHOLD, ":SOUR:VOLT:LIM:AC?" }, | |
177 | { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_THRESHOLD, ":SOUR:VOLT:LIM:AC %.1f" }, | |
562a3490 | 178 | /* This is not a current limit mode. It is overcurrent protection. */ |
4ee1e2f3 AG |
179 | { SCPI_CMD_GET_OVER_CURRENT_PROTECTION_THRESHOLD, ":SOUR:CURR:LIM?" }, |
180 | { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_THRESHOLD, ":SOUR:CURR:LIM %.2f" }, | |
91ef511d | 181 | ALL_ZERO |
4ee1e2f3 AG |
182 | }; |
183 | ||
5281993e | 184 | /* Chroma 62000 series DC source */ |
5281993e | 185 | static const uint32_t chroma_62000_devopts[] = { |
e91bb0a6 | 186 | SR_CONF_CONTINUOUS, |
88e4daa9 ML |
187 | SR_CONF_LIMIT_SAMPLES | SR_CONF_GET | SR_CONF_SET, |
188 | SR_CONF_LIMIT_MSEC | SR_CONF_GET | SR_CONF_SET, | |
5281993e AG |
189 | }; |
190 | ||
191 | static const uint32_t chroma_62000_devopts_cg[] = { | |
192 | SR_CONF_OVER_VOLTAGE_PROTECTION_THRESHOLD | SR_CONF_GET | SR_CONF_SET, | |
193 | SR_CONF_OVER_CURRENT_PROTECTION_THRESHOLD | SR_CONF_GET | SR_CONF_SET, | |
194 | SR_CONF_VOLTAGE | SR_CONF_GET, | |
195 | SR_CONF_VOLTAGE_TARGET | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST, | |
196 | SR_CONF_CURRENT | SR_CONF_GET, | |
197 | SR_CONF_CURRENT_LIMIT | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST, | |
198 | SR_CONF_ENABLED | SR_CONF_GET | SR_CONF_SET, | |
199 | }; | |
200 | ||
5281993e | 201 | static const struct channel_group_spec chroma_62000_cg[] = { |
f2bbcc33 | 202 | { "1", CH_IDX(0), PPS_OVP | PPS_OCP, SR_MQFLAG_DC }, |
5281993e AG |
203 | }; |
204 | ||
205 | static const struct scpi_command chroma_62000_cmd[] = { | |
206 | { SCPI_CMD_REMOTE, ":CONF:REM ON" }, | |
207 | { SCPI_CMD_LOCAL, ":CONF:REM OFF" }, | |
208 | { SCPI_CMD_BEEPER, ":CONF:BEEP?" }, | |
209 | { SCPI_CMD_BEEPER_ENABLE, ":CONF:BEEP ON" }, | |
210 | { SCPI_CMD_BEEPER_DISABLE, ":CONF:BEEP OFF" }, | |
211 | { SCPI_CMD_GET_MEAS_VOLTAGE, ":MEAS:VOLT?" }, | |
212 | { SCPI_CMD_GET_MEAS_CURRENT, ":MEAS:CURR?" }, | |
213 | { SCPI_CMD_GET_MEAS_POWER, ":MEAS:POW?" }, | |
214 | { SCPI_CMD_GET_VOLTAGE_TARGET, ":SOUR:VOLT?" }, | |
215 | { SCPI_CMD_SET_VOLTAGE_TARGET, ":SOUR:VOLT %.2f" }, | |
216 | { SCPI_CMD_GET_CURRENT_LIMIT, ":SOUR:CURR?" }, | |
217 | { SCPI_CMD_SET_CURRENT_LIMIT, ":SOUR:CURR %.6f" }, | |
218 | { SCPI_CMD_GET_OUTPUT_ENABLED, ":CONF:OUTP?" }, | |
219 | { SCPI_CMD_SET_OUTPUT_ENABLE, ":CONF:OUTP ON" }, | |
220 | { SCPI_CMD_SET_OUTPUT_DISABLE, ":CONF:OUTP OFF" }, | |
221 | { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_THRESHOLD, ":SOUR:VOLT:PROT:HIGH?" }, | |
222 | { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_THRESHOLD, ":SOUR:VOLT:PROT:HIGH %.6f" }, | |
223 | { SCPI_CMD_GET_OVER_CURRENT_PROTECTION_THRESHOLD, ":SOUR:CURR:PROT:HIGH?" }, | |
224 | { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_THRESHOLD, ":SOUR:CURR:PROT:HIGH %.6f" }, | |
91ef511d | 225 | ALL_ZERO |
5281993e AG |
226 | }; |
227 | ||
9a5185c7 AG |
228 | static int chroma_62000p_probe_channels(struct sr_dev_inst *sdi, |
229 | struct sr_scpi_hw_info *hw_info, | |
230 | struct channel_spec **channels, unsigned int *num_channels, | |
231 | struct channel_group_spec **channel_groups, | |
232 | unsigned int *num_channel_groups) | |
233 | { | |
6ed709fe | 234 | unsigned int volts, amps, watts; |
9a5185c7 AG |
235 | struct channel_spec *channel; |
236 | ||
237 | (void)sdi; | |
238 | ||
6ed709fe AJ |
239 | sscanf(hw_info->model, "620%uP-%u-%u", &watts, &volts, &s); |
240 | watts *= 100; | |
241 | sr_dbg("Found device rated for %d V, %d A and %d W", volts, amps, watts); | |
9a5185c7 AG |
242 | |
243 | if (volts > 600) { | |
244 | sr_err("Probed max voltage of %u V is out of spec.", volts); | |
245 | return SR_ERR_BUG; | |
246 | } | |
247 | ||
6ed709fe | 248 | if (amps > 120) { |
9a5185c7 AG |
249 | sr_err("Probed max current of %u A is out of spec.", amps); |
250 | return SR_ERR_BUG; | |
251 | } | |
252 | ||
6ed709fe AJ |
253 | if (watts > 5000) { |
254 | sr_err("Probed max power of %u W is out of spec.", watts); | |
255 | return SR_ERR_BUG; | |
256 | } | |
257 | ||
9a5185c7 AG |
258 | channel = g_malloc0(sizeof(struct channel_spec)); |
259 | channel->name = "1"; | |
6ed709fe | 260 | channel->voltage[0] = channel->current[0] = channel->power[0] = 0.0; |
bcee1299 UH |
261 | channel->voltage[1] = volts; |
262 | channel->current[1] = amps; | |
263 | channel->power[1] = watts; | |
9a5185c7 | 264 | channel->voltage[2] = channel->current[2] = 0.01; |
6ed709fe AJ |
265 | channel->voltage[3] = channel->voltage[4] = 3; |
266 | channel->current[3] = channel->current[4] = 4; | |
9a5185c7 AG |
267 | *channels = channel; |
268 | *num_channels = 1; | |
269 | ||
270 | *channel_groups = g_malloc(sizeof(struct channel_group_spec)); | |
271 | **channel_groups = chroma_62000_cg[0]; | |
272 | *num_channel_groups = 1; | |
273 | ||
274 | return SR_OK; | |
275 | } | |
276 | ||
22fdb67f MA |
277 | /* Envox EEZ PSU Series */ |
278 | static const uint32_t eez_psu_devopts[] = { | |
279 | SR_CONF_CONTINUOUS, | |
280 | SR_CONF_LIMIT_SAMPLES | SR_CONF_GET | SR_CONF_SET, | |
281 | SR_CONF_LIMIT_MSEC | SR_CONF_GET | SR_CONF_SET, | |
282 | }; | |
283 | ||
284 | static const uint32_t eez_psu_devopts_cg[] = { | |
285 | SR_CONF_VOLTAGE | SR_CONF_GET, | |
286 | SR_CONF_VOLTAGE_TARGET | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST, | |
287 | SR_CONF_CURRENT | SR_CONF_GET, | |
288 | SR_CONF_CURRENT_LIMIT | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST, | |
289 | SR_CONF_ENABLED | SR_CONF_GET | SR_CONF_SET, | |
290 | SR_CONF_REGULATION | SR_CONF_GET, | |
291 | SR_CONF_OVER_VOLTAGE_PROTECTION_ACTIVE | SR_CONF_GET, | |
292 | SR_CONF_OVER_VOLTAGE_PROTECTION_THRESHOLD | SR_CONF_GET, | |
293 | SR_CONF_OVER_CURRENT_PROTECTION_ACTIVE | SR_CONF_GET, | |
294 | SR_CONF_OVER_CURRENT_PROTECTION_THRESHOLD | SR_CONF_GET, | |
295 | }; | |
296 | ||
297 | static const struct scpi_command eez_psu_cmd[] = { | |
298 | { SCPI_CMD_REMOTE, "SYST:REMOTE" }, | |
299 | { SCPI_CMD_LOCAL, "SYST:LOCAL" }, | |
300 | { SCPI_CMD_SELECT_CHANNEL, ":INST:NSEL %s" }, | |
301 | { SCPI_CMD_GET_MEAS_VOLTAGE, ":MEAS:VOLT?" }, | |
302 | { SCPI_CMD_GET_MEAS_CURRENT, ":MEAS:CURR?" }, | |
303 | { SCPI_CMD_GET_MEAS_POWER, ":MEAS:POWER?" }, | |
304 | { SCPI_CMD_GET_OUTPUT_REGULATION, ":OUTP:MODE?" }, | |
305 | { SCPI_CMD_GET_VOLTAGE_TARGET, ":SOUR:VOLT?" }, | |
306 | { SCPI_CMD_SET_VOLTAGE_TARGET, ":SOUR:VOLT %.2f" }, | |
307 | { SCPI_CMD_GET_CURRENT_LIMIT, ":SOUR:CURR?" }, | |
308 | { SCPI_CMD_SET_CURRENT_LIMIT, ":SOUR:CURR %.6f" }, | |
309 | { SCPI_CMD_GET_OUTPUT_ENABLED, ":OUTP?" }, | |
310 | { SCPI_CMD_SET_OUTPUT_ENABLE, ":OUTP ON" }, | |
311 | { SCPI_CMD_SET_OUTPUT_DISABLE, ":OUTP OFF" }, | |
312 | { SCPI_CMD_GET_OVER_CURRENT_PROTECTION_THRESHOLD, ":SOUR:CURR:PROT?" }, | |
313 | { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_THRESHOLD, ":SOUR:VOLT:PROT?" }, | |
314 | ALL_ZERO | |
315 | }; | |
316 | ||
317 | /* | |
318 | * The EEZ BB3 protocol currently specifies up to six channels. The older | |
319 | * EEZ PSU design only has room for two in its enclosure design. | |
320 | * | |
321 | * If a future model's SCPI spec allows more than six models then we can | |
322 | * extend this to support more. | |
323 | */ | |
324 | static const char *eez_psu_channel_names[] = { "1", "2", "3", "4", "5", "6", }; | |
325 | ||
326 | static int eez_psu_probe_channels(struct sr_dev_inst *sdi, | |
327 | struct sr_scpi_hw_info *hw_info, | |
328 | struct channel_spec **channels, unsigned int *num_channels, | |
329 | struct channel_group_spec **channel_groups, | |
330 | unsigned int *num_channel_groups) | |
331 | { | |
332 | struct sr_scpi_dev_inst *scpi; | |
333 | int ret, intval; | |
334 | size_t i, channel_count; | |
335 | double limit_val; | |
336 | const char *channel_name; | |
337 | ||
338 | /* | |
339 | * The EEZ PSU family is intended by the designer to be end-user | |
340 | * customizable, so this is intentionally a little more dynamic | |
341 | * than strictly necessary for the "stock" models, to make it | |
342 | * more likely to automatically support end-user upgrades of the | |
343 | * various ranges. | |
344 | * | |
345 | * The BB3 in particular supports various different modular | |
346 | * power supply frontends that offer different voltage/current | |
347 | * limits and different numbers of independent channels, such as | |
348 | * three PSU modules that have two channels each for a total of | |
349 | * six controllable channels. | |
350 | * | |
351 | * This currently supports both the original EEZ PSU design | |
352 | * (H24005, when in its stock build configuration) and the | |
353 | * successor EEZ BB3 design. | |
354 | */ | |
355 | ||
356 | scpi = sdi->conn; | |
357 | ret = sr_scpi_get_int(scpi, ":SYST:CHAN:COUN?", &intval); | |
358 | if (ret != SR_OK) { | |
359 | sr_err("Failed to probe EEZ PSU channel count."); | |
360 | return ret; | |
361 | } | |
362 | if (intval < 0) { | |
363 | sr_err("Suspicious channel count %d, ignoring.", intval); | |
364 | return SR_ERR_DATA; | |
365 | } | |
366 | channel_count = intval; | |
367 | if (channel_count > ARRAY_SIZE(eez_psu_channel_names)) { | |
368 | /* | |
369 | * No known EEZ PSU specifies more than six channels at | |
370 | * the time of writing, so it would be weird to get here | |
371 | * but we'll allow it to be robust. | |
372 | */ | |
373 | sr_warn("Only using first %zu of %zu EEZ PSU channels.", | |
374 | channel_count, ARRAY_SIZE(eez_psu_channel_names)); | |
375 | channel_count = ARRAY_SIZE(eez_psu_channel_names); | |
376 | } | |
377 | ||
378 | sr_spew("EEZ PSU (%s) has channel count %zu.", | |
379 | hw_info->model, channel_count); | |
380 | ||
381 | *channels = g_malloc0(sizeof(**channels) * channel_count); | |
382 | *channel_groups = g_malloc0(sizeof(**channel_groups) * channel_count); | |
383 | for (i = 0; i < channel_count; i++) { | |
384 | channel_name = eez_psu_channel_names[i]; | |
385 | ||
386 | /* | |
387 | * Select the channel to prepare for our various "get" | |
388 | * calls below. | |
389 | */ | |
390 | ret = sr_scpi_send(scpi, ":INST:NSEL %s", channel_name); | |
391 | if (ret != SR_OK) { | |
392 | sr_err("Failed to select %s to retrieve its limits.", | |
393 | channel_name); | |
394 | return ret; | |
395 | } | |
396 | ||
397 | (*channel_groups)[i].name = channel_name; | |
398 | (*channel_groups)[i].channel_index_mask = CH_IDX(i); | |
399 | (*channel_groups)[i].features = PPS_OVP | PPS_OCP; | |
400 | (*channel_groups)[i].mqflags = SR_MQFLAG_DC; | |
401 | ||
402 | (*channels)[i].name = channel_name; | |
403 | ||
404 | ret = sr_scpi_get_double(scpi, | |
405 | ":SYST:CHAN:INFO:CURR?", &limit_val); | |
406 | if (ret != SR_OK) { | |
407 | sr_err("Failed to read the current limit for %s.", | |
408 | channel_name); | |
409 | return ret; | |
410 | } | |
411 | (*channels)[i].current[0] = 0.0; | |
412 | (*channels)[i].current[1] = limit_val; | |
413 | (*channels)[i].current[2] = 0.01; /* Programming resolution. */ | |
414 | (*channels)[i].current[3] = 2; /* Spec digits. */ | |
415 | (*channels)[i].current[4] = 2; /* Encoding digits. */ | |
416 | ||
417 | ret = sr_scpi_get_double(scpi, | |
418 | ":SYST:CHAN:INFO:VOLT?", &limit_val); | |
419 | if (ret != SR_OK) { | |
420 | sr_err("Failed to read the voltage limit for %s.", | |
421 | channel_name); | |
422 | return ret; | |
423 | } | |
424 | (*channels)[i].voltage[0] = 0.0; | |
425 | (*channels)[i].voltage[1] = limit_val; | |
426 | (*channels)[i].voltage[2] = 0.01; /* Programming resolution. */ | |
427 | (*channels)[i].voltage[3] = 2; /* Spec digits. */ | |
428 | (*channels)[i].voltage[4] = 2; /* Encoding digits. */ | |
429 | ||
430 | ret = sr_scpi_get_double(scpi, | |
431 | ":SYST:CHAN:INFO:POW?", &limit_val); | |
432 | if (ret != SR_OK) { | |
433 | sr_err("Failed to read the power limit for %s.", | |
434 | channel_name); | |
435 | return ret; | |
436 | } | |
437 | (*channels)[i].power[0] = 0.0; | |
438 | (*channels)[i].power[1] = limit_val; | |
439 | (*channels)[i].power[2] = 0.01; /* Programming resolution. */ | |
440 | (*channels)[i].power[3] = 2; /* Spec digits. */ | |
441 | (*channels)[i].power[4] = 2; /* Encoding digits. */ | |
442 | } | |
443 | *num_channels = *num_channel_groups = channel_count; | |
444 | ||
445 | return SR_OK; | |
446 | } | |
447 | ||
319fe9ce UH |
448 | /* Rigol DP700 series */ |
449 | static const uint32_t rigol_dp700_devopts[] = { | |
450 | SR_CONF_CONTINUOUS, | |
88e4daa9 ML |
451 | SR_CONF_LIMIT_SAMPLES | SR_CONF_GET | SR_CONF_SET, |
452 | SR_CONF_LIMIT_MSEC | SR_CONF_GET | SR_CONF_SET, | |
319fe9ce UH |
453 | }; |
454 | ||
455 | static const uint32_t rigol_dp700_devopts_cg[] = { | |
456 | SR_CONF_REGULATION | SR_CONF_GET, | |
457 | SR_CONF_OVER_VOLTAGE_PROTECTION_ENABLED | SR_CONF_GET | SR_CONF_SET, | |
458 | SR_CONF_OVER_VOLTAGE_PROTECTION_ACTIVE | SR_CONF_GET, | |
d828b05e | 459 | SR_CONF_OVER_VOLTAGE_PROTECTION_THRESHOLD | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST, |
319fe9ce UH |
460 | SR_CONF_OVER_CURRENT_PROTECTION_ENABLED | SR_CONF_GET | SR_CONF_SET, |
461 | SR_CONF_OVER_CURRENT_PROTECTION_ACTIVE | SR_CONF_GET, | |
d828b05e | 462 | SR_CONF_OVER_CURRENT_PROTECTION_THRESHOLD | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST, |
319fe9ce UH |
463 | SR_CONF_VOLTAGE | SR_CONF_GET, |
464 | SR_CONF_VOLTAGE_TARGET | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST, | |
465 | SR_CONF_CURRENT | SR_CONF_GET, | |
466 | SR_CONF_CURRENT_LIMIT | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST, | |
467 | SR_CONF_ENABLED | SR_CONF_GET | SR_CONF_SET, | |
468 | }; | |
469 | ||
470 | static const struct channel_spec rigol_dp711_ch[] = { | |
d828b05e | 471 | { "1", { 0, 30, 0.01, 3, 3 }, { 0, 5, 0.01, 3, 3 }, { 0, 150, 0, 3, 3 }, FREQ_DC_ONLY, { 0.01, 33, 0.01}, { 0.01, 5.5, 0.01 } }, |
319fe9ce UH |
472 | }; |
473 | ||
474 | static const struct channel_spec rigol_dp712_ch[] = { | |
d828b05e | 475 | { "1", { 0, 50, 0.01, 3, 3 }, { 0, 3, 0.01, 3, 3 }, { 0, 150, 0, 3, 3 }, FREQ_DC_ONLY, { 0.01, 55, 0.01}, { 0.01, 3.3, 0.01 } }, |
319fe9ce UH |
476 | }; |
477 | ||
478 | static const struct channel_group_spec rigol_dp700_cg[] = { | |
f2bbcc33 | 479 | { "1", CH_IDX(0), PPS_OVP | PPS_OCP, SR_MQFLAG_DC }, |
319fe9ce UH |
480 | }; |
481 | ||
482 | /* Same as the DP800 series, except for the missing :SYST:OTP* commands. */ | |
483 | static const struct scpi_command rigol_dp700_cmd[] = { | |
484 | { SCPI_CMD_REMOTE, "SYST:REMOTE" }, | |
485 | { SCPI_CMD_LOCAL, "SYST:LOCAL" }, | |
486 | { SCPI_CMD_BEEPER, "SYST:BEEP:STAT?" }, | |
487 | { SCPI_CMD_BEEPER_ENABLE, "SYST:BEEP:STAT ON" }, | |
488 | { SCPI_CMD_BEEPER_DISABLE, "SYST:BEEP:STAT OFF" }, | |
489 | { SCPI_CMD_SELECT_CHANNEL, ":INST:NSEL %s" }, | |
490 | { SCPI_CMD_GET_MEAS_VOLTAGE, ":MEAS:VOLT?" }, | |
491 | { SCPI_CMD_GET_MEAS_CURRENT, ":MEAS:CURR?" }, | |
492 | { SCPI_CMD_GET_MEAS_POWER, ":MEAS:POWE?" }, | |
493 | { SCPI_CMD_GET_VOLTAGE_TARGET, ":SOUR:VOLT?" }, | |
494 | { SCPI_CMD_SET_VOLTAGE_TARGET, ":SOUR:VOLT %.6f" }, | |
495 | { SCPI_CMD_GET_CURRENT_LIMIT, ":SOUR:CURR?" }, | |
496 | { SCPI_CMD_SET_CURRENT_LIMIT, ":SOUR:CURR %.6f" }, | |
497 | { SCPI_CMD_GET_OUTPUT_ENABLED, ":OUTP?" }, | |
498 | { SCPI_CMD_SET_OUTPUT_ENABLE, ":OUTP ON" }, | |
499 | { SCPI_CMD_SET_OUTPUT_DISABLE, ":OUTP OFF" }, | |
500 | { SCPI_CMD_GET_OUTPUT_REGULATION, ":OUTP:MODE?" }, | |
501 | { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_ENABLED, ":OUTP:OVP?" }, | |
502 | { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_ENABLE, ":OUTP:OVP ON" }, | |
503 | { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_DISABLE, ":OUTP:OVP OFF" }, | |
504 | { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_ACTIVE, ":OUTP:OVP:QUES?" }, | |
505 | { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_THRESHOLD, ":OUTP:OVP:VAL?" }, | |
506 | { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_THRESHOLD, ":OUTP:OVP:VAL %.6f" }, | |
507 | { SCPI_CMD_GET_OVER_CURRENT_PROTECTION_ENABLED, ":OUTP:OCP?" }, | |
508 | { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_ENABLE, ":OUTP:OCP:STAT ON" }, | |
509 | { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_DISABLE, ":OUTP:OCP:STAT OFF" }, | |
510 | { SCPI_CMD_GET_OVER_CURRENT_PROTECTION_ACTIVE, ":OUTP:OCP:QUES?" }, | |
511 | { SCPI_CMD_GET_OVER_CURRENT_PROTECTION_THRESHOLD, ":OUTP:OCP:VAL?" }, | |
512 | { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_THRESHOLD, ":OUTP:OCP:VAL %.6f" }, | |
513 | ALL_ZERO | |
514 | }; | |
515 | ||
d4eabea8 | 516 | /* Rigol DP800 series */ |
584560f1 | 517 | static const uint32_t rigol_dp800_devopts[] = { |
e91bb0a6 | 518 | SR_CONF_CONTINUOUS, |
5827f61b | 519 | SR_CONF_OVER_TEMPERATURE_PROTECTION | SR_CONF_GET | SR_CONF_SET, |
88e4daa9 ML |
520 | SR_CONF_LIMIT_SAMPLES | SR_CONF_GET | SR_CONF_SET, |
521 | SR_CONF_LIMIT_MSEC | SR_CONF_GET | SR_CONF_SET, | |
d4eabea8 BV |
522 | }; |
523 | ||
584560f1 | 524 | static const uint32_t rigol_dp800_devopts_cg[] = { |
7a0b98b5 | 525 | SR_CONF_REGULATION | SR_CONF_GET, |
5827f61b BV |
526 | SR_CONF_OVER_VOLTAGE_PROTECTION_ENABLED | SR_CONF_GET | SR_CONF_SET, |
527 | SR_CONF_OVER_VOLTAGE_PROTECTION_ACTIVE | SR_CONF_GET, | |
528 | SR_CONF_OVER_VOLTAGE_PROTECTION_THRESHOLD | SR_CONF_GET | SR_CONF_SET, | |
529 | SR_CONF_OVER_CURRENT_PROTECTION_ENABLED | SR_CONF_GET | SR_CONF_SET, | |
530 | SR_CONF_OVER_CURRENT_PROTECTION_ACTIVE | SR_CONF_GET, | |
531 | SR_CONF_OVER_CURRENT_PROTECTION_THRESHOLD | SR_CONF_GET | SR_CONF_SET, | |
7a0b98b5 AJ |
532 | SR_CONF_VOLTAGE | SR_CONF_GET, |
533 | SR_CONF_VOLTAGE_TARGET | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST, | |
534 | SR_CONF_CURRENT | SR_CONF_GET, | |
535 | SR_CONF_CURRENT_LIMIT | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST, | |
536 | SR_CONF_ENABLED | SR_CONF_GET | SR_CONF_SET, | |
d4eabea8 BV |
537 | }; |
538 | ||
8cb5affe | 539 | static const struct channel_spec rigol_dp821a_ch[] = { |
49a468ed FS |
540 | { "1", { 0, 60, 0.001, 3, 3 }, { 0, 1, 0.0001, 4, 4 }, { 0, 60, 0, 3, 4 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS }, |
541 | { "2", { 0, 8, 0.001, 3, 3 }, { 0, 10, 0.001, 3, 3 }, { 0, 80, 0, 3, 3 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS }, | |
cfcdf576 ML |
542 | }; |
543 | ||
8cb5affe | 544 | static const struct channel_spec rigol_dp831_ch[] = { |
49a468ed FS |
545 | { "1", { 0, 8, 0.001, 3, 4 }, { 0, 5, 0.0003, 3, 4 }, { 0, 40, 0, 3, 4 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS }, |
546 | { "2", { 0, 30, 0.001, 3, 4 }, { 0, 2, 0.0001, 3, 4 }, { 0, 60, 0, 3, 4 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS }, | |
547 | { "3", { 0, -30, 0.001, 3, 4 }, { 0, 2, 0.0001, 3, 4 }, { 0, 60, 0, 3, 4 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS }, | |
d4eabea8 BV |
548 | }; |
549 | ||
8cb5affe | 550 | static const struct channel_spec rigol_dp832_ch[] = { |
49a468ed FS |
551 | { "1", { 0, 30, 0.001, 3, 4 }, { 0, 3, 0.001, 3, 4 }, { 0, 90, 0, 3, 4 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS }, |
552 | { "2", { 0, 30, 0.001, 3, 4 }, { 0, 3, 0.001, 3, 4 }, { 0, 90, 0, 3, 4 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS }, | |
553 | { "3", { 0, 5, 0.001, 3, 4 }, { 0, 3, 0.001, 3, 4 }, { 0, 90, 0, 3, 4 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS }, | |
3222ee10 BV |
554 | }; |
555 | ||
8cb5affe | 556 | static const struct channel_group_spec rigol_dp820_cg[] = { |
f2bbcc33 FS |
557 | { "1", CH_IDX(0), PPS_OVP | PPS_OCP, SR_MQFLAG_DC }, |
558 | { "2", CH_IDX(1), PPS_OVP | PPS_OCP, SR_MQFLAG_DC }, | |
cfcdf576 ML |
559 | }; |
560 | ||
8cb5affe | 561 | static const struct channel_group_spec rigol_dp830_cg[] = { |
f2bbcc33 FS |
562 | { "1", CH_IDX(0), PPS_OVP | PPS_OCP, SR_MQFLAG_DC }, |
563 | { "2", CH_IDX(1), PPS_OVP | PPS_OCP, SR_MQFLAG_DC }, | |
564 | { "3", CH_IDX(2), PPS_OVP | PPS_OCP, SR_MQFLAG_DC }, | |
d4eabea8 BV |
565 | }; |
566 | ||
8cb5affe | 567 | static const struct scpi_command rigol_dp800_cmd[] = { |
60475cd7 BV |
568 | { SCPI_CMD_REMOTE, "SYST:REMOTE" }, |
569 | { SCPI_CMD_LOCAL, "SYST:LOCAL" }, | |
ee2860ee BV |
570 | { SCPI_CMD_BEEPER, "SYST:BEEP:STAT?" }, |
571 | { SCPI_CMD_BEEPER_ENABLE, "SYST:BEEP:STAT ON" }, | |
572 | { SCPI_CMD_BEEPER_DISABLE, "SYST:BEEP:STAT OFF" }, | |
60475cd7 BV |
573 | { SCPI_CMD_SELECT_CHANNEL, ":INST:NSEL %s" }, |
574 | { SCPI_CMD_GET_MEAS_VOLTAGE, ":MEAS:VOLT?" }, | |
575 | { SCPI_CMD_GET_MEAS_CURRENT, ":MEAS:CURR?" }, | |
576 | { SCPI_CMD_GET_MEAS_POWER, ":MEAS:POWE?" }, | |
577 | { SCPI_CMD_GET_VOLTAGE_TARGET, ":SOUR:VOLT?" }, | |
578 | { SCPI_CMD_SET_VOLTAGE_TARGET, ":SOUR:VOLT %.6f" }, | |
579 | { SCPI_CMD_GET_CURRENT_LIMIT, ":SOUR:CURR?" }, | |
580 | { SCPI_CMD_SET_CURRENT_LIMIT, ":SOUR:CURR %.6f" }, | |
581 | { SCPI_CMD_GET_OUTPUT_ENABLED, ":OUTP?" }, | |
582 | { SCPI_CMD_SET_OUTPUT_ENABLE, ":OUTP ON" }, | |
583 | { SCPI_CMD_SET_OUTPUT_DISABLE, ":OUTP OFF" }, | |
584 | { SCPI_CMD_GET_OUTPUT_REGULATION, ":OUTP:MODE?" }, | |
d4eabea8 | 585 | { SCPI_CMD_GET_OVER_TEMPERATURE_PROTECTION, ":SYST:OTP?" }, |
53a81803 BV |
586 | { SCPI_CMD_SET_OVER_TEMPERATURE_PROTECTION_ENABLE, ":SYST:OTP ON" }, |
587 | { SCPI_CMD_SET_OVER_TEMPERATURE_PROTECTION_DISABLE, ":SYST:OTP OFF" }, | |
60475cd7 BV |
588 | { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_ENABLED, ":OUTP:OVP?" }, |
589 | { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_ENABLE, ":OUTP:OVP ON" }, | |
590 | { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_DISABLE, ":OUTP:OVP OFF" }, | |
591 | { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_ACTIVE, ":OUTP:OVP:QUES?" }, | |
592 | { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_THRESHOLD, ":OUTP:OVP:VAL?" }, | |
593 | { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_THRESHOLD, ":OUTP:OVP:VAL %.6f" }, | |
594 | { SCPI_CMD_GET_OVER_CURRENT_PROTECTION_ENABLED, ":OUTP:OCP?" }, | |
595 | { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_ENABLE, ":OUTP:OCP:STAT ON" }, | |
596 | { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_DISABLE, ":OUTP:OCP:STAT OFF" }, | |
597 | { SCPI_CMD_GET_OVER_CURRENT_PROTECTION_ACTIVE, ":OUTP:OCP:QUES?" }, | |
598 | { SCPI_CMD_GET_OVER_CURRENT_PROTECTION_THRESHOLD, ":OUTP:OCP:VAL?" }, | |
599 | { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_THRESHOLD, ":OUTP:OCP:VAL %.6f" }, | |
91ef511d | 600 | ALL_ZERO |
d4eabea8 BV |
601 | }; |
602 | ||
dbc519f7 | 603 | /* HP 663xA series */ |
e76a3575 AG |
604 | static const uint32_t hp_6630a_devopts[] = { |
605 | SR_CONF_CONTINUOUS, | |
88e4daa9 ML |
606 | SR_CONF_LIMIT_SAMPLES | SR_CONF_GET | SR_CONF_SET, |
607 | SR_CONF_LIMIT_MSEC | SR_CONF_GET | SR_CONF_SET, | |
7c517d02 FS |
608 | }; |
609 | ||
610 | static const uint32_t hp_6630a_devopts_cg[] = { | |
e76a3575 AG |
611 | SR_CONF_ENABLED | SR_CONF_SET, |
612 | SR_CONF_VOLTAGE | SR_CONF_GET, | |
613 | SR_CONF_CURRENT | SR_CONF_GET, | |
614 | SR_CONF_VOLTAGE_TARGET | SR_CONF_SET | SR_CONF_LIST, | |
615 | SR_CONF_CURRENT_LIMIT | SR_CONF_SET | SR_CONF_LIST, | |
f083ae63 | 616 | SR_CONF_OVER_VOLTAGE_PROTECTION_ACTIVE | SR_CONF_GET, |
49a468ed | 617 | SR_CONF_OVER_VOLTAGE_PROTECTION_THRESHOLD | SR_CONF_SET | SR_CONF_LIST, |
e76a3575 | 618 | SR_CONF_OVER_CURRENT_PROTECTION_ENABLED | SR_CONF_SET, |
f083ae63 FS |
619 | SR_CONF_OVER_CURRENT_PROTECTION_ACTIVE | SR_CONF_GET, |
620 | SR_CONF_OVER_TEMPERATURE_PROTECTION_ACTIVE | SR_CONF_GET, | |
0ad7074c | 621 | SR_CONF_REGULATION | SR_CONF_GET, |
e76a3575 AG |
622 | }; |
623 | ||
5ce427c7 FS |
624 | static const struct channel_spec hp_6632a_ch[] = { |
625 | { "1", { 0, 20.475, 0.005, 3, 4 }, { 0, 5.1188, 0.00125, 4, 5 }, { 0, 104.80743 }, FREQ_DC_ONLY, { 0, 22, 0.1 }, NO_OCP_LIMITS }, | |
626 | }; | |
627 | ||
dbc519f7 FS |
628 | static const struct channel_spec hp_6633a_ch[] = { |
629 | { "1", { 0, 51.188, 0.0125, 3, 4 }, { 0, 2.0475, 0.0005, 4, 5 }, { 0, 104.80743 }, FREQ_DC_ONLY, { 0, 55, 0.25 }, NO_OCP_LIMITS }, | |
630 | }; | |
631 | ||
5ce427c7 FS |
632 | static const struct channel_spec hp_6634a_ch[] = { |
633 | { "1", { 0, 102.38, 0.025, 3, 4 }, { 0, 1.0238, 0.00025, 4, 5 }, { 0, 104.81664 }, FREQ_DC_ONLY, { 0, 110, 0.5 }, NO_OCP_LIMITS }, | |
634 | }; | |
635 | ||
dbc519f7 FS |
636 | static const struct channel_group_spec hp_6630a_cg[] = { |
637 | { "1", CH_IDX(0), PPS_OVP | PPS_OCP, SR_MQFLAG_DC }, | |
638 | }; | |
639 | ||
640 | static const struct scpi_command hp_6630a_cmd[] = { | |
641 | { SCPI_CMD_SET_OUTPUT_ENABLE, "OUT 1" }, | |
642 | { SCPI_CMD_SET_OUTPUT_DISABLE, "OUT 0" }, | |
643 | { SCPI_CMD_GET_MEAS_VOLTAGE, "VOUT?" }, | |
644 | { SCPI_CMD_GET_MEAS_CURRENT, "IOUT?" }, | |
645 | { SCPI_CMD_SET_VOLTAGE_TARGET, "VSET %.4f" }, | |
646 | { SCPI_CMD_SET_CURRENT_LIMIT, "ISET %.4f" }, | |
f083ae63 FS |
647 | { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_ACTIVE, "STS?" }, |
648 | { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_THRESHOLD, "OVSET %.4f" }, | |
dbc519f7 FS |
649 | { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_ENABLE, "OCP 1" }, |
650 | { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_DISABLE, "OCP 0" }, | |
f083ae63 FS |
651 | { SCPI_CMD_GET_OVER_CURRENT_PROTECTION_ACTIVE, "STS?" }, |
652 | { SCPI_CMD_GET_OVER_TEMPERATURE_PROTECTION_ACTIVE, "STS?" }, | |
0ad7074c | 653 | { SCPI_CMD_GET_OUTPUT_REGULATION, "STS?" }, |
dbc519f7 FS |
654 | ALL_ZERO |
655 | }; | |
656 | ||
fd243315 | 657 | static int hp_6630a_init_acquisition(const struct sr_dev_inst *sdi) |
fdf03652 FS |
658 | { |
659 | struct sr_scpi_dev_inst *scpi; | |
fdf03652 FS |
660 | |
661 | scpi = sdi->conn; | |
662 | ||
663 | /* | |
664 | * Monitor CV (1), CC+ (2), UR (4), OVP (8), OTP (16), OCP (64) and | |
665 | * CC- (256) bits of the Status Register for the FAULT? query. | |
666 | */ | |
b89e6db9 | 667 | return sr_scpi_send(scpi, "UNMASK 607"); |
fdf03652 FS |
668 | } |
669 | ||
670 | static int hp_6630a_update_status(const struct sr_dev_inst *sdi) | |
671 | { | |
672 | struct sr_scpi_dev_inst *scpi; | |
673 | int ret; | |
674 | int fault; | |
675 | gboolean cv, cc_pos, unreg, cc_neg; | |
676 | gboolean regulation_changed; | |
677 | char *regulation; | |
678 | ||
679 | scpi = sdi->conn; | |
680 | ||
681 | /* | |
682 | * Use the FAULT register (only 0->1 transitions), this way multiple set | |
683 | * regulation bits in the STS/ASTS registers are ignored. In rare cases | |
684 | * we will miss some changes (1->0 transitions, e.g. no regulation at all), | |
685 | * but SPS/ASPS doesn't work either, unless all states are stored and | |
686 | * compared to the states in STS/ASTS. | |
687 | * TODO: Use SPoll or SRQ when SCPI over GPIB is used. | |
688 | */ | |
689 | ret = sr_scpi_get_int(scpi, "FAULT?", &fault); | |
690 | if (ret != SR_OK) | |
691 | return ret; | |
692 | ||
693 | /* OVP */ | |
694 | if (fault & (1 << 3)) | |
695 | sr_session_send_meta(sdi, SR_CONF_OVER_VOLTAGE_PROTECTION_ACTIVE, | |
696 | g_variant_new_boolean(fault & (1 << 3))); | |
697 | ||
698 | /* OCP */ | |
699 | if (fault & (1 << 6)) | |
700 | sr_session_send_meta(sdi, SR_CONF_OVER_CURRENT_PROTECTION_ACTIVE, | |
701 | g_variant_new_boolean(fault & (1 << 6))); | |
702 | ||
703 | /* OTP */ | |
704 | if (fault & (1 << 4)) | |
705 | sr_session_send_meta(sdi, SR_CONF_OVER_TEMPERATURE_PROTECTION_ACTIVE, | |
706 | g_variant_new_boolean(fault & (1 << 4))); | |
707 | ||
708 | /* CV */ | |
709 | cv = (fault & (1 << 0)); | |
710 | regulation_changed = (fault & (1 << 0)); | |
711 | /* CC+ */ | |
712 | cc_pos = (fault & (1 << 1)); | |
713 | regulation_changed = (fault & (1 << 1)) | regulation_changed; | |
714 | /* UNREG */ | |
715 | unreg = (fault & (1 << 2)); | |
716 | regulation_changed = (fault & (1 << 2)) | regulation_changed; | |
717 | /* CC- */ | |
718 | cc_neg = (fault & (1 << 9)); | |
719 | regulation_changed = (fault & (1 << 9)) | regulation_changed; | |
720 | ||
721 | if (regulation_changed) { | |
b89e6db9 | 722 | if (cv && !cc_pos && !cc_neg && !unreg) |
fdf03652 FS |
723 | regulation = "CV"; |
724 | else if (cc_pos && !cv && !cc_neg && !unreg) | |
725 | regulation = "CC"; | |
726 | else if (cc_neg && !cv && !cc_pos && !unreg) | |
727 | regulation = "CC-"; | |
728 | else if (unreg && !cv && !cc_pos && !cc_neg) | |
729 | regulation = "UR"; | |
b89e6db9 | 730 | else if (!cv && !cc_pos && !cc_neg && !unreg) |
fdf03652 FS |
731 | regulation = ""; |
732 | else { | |
733 | sr_dbg("Undefined regulation for HP 66xxA " | |
734 | "(CV=%i, CC+=%i, CC-=%i, UR=%i).", | |
735 | cv, cc_pos, cc_neg, unreg); | |
736 | return FALSE; | |
737 | } | |
738 | sr_session_send_meta(sdi, SR_CONF_REGULATION, | |
739 | g_variant_new_string(regulation)); | |
740 | } | |
741 | ||
742 | return SR_OK; | |
743 | } | |
744 | ||
dbc519f7 | 745 | /* HP 663xB series */ |
a61c8cce | 746 | static const uint32_t hp_6630b_devopts[] = { |
e91bb0a6 | 747 | SR_CONF_CONTINUOUS, |
88e4daa9 ML |
748 | SR_CONF_LIMIT_SAMPLES | SR_CONF_GET | SR_CONF_SET, |
749 | SR_CONF_LIMIT_MSEC | SR_CONF_GET | SR_CONF_SET, | |
7c517d02 FS |
750 | }; |
751 | ||
a61c8cce | 752 | static const uint32_t hp_6630b_devopts_cg[] = { |
7a0b98b5 AJ |
753 | SR_CONF_ENABLED | SR_CONF_GET | SR_CONF_SET, |
754 | SR_CONF_VOLTAGE | SR_CONF_GET, | |
755 | SR_CONF_CURRENT | SR_CONF_GET, | |
756 | SR_CONF_VOLTAGE_TARGET | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST, | |
757 | SR_CONF_CURRENT_LIMIT | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST, | |
8b5eadf4 | 758 | SR_CONF_OVER_VOLTAGE_PROTECTION_ACTIVE | SR_CONF_GET, |
49a468ed | 759 | SR_CONF_OVER_VOLTAGE_PROTECTION_THRESHOLD | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST, |
7e381bfc | 760 | SR_CONF_OVER_CURRENT_PROTECTION_ENABLED | SR_CONF_GET | SR_CONF_SET, |
8b5eadf4 FS |
761 | SR_CONF_OVER_CURRENT_PROTECTION_ACTIVE | SR_CONF_GET, |
762 | SR_CONF_OVER_TEMPERATURE_PROTECTION_ACTIVE | SR_CONF_GET, | |
43ff1110 | 763 | SR_CONF_REGULATION | SR_CONF_GET, |
bc4a2a46 BV |
764 | }; |
765 | ||
5ce427c7 FS |
766 | static const struct channel_spec hp_6611c_ch[] = { |
767 | { "1", { 0, 8.19, 0.002, 3, 4 }, { 0, 5.1188, 0.00125, 4, 5 }, { 0, 41.92297 }, FREQ_DC_ONLY, { 0, 12, 0.06 }, NO_OCP_LIMITS }, | |
768 | }; | |
769 | ||
770 | static const struct channel_spec hp_6612c_ch[] = { | |
771 | { "1", { 0, 20.475, 0.005, 3, 4 }, { 0, 2.0475, 0.0005, 4, 5 }, { 0, 41.92256 }, FREQ_DC_ONLY, { 0, 22, 0.1 }, NO_OCP_LIMITS }, | |
772 | }; | |
773 | ||
774 | static const struct channel_spec hp_6613c_ch[] = { | |
775 | { "1", { 0, 51.188, 0.0125, 3, 4 }, { 0, 1.0238, 0.00025, 4, 5 }, { 0, 52.40627 }, FREQ_DC_ONLY, { 0, 55, 0.25 }, NO_OCP_LIMITS }, | |
776 | }; | |
777 | ||
778 | static const struct channel_spec hp_6614c_ch[] = { | |
779 | { "1", { 0, 102.38, 0.025, 3, 4 }, { 0, 0.5118, 0.000125, 4, 5 }, { 0, 52.39808 }, FREQ_DC_ONLY, { 0, 110, 0.5 }, NO_OCP_LIMITS }, | |
780 | }; | |
781 | ||
a61c8cce | 782 | static const struct channel_spec hp_6631b_ch[] = { |
49a468ed | 783 | { "1", { 0, 8.19, 0.002, 3, 4 }, { 0, 10.237, 0.00263, 4, 5 }, { 0, 83.84103 }, FREQ_DC_ONLY, { 0, 12, 0.06 }, NO_OCP_LIMITS }, |
a61c8cce FS |
784 | }; |
785 | ||
8cb5affe | 786 | static const struct channel_spec hp_6632b_ch[] = { |
49a468ed | 787 | { "1", { 0, 20.475, 0.005, 3, 4 }, { 0, 5.1188, 0.00132, 4, 5 }, { 0, 104.80743 }, FREQ_DC_ONLY, { 0, 22, 0.1 }, NO_OCP_LIMITS }, |
bc4a2a46 BV |
788 | }; |
789 | ||
0b0f40d8 MW |
790 | static const struct channel_spec hp_66312a_ch[] = { |
791 | { "1", { 0, 20.475, 0.0001, 4, 5 }, { 0, 2.0475, 0.0001, 4, 5 }, { 0, 41.92256 }, FREQ_DC_ONLY, { 0, 22, 0.01 }, NO_OCP_LIMITS }, | |
792 | }; | |
793 | ||
a61c8cce | 794 | static const struct channel_spec hp_66332a_ch[] = { |
49a468ed | 795 | { "1", { 0, 20.475, 0.005, 3, 4 }, { 0, 5.1188, 0.00132, 4, 5 }, { 0, 104.80743 }, FREQ_DC_ONLY, { 0, 22, 0.1 }, NO_OCP_LIMITS }, |
a61c8cce FS |
796 | }; |
797 | ||
798 | static const struct channel_spec hp_6633b_ch[] = { | |
49a468ed | 799 | { "1", { 0, 51.188, 0.0125, 3, 4 }, { 0, 2.0475, 0.000526, 4, 5 }, { 0, 104.80743 }, FREQ_DC_ONLY, { 0, 55, 0.25 }, NO_OCP_LIMITS }, |
a61c8cce FS |
800 | }; |
801 | ||
802 | static const struct channel_spec hp_6634b_ch[] = { | |
49a468ed | 803 | { "1", { 0, 102.38, 0.025, 3, 4 }, { 0, 1.0238, 0.000263, 4, 5 }, { 0, 104.81664 }, FREQ_DC_ONLY, { 0, 110, 0.5 }, NO_OCP_LIMITS }, |
a61c8cce FS |
804 | }; |
805 | ||
dbc519f7 | 806 | static const struct channel_group_spec hp_6630b_cg[] = { |
3d1aa50f | 807 | { "1", CH_IDX(0), PPS_OVP | PPS_OCP, SR_MQFLAG_DC }, |
bc4a2a46 BV |
808 | }; |
809 | ||
a61c8cce | 810 | static const struct scpi_command hp_6630b_cmd[] = { |
26e96658 FS |
811 | /* |
812 | * SCPI_CMD_REMOTE and SCPI_CMD_LOCAL are not used when GPIB is used, | |
813 | * otherwise the device will report (non critical) error 602. | |
814 | */ | |
7e381bfc FS |
815 | { SCPI_CMD_REMOTE, "SYST:REM" }, |
816 | { SCPI_CMD_LOCAL, "SYST:LOC" }, | |
bc4a2a46 | 817 | { SCPI_CMD_GET_OUTPUT_ENABLED, "OUTP:STAT?" }, |
53a81803 BV |
818 | { SCPI_CMD_SET_OUTPUT_ENABLE, "OUTP:STAT ON" }, |
819 | { SCPI_CMD_SET_OUTPUT_DISABLE, "OUTP:STAT OFF" }, | |
bc4a2a46 BV |
820 | { SCPI_CMD_GET_MEAS_VOLTAGE, ":MEAS:VOLT?" }, |
821 | { SCPI_CMD_GET_MEAS_CURRENT, ":MEAS:CURR?" }, | |
ca95e90f BV |
822 | { SCPI_CMD_GET_VOLTAGE_TARGET, ":SOUR:VOLT?" }, |
823 | { SCPI_CMD_SET_VOLTAGE_TARGET, ":SOUR:VOLT %.6f" }, | |
824 | { SCPI_CMD_GET_CURRENT_LIMIT, ":SOUR:CURR?" }, | |
825 | { SCPI_CMD_SET_CURRENT_LIMIT, ":SOUR:CURR %.6f" }, | |
7e381bfc FS |
826 | { SCPI_CMD_GET_OVER_CURRENT_PROTECTION_ENABLED, ":CURR:PROT:STAT?" }, |
827 | { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_ENABLE, ":CURR:PROT:STAT 1" }, | |
828 | { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_DISABLE, ":CURR:PROT:STAT 0" }, | |
8b5eadf4 FS |
829 | { SCPI_CMD_GET_OVER_CURRENT_PROTECTION_ACTIVE, "STAT:QUES:COND?" }, |
830 | { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_ACTIVE, "STAT:QUES:COND?" }, | |
7e381bfc FS |
831 | { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_THRESHOLD, ":VOLT:PROT?" }, |
832 | { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_THRESHOLD, ":VOLT:PROT %.6f" }, | |
8b5eadf4 | 833 | { SCPI_CMD_GET_OVER_TEMPERATURE_PROTECTION_ACTIVE, "STAT:QUES:COND?" }, |
43ff1110 | 834 | { SCPI_CMD_GET_OUTPUT_REGULATION, "STAT:OPER:COND?" }, |
91ef511d | 835 | ALL_ZERO |
bc4a2a46 BV |
836 | }; |
837 | ||
fd243315 | 838 | static int hp_6630b_init_acquisition(const struct sr_dev_inst *sdi) |
fe4bb774 FS |
839 | { |
840 | struct sr_scpi_dev_inst *scpi; | |
841 | int ret; | |
842 | ||
843 | scpi = sdi->conn; | |
844 | ||
845 | /* | |
846 | * Monitor CV (256), CC+ (1024) and CC- (2048) bits of the | |
847 | * Operational Status Register. | |
848 | * Use both positive and negative transitions of the status bits. | |
849 | */ | |
850 | ret = sr_scpi_send(scpi, "STAT:OPER:PTR 3328;NTR 3328;ENAB 3328"); | |
851 | if (ret != SR_OK) | |
852 | return ret; | |
853 | ||
854 | /* | |
855 | * Monitor OVP (1), OCP (2), OTP (16) and Unreg (1024) bits of the | |
856 | * Questionable Status Register. | |
857 | * Use both positive and negative transitions of the status bits. | |
858 | */ | |
859 | ret = sr_scpi_send(scpi, "STAT:QUES:PTR 1043;NTR 1043;ENAB 1043"); | |
860 | if (ret != SR_OK) | |
861 | return ret; | |
862 | ||
863 | /* | |
864 | * Service Request Enable Register set for Operational Status Register | |
865 | * bits (128) and Questionable Status Register bits (8). | |
866 | * This masks the Status Register generating a SRQ/RQS. Not implemented yet! | |
867 | */ | |
868 | /* | |
869 | ret = sr_scpi_send(scpi, "*SRE 136"); | |
870 | if (ret != SR_OK) | |
871 | return ret; | |
872 | */ | |
873 | ||
874 | return SR_OK; | |
875 | } | |
876 | ||
877 | static int hp_6630b_update_status(const struct sr_dev_inst *sdi) | |
878 | { | |
879 | struct sr_scpi_dev_inst *scpi; | |
880 | int ret; | |
881 | int stb; | |
882 | int ques_even, ques_cond; | |
883 | int oper_even, oper_cond; | |
884 | gboolean output_enabled; | |
885 | gboolean unreg, cv, cc_pos, cc_neg; | |
886 | gboolean regulation_changed; | |
887 | char *regulation; | |
888 | ||
889 | scpi = sdi->conn; | |
890 | ||
891 | unreg = FALSE; | |
892 | cv = FALSE; | |
893 | cc_pos = FALSE; | |
894 | cc_neg = FALSE; | |
895 | regulation_changed = FALSE; | |
896 | ||
897 | /* | |
898 | * Use SPoll when SCPI uses GPIB as transport layer. | |
899 | * SPoll is approx. twice as fast as a normal GPIB write + read would be! | |
900 | */ | |
901 | #ifdef HAVE_LIBGPIB | |
902 | char spoll_buf; | |
903 | ||
904 | if (scpi->transport == SCPI_TRANSPORT_LIBGPIB) { | |
905 | ret = sr_scpi_gpib_spoll(scpi, &spoll_buf); | |
906 | if (ret != SR_OK) | |
907 | return ret; | |
908 | stb = (uint8_t)spoll_buf; | |
909 | } | |
910 | else { | |
911 | #endif | |
912 | ret = sr_scpi_get_int(scpi, "*STB?", &stb); | |
913 | if (ret != SR_OK) | |
914 | return ret; | |
915 | #ifdef HAVE_LIBGPIB | |
916 | } | |
917 | #endif | |
918 | ||
919 | /* Questionable status summary bit */ | |
920 | if (stb & (1 << 3)) { | |
921 | /* Read the event register to clear it! */ | |
922 | ret = sr_scpi_get_int(scpi, "STAT:QUES:EVEN?", &ques_even); | |
923 | if (ret != SR_OK) | |
924 | return ret; | |
925 | /* Now get the values. */ | |
926 | ret = sr_scpi_get_int(scpi, "STAT:QUES:COND?", &ques_cond); | |
927 | if (ret != SR_OK) | |
928 | return ret; | |
929 | ||
930 | /* OVP */ | |
931 | if (ques_even & (1 << 0)) | |
932 | sr_session_send_meta(sdi, SR_CONF_OVER_VOLTAGE_PROTECTION_ACTIVE, | |
933 | g_variant_new_boolean(ques_cond & (1 << 0))); | |
934 | ||
935 | /* OCP */ | |
936 | if (ques_even & (1 << 1)) | |
937 | sr_session_send_meta(sdi, SR_CONF_OVER_CURRENT_PROTECTION_ACTIVE, | |
938 | g_variant_new_boolean(ques_cond & (1 << 1))); | |
939 | ||
940 | /* OTP */ | |
941 | if (ques_even & (1 << 4)) | |
942 | sr_session_send_meta(sdi, SR_CONF_OVER_TEMPERATURE_PROTECTION_ACTIVE, | |
943 | g_variant_new_boolean(ques_cond & (1 << 4))); | |
944 | ||
945 | /* UNREG */ | |
946 | unreg = (ques_cond & (1 << 10)); | |
947 | regulation_changed = (ques_even & (1 << 10)) | regulation_changed; | |
948 | ||
949 | /* | |
950 | * Check if output state has changed, due to one of the | |
951 | * questionable states changed. | |
b89e6db9 UH |
952 | * NOTE: The output state is sent even if it hasn't changed, |
953 | * but that only happens rarely. | |
fe4bb774 FS |
954 | */ |
955 | ret = sr_scpi_get_bool(scpi, "OUTP:STAT?", &output_enabled); | |
956 | if (ret != SR_OK) | |
957 | return ret; | |
958 | sr_session_send_meta(sdi, SR_CONF_ENABLED, | |
959 | g_variant_new_boolean(output_enabled)); | |
960 | } | |
961 | ||
962 | /* Operation status summary bit */ | |
963 | if (stb & (1 << 7)) { | |
964 | /* Read the event register to clear it! */ | |
965 | ret = sr_scpi_get_int(scpi, "STAT:OPER:EVEN?", &oper_even); | |
966 | if (ret != SR_OK) | |
967 | return ret; | |
968 | /* Now get the values. */ | |
969 | ret = sr_scpi_get_int(scpi, "STAT:OPER:COND?", &oper_cond); | |
970 | if (ret != SR_OK) | |
971 | return ret; | |
972 | ||
973 | /* CV */ | |
974 | cv = (oper_cond & (1 << 8)); | |
975 | regulation_changed = (oper_even & (1 << 8)) | regulation_changed; | |
976 | /* CC+ */ | |
977 | cc_pos = (oper_cond & (1 << 10)); | |
978 | regulation_changed = (oper_even & (1 << 10)) | regulation_changed; | |
979 | /* CC- */ | |
980 | cc_neg = (oper_cond & (1 << 11)); | |
981 | regulation_changed = (oper_even & (1 << 11)) | regulation_changed; | |
982 | } | |
983 | ||
984 | if (regulation_changed) { | |
b89e6db9 | 985 | if (cv && !cc_pos && !cc_neg && !unreg) |
fe4bb774 FS |
986 | regulation = "CV"; |
987 | else if (cc_pos && !cv && !cc_neg && !unreg) | |
988 | regulation = "CC"; | |
989 | else if (cc_neg && !cv && !cc_pos && !unreg) | |
990 | regulation = "CC-"; | |
991 | else if (unreg && !cv && !cc_pos && !cc_neg) | |
992 | regulation = "UR"; | |
b89e6db9 UH |
993 | else if (!cv && !cc_pos && !cc_neg && !unreg) |
994 | /* This happens in case of OCP active. */ | |
fe4bb774 FS |
995 | regulation = ""; |
996 | else { | |
b89e6db9 | 997 | /* This happens from time to time (CV and CC+ active). */ |
fe4bb774 FS |
998 | sr_dbg("Undefined regulation for HP 66xxB " |
999 | "(CV=%i, CC+=%i, CC-=%i, UR=%i).", | |
1000 | cv, cc_pos, cc_neg, unreg); | |
1001 | return FALSE; | |
1002 | } | |
1003 | sr_session_send_meta(sdi, SR_CONF_REGULATION, | |
1004 | g_variant_new_string(regulation)); | |
1005 | } | |
1006 | ||
1007 | return SR_OK; | |
1008 | } | |
1009 | ||
5433907e PA |
1010 | /* Owon P4000 series */ |
1011 | static const uint32_t owon_p4000_devopts[] = { | |
1012 | SR_CONF_CONTINUOUS, | |
1013 | SR_CONF_LIMIT_SAMPLES | SR_CONF_GET | SR_CONF_SET, | |
1014 | SR_CONF_LIMIT_MSEC | SR_CONF_GET | SR_CONF_SET | |
1015 | }; | |
1016 | ||
1017 | static const uint32_t owon_p4000_devopts_cg[] = { | |
1018 | SR_CONF_ENABLED | SR_CONF_GET | SR_CONF_SET, | |
1019 | SR_CONF_VOLTAGE | SR_CONF_GET, | |
1020 | SR_CONF_VOLTAGE_TARGET | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST, | |
1021 | SR_CONF_CURRENT | SR_CONF_GET, | |
1022 | SR_CONF_CURRENT_LIMIT | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST, | |
1023 | SR_CONF_OVER_VOLTAGE_PROTECTION_THRESHOLD | SR_CONF_GET | SR_CONF_SET, | |
1024 | SR_CONF_OVER_CURRENT_PROTECTION_THRESHOLD | SR_CONF_GET | SR_CONF_SET, | |
1025 | }; | |
1026 | ||
1027 | static const struct channel_spec owon_p4603_ch[] = { | |
1028 | { "1", { 0.01, 60, 0.001, 3, 3 }, { 0.001, 3, 0.001, 3, 3 }, { 0, 180, 0, 3, 3 }, FREQ_DC_ONLY, { 0.01, 61, 0.001}, { 0.001, 3.1, 0.001} }, | |
1029 | }; | |
1030 | ||
1031 | static const struct channel_spec owon_p4305_ch[] = { | |
1032 | { "1", { 0.01, 30, 0.001, 3, 3 }, { 0.001, 5, 0.001, 3, 3 }, { 0, 180, 0, 3, 3 }, FREQ_DC_ONLY, { 0.01, 31, 0.001}, { 0.001, 3.1, 0.001} }, | |
1033 | }; | |
1034 | ||
1035 | static const struct channel_group_spec owon_p4000_cg[] = { | |
1036 | { "1", CH_IDX(0), PPS_OVP | PPS_OCP, SR_MQFLAG_DC }, | |
1037 | }; | |
1038 | ||
1039 | static const struct scpi_command owon_p4000_cmd[] = { | |
1040 | { SCPI_CMD_GET_MEAS_VOLTAGE, "MEAS:VOLT?" }, | |
1041 | { SCPI_CMD_GET_MEAS_CURRENT, "MEAS:CURR?" }, | |
1042 | { SCPI_CMD_GET_MEAS_POWER, "MEAS:POW?" }, | |
1043 | { SCPI_CMD_GET_VOLTAGE_TARGET, "VOLT?" }, | |
1044 | { SCPI_CMD_SET_VOLTAGE_TARGET, "VOLT %.6f" }, | |
1045 | { SCPI_CMD_GET_CURRENT_LIMIT, "CURR?" }, | |
1046 | { SCPI_CMD_SET_CURRENT_LIMIT, "CURR %.6f" }, | |
1047 | { SCPI_CMD_GET_OUTPUT_ENABLED, "OUTP?" }, | |
1048 | { SCPI_CMD_SET_OUTPUT_ENABLE, "OUTP 1" }, | |
1049 | { SCPI_CMD_SET_OUTPUT_DISABLE, "OUTP 0" }, | |
1050 | { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_THRESHOLD, "VOLT:LIM?" }, | |
1051 | { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_THRESHOLD, "VOLT:LIM %.6f" }, | |
1052 | { SCPI_CMD_GET_OVER_CURRENT_PROTECTION_THRESHOLD, "CURR:LIM?" }, | |
1053 | { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_THRESHOLD, "CURR:LIM %.6f" }, | |
1054 | ALL_ZERO | |
1055 | }; | |
1056 | ||
20a28434 SS |
1057 | /* Owon SPE series*/ |
1058 | ||
1059 | static const struct channel_spec owon_spe6103_ch[] = { | |
1060 | { "1", { 0.01, 60, 0.01, 3, 3 }, { 0.001, 10, 0.001, 3, 3 }, { 0, 300, 0, 3, 3 }, FREQ_DC_ONLY, { 0.01, 61, 0.01}, { 0.001, 10.1, 0.001} }, | |
1061 | }; | |
1062 | ||
1063 | static const struct scpi_command owon_spe6103_cmd[] = { | |
1064 | { SCPI_CMD_REMOTE, "SYST:REM" }, | |
1065 | { SCPI_CMD_LOCAL, "SYST:LOC" }, | |
1066 | { SCPI_CMD_GET_MEAS_VOLTAGE, "MEAS:VOLT?" }, | |
1067 | { SCPI_CMD_GET_MEAS_CURRENT, "MEAS:CURR?" }, | |
1068 | { SCPI_CMD_GET_MEAS_POWER, "MEAS:POW?" }, | |
1069 | { SCPI_CMD_GET_VOLTAGE_TARGET, "VOLT?" }, | |
1070 | { SCPI_CMD_SET_VOLTAGE_TARGET, "VOLT %.6f" }, | |
1071 | { SCPI_CMD_GET_CURRENT_LIMIT, "CURR?" }, | |
1072 | { SCPI_CMD_SET_CURRENT_LIMIT, "CURR %.6f" }, | |
1073 | { SCPI_CMD_GET_OUTPUT_ENABLED, "OUTP?" }, | |
1074 | { SCPI_CMD_SET_OUTPUT_ENABLE, "OUTP 1" }, | |
1075 | { SCPI_CMD_SET_OUTPUT_DISABLE, "OUTP 0" }, | |
1076 | { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_THRESHOLD, "VOLT:LIM?" }, | |
1077 | { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_THRESHOLD, "VOLT:LIM %.6f" }, | |
1078 | { SCPI_CMD_GET_OVER_CURRENT_PROTECTION_THRESHOLD, "CURR:LIM?" }, | |
1079 | { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_THRESHOLD, "CURR:LIM %.6f" }, | |
1080 | ALL_ZERO | |
1081 | }; | |
1082 | ||
c3eadb07 | 1083 | /* Philips/Fluke PM2800 series */ |
9d9cf1c4 | 1084 | static const uint32_t philips_pm2800_devopts[] = { |
e91bb0a6 | 1085 | SR_CONF_CONTINUOUS, |
88e4daa9 ML |
1086 | SR_CONF_LIMIT_SAMPLES | SR_CONF_GET | SR_CONF_SET, |
1087 | SR_CONF_LIMIT_MSEC | SR_CONF_GET | SR_CONF_SET, | |
9d9cf1c4 BV |
1088 | }; |
1089 | ||
c3eadb07 | 1090 | static const uint32_t philips_pm2800_devopts_cg[] = { |
7a0b98b5 AJ |
1091 | SR_CONF_ENABLED | SR_CONF_GET | SR_CONF_SET, |
1092 | SR_CONF_VOLTAGE | SR_CONF_GET, | |
1093 | SR_CONF_VOLTAGE_TARGET | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST, | |
1094 | SR_CONF_CURRENT | SR_CONF_GET, | |
1095 | SR_CONF_CURRENT_LIMIT | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST, | |
c3eadb07 BV |
1096 | SR_CONF_OVER_VOLTAGE_PROTECTION_ACTIVE | SR_CONF_GET, |
1097 | SR_CONF_OVER_VOLTAGE_PROTECTION_THRESHOLD | SR_CONF_GET | SR_CONF_SET, | |
1098 | SR_CONF_OVER_CURRENT_PROTECTION_ENABLED | SR_CONF_GET | SR_CONF_SET, | |
1099 | SR_CONF_OVER_CURRENT_PROTECTION_ACTIVE | SR_CONF_GET, | |
7a0b98b5 | 1100 | SR_CONF_REGULATION | SR_CONF_GET, |
c3eadb07 BV |
1101 | }; |
1102 | ||
1103 | enum philips_pm2800_modules { | |
1104 | PM2800_MOD_30V_10A = 1, | |
1105 | PM2800_MOD_60V_5A, | |
1106 | PM2800_MOD_60V_10A, | |
1107 | PM2800_MOD_8V_15A, | |
1108 | PM2800_MOD_60V_2A, | |
1109 | PM2800_MOD_120V_1A, | |
1110 | }; | |
1111 | ||
329733d9 | 1112 | static const struct philips_pm2800_module_spec { |
c3eadb07 | 1113 | /* Min, max, programming resolution. */ |
bcee1299 UH |
1114 | double voltage[5]; |
1115 | double current[5]; | |
1116 | double power[5]; | |
c3eadb07 BV |
1117 | } philips_pm2800_module_specs[] = { |
1118 | /* Autoranging modules. */ | |
6ed709fe AJ |
1119 | [PM2800_MOD_30V_10A] = { { 0, 30, 0.0075, 2, 4 }, { 0, 10, 0.0025, 2, 4 }, { 0, 60 } }, |
1120 | [PM2800_MOD_60V_5A] = { { 0, 60, 0.015, 2, 3 }, { 0, 5, 0.00125, 2, 5 }, { 0, 60 } }, | |
1121 | [PM2800_MOD_60V_10A] = { { 0, 60, 0.015, 2, 3 }, { 0, 10, 0.0025, 2, 5 }, { 0, 120 } }, | |
c3eadb07 | 1122 | /* Linear modules. */ |
6ed709fe AJ |
1123 | [PM2800_MOD_8V_15A] = { { 0, 8, 0.002, 3, 3 }, { -15, 15, 0.00375, 3, 5 }, { 0, 120 } }, |
1124 | [PM2800_MOD_60V_2A] = { { 0, 60, 0.015, 2, 3 }, { -2, 2, 0.0005, 3, 4 }, { 0, 120 } }, | |
1125 | [PM2800_MOD_120V_1A] = { { 0, 120, 0.030, 2, 2 }, { -1, 1, 0.00025, 3, 5 }, { 0, 120 } }, | |
c3eadb07 BV |
1126 | }; |
1127 | ||
329733d9 | 1128 | static const struct philips_pm2800_model { |
c3eadb07 BV |
1129 | unsigned int chassis; |
1130 | unsigned int num_modules; | |
1131 | unsigned int set; | |
1132 | unsigned int modules[3]; | |
1133 | } philips_pm2800_matrix[] = { | |
1134 | /* Autoranging chassis. */ | |
1135 | { 1, 1, 0, { PM2800_MOD_30V_10A, 0, 0 } }, | |
1136 | { 1, 1, 1, { PM2800_MOD_60V_5A, 0, 0 } }, | |
1137 | { 1, 2, 0, { PM2800_MOD_30V_10A, PM2800_MOD_30V_10A, 0 } }, | |
1138 | { 1, 2, 1, { PM2800_MOD_60V_5A, PM2800_MOD_60V_5A, 0 } }, | |
1139 | { 1, 2, 2, { PM2800_MOD_30V_10A, PM2800_MOD_60V_5A, 0 } }, | |
1140 | { 1, 2, 3, { PM2800_MOD_30V_10A, PM2800_MOD_60V_10A, 0 } }, | |
1141 | { 1, 2, 4, { PM2800_MOD_60V_5A, PM2800_MOD_60V_10A, 0 } }, | |
1142 | { 1, 3, 0, { PM2800_MOD_30V_10A, PM2800_MOD_30V_10A, PM2800_MOD_30V_10A } }, | |
1143 | { 1, 3, 1, { PM2800_MOD_60V_5A, PM2800_MOD_60V_5A, PM2800_MOD_60V_5A } }, | |
1144 | { 1, 3, 2, { PM2800_MOD_30V_10A, PM2800_MOD_30V_10A, PM2800_MOD_60V_5A } }, | |
1145 | { 1, 3, 3, { PM2800_MOD_30V_10A, PM2800_MOD_60V_5A, PM2800_MOD_60V_5A } }, | |
1146 | /* Linear chassis. */ | |
1147 | { 3, 1, 0, { PM2800_MOD_60V_2A, 0, 0 } }, | |
1148 | { 3, 1, 1, { PM2800_MOD_120V_1A, 0, 0 } }, | |
1149 | { 3, 1, 2, { PM2800_MOD_8V_15A, 0, 0 } }, | |
1150 | { 3, 2, 0, { PM2800_MOD_60V_2A, 0, 0 } }, | |
1151 | { 3, 2, 1, { PM2800_MOD_120V_1A, 0, 0 } }, | |
1152 | { 3, 2, 2, { PM2800_MOD_60V_2A, PM2800_MOD_120V_1A, 0 } }, | |
1153 | { 3, 2, 3, { PM2800_MOD_8V_15A, PM2800_MOD_8V_15A, 0 } }, | |
1154 | }; | |
1155 | ||
329733d9 | 1156 | static const char *philips_pm2800_names[] = { "1", "2", "3" }; |
c3eadb07 BV |
1157 | |
1158 | static int philips_pm2800_probe_channels(struct sr_dev_inst *sdi, | |
1159 | struct sr_scpi_hw_info *hw_info, | |
1160 | struct channel_spec **channels, unsigned int *num_channels, | |
1161 | struct channel_group_spec **channel_groups, unsigned int *num_channel_groups) | |
1162 | { | |
329733d9 UH |
1163 | const struct philips_pm2800_model *model; |
1164 | const struct philips_pm2800_module_spec *spec; | |
c3eadb07 BV |
1165 | unsigned int chassis, num_modules, set, module, m, i; |
1166 | ||
1167 | (void)sdi; | |
1168 | ||
1169 | /* | |
1170 | * The model number as reported by *IDN? looks like e.g. PM2813/11, | |
1171 | * Where "PM28" is fixed, followed by the chassis code (1 = autoranging, | |
1172 | * 3 = linear series) and the number of modules: 1-3 for autoranging, | |
1173 | * 1-2 for linear. | |
1174 | * After the slash, the first digit denotes the module set. The | |
1175 | * digit after that denotes front (5) or rear (1) binding posts. | |
1176 | */ | |
1177 | chassis = hw_info->model[4] - 0x30; | |
1178 | num_modules = hw_info->model[5] - 0x30; | |
1179 | set = hw_info->model[7] - 0x30; | |
1180 | for (m = 0; m < ARRAY_SIZE(philips_pm2800_matrix); m++) { | |
1181 | model = &philips_pm2800_matrix[m]; | |
1182 | if (model->chassis == chassis && model->num_modules == num_modules | |
1183 | && model->set == set) | |
1184 | break; | |
1185 | } | |
1186 | if (m == ARRAY_SIZE(philips_pm2800_matrix)) { | |
1187 | sr_dbg("Model %s not found in matrix.", hw_info->model); | |
1188 | return SR_ERR; | |
1189 | } | |
1190 | ||
1191 | sr_dbg("Found %d output channel%s:", num_modules, num_modules > 1 ? "s" : ""); | |
1192 | *channels = g_malloc0(sizeof(struct channel_spec) * num_modules); | |
1193 | *channel_groups = g_malloc0(sizeof(struct channel_group_spec) * num_modules); | |
1194 | for (i = 0; i < num_modules; i++) { | |
1195 | module = model->modules[i]; | |
1196 | spec = &philips_pm2800_module_specs[module]; | |
6ed709fe | 1197 | sr_dbg("output %d: %.0f - %.0fV, %.0f - %.0fA, %.0f - %.0fW", i + 1, |
c3eadb07 | 1198 | spec->voltage[0], spec->voltage[1], |
6ed709fe | 1199 | spec->current[0], spec->current[1], |
d9251a2c | 1200 | spec->power[0], spec->power[1]); |
329733d9 | 1201 | (*channels)[i].name = (char *)philips_pm2800_names[i]; |
bcee1299 | 1202 | memcpy(&((*channels)[i].voltage), spec, sizeof(double) * 15); |
329733d9 | 1203 | (*channel_groups)[i].name = (char *)philips_pm2800_names[i]; |
c3eadb07 BV |
1204 | (*channel_groups)[i].channel_index_mask = 1 << i; |
1205 | (*channel_groups)[i].features = PPS_OTP | PPS_OVP | PPS_OCP; | |
f2bbcc33 | 1206 | (*channel_groups)[i].mqflags = SR_MQFLAG_DC; |
c3eadb07 BV |
1207 | } |
1208 | *num_channels = *num_channel_groups = num_modules; | |
1209 | ||
1210 | return SR_OK; | |
1211 | } | |
1212 | ||
8cb5affe | 1213 | static const struct scpi_command philips_pm2800_cmd[] = { |
c3eadb07 BV |
1214 | { SCPI_CMD_SELECT_CHANNEL, ":INST:NSEL %s" }, |
1215 | { SCPI_CMD_GET_MEAS_VOLTAGE, ":MEAS:VOLT?" }, | |
1216 | { SCPI_CMD_GET_MEAS_CURRENT, ":MEAS:CURR?" }, | |
1217 | { SCPI_CMD_GET_VOLTAGE_TARGET, ":SOUR:VOLT?" }, | |
1218 | { SCPI_CMD_SET_VOLTAGE_TARGET, ":SOUR:VOLT %.6f" }, | |
1219 | { SCPI_CMD_GET_CURRENT_LIMIT, ":SOUR:CURR?" }, | |
1220 | { SCPI_CMD_SET_CURRENT_LIMIT, ":SOUR:CURR %.6f" }, | |
1221 | { SCPI_CMD_GET_OUTPUT_ENABLED, ":OUTP?" }, | |
1222 | { SCPI_CMD_SET_OUTPUT_ENABLE, ":OUTP ON" }, | |
1223 | { SCPI_CMD_SET_OUTPUT_DISABLE, ":OUTP OFF" }, | |
1224 | { SCPI_CMD_GET_OUTPUT_REGULATION, ":SOUR:FUNC:MODE?" }, | |
1225 | { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_ACTIVE, ":SOUR:VOLT:PROT:TRIP?" }, | |
1226 | { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_THRESHOLD, ":SOUR:VOLT:PROT:LEV?" }, | |
1227 | { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_THRESHOLD, ":SOUR:VOLT:PROT:LEV %.6f" }, | |
1228 | { SCPI_CMD_GET_OVER_CURRENT_PROTECTION_ENABLED, ":SOUR:CURR:PROT:STAT?" }, | |
1229 | { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_ENABLE, ":SOUR:CURR:PROT:STAT ON" }, | |
1230 | { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_DISABLE, ":SOUR:CURR:PROT:STAT OFF" }, | |
1231 | { SCPI_CMD_GET_OVER_CURRENT_PROTECTION_ACTIVE, ":SOUR:CURR:PROT:TRIP?" }, | |
91ef511d | 1232 | ALL_ZERO |
c3eadb07 BV |
1233 | }; |
1234 | ||
81eb36d6 MS |
1235 | static const uint32_t rs_hmc8043_devopts[] = { |
1236 | SR_CONF_CONTINUOUS, | |
88e4daa9 ML |
1237 | SR_CONF_LIMIT_SAMPLES | SR_CONF_GET | SR_CONF_SET, |
1238 | SR_CONF_LIMIT_MSEC | SR_CONF_GET | SR_CONF_SET, | |
81eb36d6 MS |
1239 | }; |
1240 | ||
1241 | static const uint32_t rs_hmc8043_devopts_cg[] = { | |
1242 | SR_CONF_OVER_VOLTAGE_PROTECTION_ENABLED | SR_CONF_GET | SR_CONF_SET, | |
1243 | SR_CONF_OVER_VOLTAGE_PROTECTION_ACTIVE | SR_CONF_GET, | |
1244 | SR_CONF_OVER_VOLTAGE_PROTECTION_THRESHOLD | SR_CONF_GET | SR_CONF_SET, | |
1245 | SR_CONF_VOLTAGE | SR_CONF_GET, | |
1246 | SR_CONF_VOLTAGE_TARGET | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST, | |
1247 | SR_CONF_CURRENT | SR_CONF_GET, | |
1248 | SR_CONF_CURRENT_LIMIT | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST, | |
1249 | SR_CONF_ENABLED | SR_CONF_GET | SR_CONF_SET, | |
1250 | }; | |
1251 | ||
1252 | static const struct channel_spec rs_hmc8043_ch[] = { | |
49a468ed FS |
1253 | { "1", { 0, 32.050, 0.001, 3, 4 }, { 0.001, 3, 0.001, 3, 4 }, { 0, 0, 0, 0, 4 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS }, |
1254 | { "2", { 0, 32.050, 0.001, 3, 4 }, { 0.001, 3, 0.001, 3, 4 }, { 0, 0, 0, 0, 4 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS }, | |
1255 | { "3", { 0, 32.050, 0.001, 3, 4 }, { 0.001, 3, 0.001, 3, 4 }, { 0, 0, 0, 0, 4 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS }, | |
81eb36d6 MS |
1256 | }; |
1257 | ||
1258 | static const struct channel_group_spec rs_hmc8043_cg[] = { | |
f2bbcc33 FS |
1259 | { "1", CH_IDX(0), PPS_OVP, SR_MQFLAG_DC }, |
1260 | { "2", CH_IDX(1), PPS_OVP, SR_MQFLAG_DC }, | |
1261 | { "3", CH_IDX(2), PPS_OVP, SR_MQFLAG_DC }, | |
81eb36d6 MS |
1262 | }; |
1263 | ||
1264 | static const struct scpi_command rs_hmc8043_cmd[] = { | |
1265 | { SCPI_CMD_SELECT_CHANNEL, "INST:NSEL %s" }, | |
1266 | { SCPI_CMD_GET_MEAS_VOLTAGE, "MEAS:VOLT?" }, | |
1267 | { SCPI_CMD_GET_MEAS_CURRENT, "MEAS:CURR?" }, | |
1268 | { SCPI_CMD_GET_VOLTAGE_TARGET, "VOLT?" }, | |
1269 | { SCPI_CMD_SET_VOLTAGE_TARGET, "VOLT %.6f" }, | |
1270 | { SCPI_CMD_GET_CURRENT_LIMIT, "CURR?" }, | |
1271 | { SCPI_CMD_SET_CURRENT_LIMIT, "CURR %.6f" }, | |
1272 | { SCPI_CMD_GET_OUTPUT_ENABLED, "OUTP?" }, | |
1273 | { SCPI_CMD_SET_OUTPUT_ENABLE, "OUTP ON" }, | |
1274 | { SCPI_CMD_SET_OUTPUT_DISABLE, "OUTP OFF" }, | |
1275 | { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_ACTIVE, "VOLT:PROT:TRIP?" }, | |
1276 | { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_THRESHOLD, "VOLT:PROT:LEV?" }, | |
1277 | { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_THRESHOLD, "VOLT:PROT:LEV %.6f" }, | |
1278 | { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_ENABLED, "VOLT:PROT:STAT?" }, | |
1279 | { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_ENABLE, "VOLT:PROT:STAT ON" }, | |
1280 | { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_DISABLE, "VOLT:PROT:STAT OFF" }, | |
1281 | ALL_ZERO | |
1282 | }; | |
1283 | ||
bd5f0a14 FS |
1284 | static const uint32_t rs_hmp4040_devopts[] = { |
1285 | SR_CONF_CONTINUOUS, | |
1286 | SR_CONF_LIMIT_SAMPLES | SR_CONF_GET | SR_CONF_SET, | |
1287 | SR_CONF_LIMIT_MSEC | SR_CONF_GET | SR_CONF_SET, | |
1288 | }; | |
1289 | ||
1290 | static const uint32_t rs_hmp4040_devopts_cg[] = { | |
1291 | SR_CONF_OVER_VOLTAGE_PROTECTION_ENABLED | SR_CONF_GET, | |
1292 | SR_CONF_OVER_VOLTAGE_PROTECTION_ACTIVE | SR_CONF_GET, | |
1293 | SR_CONF_OVER_VOLTAGE_PROTECTION_THRESHOLD | SR_CONF_GET | SR_CONF_SET, | |
1294 | SR_CONF_VOLTAGE | SR_CONF_GET, | |
1295 | SR_CONF_VOLTAGE_TARGET | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST, | |
1296 | SR_CONF_CURRENT | SR_CONF_GET, | |
1297 | SR_CONF_CURRENT_LIMIT | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST, | |
1298 | SR_CONF_ENABLED | SR_CONF_GET | SR_CONF_SET, | |
1299 | SR_CONF_OVER_TEMPERATURE_PROTECTION_ACTIVE | SR_CONF_GET, | |
1300 | SR_CONF_REGULATION | SR_CONF_GET, | |
1301 | }; | |
1302 | ||
1c5d5905 GS |
1303 | static const struct channel_spec rs_hmp2020_ch[] = { |
1304 | { "1", { 0, 32.050, 0.001, 3, 4 }, { 0.001, 10.01, 0.0002, 3, 4 }, { 0, 0, 0, 0, 4 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS }, | |
1305 | { "2", { 0, 32.050, 0.001, 3, 4 }, { 0.001, 5.01, 0.0001, 3, 4 }, { 0, 0, 0, 0, 4 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS }, | |
1306 | }; | |
1307 | ||
1308 | static const struct channel_spec rs_hmp2030_ch[] = { | |
1309 | { "1", { 0, 32.050, 0.001, 3, 4 }, { 0.001, 5.01, 0.0001, 3, 4 }, { 0, 0, 0, 0, 4 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS }, | |
1310 | { "2", { 0, 32.050, 0.001, 3, 4 }, { 0.001, 5.01, 0.0001, 3, 4 }, { 0, 0, 0, 0, 4 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS }, | |
1311 | { "3", { 0, 32.050, 0.001, 3, 4 }, { 0.001, 5.01, 0.0001, 3, 4 }, { 0, 0, 0, 0, 4 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS }, | |
1312 | }; | |
1313 | ||
bd5f0a14 | 1314 | static const struct channel_spec rs_hmp4040_ch[] = { |
7320ce5e GS |
1315 | { "1", { 0, 32.050, 0.001, 3, 4 }, { 0.001, 10.01, 0.0002, 3, 4 }, { 0, 0, 0, 0, 4 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS }, |
1316 | { "2", { 0, 32.050, 0.001, 3, 4 }, { 0.001, 10.01, 0.0002, 3, 4 }, { 0, 0, 0, 0, 4 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS }, | |
1317 | { "3", { 0, 32.050, 0.001, 3, 4 }, { 0.001, 10.01, 0.0002, 3, 4 }, { 0, 0, 0, 0, 4 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS }, | |
1318 | { "4", { 0, 32.050, 0.001, 3, 4 }, { 0.001, 10.01, 0.0002, 3, 4 }, { 0, 0, 0, 0, 4 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS }, | |
bd5f0a14 FS |
1319 | }; |
1320 | ||
1321 | static const struct channel_group_spec rs_hmp4040_cg[] = { | |
1322 | { "1", CH_IDX(0), PPS_OVP | PPS_OTP, SR_MQFLAG_DC }, | |
1323 | { "2", CH_IDX(1), PPS_OVP | PPS_OTP, SR_MQFLAG_DC }, | |
1324 | { "3", CH_IDX(2), PPS_OVP | PPS_OTP, SR_MQFLAG_DC }, | |
1325 | { "4", CH_IDX(3), PPS_OVP | PPS_OTP, SR_MQFLAG_DC }, | |
1326 | }; | |
1327 | ||
1328 | /* | |
1329 | * Developer's note: Currently unused device commands. Some of them | |
1330 | * are not in use because SCPI_CMD codes are not defined yet. | |
1331 | * OUTP:GEN | |
1332 | * VOLT? MAX, CURR? MAX | |
1333 | * VOLT:PROT:CLE (could set SR_CONF_OVER_VOLTAGE_PROTECTION_ACTIVE) | |
1334 | * VOLT:PROT:MODE | |
1335 | * FUSE:STAT, FUSE:TRIP?, FUSE:LINK, FUSE:UNL | |
1336 | * ARB:... | |
1337 | * SYST:LOC, SYST:REM, SYST:RWL, SYST:MIX | |
1338 | * SYST:BEEP:IMM | |
1339 | */ | |
1340 | static const struct scpi_command rs_hmp4040_cmd[] = { | |
f403cb9d GS |
1341 | { SCPI_CMD_REMOTE, "SYST:REM" }, |
1342 | { SCPI_CMD_LOCAL, "SYST:LOC" }, | |
bd5f0a14 FS |
1343 | { SCPI_CMD_SELECT_CHANNEL, "INST:NSEL %s" }, |
1344 | { SCPI_CMD_GET_MEAS_VOLTAGE, "MEAS:VOLT?" }, | |
1345 | { SCPI_CMD_GET_MEAS_CURRENT, "MEAS:CURR?" }, | |
1346 | { SCPI_CMD_GET_VOLTAGE_TARGET, "VOLT?" }, | |
1347 | { SCPI_CMD_SET_VOLTAGE_TARGET, "VOLT %.6f" }, | |
1348 | { SCPI_CMD_GET_CURRENT_LIMIT, "CURR?" }, | |
1349 | { SCPI_CMD_SET_CURRENT_LIMIT, "CURR %.6f" }, | |
1350 | { SCPI_CMD_GET_OUTPUT_ENABLED, "OUTP?" }, | |
1351 | { SCPI_CMD_SET_OUTPUT_ENABLE, "OUTP ON" }, | |
1352 | { SCPI_CMD_SET_OUTPUT_DISABLE, "OUTP OFF" }, | |
1353 | { SCPI_CMD_GET_OUTPUT_REGULATION, "STAT:QUES:INST:ISUM%s:COND?" }, | |
1354 | { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_ACTIVE, "VOLT:PROT:TRIP?" }, | |
1355 | { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_THRESHOLD, "VOLT:PROT:LEV?" }, | |
1356 | { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_THRESHOLD, "VOLT:PROT:LEV %.6f" }, | |
1357 | { SCPI_CMD_GET_OVER_TEMPERATURE_PROTECTION_ACTIVE, "STAT:QUES:INST:ISUM%s:COND?" }, | |
1358 | ALL_ZERO | |
1359 | }; | |
1360 | ||
d4eabea8 | 1361 | SR_PRIV const struct scpi_pps pps_profiles[] = { |
6cc93128 | 1362 | /* Agilent N5763A */ |
5e7377f4 | 1363 | { "Agilent", "N5763A", SCPI_DIALECT_UNKNOWN, 0, |
6cc93128 AG |
1364 | ARRAY_AND_SIZE(agilent_n5700a_devopts), |
1365 | ARRAY_AND_SIZE(agilent_n5700a_devopts_cg), | |
1366 | ARRAY_AND_SIZE(agilent_n5763a_ch), | |
1367 | ARRAY_AND_SIZE(agilent_n5700a_cg), | |
1368 | agilent_n5700a_cmd, | |
1369 | .probe_channels = NULL, | |
fd243315 | 1370 | .init_acquisition = NULL, |
7e66bf05 | 1371 | .update_status = NULL, |
6cc93128 | 1372 | }, |
ca314e06 | 1373 | |
5c9e56c9 | 1374 | /* Agilent N5767A */ |
5e7377f4 | 1375 | { "Agilent", "N5767A", SCPI_DIALECT_UNKNOWN, 0, |
5c9e56c9 AG |
1376 | ARRAY_AND_SIZE(agilent_n5700a_devopts), |
1377 | ARRAY_AND_SIZE(agilent_n5700a_devopts_cg), | |
1378 | ARRAY_AND_SIZE(agilent_n5767a_ch), | |
6cc93128 | 1379 | ARRAY_AND_SIZE(agilent_n5700a_cg), |
91ef511d | 1380 | agilent_n5700a_cmd, |
5c9e56c9 | 1381 | .probe_channels = NULL, |
fd243315 | 1382 | .init_acquisition = NULL, |
7e66bf05 | 1383 | .update_status = NULL, |
5c9e56c9 | 1384 | }, |
ca314e06 | 1385 | |
c3bfb959 | 1386 | /* BK Precision 9310 */ |
5e7377f4 | 1387 | { "BK", "^9130$", SCPI_DIALECT_UNKNOWN, 0, |
c3bfb959 MW |
1388 | ARRAY_AND_SIZE(bk_9130_devopts), |
1389 | ARRAY_AND_SIZE(bk_9130_devopts_cg), | |
1390 | ARRAY_AND_SIZE(bk_9130_ch), | |
1391 | ARRAY_AND_SIZE(bk_9130_cg), | |
1392 | bk_9130_cmd, | |
1393 | .probe_channels = NULL, | |
fd243315 | 1394 | .init_acquisition = NULL, |
7e66bf05 | 1395 | .update_status = NULL, |
c3bfb959 MW |
1396 | }, |
1397 | ||
4ee1e2f3 | 1398 | /* Chroma 61604 */ |
5e7377f4 | 1399 | { "Chroma", "61604", SCPI_DIALECT_UNKNOWN, 0, |
4ee1e2f3 AG |
1400 | ARRAY_AND_SIZE(chroma_61604_devopts), |
1401 | ARRAY_AND_SIZE(chroma_61604_devopts_cg), | |
1402 | ARRAY_AND_SIZE(chroma_61604_ch), | |
1403 | ARRAY_AND_SIZE(chroma_61604_cg), | |
91ef511d | 1404 | chroma_61604_cmd, |
4ee1e2f3 | 1405 | .probe_channels = NULL, |
fd243315 | 1406 | .init_acquisition = NULL, |
7e66bf05 | 1407 | .update_status = NULL, |
4ee1e2f3 | 1408 | }, |
ca314e06 | 1409 | |
5281993e | 1410 | /* Chroma 62000 series */ |
5e7377f4 | 1411 | { "Chroma", "620[0-9]{2}P-[0-9]{2,3}-[0-9]{1,3}", SCPI_DIALECT_UNKNOWN, 0, |
5281993e AG |
1412 | ARRAY_AND_SIZE(chroma_62000_devopts), |
1413 | ARRAY_AND_SIZE(chroma_62000_devopts_cg), | |
9a5185c7 AG |
1414 | NULL, 0, |
1415 | NULL, 0, | |
91ef511d | 1416 | chroma_62000_cmd, |
9a5185c7 | 1417 | .probe_channels = chroma_62000p_probe_channels, |
22fdb67f MA |
1418 | .init_acquisition = NULL, |
1419 | .update_status = NULL, | |
1420 | }, | |
1421 | ||
1422 | /* | |
1423 | * Envox EEZ PSU Series | |
1424 | * The documented identification strings disagree with the behavior | |
1425 | * of at least some real units (returning "EEZ"). The first of these | |
1426 | * is the documented one, while the second seems to be returned by | |
1427 | * firmware v1.02 and earlier. | |
1428 | */ | |
1429 | { "Envox", "^EEZ H24005 ", SCPI_DIALECT_UNKNOWN, 0, | |
1430 | ARRAY_AND_SIZE(eez_psu_devopts), | |
1431 | ARRAY_AND_SIZE(eez_psu_devopts_cg), | |
1432 | NULL, 0, | |
1433 | NULL, 0, | |
1434 | eez_psu_cmd, | |
1435 | .probe_channels = eez_psu_probe_channels, | |
1436 | .init_acquisition = NULL, | |
1437 | .update_status = NULL, | |
1438 | }, | |
1439 | { "EEZ", "^PSU ", SCPI_DIALECT_UNKNOWN, 0, | |
1440 | ARRAY_AND_SIZE(eez_psu_devopts), | |
1441 | ARRAY_AND_SIZE(eez_psu_devopts_cg), | |
1442 | NULL, 0, | |
1443 | NULL, 0, | |
1444 | eez_psu_cmd, | |
1445 | .probe_channels = eez_psu_probe_channels, | |
1446 | .init_acquisition = NULL, | |
1447 | .update_status = NULL, | |
1448 | }, | |
1449 | ||
1450 | /* Envox EEZ BB3 Series */ | |
1451 | { "Envox", "^BB3 ", SCPI_DIALECT_UNKNOWN, 0, | |
1452 | ARRAY_AND_SIZE(eez_psu_devopts), | |
1453 | ARRAY_AND_SIZE(eez_psu_devopts_cg), | |
1454 | NULL, 0, | |
1455 | NULL, 0, | |
1456 | eez_psu_cmd, | |
1457 | .probe_channels = eez_psu_probe_channels, | |
fd243315 | 1458 | .init_acquisition = NULL, |
7e66bf05 | 1459 | .update_status = NULL, |
5281993e | 1460 | }, |
ca314e06 | 1461 | |
5ce427c7 FS |
1462 | /* |
1463 | * This entry is for testing the HP COMP language with a HP 6632B power | |
1464 | * supply switched to the COMP language ("SYST:LANG COMP"). When used, | |
1465 | * disable the entry for the HP 6632B below! | |
1466 | */ | |
1467 | /* | |
1468 | { "HP", "6632B", SCPI_DIALECT_HP_COMP, 0, | |
1469 | ARRAY_AND_SIZE(hp_6630a_devopts), | |
1470 | ARRAY_AND_SIZE(hp_6630a_devopts_cg), | |
1471 | ARRAY_AND_SIZE(hp_6632a_ch), | |
1472 | ARRAY_AND_SIZE(hp_6630a_cg), | |
1473 | hp_6630a_cmd, | |
1474 | .probe_channels = NULL, | |
fd243315 | 1475 | hp_6630a_init_acquisition, |
5ce427c7 FS |
1476 | hp_6630a_update_status, |
1477 | }, | |
1478 | */ | |
1479 | ||
1480 | /* HP 6632A */ | |
1481 | { "HP", "6632A", SCPI_DIALECT_HP_COMP, 0, | |
1482 | ARRAY_AND_SIZE(hp_6630a_devopts), | |
1483 | ARRAY_AND_SIZE(hp_6630a_devopts_cg), | |
1484 | ARRAY_AND_SIZE(hp_6632a_ch), | |
1485 | ARRAY_AND_SIZE(hp_6630a_cg), | |
1486 | hp_6630a_cmd, | |
1487 | .probe_channels = NULL, | |
fd243315 | 1488 | hp_6630a_init_acquisition, |
5ce427c7 FS |
1489 | hp_6630a_update_status, |
1490 | }, | |
1491 | ||
e76a3575 | 1492 | /* HP 6633A */ |
5e7377f4 | 1493 | { "HP", "6633A", SCPI_DIALECT_HP_COMP, 0, |
e76a3575 | 1494 | ARRAY_AND_SIZE(hp_6630a_devopts), |
7c517d02 | 1495 | ARRAY_AND_SIZE(hp_6630a_devopts_cg), |
e76a3575 | 1496 | ARRAY_AND_SIZE(hp_6633a_ch), |
dbc519f7 | 1497 | ARRAY_AND_SIZE(hp_6630a_cg), |
e76a3575 AG |
1498 | hp_6630a_cmd, |
1499 | .probe_channels = NULL, | |
fd243315 | 1500 | hp_6630a_init_acquisition, |
fdf03652 | 1501 | hp_6630a_update_status, |
e76a3575 AG |
1502 | }, |
1503 | ||
5ce427c7 FS |
1504 | /* HP 6634A */ |
1505 | { "HP", "6634A", SCPI_DIALECT_HP_COMP, 0, | |
1506 | ARRAY_AND_SIZE(hp_6630a_devopts), | |
1507 | ARRAY_AND_SIZE(hp_6630a_devopts_cg), | |
1508 | ARRAY_AND_SIZE(hp_6634a_ch), | |
1509 | ARRAY_AND_SIZE(hp_6630a_cg), | |
1510 | hp_6630a_cmd, | |
1511 | .probe_channels = NULL, | |
fd243315 | 1512 | hp_6630a_init_acquisition, |
5ce427c7 FS |
1513 | hp_6630a_update_status, |
1514 | }, | |
1515 | ||
1516 | /* HP 6611C */ | |
1517 | { "HP", "6611C", SCPI_DIALECT_HP_66XXB, PPS_OTP, | |
1518 | ARRAY_AND_SIZE(hp_6630b_devopts), | |
1519 | ARRAY_AND_SIZE(hp_6630b_devopts_cg), | |
1520 | ARRAY_AND_SIZE(hp_6611c_ch), | |
1521 | ARRAY_AND_SIZE(hp_6630b_cg), | |
1522 | hp_6630b_cmd, | |
1523 | .probe_channels = NULL, | |
fd243315 | 1524 | hp_6630b_init_acquisition, |
5ce427c7 FS |
1525 | hp_6630b_update_status, |
1526 | }, | |
1527 | ||
1528 | /* HP 6612C */ | |
1529 | { "HP", "6612C", SCPI_DIALECT_HP_66XXB, PPS_OTP, | |
1530 | ARRAY_AND_SIZE(hp_6630b_devopts), | |
1531 | ARRAY_AND_SIZE(hp_6630b_devopts_cg), | |
1532 | ARRAY_AND_SIZE(hp_6612c_ch), | |
1533 | ARRAY_AND_SIZE(hp_6630b_cg), | |
1534 | hp_6630b_cmd, | |
1535 | .probe_channels = NULL, | |
fd243315 | 1536 | hp_6630b_init_acquisition, |
5ce427c7 FS |
1537 | hp_6630b_update_status, |
1538 | }, | |
1539 | ||
1540 | /* HP 6613C */ | |
1541 | { "HP", "6613C", SCPI_DIALECT_HP_66XXB, PPS_OTP, | |
1542 | ARRAY_AND_SIZE(hp_6630b_devopts), | |
1543 | ARRAY_AND_SIZE(hp_6630b_devopts_cg), | |
1544 | ARRAY_AND_SIZE(hp_6613c_ch), | |
1545 | ARRAY_AND_SIZE(hp_6630b_cg), | |
1546 | hp_6630b_cmd, | |
1547 | .probe_channels = NULL, | |
fd243315 | 1548 | hp_6630b_init_acquisition, |
5ce427c7 FS |
1549 | hp_6630b_update_status, |
1550 | }, | |
1551 | ||
1552 | /* HP 6614C */ | |
1553 | { "HP", "6614C", SCPI_DIALECT_HP_66XXB, PPS_OTP, | |
1554 | ARRAY_AND_SIZE(hp_6630b_devopts), | |
1555 | ARRAY_AND_SIZE(hp_6630b_devopts_cg), | |
1556 | ARRAY_AND_SIZE(hp_6614c_ch), | |
1557 | ARRAY_AND_SIZE(hp_6630b_cg), | |
1558 | hp_6630b_cmd, | |
1559 | .probe_channels = NULL, | |
fd243315 | 1560 | hp_6630b_init_acquisition, |
5ce427c7 FS |
1561 | hp_6630b_update_status, |
1562 | }, | |
1563 | ||
a61c8cce | 1564 | /* HP 6631B */ |
3d1aa50f | 1565 | { "HP", "6631B", SCPI_DIALECT_HP_66XXB, PPS_OTP, |
a61c8cce FS |
1566 | ARRAY_AND_SIZE(hp_6630b_devopts), |
1567 | ARRAY_AND_SIZE(hp_6630b_devopts_cg), | |
1568 | ARRAY_AND_SIZE(hp_6631b_ch), | |
dbc519f7 | 1569 | ARRAY_AND_SIZE(hp_6630b_cg), |
a61c8cce FS |
1570 | hp_6630b_cmd, |
1571 | .probe_channels = NULL, | |
fd243315 | 1572 | hp_6630b_init_acquisition, |
fe4bb774 | 1573 | hp_6630b_update_status, |
a61c8cce FS |
1574 | }, |
1575 | ||
bc4a2a46 | 1576 | /* HP 6632B */ |
3d1aa50f | 1577 | { "HP", "6632B", SCPI_DIALECT_HP_66XXB, PPS_OTP, |
a61c8cce FS |
1578 | ARRAY_AND_SIZE(hp_6630b_devopts), |
1579 | ARRAY_AND_SIZE(hp_6630b_devopts_cg), | |
bc4a2a46 | 1580 | ARRAY_AND_SIZE(hp_6632b_ch), |
dbc519f7 | 1581 | ARRAY_AND_SIZE(hp_6630b_cg), |
a61c8cce FS |
1582 | hp_6630b_cmd, |
1583 | .probe_channels = NULL, | |
fd243315 | 1584 | hp_6630b_init_acquisition, |
fe4bb774 | 1585 | hp_6630b_update_status, |
a61c8cce FS |
1586 | }, |
1587 | ||
0b0f40d8 MW |
1588 | /* HP 66312A */ |
1589 | { "HP", "66312A", SCPI_DIALECT_HP_66XXB, PPS_OTP, | |
1590 | ARRAY_AND_SIZE(hp_6630b_devopts), | |
1591 | ARRAY_AND_SIZE(hp_6630b_devopts_cg), | |
1592 | ARRAY_AND_SIZE(hp_66312a_ch), | |
1593 | ARRAY_AND_SIZE(hp_6630b_cg), | |
1594 | hp_6630b_cmd, | |
1595 | .probe_channels = NULL, | |
1596 | hp_6630b_init_acquisition, | |
1597 | hp_6630b_update_status, | |
1598 | }, | |
1599 | ||
a61c8cce | 1600 | /* HP 66332A */ |
3d1aa50f | 1601 | { "HP", "66332A", SCPI_DIALECT_HP_66XXB, PPS_OTP, |
a61c8cce FS |
1602 | ARRAY_AND_SIZE(hp_6630b_devopts), |
1603 | ARRAY_AND_SIZE(hp_6630b_devopts_cg), | |
1604 | ARRAY_AND_SIZE(hp_66332a_ch), | |
dbc519f7 | 1605 | ARRAY_AND_SIZE(hp_6630b_cg), |
a61c8cce FS |
1606 | hp_6630b_cmd, |
1607 | .probe_channels = NULL, | |
fd243315 | 1608 | hp_6630b_init_acquisition, |
fe4bb774 | 1609 | hp_6630b_update_status, |
a61c8cce FS |
1610 | }, |
1611 | ||
1612 | /* HP 6633B */ | |
3d1aa50f | 1613 | { "HP", "6633B", SCPI_DIALECT_HP_66XXB, PPS_OTP, |
a61c8cce FS |
1614 | ARRAY_AND_SIZE(hp_6630b_devopts), |
1615 | ARRAY_AND_SIZE(hp_6630b_devopts_cg), | |
1616 | ARRAY_AND_SIZE(hp_6633b_ch), | |
dbc519f7 | 1617 | ARRAY_AND_SIZE(hp_6630b_cg), |
a61c8cce FS |
1618 | hp_6630b_cmd, |
1619 | .probe_channels = NULL, | |
fd243315 | 1620 | hp_6630b_init_acquisition, |
fe4bb774 | 1621 | hp_6630b_update_status, |
a61c8cce FS |
1622 | }, |
1623 | ||
1624 | /* HP 6634B */ | |
3d1aa50f | 1625 | { "HP", "6634B", SCPI_DIALECT_HP_66XXB, PPS_OTP, |
a61c8cce FS |
1626 | ARRAY_AND_SIZE(hp_6630b_devopts), |
1627 | ARRAY_AND_SIZE(hp_6630b_devopts_cg), | |
1628 | ARRAY_AND_SIZE(hp_6634b_ch), | |
dbc519f7 | 1629 | ARRAY_AND_SIZE(hp_6630b_cg), |
a61c8cce | 1630 | hp_6630b_cmd, |
c3eadb07 | 1631 | .probe_channels = NULL, |
fd243315 | 1632 | hp_6630b_init_acquisition, |
fe4bb774 | 1633 | hp_6630b_update_status, |
bc4a2a46 BV |
1634 | }, |
1635 | ||
319fe9ce | 1636 | /* Rigol DP700 series */ |
5e7377f4 | 1637 | { "Rigol", "^DP711$", SCPI_DIALECT_UNKNOWN, 0, |
319fe9ce UH |
1638 | ARRAY_AND_SIZE(rigol_dp700_devopts), |
1639 | ARRAY_AND_SIZE(rigol_dp700_devopts_cg), | |
1640 | ARRAY_AND_SIZE(rigol_dp711_ch), | |
1641 | ARRAY_AND_SIZE(rigol_dp700_cg), | |
1642 | rigol_dp700_cmd, | |
1643 | .probe_channels = NULL, | |
fd243315 | 1644 | .init_acquisition = NULL, |
7e66bf05 | 1645 | .update_status = NULL, |
319fe9ce | 1646 | }, |
5e7377f4 | 1647 | { "Rigol", "^DP712$", SCPI_DIALECT_UNKNOWN, 0, |
319fe9ce UH |
1648 | ARRAY_AND_SIZE(rigol_dp700_devopts), |
1649 | ARRAY_AND_SIZE(rigol_dp700_devopts_cg), | |
1650 | ARRAY_AND_SIZE(rigol_dp712_ch), | |
1651 | ARRAY_AND_SIZE(rigol_dp700_cg), | |
1652 | rigol_dp700_cmd, | |
1653 | .probe_channels = NULL, | |
fd243315 | 1654 | .init_acquisition = NULL, |
7e66bf05 | 1655 | .update_status = NULL, |
319fe9ce UH |
1656 | }, |
1657 | ||
d4eabea8 | 1658 | /* Rigol DP800 series */ |
5e7377f4 | 1659 | { "Rigol", "^DP821A$", SCPI_DIALECT_UNKNOWN, PPS_OTP, |
cfcdf576 ML |
1660 | ARRAY_AND_SIZE(rigol_dp800_devopts), |
1661 | ARRAY_AND_SIZE(rigol_dp800_devopts_cg), | |
1662 | ARRAY_AND_SIZE(rigol_dp821a_ch), | |
1663 | ARRAY_AND_SIZE(rigol_dp820_cg), | |
91ef511d | 1664 | rigol_dp800_cmd, |
cfcdf576 | 1665 | .probe_channels = NULL, |
fd243315 | 1666 | .init_acquisition = NULL, |
7e66bf05 | 1667 | .update_status = NULL, |
cfcdf576 | 1668 | }, |
5e7377f4 | 1669 | { "Rigol", "^DP831A$", SCPI_DIALECT_UNKNOWN, PPS_OTP, |
3222ee10 BV |
1670 | ARRAY_AND_SIZE(rigol_dp800_devopts), |
1671 | ARRAY_AND_SIZE(rigol_dp800_devopts_cg), | |
1672 | ARRAY_AND_SIZE(rigol_dp831_ch), | |
cfcdf576 | 1673 | ARRAY_AND_SIZE(rigol_dp830_cg), |
91ef511d | 1674 | rigol_dp800_cmd, |
c3eadb07 | 1675 | .probe_channels = NULL, |
fd243315 | 1676 | .init_acquisition = NULL, |
7e66bf05 | 1677 | .update_status = NULL, |
3222ee10 | 1678 | }, |
5e7377f4 | 1679 | { "Rigol", "^(DP832|DP832A)$", SCPI_DIALECT_UNKNOWN, PPS_OTP, |
3222ee10 BV |
1680 | ARRAY_AND_SIZE(rigol_dp800_devopts), |
1681 | ARRAY_AND_SIZE(rigol_dp800_devopts_cg), | |
1682 | ARRAY_AND_SIZE(rigol_dp832_ch), | |
cfcdf576 | 1683 | ARRAY_AND_SIZE(rigol_dp830_cg), |
91ef511d | 1684 | rigol_dp800_cmd, |
c3eadb07 | 1685 | .probe_channels = NULL, |
fd243315 | 1686 | .init_acquisition = NULL, |
7e66bf05 | 1687 | .update_status = NULL, |
c3eadb07 BV |
1688 | }, |
1689 | ||
5433907e PA |
1690 | /* Owon P4000 series */ |
1691 | { "OWON", "^P4305$", SCPI_DIALECT_UNKNOWN, 0, | |
1692 | ARRAY_AND_SIZE(owon_p4000_devopts), | |
1693 | ARRAY_AND_SIZE(owon_p4000_devopts_cg), | |
1694 | ARRAY_AND_SIZE(owon_p4305_ch), | |
1695 | ARRAY_AND_SIZE(owon_p4000_cg), | |
1696 | owon_p4000_cmd, | |
1697 | .probe_channels = NULL, | |
1698 | .init_acquisition = NULL, | |
1699 | .update_status = NULL, | |
1700 | }, | |
1701 | { "OWON", "^P4603$", SCPI_DIALECT_UNKNOWN, 0, | |
1702 | ARRAY_AND_SIZE(owon_p4000_devopts), | |
1703 | ARRAY_AND_SIZE(owon_p4000_devopts_cg), | |
1704 | ARRAY_AND_SIZE(owon_p4603_ch), | |
1705 | ARRAY_AND_SIZE(owon_p4000_cg), | |
1706 | owon_p4000_cmd, | |
1707 | .probe_channels = NULL, | |
1708 | .init_acquisition = NULL, | |
1709 | .update_status = NULL, | |
1710 | }, | |
1711 | ||
20a28434 SS |
1712 | { "OWON", "^SPE6103$", SCPI_DIALECT_UNKNOWN, 0, |
1713 | ARRAY_AND_SIZE(owon_p4000_devopts), | |
1714 | ARRAY_AND_SIZE(owon_p4000_devopts_cg), | |
1715 | ARRAY_AND_SIZE(owon_spe6103_ch), | |
1716 | ARRAY_AND_SIZE(owon_p4000_cg), | |
1717 | owon_spe6103_cmd, | |
1718 | .probe_channels = NULL, | |
1719 | .init_acquisition = NULL, | |
1720 | .update_status = NULL, | |
1721 | }, | |
1722 | ||
c3eadb07 | 1723 | /* Philips/Fluke PM2800 series */ |
5e7377f4 | 1724 | { "Philips", "^PM28[13][123]/[01234]{1,2}$", SCPI_DIALECT_PHILIPS, 0, |
9d9cf1c4 | 1725 | ARRAY_AND_SIZE(philips_pm2800_devopts), |
c3eadb07 BV |
1726 | ARRAY_AND_SIZE(philips_pm2800_devopts_cg), |
1727 | NULL, 0, | |
1728 | NULL, 0, | |
91ef511d | 1729 | philips_pm2800_cmd, |
c3eadb07 | 1730 | philips_pm2800_probe_channels, |
fd243315 | 1731 | .init_acquisition = NULL, |
7e66bf05 | 1732 | .update_status = NULL, |
d4eabea8 | 1733 | }, |
81eb36d6 MS |
1734 | |
1735 | /* Rohde & Schwarz HMC8043 */ | |
5e7377f4 | 1736 | { "Rohde&Schwarz", "HMC8043", SCPI_DIALECT_UNKNOWN, 0, |
81eb36d6 MS |
1737 | ARRAY_AND_SIZE(rs_hmc8043_devopts), |
1738 | ARRAY_AND_SIZE(rs_hmc8043_devopts_cg), | |
1739 | ARRAY_AND_SIZE(rs_hmc8043_ch), | |
1740 | ARRAY_AND_SIZE(rs_hmc8043_cg), | |
1741 | rs_hmc8043_cmd, | |
1742 | .probe_channels = NULL, | |
fd243315 | 1743 | .init_acquisition = NULL, |
7e66bf05 | 1744 | .update_status = NULL, |
81eb36d6 | 1745 | }, |
bd5f0a14 FS |
1746 | |
1747 | /* Hameg / Rohde&Schwarz HMP4000 series */ | |
22f76e18 GS |
1748 | /* TODO Match on regex, pass scpi_pps item to .probe_channels(). */ |
1749 | { "HAMEG", "HMP4030", SCPI_DIALECT_HMP, 0, | |
1750 | ARRAY_AND_SIZE(rs_hmp4040_devopts), | |
1751 | ARRAY_AND_SIZE(rs_hmp4040_devopts_cg), | |
1752 | rs_hmp4040_ch, 3, | |
1753 | rs_hmp4040_cg, 3, | |
1754 | rs_hmp4040_cmd, | |
1755 | .probe_channels = NULL, | |
f403cb9d | 1756 | .init_acquisition = NULL, |
22f76e18 GS |
1757 | .update_status = NULL, |
1758 | }, | |
bd5f0a14 FS |
1759 | { "HAMEG", "HMP4040", SCPI_DIALECT_HMP, 0, |
1760 | ARRAY_AND_SIZE(rs_hmp4040_devopts), | |
1761 | ARRAY_AND_SIZE(rs_hmp4040_devopts_cg), | |
1762 | ARRAY_AND_SIZE(rs_hmp4040_ch), | |
1763 | ARRAY_AND_SIZE(rs_hmp4040_cg), | |
1764 | rs_hmp4040_cmd, | |
1765 | .probe_channels = NULL, | |
f403cb9d | 1766 | .init_acquisition = NULL, |
bd5f0a14 FS |
1767 | .update_status = NULL, |
1768 | }, | |
1c5d5905 GS |
1769 | { "ROHDE&SCHWARZ", "HMP2020", SCPI_DIALECT_HMP, 0, |
1770 | ARRAY_AND_SIZE(rs_hmp4040_devopts), | |
1771 | ARRAY_AND_SIZE(rs_hmp4040_devopts_cg), | |
1772 | rs_hmp2020_ch, 2, | |
1773 | rs_hmp4040_cg, 2, | |
1774 | rs_hmp4040_cmd, | |
1775 | .probe_channels = NULL, | |
1776 | .init_acquisition = NULL, | |
1777 | .update_status = NULL, | |
1778 | }, | |
1779 | { "ROHDE&SCHWARZ", "HMP2030", SCPI_DIALECT_HMP, 0, | |
1780 | ARRAY_AND_SIZE(rs_hmp4040_devopts), | |
1781 | ARRAY_AND_SIZE(rs_hmp4040_devopts_cg), | |
1782 | rs_hmp2030_ch, 3, | |
1783 | rs_hmp4040_cg, 3, | |
1784 | rs_hmp4040_cmd, | |
1785 | .probe_channels = NULL, | |
1786 | .init_acquisition = NULL, | |
1787 | .update_status = NULL, | |
1788 | }, | |
22f76e18 GS |
1789 | { "ROHDE&SCHWARZ", "HMP4030", SCPI_DIALECT_HMP, 0, |
1790 | ARRAY_AND_SIZE(rs_hmp4040_devopts), | |
1791 | ARRAY_AND_SIZE(rs_hmp4040_devopts_cg), | |
1792 | rs_hmp4040_ch, 3, | |
1793 | rs_hmp4040_cg, 3, | |
1794 | rs_hmp4040_cmd, | |
1795 | .probe_channels = NULL, | |
f403cb9d | 1796 | .init_acquisition = NULL, |
22f76e18 GS |
1797 | .update_status = NULL, |
1798 | }, | |
1799 | { "ROHDE&SCHWARZ", "HMP4040", SCPI_DIALECT_HMP, 0, | |
1800 | ARRAY_AND_SIZE(rs_hmp4040_devopts), | |
1801 | ARRAY_AND_SIZE(rs_hmp4040_devopts_cg), | |
1802 | ARRAY_AND_SIZE(rs_hmp4040_ch), | |
1803 | ARRAY_AND_SIZE(rs_hmp4040_cg), | |
1804 | rs_hmp4040_cmd, | |
1805 | .probe_channels = NULL, | |
f403cb9d | 1806 | .init_acquisition = NULL, |
22f76e18 GS |
1807 | .update_status = NULL, |
1808 | }, | |
d4eabea8 | 1809 | }; |
d4eabea8 | 1810 | |
1beccaed | 1811 | SR_PRIV unsigned int num_pps_profiles = ARRAY_SIZE(pps_profiles); |