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scpi-pps: Add support for Owon P4000 series.
[libsigrok.git] / src / hardware / scpi-pps / profiles.c
CommitLineData
d4eabea8
BV		 1/*
2 * This file is part of the libsigrok project.
3 *
4 * Copyright (C) 2014 Bert Vermeulen <bert@biot.com>
4ee1e2f3
AG		 5 * Copyright (C) 2015 Google, Inc.
6 * (Written by Alexandru Gagniuc <mrnuke@google.com> for Google, Inc.)
7e66bf05 7 * Copyright (C) 2017,2019 Frank Stettner <frank-stettner@gmx.net>
d4eabea8
BV		 8 *
9 * This program is free software: you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation, either version 3 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program. If not, see <http://www.gnu.org/licenses/>.
21 */
22
6ec6c43b 23#include <config.h>
22c18b03 24#include <string.h>
ba464a12 25#include <strings.h>
d4eabea8
BV		 26#include "protocol.h"
27
28#define CH_IDX(x) (1 << x)
6ed709fe 29#define FREQ_DC_ONLY {0, 0, 0, 0, 0}
49a468ed
FS		 30#define NO_OVP_LIMITS {0, 0, 0, 0, 0}
31#define NO_OCP_LIMITS {0, 0, 0, 0, 0}
d4eabea8 32
5c9e56c9
AG		 33/* Agilent/Keysight N5700A series */
34static const uint32_t agilent_n5700a_devopts[] = {
e91bb0a6 35 SR_CONF_CONTINUOUS,
88e4daa9
ML		 36 SR_CONF_LIMIT_SAMPLES | SR_CONF_GET | SR_CONF_SET,
37 SR_CONF_LIMIT_MSEC | SR_CONF_GET | SR_CONF_SET,
5c9e56c9
AG		 38};
39
40static const uint32_t agilent_n5700a_devopts_cg[] = {
41 SR_CONF_OVER_VOLTAGE_PROTECTION_THRESHOLD | SR_CONF_GET | SR_CONF_SET,
42 SR_CONF_OVER_CURRENT_PROTECTION_ENABLED | SR_CONF_GET | SR_CONF_SET,
43 SR_CONF_OVER_CURRENT_PROTECTION_THRESHOLD | SR_CONF_GET | SR_CONF_SET,
da005885
UH		 44 SR_CONF_VOLTAGE | SR_CONF_GET,
45 SR_CONF_VOLTAGE_TARGET | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
46 SR_CONF_CURRENT | SR_CONF_GET,
47 SR_CONF_ENABLED | SR_CONF_GET | SR_CONF_SET,
5c9e56c9
AG		 48};
49
6cc93128 50static const struct channel_group_spec agilent_n5700a_cg[] = {
f2bbcc33 51 { "1", CH_IDX(0), PPS_OVP | PPS_OCP, SR_MQFLAG_DC },
6cc93128
AG		 52};
53
8cb5affe 54static const struct channel_spec agilent_n5767a_ch[] = {
49a468ed 55 { "1", { 0, 60, 0.0072, 3, 4 }, { 0, 25, 0.003, 3, 4 }, { 0, 1500 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS },
5c9e56c9
AG		 56};
57
6cc93128 58static const struct channel_spec agilent_n5763a_ch[] = {
49a468ed 59 { "1", { 0, 12.5, 0.0015, 3, 4 }, { 0, 120, 0.0144, 3, 4 }, { 0, 1500 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS },
5c9e56c9
AG		 60};
61
62/*
63 * TODO: OVER_CURRENT_PROTECTION_ACTIVE status can be determined by the OC bit
562a3490 64 * in STAT:QUES:EVEN?, but this is not implemented.
5c9e56c9 65 */
8cb5affe 66static const struct scpi_command agilent_n5700a_cmd[] = {
5c9e56c9
AG		 67 { SCPI_CMD_REMOTE, "SYST:COMM:RLST REM" },
68 { SCPI_CMD_LOCAL, "SYST:COMM:RLST LOC" },
69 { SCPI_CMD_GET_MEAS_VOLTAGE, ":MEAS:VOLT?" },
70 { SCPI_CMD_GET_MEAS_CURRENT, "MEAS:CURR?" },
71 { SCPI_CMD_GET_VOLTAGE_TARGET, ":SOUR:VOLT?" },
72 { SCPI_CMD_SET_VOLTAGE_TARGET, ":SOUR:VOLT %.6f" },
73 { SCPI_CMD_GET_CURRENT_LIMIT, ":SOUR:CURR?" },
74 { SCPI_CMD_SET_CURRENT_LIMIT, ":SOUR:CURR %.6f" },
75 { SCPI_CMD_GET_OUTPUT_ENABLED, ":OUTP:STAT?" },
76 { SCPI_CMD_SET_OUTPUT_ENABLE, ":OUTP ON" },
77 { SCPI_CMD_SET_OUTPUT_DISABLE, ":OUTP OFF" },
78 { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_THRESHOLD, ":VOLT:PROT?" },
79 { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_THRESHOLD, ":VOLT:PROT %.6f" },
80 { SCPI_CMD_GET_OVER_CURRENT_PROTECTION_ENABLED, ":CURR:PROT:STAT?" },
81 { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_ENABLE, ":CURR:PROT:STAT ON?"},
82 { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_DISABLE, ":CURR:PROT:STAT OFF?"},
562a3490 83 /* Current limit (CC mode) and OCP are set using the same command. */
5c9e56c9
AG		 84 { SCPI_CMD_GET_OVER_CURRENT_PROTECTION_THRESHOLD, ":SOUR:CURR?" },
85 { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_THRESHOLD, ":SOUR:CURR %.6f" },
91ef511d 86 ALL_ZERO
5c9e56c9
AG		 87};
88
c3bfb959
MW		 89/* BK Precision 9130 series */
90static const uint32_t bk_9130_devopts[] = {
91 SR_CONF_CONTINUOUS,
92 SR_CONF_LIMIT_SAMPLES | SR_CONF_GET | SR_CONF_SET,
93 SR_CONF_LIMIT_MSEC | SR_CONF_GET | SR_CONF_SET,
94};
95
96static const uint32_t bk_9130_devopts_cg[] = {
97 SR_CONF_OVER_VOLTAGE_PROTECTION_THRESHOLD | SR_CONF_GET | SR_CONF_SET,
98 SR_CONF_VOLTAGE | SR_CONF_GET,
99 SR_CONF_VOLTAGE_TARGET | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
100 SR_CONF_CURRENT | SR_CONF_GET,
101 SR_CONF_CURRENT_LIMIT | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
102 SR_CONF_ENABLED | SR_CONF_GET | SR_CONF_SET,
103};
104
105static const struct channel_spec bk_9130_ch[] = {
106 { "1", { 0, 30, 0.001, 3, 3 }, { 0, 3, 0.001, 3, 3 }, { 0, 90, 0, 3, 3 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS },
107 { "2", { 0, 30, 0.001, 3, 3 }, { 0, 3, 0.001, 3, 3 }, { 0, 90, 0, 3, 3 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS },
108 { "3", { 0, 5, 0.001, 3, 3 }, { 0, 3, 0.001, 3, 3 }, { 0, 15, 0, 3, 3 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS },
109};
110
111static const struct channel_group_spec bk_9130_cg[] = {
f2bbcc33
FS		 112 { "1", CH_IDX(0), PPS_OVP, SR_MQFLAG_DC },
113 { "2", CH_IDX(1), PPS_OVP, SR_MQFLAG_DC },
114 { "3", CH_IDX(2), PPS_OVP, SR_MQFLAG_DC },
c3bfb959
MW		 115};
116
117static const struct scpi_command bk_9130_cmd[] = {
118 { SCPI_CMD_REMOTE, "SYST:REMOTE" },
119 { SCPI_CMD_LOCAL, "SYST:LOCAL" },
120 { SCPI_CMD_SELECT_CHANNEL, ":INST:NSEL %s" },
121 { SCPI_CMD_GET_MEAS_VOLTAGE, ":MEAS:VOLT?" },
122 { SCPI_CMD_GET_MEAS_CURRENT, ":MEAS:CURR?" },
123 { SCPI_CMD_GET_MEAS_POWER, ":MEAS:POWER?" },
124 { SCPI_CMD_GET_VOLTAGE_TARGET, ":SOUR:VOLT?" },
125 { SCPI_CMD_SET_VOLTAGE_TARGET, ":SOUR:VOLT %.6f" },
126 { SCPI_CMD_GET_CURRENT_LIMIT, ":SOUR:CURR?" },
127 { SCPI_CMD_SET_CURRENT_LIMIT, ":SOUR:CURR %.6f" },
128 { SCPI_CMD_GET_OUTPUT_ENABLED, ":OUTP?" },
129 { SCPI_CMD_SET_OUTPUT_ENABLE, ":OUTP 1" },
130 { SCPI_CMD_SET_OUTPUT_DISABLE, ":OUTP 0" },
131 { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_THRESHOLD, ":SOUR:VOLT:PROT?" },
132 { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_THRESHOLD, ":SOUR:VOLT:PROT %.6f" },
133 ALL_ZERO
134};
135
4ee1e2f3
AG		 136/* Chroma 61600 series AC source */
137static const uint32_t chroma_61604_devopts[] = {
e91bb0a6 138 SR_CONF_CONTINUOUS,
88e4daa9
ML		 139 SR_CONF_LIMIT_SAMPLES | SR_CONF_GET | SR_CONF_SET,
140 SR_CONF_LIMIT_MSEC | SR_CONF_GET | SR_CONF_SET,
4ee1e2f3
AG		 141};
142
143static const uint32_t chroma_61604_devopts_cg[] = {
144 SR_CONF_OVER_VOLTAGE_PROTECTION_THRESHOLD | SR_CONF_GET | SR_CONF_SET,
145 SR_CONF_OVER_CURRENT_PROTECTION_THRESHOLD | SR_CONF_GET | SR_CONF_SET,
da005885
UH		 146 SR_CONF_VOLTAGE | SR_CONF_GET,
147 SR_CONF_VOLTAGE_TARGET | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
6c0c9dd2
AG		 148 SR_CONF_OUTPUT_FREQUENCY | SR_CONF_GET,
149 SR_CONF_OUTPUT_FREQUENCY_TARGET | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
da005885
UH		 150 SR_CONF_CURRENT | SR_CONF_GET,
151 SR_CONF_ENABLED | SR_CONF_GET | SR_CONF_SET,
4ee1e2f3
AG		 152};
153
8cb5affe 154static const struct channel_spec chroma_61604_ch[] = {
49a468ed 155 { "1", { 0, 300, 0.1, 1, 1 }, { 0, 16, 0.1, 2, 2 }, { 0, 2000, 0, 1, 1 }, { 1.0, 1000.0, 0.01 }, NO_OVP_LIMITS, NO_OCP_LIMITS },
4ee1e2f3
AG		 156};
157
8cb5affe 158static const struct channel_group_spec chroma_61604_cg[] = {
f2bbcc33 159 { "1", CH_IDX(0), PPS_OVP | PPS_OCP, SR_MQFLAG_AC },
4ee1e2f3
AG		 160};
161
8cb5affe 162static const struct scpi_command chroma_61604_cmd[] = {
4ee1e2f3
AG		 163 { SCPI_CMD_REMOTE, "SYST:REM" },
164 { SCPI_CMD_LOCAL, "SYST:LOC" },
165 { SCPI_CMD_GET_MEAS_VOLTAGE, ":FETC:VOLT:ACDC?" },
6c0c9dd2 166 { SCPI_CMD_GET_MEAS_FREQUENCY, ":FETC:FREQ?" },
4ee1e2f3
AG		 167 { SCPI_CMD_GET_MEAS_CURRENT, ":FETC:CURR:AC?" },
168 { SCPI_CMD_GET_MEAS_POWER, ":FETC:POW:AC?" },
169 { SCPI_CMD_GET_VOLTAGE_TARGET, ":SOUR:VOLT:AC?" },
170 { SCPI_CMD_SET_VOLTAGE_TARGET, ":SOUR:VOLT:AC %.1f" },
6c0c9dd2
AG		 171 { SCPI_CMD_GET_FREQUENCY_TARGET, ":SOUR:FREQ?" },
172 { SCPI_CMD_SET_FREQUENCY_TARGET, ":SOUR:FREQ %.2f" },
4ee1e2f3
AG		 173 { SCPI_CMD_GET_OUTPUT_ENABLED, ":OUTP?" },
174 { SCPI_CMD_SET_OUTPUT_ENABLE, ":OUTP ON" },
175 { SCPI_CMD_SET_OUTPUT_DISABLE, ":OUTP OFF" },
176 { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_THRESHOLD, ":SOUR:VOLT:LIM:AC?" },
177 { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_THRESHOLD, ":SOUR:VOLT:LIM:AC %.1f" },
562a3490 178 /* This is not a current limit mode. It is overcurrent protection. */
4ee1e2f3
AG		 179 { SCPI_CMD_GET_OVER_CURRENT_PROTECTION_THRESHOLD, ":SOUR:CURR:LIM?" },
180 { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_THRESHOLD, ":SOUR:CURR:LIM %.2f" },
91ef511d 181 ALL_ZERO
4ee1e2f3
AG		 182};
183
5281993e 184/* Chroma 62000 series DC source */
5281993e 185static const uint32_t chroma_62000_devopts[] = {
e91bb0a6 186 SR_CONF_CONTINUOUS,
88e4daa9
ML		 187 SR_CONF_LIMIT_SAMPLES | SR_CONF_GET | SR_CONF_SET,
188 SR_CONF_LIMIT_MSEC | SR_CONF_GET | SR_CONF_SET,
5281993e
AG		 189};
190
191static const uint32_t chroma_62000_devopts_cg[] = {
192 SR_CONF_OVER_VOLTAGE_PROTECTION_THRESHOLD | SR_CONF_GET | SR_CONF_SET,
193 SR_CONF_OVER_CURRENT_PROTECTION_THRESHOLD | SR_CONF_GET | SR_CONF_SET,
194 SR_CONF_VOLTAGE | SR_CONF_GET,
195 SR_CONF_VOLTAGE_TARGET | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
196 SR_CONF_CURRENT | SR_CONF_GET,
197 SR_CONF_CURRENT_LIMIT | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
198 SR_CONF_ENABLED | SR_CONF_GET | SR_CONF_SET,
199};
200
5281993e 201static const struct channel_group_spec chroma_62000_cg[] = {
f2bbcc33 202 { "1", CH_IDX(0), PPS_OVP | PPS_OCP, SR_MQFLAG_DC },
5281993e
AG		 203};
204
205static const struct scpi_command chroma_62000_cmd[] = {
206 { SCPI_CMD_REMOTE, ":CONF:REM ON" },
207 { SCPI_CMD_LOCAL, ":CONF:REM OFF" },
208 { SCPI_CMD_BEEPER, ":CONF:BEEP?" },
209 { SCPI_CMD_BEEPER_ENABLE, ":CONF:BEEP ON" },
210 { SCPI_CMD_BEEPER_DISABLE, ":CONF:BEEP OFF" },
211 { SCPI_CMD_GET_MEAS_VOLTAGE, ":MEAS:VOLT?" },
212 { SCPI_CMD_GET_MEAS_CURRENT, ":MEAS:CURR?" },
213 { SCPI_CMD_GET_MEAS_POWER, ":MEAS:POW?" },
214 { SCPI_CMD_GET_VOLTAGE_TARGET, ":SOUR:VOLT?" },
215 { SCPI_CMD_SET_VOLTAGE_TARGET, ":SOUR:VOLT %.2f" },
216 { SCPI_CMD_GET_CURRENT_LIMIT, ":SOUR:CURR?" },
217 { SCPI_CMD_SET_CURRENT_LIMIT, ":SOUR:CURR %.6f" },
218 { SCPI_CMD_GET_OUTPUT_ENABLED, ":CONF:OUTP?" },
219 { SCPI_CMD_SET_OUTPUT_ENABLE, ":CONF:OUTP ON" },
220 { SCPI_CMD_SET_OUTPUT_DISABLE, ":CONF:OUTP OFF" },
221 { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_THRESHOLD, ":SOUR:VOLT:PROT:HIGH?" },
222 { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_THRESHOLD, ":SOUR:VOLT:PROT:HIGH %.6f" },
223 { SCPI_CMD_GET_OVER_CURRENT_PROTECTION_THRESHOLD, ":SOUR:CURR:PROT:HIGH?" },
224 { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_THRESHOLD, ":SOUR:CURR:PROT:HIGH %.6f" },
91ef511d 225 ALL_ZERO
5281993e
AG		 226};
227
9a5185c7
AG		 228static int chroma_62000p_probe_channels(struct sr_dev_inst *sdi,
229 struct sr_scpi_hw_info *hw_info,
230 struct channel_spec **channels, unsigned int *num_channels,
231 struct channel_group_spec **channel_groups,
232 unsigned int *num_channel_groups)
233{
6ed709fe 234 unsigned int volts, amps, watts;
9a5185c7
AG		 235 struct channel_spec *channel;
236
237 (void)sdi;
238
6ed709fe
AJ		 239 sscanf(hw_info->model, "620%uP-%u-%u", &watts, &volts, &amps);
240 watts *= 100;
241 sr_dbg("Found device rated for %d V, %d A and %d W", volts, amps, watts);
9a5185c7
AG		 242
243 if (volts > 600) {
244 sr_err("Probed max voltage of %u V is out of spec.", volts);
245 return SR_ERR_BUG;
246 }
247
6ed709fe 248 if (amps > 120) {
9a5185c7
AG		 249 sr_err("Probed max current of %u A is out of spec.", amps);
250 return SR_ERR_BUG;
251 }
252
6ed709fe
AJ		 253 if (watts > 5000) {
254 sr_err("Probed max power of %u W is out of spec.", watts);
255 return SR_ERR_BUG;
256 }
257
9a5185c7
AG		 258 channel = g_malloc0(sizeof(struct channel_spec));
259 channel->name = "1";
6ed709fe 260 channel->voltage[0] = channel->current[0] = channel->power[0] = 0.0;
bcee1299
UH		 261 channel->voltage[1] = volts;
262 channel->current[1] = amps;
263 channel->power[1] = watts;
9a5185c7 264 channel->voltage[2] = channel->current[2] = 0.01;
6ed709fe
AJ		 265 channel->voltage[3] = channel->voltage[4] = 3;
266 channel->current[3] = channel->current[4] = 4;
9a5185c7
AG		 267 *channels = channel;
268 *num_channels = 1;
269
270 *channel_groups = g_malloc(sizeof(struct channel_group_spec));
271 **channel_groups = chroma_62000_cg[0];
272 *num_channel_groups = 1;
273
274 return SR_OK;
275}
276
319fe9ce
UH		 277/* Rigol DP700 series */
278static const uint32_t rigol_dp700_devopts[] = {
279 SR_CONF_CONTINUOUS,
88e4daa9
ML		 280 SR_CONF_LIMIT_SAMPLES | SR_CONF_GET | SR_CONF_SET,
281 SR_CONF_LIMIT_MSEC | SR_CONF_GET | SR_CONF_SET,
319fe9ce
UH		 282};
283
284static const uint32_t rigol_dp700_devopts_cg[] = {
285 SR_CONF_REGULATION | SR_CONF_GET,
286 SR_CONF_OVER_VOLTAGE_PROTECTION_ENABLED | SR_CONF_GET | SR_CONF_SET,
287 SR_CONF_OVER_VOLTAGE_PROTECTION_ACTIVE | SR_CONF_GET,
d828b05e 288 SR_CONF_OVER_VOLTAGE_PROTECTION_THRESHOLD | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
319fe9ce
UH		 289 SR_CONF_OVER_CURRENT_PROTECTION_ENABLED | SR_CONF_GET | SR_CONF_SET,
290 SR_CONF_OVER_CURRENT_PROTECTION_ACTIVE | SR_CONF_GET,
d828b05e 291 SR_CONF_OVER_CURRENT_PROTECTION_THRESHOLD | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
319fe9ce
UH		 292 SR_CONF_VOLTAGE | SR_CONF_GET,
293 SR_CONF_VOLTAGE_TARGET | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
294 SR_CONF_CURRENT | SR_CONF_GET,
295 SR_CONF_CURRENT_LIMIT | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
296 SR_CONF_ENABLED | SR_CONF_GET | SR_CONF_SET,
297};
298
299static const struct channel_spec rigol_dp711_ch[] = {
d828b05e 300 { "1", { 0, 30, 0.01, 3, 3 }, { 0, 5, 0.01, 3, 3 }, { 0, 150, 0, 3, 3 }, FREQ_DC_ONLY, { 0.01, 33, 0.01}, { 0.01, 5.5, 0.01 } },
319fe9ce
UH		 301};
302
303static const struct channel_spec rigol_dp712_ch[] = {
d828b05e 304 { "1", { 0, 50, 0.01, 3, 3 }, { 0, 3, 0.01, 3, 3 }, { 0, 150, 0, 3, 3 }, FREQ_DC_ONLY, { 0.01, 55, 0.01}, { 0.01, 3.3, 0.01 } },
319fe9ce
UH		 305};
306
307static const struct channel_group_spec rigol_dp700_cg[] = {
f2bbcc33 308 { "1", CH_IDX(0), PPS_OVP | PPS_OCP, SR_MQFLAG_DC },
319fe9ce
UH		 309};
310
311/* Same as the DP800 series, except for the missing :SYST:OTP* commands. */
312static const struct scpi_command rigol_dp700_cmd[] = {
313 { SCPI_CMD_REMOTE, "SYST:REMOTE" },
314 { SCPI_CMD_LOCAL, "SYST:LOCAL" },
315 { SCPI_CMD_BEEPER, "SYST:BEEP:STAT?" },
316 { SCPI_CMD_BEEPER_ENABLE, "SYST:BEEP:STAT ON" },
317 { SCPI_CMD_BEEPER_DISABLE, "SYST:BEEP:STAT OFF" },
318 { SCPI_CMD_SELECT_CHANNEL, ":INST:NSEL %s" },
319 { SCPI_CMD_GET_MEAS_VOLTAGE, ":MEAS:VOLT?" },
320 { SCPI_CMD_GET_MEAS_CURRENT, ":MEAS:CURR?" },
321 { SCPI_CMD_GET_MEAS_POWER, ":MEAS:POWE?" },
322 { SCPI_CMD_GET_VOLTAGE_TARGET, ":SOUR:VOLT?" },
323 { SCPI_CMD_SET_VOLTAGE_TARGET, ":SOUR:VOLT %.6f" },
324 { SCPI_CMD_GET_CURRENT_LIMIT, ":SOUR:CURR?" },
325 { SCPI_CMD_SET_CURRENT_LIMIT, ":SOUR:CURR %.6f" },
326 { SCPI_CMD_GET_OUTPUT_ENABLED, ":OUTP?" },
327 { SCPI_CMD_SET_OUTPUT_ENABLE, ":OUTP ON" },
328 { SCPI_CMD_SET_OUTPUT_DISABLE, ":OUTP OFF" },
329 { SCPI_CMD_GET_OUTPUT_REGULATION, ":OUTP:MODE?" },
330 { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_ENABLED, ":OUTP:OVP?" },
331 { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_ENABLE, ":OUTP:OVP ON" },
332 { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_DISABLE, ":OUTP:OVP OFF" },
333 { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_ACTIVE, ":OUTP:OVP:QUES?" },
334 { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_THRESHOLD, ":OUTP:OVP:VAL?" },
335 { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_THRESHOLD, ":OUTP:OVP:VAL %.6f" },
336 { SCPI_CMD_GET_OVER_CURRENT_PROTECTION_ENABLED, ":OUTP:OCP?" },
337 { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_ENABLE, ":OUTP:OCP:STAT ON" },
338 { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_DISABLE, ":OUTP:OCP:STAT OFF" },
339 { SCPI_CMD_GET_OVER_CURRENT_PROTECTION_ACTIVE, ":OUTP:OCP:QUES?" },
340 { SCPI_CMD_GET_OVER_CURRENT_PROTECTION_THRESHOLD, ":OUTP:OCP:VAL?" },
341 { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_THRESHOLD, ":OUTP:OCP:VAL %.6f" },
342 ALL_ZERO
343};
344
d4eabea8 345/* Rigol DP800 series */
584560f1 346static const uint32_t rigol_dp800_devopts[] = {
e91bb0a6 347 SR_CONF_CONTINUOUS,
5827f61b 348 SR_CONF_OVER_TEMPERATURE_PROTECTION | SR_CONF_GET | SR_CONF_SET,
88e4daa9
ML		 349 SR_CONF_LIMIT_SAMPLES | SR_CONF_GET | SR_CONF_SET,
350 SR_CONF_LIMIT_MSEC | SR_CONF_GET | SR_CONF_SET,
d4eabea8
BV		 351};
352
584560f1 353static const uint32_t rigol_dp800_devopts_cg[] = {
7a0b98b5 354 SR_CONF_REGULATION | SR_CONF_GET,
5827f61b
BV		 355 SR_CONF_OVER_VOLTAGE_PROTECTION_ENABLED | SR_CONF_GET | SR_CONF_SET,
356 SR_CONF_OVER_VOLTAGE_PROTECTION_ACTIVE | SR_CONF_GET,
357 SR_CONF_OVER_VOLTAGE_PROTECTION_THRESHOLD | SR_CONF_GET | SR_CONF_SET,
358 SR_CONF_OVER_CURRENT_PROTECTION_ENABLED | SR_CONF_GET | SR_CONF_SET,
359 SR_CONF_OVER_CURRENT_PROTECTION_ACTIVE | SR_CONF_GET,
360 SR_CONF_OVER_CURRENT_PROTECTION_THRESHOLD | SR_CONF_GET | SR_CONF_SET,
7a0b98b5
AJ		 361 SR_CONF_VOLTAGE | SR_CONF_GET,
362 SR_CONF_VOLTAGE_TARGET | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
363 SR_CONF_CURRENT | SR_CONF_GET,
364 SR_CONF_CURRENT_LIMIT | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
365 SR_CONF_ENABLED | SR_CONF_GET | SR_CONF_SET,
d4eabea8
BV		 366};
367
8cb5affe 368static const struct channel_spec rigol_dp821a_ch[] = {
49a468ed
FS		 369 { "1", { 0, 60, 0.001, 3, 3 }, { 0, 1, 0.0001, 4, 4 }, { 0, 60, 0, 3, 4 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS },
370 { "2", { 0, 8, 0.001, 3, 3 }, { 0, 10, 0.001, 3, 3 }, { 0, 80, 0, 3, 3 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS },
cfcdf576
ML		 371};
372
8cb5affe 373static const struct channel_spec rigol_dp831_ch[] = {
49a468ed
FS		 374 { "1", { 0, 8, 0.001, 3, 4 }, { 0, 5, 0.0003, 3, 4 }, { 0, 40, 0, 3, 4 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS },
375 { "2", { 0, 30, 0.001, 3, 4 }, { 0, 2, 0.0001, 3, 4 }, { 0, 60, 0, 3, 4 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS },
376 { "3", { 0, -30, 0.001, 3, 4 }, { 0, 2, 0.0001, 3, 4 }, { 0, 60, 0, 3, 4 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS },
d4eabea8
BV		 377};
378
8cb5affe 379static const struct channel_spec rigol_dp832_ch[] = {
49a468ed
FS		 380 { "1", { 0, 30, 0.001, 3, 4 }, { 0, 3, 0.001, 3, 4 }, { 0, 90, 0, 3, 4 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS },
381 { "2", { 0, 30, 0.001, 3, 4 }, { 0, 3, 0.001, 3, 4 }, { 0, 90, 0, 3, 4 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS },
382 { "3", { 0, 5, 0.001, 3, 4 }, { 0, 3, 0.001, 3, 4 }, { 0, 90, 0, 3, 4 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS },
3222ee10
BV		 383};
384
8cb5affe 385static const struct channel_group_spec rigol_dp820_cg[] = {
f2bbcc33
FS		 386 { "1", CH_IDX(0), PPS_OVP | PPS_OCP, SR_MQFLAG_DC },
387 { "2", CH_IDX(1), PPS_OVP | PPS_OCP, SR_MQFLAG_DC },
cfcdf576
ML		 388};
389
8cb5affe 390static const struct channel_group_spec rigol_dp830_cg[] = {
f2bbcc33
FS		 391 { "1", CH_IDX(0), PPS_OVP | PPS_OCP, SR_MQFLAG_DC },
392 { "2", CH_IDX(1), PPS_OVP | PPS_OCP, SR_MQFLAG_DC },
393 { "3", CH_IDX(2), PPS_OVP | PPS_OCP, SR_MQFLAG_DC },
d4eabea8
BV		 394};
395
8cb5affe 396static const struct scpi_command rigol_dp800_cmd[] = {
60475cd7
BV		 397 { SCPI_CMD_REMOTE, "SYST:REMOTE" },
398 { SCPI_CMD_LOCAL, "SYST:LOCAL" },
ee2860ee
BV		 399 { SCPI_CMD_BEEPER, "SYST:BEEP:STAT?" },
400 { SCPI_CMD_BEEPER_ENABLE, "SYST:BEEP:STAT ON" },
401 { SCPI_CMD_BEEPER_DISABLE, "SYST:BEEP:STAT OFF" },
60475cd7
BV		 402 { SCPI_CMD_SELECT_CHANNEL, ":INST:NSEL %s" },
403 { SCPI_CMD_GET_MEAS_VOLTAGE, ":MEAS:VOLT?" },
404 { SCPI_CMD_GET_MEAS_CURRENT, ":MEAS:CURR?" },
405 { SCPI_CMD_GET_MEAS_POWER, ":MEAS:POWE?" },
406 { SCPI_CMD_GET_VOLTAGE_TARGET, ":SOUR:VOLT?" },
407 { SCPI_CMD_SET_VOLTAGE_TARGET, ":SOUR:VOLT %.6f" },
408 { SCPI_CMD_GET_CURRENT_LIMIT, ":SOUR:CURR?" },
409 { SCPI_CMD_SET_CURRENT_LIMIT, ":SOUR:CURR %.6f" },
410 { SCPI_CMD_GET_OUTPUT_ENABLED, ":OUTP?" },
411 { SCPI_CMD_SET_OUTPUT_ENABLE, ":OUTP ON" },
412 { SCPI_CMD_SET_OUTPUT_DISABLE, ":OUTP OFF" },
413 { SCPI_CMD_GET_OUTPUT_REGULATION, ":OUTP:MODE?" },
d4eabea8 414 { SCPI_CMD_GET_OVER_TEMPERATURE_PROTECTION, ":SYST:OTP?" },
53a81803
BV		 415 { SCPI_CMD_SET_OVER_TEMPERATURE_PROTECTION_ENABLE, ":SYST:OTP ON" },
416 { SCPI_CMD_SET_OVER_TEMPERATURE_PROTECTION_DISABLE, ":SYST:OTP OFF" },
60475cd7
BV		 417 { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_ENABLED, ":OUTP:OVP?" },
418 { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_ENABLE, ":OUTP:OVP ON" },
419 { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_DISABLE, ":OUTP:OVP OFF" },
420 { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_ACTIVE, ":OUTP:OVP:QUES?" },
421 { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_THRESHOLD, ":OUTP:OVP:VAL?" },
422 { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_THRESHOLD, ":OUTP:OVP:VAL %.6f" },
423 { SCPI_CMD_GET_OVER_CURRENT_PROTECTION_ENABLED, ":OUTP:OCP?" },
424 { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_ENABLE, ":OUTP:OCP:STAT ON" },
425 { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_DISABLE, ":OUTP:OCP:STAT OFF" },
426 { SCPI_CMD_GET_OVER_CURRENT_PROTECTION_ACTIVE, ":OUTP:OCP:QUES?" },
427 { SCPI_CMD_GET_OVER_CURRENT_PROTECTION_THRESHOLD, ":OUTP:OCP:VAL?" },
428 { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_THRESHOLD, ":OUTP:OCP:VAL %.6f" },
91ef511d 429 ALL_ZERO
d4eabea8
BV		 430};
431
dbc519f7 432/* HP 663xA series */
e76a3575
AG		 433static const uint32_t hp_6630a_devopts[] = {
434 SR_CONF_CONTINUOUS,
88e4daa9
ML		 435 SR_CONF_LIMIT_SAMPLES | SR_CONF_GET | SR_CONF_SET,
436 SR_CONF_LIMIT_MSEC | SR_CONF_GET | SR_CONF_SET,
7c517d02
FS		 437};
438
439static const uint32_t hp_6630a_devopts_cg[] = {
e76a3575
AG		 440 SR_CONF_ENABLED | SR_CONF_SET,
441 SR_CONF_VOLTAGE | SR_CONF_GET,
442 SR_CONF_CURRENT | SR_CONF_GET,
443 SR_CONF_VOLTAGE_TARGET | SR_CONF_SET | SR_CONF_LIST,
444 SR_CONF_CURRENT_LIMIT | SR_CONF_SET | SR_CONF_LIST,
f083ae63 445 SR_CONF_OVER_VOLTAGE_PROTECTION_ACTIVE | SR_CONF_GET,
49a468ed 446 SR_CONF_OVER_VOLTAGE_PROTECTION_THRESHOLD | SR_CONF_SET | SR_CONF_LIST,
e76a3575 447 SR_CONF_OVER_CURRENT_PROTECTION_ENABLED | SR_CONF_SET,
f083ae63
FS		 448 SR_CONF_OVER_CURRENT_PROTECTION_ACTIVE | SR_CONF_GET,
449 SR_CONF_OVER_TEMPERATURE_PROTECTION_ACTIVE | SR_CONF_GET,
0ad7074c 450 SR_CONF_REGULATION | SR_CONF_GET,
e76a3575
AG		 451};
452
5ce427c7
FS		 453static const struct channel_spec hp_6632a_ch[] = {
454 { "1", { 0, 20.475, 0.005, 3, 4 }, { 0, 5.1188, 0.00125, 4, 5 }, { 0, 104.80743 }, FREQ_DC_ONLY, { 0, 22, 0.1 }, NO_OCP_LIMITS },
455};
456
dbc519f7
FS		 457static const struct channel_spec hp_6633a_ch[] = {
458 { "1", { 0, 51.188, 0.0125, 3, 4 }, { 0, 2.0475, 0.0005, 4, 5 }, { 0, 104.80743 }, FREQ_DC_ONLY, { 0, 55, 0.25 }, NO_OCP_LIMITS },
459};
460
5ce427c7
FS		 461static const struct channel_spec hp_6634a_ch[] = {
462 { "1", { 0, 102.38, 0.025, 3, 4 }, { 0, 1.0238, 0.00025, 4, 5 }, { 0, 104.81664 }, FREQ_DC_ONLY, { 0, 110, 0.5 }, NO_OCP_LIMITS },
463};
464
dbc519f7
FS		 465static const struct channel_group_spec hp_6630a_cg[] = {
466 { "1", CH_IDX(0), PPS_OVP | PPS_OCP, SR_MQFLAG_DC },
467};
468
469static const struct scpi_command hp_6630a_cmd[] = {
470 { SCPI_CMD_SET_OUTPUT_ENABLE, "OUT 1" },
471 { SCPI_CMD_SET_OUTPUT_DISABLE, "OUT 0" },
472 { SCPI_CMD_GET_MEAS_VOLTAGE, "VOUT?" },
473 { SCPI_CMD_GET_MEAS_CURRENT, "IOUT?" },
474 { SCPI_CMD_SET_VOLTAGE_TARGET, "VSET %.4f" },
475 { SCPI_CMD_SET_CURRENT_LIMIT, "ISET %.4f" },
f083ae63
FS		 476 { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_ACTIVE, "STS?" },
477 { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_THRESHOLD, "OVSET %.4f" },
dbc519f7
FS		 478 { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_ENABLE, "OCP 1" },
479 { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_DISABLE, "OCP 0" },
f083ae63
FS		 480 { SCPI_CMD_GET_OVER_CURRENT_PROTECTION_ACTIVE, "STS?" },
481 { SCPI_CMD_GET_OVER_TEMPERATURE_PROTECTION_ACTIVE, "STS?" },
0ad7074c 482 { SCPI_CMD_GET_OUTPUT_REGULATION, "STS?" },
dbc519f7
FS		 483 ALL_ZERO
484};
485
fd243315 486static int hp_6630a_init_acquisition(const struct sr_dev_inst *sdi)
fdf03652
FS		 487{
488 struct sr_scpi_dev_inst *scpi;
fdf03652
FS		 489
490 scpi = sdi->conn;
491
492 /*
493 * Monitor CV (1), CC+ (2), UR (4), OVP (8), OTP (16), OCP (64) and
494 * CC- (256) bits of the Status Register for the FAULT? query.
495 */
b89e6db9 496 return sr_scpi_send(scpi, "UNMASK 607");
fdf03652
FS		 497}
498
499static int hp_6630a_update_status(const struct sr_dev_inst *sdi)
500{
501 struct sr_scpi_dev_inst *scpi;
502 int ret;
503 int fault;
504 gboolean cv, cc_pos, unreg, cc_neg;
505 gboolean regulation_changed;
506 char *regulation;
507
508 scpi = sdi->conn;
509
510 /*
511 * Use the FAULT register (only 0->1 transitions), this way multiple set
512 * regulation bits in the STS/ASTS registers are ignored. In rare cases
513 * we will miss some changes (1->0 transitions, e.g. no regulation at all),
514 * but SPS/ASPS doesn't work either, unless all states are stored and
515 * compared to the states in STS/ASTS.
516 * TODO: Use SPoll or SRQ when SCPI over GPIB is used.
517 */
518 ret = sr_scpi_get_int(scpi, "FAULT?", &fault);
519 if (ret != SR_OK)
520 return ret;
521
522 /* OVP */
523 if (fault & (1 << 3))
524 sr_session_send_meta(sdi, SR_CONF_OVER_VOLTAGE_PROTECTION_ACTIVE,
525 g_variant_new_boolean(fault & (1 << 3)));
526
527 /* OCP */
528 if (fault & (1 << 6))
529 sr_session_send_meta(sdi, SR_CONF_OVER_CURRENT_PROTECTION_ACTIVE,
530 g_variant_new_boolean(fault & (1 << 6)));
531
532 /* OTP */
533 if (fault & (1 << 4))
534 sr_session_send_meta(sdi, SR_CONF_OVER_TEMPERATURE_PROTECTION_ACTIVE,
535 g_variant_new_boolean(fault & (1 << 4)));
536
537 /* CV */
538 cv = (fault & (1 << 0));
539 regulation_changed = (fault & (1 << 0));
540 /* CC+ */
541 cc_pos = (fault & (1 << 1));
542 regulation_changed = (fault & (1 << 1)) | regulation_changed;
543 /* UNREG */
544 unreg = (fault & (1 << 2));
545 regulation_changed = (fault & (1 << 2)) | regulation_changed;
546 /* CC- */
547 cc_neg = (fault & (1 << 9));
548 regulation_changed = (fault & (1 << 9)) | regulation_changed;
549
550 if (regulation_changed) {
b89e6db9 551 if (cv && !cc_pos && !cc_neg && !unreg)
fdf03652
FS		 552 regulation = "CV";
553 else if (cc_pos && !cv && !cc_neg && !unreg)
554 regulation = "CC";
555 else if (cc_neg && !cv && !cc_pos && !unreg)
556 regulation = "CC-";
557 else if (unreg && !cv && !cc_pos && !cc_neg)
558 regulation = "UR";
b89e6db9 559 else if (!cv && !cc_pos && !cc_neg && !unreg)
fdf03652
FS		 560 regulation = "";
561 else {
562 sr_dbg("Undefined regulation for HP 66xxA "
563 "(CV=%i, CC+=%i, CC-=%i, UR=%i).",
564 cv, cc_pos, cc_neg, unreg);
565 return FALSE;
566 }
567 sr_session_send_meta(sdi, SR_CONF_REGULATION,
568 g_variant_new_string(regulation));
569 }
570
571 return SR_OK;
572}
573
dbc519f7 574/* HP 663xB series */
a61c8cce 575static const uint32_t hp_6630b_devopts[] = {
e91bb0a6 576 SR_CONF_CONTINUOUS,
88e4daa9
ML		 577 SR_CONF_LIMIT_SAMPLES | SR_CONF_GET | SR_CONF_SET,
578 SR_CONF_LIMIT_MSEC | SR_CONF_GET | SR_CONF_SET,
7c517d02
FS		 579};
580
a61c8cce 581static const uint32_t hp_6630b_devopts_cg[] = {
7a0b98b5
AJ		 582 SR_CONF_ENABLED | SR_CONF_GET | SR_CONF_SET,
583 SR_CONF_VOLTAGE | SR_CONF_GET,
584 SR_CONF_CURRENT | SR_CONF_GET,
585 SR_CONF_VOLTAGE_TARGET | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
586 SR_CONF_CURRENT_LIMIT | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
8b5eadf4 587 SR_CONF_OVER_VOLTAGE_PROTECTION_ACTIVE | SR_CONF_GET,
49a468ed 588 SR_CONF_OVER_VOLTAGE_PROTECTION_THRESHOLD | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
7e381bfc 589 SR_CONF_OVER_CURRENT_PROTECTION_ENABLED | SR_CONF_GET | SR_CONF_SET,
8b5eadf4
FS		 590 SR_CONF_OVER_CURRENT_PROTECTION_ACTIVE | SR_CONF_GET,
591 SR_CONF_OVER_TEMPERATURE_PROTECTION_ACTIVE | SR_CONF_GET,
43ff1110 592 SR_CONF_REGULATION | SR_CONF_GET,
bc4a2a46
BV		 593};
594
5ce427c7
FS		 595static const struct channel_spec hp_6611c_ch[] = {
596 { "1", { 0, 8.19, 0.002, 3, 4 }, { 0, 5.1188, 0.00125, 4, 5 }, { 0, 41.92297 }, FREQ_DC_ONLY, { 0, 12, 0.06 }, NO_OCP_LIMITS },
597};
598
599static const struct channel_spec hp_6612c_ch[] = {
600 { "1", { 0, 20.475, 0.005, 3, 4 }, { 0, 2.0475, 0.0005, 4, 5 }, { 0, 41.92256 }, FREQ_DC_ONLY, { 0, 22, 0.1 }, NO_OCP_LIMITS },
601};
602
603static const struct channel_spec hp_6613c_ch[] = {
604 { "1", { 0, 51.188, 0.0125, 3, 4 }, { 0, 1.0238, 0.00025, 4, 5 }, { 0, 52.40627 }, FREQ_DC_ONLY, { 0, 55, 0.25 }, NO_OCP_LIMITS },
605};
606
607static const struct channel_spec hp_6614c_ch[] = {
608 { "1", { 0, 102.38, 0.025, 3, 4 }, { 0, 0.5118, 0.000125, 4, 5 }, { 0, 52.39808 }, FREQ_DC_ONLY, { 0, 110, 0.5 }, NO_OCP_LIMITS },
609};
610
a61c8cce 611static const struct channel_spec hp_6631b_ch[] = {
49a468ed 612 { "1", { 0, 8.19, 0.002, 3, 4 }, { 0, 10.237, 0.00263, 4, 5 }, { 0, 83.84103 }, FREQ_DC_ONLY, { 0, 12, 0.06 }, NO_OCP_LIMITS },
a61c8cce
FS		 613};
614
8cb5affe 615static const struct channel_spec hp_6632b_ch[] = {
49a468ed 616 { "1", { 0, 20.475, 0.005, 3, 4 }, { 0, 5.1188, 0.00132, 4, 5 }, { 0, 104.80743 }, FREQ_DC_ONLY, { 0, 22, 0.1 }, NO_OCP_LIMITS },
bc4a2a46
BV		 617};
618
0b0f40d8
MW		 619static const struct channel_spec hp_66312a_ch[] = {
620 { "1", { 0, 20.475, 0.0001, 4, 5 }, { 0, 2.0475, 0.0001, 4, 5 }, { 0, 41.92256 }, FREQ_DC_ONLY, { 0, 22, 0.01 }, NO_OCP_LIMITS },
621};
622
a61c8cce 623static const struct channel_spec hp_66332a_ch[] = {
49a468ed 624 { "1", { 0, 20.475, 0.005, 3, 4 }, { 0, 5.1188, 0.00132, 4, 5 }, { 0, 104.80743 }, FREQ_DC_ONLY, { 0, 22, 0.1 }, NO_OCP_LIMITS },
a61c8cce
FS		 625};
626
627static const struct channel_spec hp_6633b_ch[] = {
49a468ed 628 { "1", { 0, 51.188, 0.0125, 3, 4 }, { 0, 2.0475, 0.000526, 4, 5 }, { 0, 104.80743 }, FREQ_DC_ONLY, { 0, 55, 0.25 }, NO_OCP_LIMITS },
a61c8cce
FS		 629};
630
631static const struct channel_spec hp_6634b_ch[] = {
49a468ed 632 { "1", { 0, 102.38, 0.025, 3, 4 }, { 0, 1.0238, 0.000263, 4, 5 }, { 0, 104.81664 }, FREQ_DC_ONLY, { 0, 110, 0.5 }, NO_OCP_LIMITS },
a61c8cce
FS		 633};
634
dbc519f7 635static const struct channel_group_spec hp_6630b_cg[] = {
3d1aa50f 636 { "1", CH_IDX(0), PPS_OVP | PPS_OCP, SR_MQFLAG_DC },
bc4a2a46
BV		 637};
638
a61c8cce 639static const struct scpi_command hp_6630b_cmd[] = {
26e96658
FS		 640 /*
641 * SCPI_CMD_REMOTE and SCPI_CMD_LOCAL are not used when GPIB is used,
642 * otherwise the device will report (non critical) error 602.
643 */
7e381bfc
FS		 644 { SCPI_CMD_REMOTE, "SYST:REM" },
645 { SCPI_CMD_LOCAL, "SYST:LOC" },
bc4a2a46 646 { SCPI_CMD_GET_OUTPUT_ENABLED, "OUTP:STAT?" },
53a81803
BV		 647 { SCPI_CMD_SET_OUTPUT_ENABLE, "OUTP:STAT ON" },
648 { SCPI_CMD_SET_OUTPUT_DISABLE, "OUTP:STAT OFF" },
bc4a2a46
BV		 649 { SCPI_CMD_GET_MEAS_VOLTAGE, ":MEAS:VOLT?" },
650 { SCPI_CMD_GET_MEAS_CURRENT, ":MEAS:CURR?" },
ca95e90f
BV		 651 { SCPI_CMD_GET_VOLTAGE_TARGET, ":SOUR:VOLT?" },
652 { SCPI_CMD_SET_VOLTAGE_TARGET, ":SOUR:VOLT %.6f" },
653 { SCPI_CMD_GET_CURRENT_LIMIT, ":SOUR:CURR?" },
654 { SCPI_CMD_SET_CURRENT_LIMIT, ":SOUR:CURR %.6f" },
7e381bfc
FS		 655 { SCPI_CMD_GET_OVER_CURRENT_PROTECTION_ENABLED, ":CURR:PROT:STAT?" },
656 { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_ENABLE, ":CURR:PROT:STAT 1" },
657 { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_DISABLE, ":CURR:PROT:STAT 0" },
8b5eadf4
FS		 658 { SCPI_CMD_GET_OVER_CURRENT_PROTECTION_ACTIVE, "STAT:QUES:COND?" },
659 { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_ACTIVE, "STAT:QUES:COND?" },
7e381bfc
FS		 660 { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_THRESHOLD, ":VOLT:PROT?" },
661 { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_THRESHOLD, ":VOLT:PROT %.6f" },
8b5eadf4 662 { SCPI_CMD_GET_OVER_TEMPERATURE_PROTECTION_ACTIVE, "STAT:QUES:COND?" },
43ff1110 663 { SCPI_CMD_GET_OUTPUT_REGULATION, "STAT:OPER:COND?" },
91ef511d 664 ALL_ZERO
bc4a2a46
BV		 665};
666
fd243315 667static int hp_6630b_init_acquisition(const struct sr_dev_inst *sdi)
fe4bb774
FS		 668{
669 struct sr_scpi_dev_inst *scpi;
670 int ret;
671
672 scpi = sdi->conn;
673
674 /*
675 * Monitor CV (256), CC+ (1024) and CC- (2048) bits of the
676 * Operational Status Register.
677 * Use both positive and negative transitions of the status bits.
678 */
679 ret = sr_scpi_send(scpi, "STAT:OPER:PTR 3328;NTR 3328;ENAB 3328");
680 if (ret != SR_OK)
681 return ret;
682
683 /*
684 * Monitor OVP (1), OCP (2), OTP (16) and Unreg (1024) bits of the
685 * Questionable Status Register.
686 * Use both positive and negative transitions of the status bits.
687 */
688 ret = sr_scpi_send(scpi, "STAT:QUES:PTR 1043;NTR 1043;ENAB 1043");
689 if (ret != SR_OK)
690 return ret;
691
692 /*
693 * Service Request Enable Register set for Operational Status Register
694 * bits (128) and Questionable Status Register bits (8).
695 * This masks the Status Register generating a SRQ/RQS. Not implemented yet!
696 */
697 /*
698 ret = sr_scpi_send(scpi, "*SRE 136");
699 if (ret != SR_OK)
700 return ret;
701 */
702
703 return SR_OK;
704}
705
706static int hp_6630b_update_status(const struct sr_dev_inst *sdi)
707{
708 struct sr_scpi_dev_inst *scpi;
709 int ret;
710 int stb;
711 int ques_even, ques_cond;
712 int oper_even, oper_cond;
713 gboolean output_enabled;
714 gboolean unreg, cv, cc_pos, cc_neg;
715 gboolean regulation_changed;
716 char *regulation;
717
718 scpi = sdi->conn;
719
720 unreg = FALSE;
721 cv = FALSE;
722 cc_pos = FALSE;
723 cc_neg = FALSE;
724 regulation_changed = FALSE;
725
726 /*
727 * Use SPoll when SCPI uses GPIB as transport layer.
728 * SPoll is approx. twice as fast as a normal GPIB write + read would be!
729 */
730#ifdef HAVE_LIBGPIB
731 char spoll_buf;
732
733 if (scpi->transport == SCPI_TRANSPORT_LIBGPIB) {
734 ret = sr_scpi_gpib_spoll(scpi, &spoll_buf);
735 if (ret != SR_OK)
736 return ret;
737 stb = (uint8_t)spoll_buf;
738 }
739 else {
740#endif
741 ret = sr_scpi_get_int(scpi, "*STB?", &stb);
742 if (ret != SR_OK)
743 return ret;
744#ifdef HAVE_LIBGPIB
745 }
746#endif
747
748 /* Questionable status summary bit */
749 if (stb & (1 << 3)) {
750 /* Read the event register to clear it! */
751 ret = sr_scpi_get_int(scpi, "STAT:QUES:EVEN?", &ques_even);
752 if (ret != SR_OK)
753 return ret;
754 /* Now get the values. */
755 ret = sr_scpi_get_int(scpi, "STAT:QUES:COND?", &ques_cond);
756 if (ret != SR_OK)
757 return ret;
758
759 /* OVP */
760 if (ques_even & (1 << 0))
761 sr_session_send_meta(sdi, SR_CONF_OVER_VOLTAGE_PROTECTION_ACTIVE,
762 g_variant_new_boolean(ques_cond & (1 << 0)));
763
764 /* OCP */
765 if (ques_even & (1 << 1))
766 sr_session_send_meta(sdi, SR_CONF_OVER_CURRENT_PROTECTION_ACTIVE,
767 g_variant_new_boolean(ques_cond & (1 << 1)));
768
769 /* OTP */
770 if (ques_even & (1 << 4))
771 sr_session_send_meta(sdi, SR_CONF_OVER_TEMPERATURE_PROTECTION_ACTIVE,
772 g_variant_new_boolean(ques_cond & (1 << 4)));
773
774 /* UNREG */
775 unreg = (ques_cond & (1 << 10));
776 regulation_changed = (ques_even & (1 << 10)) | regulation_changed;
777
778 /*
779 * Check if output state has changed, due to one of the
780 * questionable states changed.
b89e6db9
UH		 781 * NOTE: The output state is sent even if it hasn't changed,
782 * but that only happens rarely.
fe4bb774
FS		 783 */
784 ret = sr_scpi_get_bool(scpi, "OUTP:STAT?", &output_enabled);
785 if (ret != SR_OK)
786 return ret;
787 sr_session_send_meta(sdi, SR_CONF_ENABLED,
788 g_variant_new_boolean(output_enabled));
789 }
790
791 /* Operation status summary bit */
792 if (stb & (1 << 7)) {
793 /* Read the event register to clear it! */
794 ret = sr_scpi_get_int(scpi, "STAT:OPER:EVEN?", &oper_even);
795 if (ret != SR_OK)
796 return ret;
797 /* Now get the values. */
798 ret = sr_scpi_get_int(scpi, "STAT:OPER:COND?", &oper_cond);
799 if (ret != SR_OK)
800 return ret;
801
802 /* CV */
803 cv = (oper_cond & (1 << 8));
804 regulation_changed = (oper_even & (1 << 8)) | regulation_changed;
805 /* CC+ */
806 cc_pos = (oper_cond & (1 << 10));
807 regulation_changed = (oper_even & (1 << 10)) | regulation_changed;
808 /* CC- */
809 cc_neg = (oper_cond & (1 << 11));
810 regulation_changed = (oper_even & (1 << 11)) | regulation_changed;
811 }
812
813 if (regulation_changed) {
b89e6db9 814 if (cv && !cc_pos && !cc_neg && !unreg)
fe4bb774
FS		 815 regulation = "CV";
816 else if (cc_pos && !cv && !cc_neg && !unreg)
817 regulation = "CC";
818 else if (cc_neg && !cv && !cc_pos && !unreg)
819 regulation = "CC-";
820 else if (unreg && !cv && !cc_pos && !cc_neg)
821 regulation = "UR";
b89e6db9
UH		 822 else if (!cv && !cc_pos && !cc_neg && !unreg)
823 /* This happens in case of OCP active. */
fe4bb774
FS		 824 regulation = "";
825 else {
b89e6db9 826 /* This happens from time to time (CV and CC+ active). */
fe4bb774
FS		 827 sr_dbg("Undefined regulation for HP 66xxB "
828 "(CV=%i, CC+=%i, CC-=%i, UR=%i).",
829 cv, cc_pos, cc_neg, unreg);
830 return FALSE;
831 }
832 sr_session_send_meta(sdi, SR_CONF_REGULATION,
833 g_variant_new_string(regulation));
834 }
835
836 return SR_OK;
837}
838
5433907e
PA		 839/* Owon P4000 series */
840static const uint32_t owon_p4000_devopts[] = {
841 SR_CONF_CONTINUOUS,
842 SR_CONF_LIMIT_SAMPLES | SR_CONF_GET | SR_CONF_SET,
843 SR_CONF_LIMIT_MSEC | SR_CONF_GET | SR_CONF_SET
844};
845
846static const uint32_t owon_p4000_devopts_cg[] = {
847 SR_CONF_ENABLED | SR_CONF_GET | SR_CONF_SET,
848 SR_CONF_VOLTAGE | SR_CONF_GET,
849 SR_CONF_VOLTAGE_TARGET | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
850 SR_CONF_CURRENT | SR_CONF_GET,
851 SR_CONF_CURRENT_LIMIT | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
852 SR_CONF_OVER_VOLTAGE_PROTECTION_THRESHOLD | SR_CONF_GET | SR_CONF_SET,
853 SR_CONF_OVER_CURRENT_PROTECTION_THRESHOLD | SR_CONF_GET | SR_CONF_SET,
854};
855
856static const struct channel_spec owon_p4603_ch[] = {
857 { "1", { 0.01, 60, 0.001, 3, 3 }, { 0.001, 3, 0.001, 3, 3 }, { 0, 180, 0, 3, 3 }, FREQ_DC_ONLY, { 0.01, 61, 0.001}, { 0.001, 3.1, 0.001} },
858};
859
860static const struct channel_spec owon_p4305_ch[] = {
861 { "1", { 0.01, 30, 0.001, 3, 3 }, { 0.001, 5, 0.001, 3, 3 }, { 0, 180, 0, 3, 3 }, FREQ_DC_ONLY, { 0.01, 31, 0.001}, { 0.001, 3.1, 0.001} },
862};
863
864static const struct channel_group_spec owon_p4000_cg[] = {
865 { "1", CH_IDX(0), PPS_OVP | PPS_OCP, SR_MQFLAG_DC },
866};
867
868static const struct scpi_command owon_p4000_cmd[] = {
869 { SCPI_CMD_GET_MEAS_VOLTAGE, "MEAS:VOLT?" },
870 { SCPI_CMD_GET_MEAS_CURRENT, "MEAS:CURR?" },
871 { SCPI_CMD_GET_MEAS_POWER, "MEAS:POW?" },
872 { SCPI_CMD_GET_VOLTAGE_TARGET, "VOLT?" },
873 { SCPI_CMD_SET_VOLTAGE_TARGET, "VOLT %.6f" },
874 { SCPI_CMD_GET_CURRENT_LIMIT, "CURR?" },
875 { SCPI_CMD_SET_CURRENT_LIMIT, "CURR %.6f" },
876 { SCPI_CMD_GET_OUTPUT_ENABLED, "OUTP?" },
877 { SCPI_CMD_SET_OUTPUT_ENABLE, "OUTP 1" },
878 { SCPI_CMD_SET_OUTPUT_DISABLE, "OUTP 0" },
879 { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_THRESHOLD, "VOLT:LIM?" },
880 { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_THRESHOLD, "VOLT:LIM %.6f" },
881 { SCPI_CMD_GET_OVER_CURRENT_PROTECTION_THRESHOLD, "CURR:LIM?" },
882 { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_THRESHOLD, "CURR:LIM %.6f" },
883 ALL_ZERO
884};
885
c3eadb07 886/* Philips/Fluke PM2800 series */
9d9cf1c4 887static const uint32_t philips_pm2800_devopts[] = {
e91bb0a6 888 SR_CONF_CONTINUOUS,
88e4daa9
ML		 889 SR_CONF_LIMIT_SAMPLES | SR_CONF_GET | SR_CONF_SET,
890 SR_CONF_LIMIT_MSEC | SR_CONF_GET | SR_CONF_SET,
9d9cf1c4
BV		 891};
892
c3eadb07 893static const uint32_t philips_pm2800_devopts_cg[] = {
7a0b98b5
AJ		 894 SR_CONF_ENABLED | SR_CONF_GET | SR_CONF_SET,
895 SR_CONF_VOLTAGE | SR_CONF_GET,
896 SR_CONF_VOLTAGE_TARGET | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
897 SR_CONF_CURRENT | SR_CONF_GET,
898 SR_CONF_CURRENT_LIMIT | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
c3eadb07
BV		 899 SR_CONF_OVER_VOLTAGE_PROTECTION_ACTIVE | SR_CONF_GET,
900 SR_CONF_OVER_VOLTAGE_PROTECTION_THRESHOLD | SR_CONF_GET | SR_CONF_SET,
901 SR_CONF_OVER_CURRENT_PROTECTION_ENABLED | SR_CONF_GET | SR_CONF_SET,
902 SR_CONF_OVER_CURRENT_PROTECTION_ACTIVE | SR_CONF_GET,
7a0b98b5 903 SR_CONF_REGULATION | SR_CONF_GET,
c3eadb07
BV		 904};
905
906enum philips_pm2800_modules {
907 PM2800_MOD_30V_10A = 1,
908 PM2800_MOD_60V_5A,
909 PM2800_MOD_60V_10A,
910 PM2800_MOD_8V_15A,
911 PM2800_MOD_60V_2A,
912 PM2800_MOD_120V_1A,
913};
914
329733d9 915static const struct philips_pm2800_module_spec {
c3eadb07 916 /* Min, max, programming resolution. */
bcee1299
UH		 917 double voltage[5];
918 double current[5];
919 double power[5];
c3eadb07
BV		 920} philips_pm2800_module_specs[] = {
921 /* Autoranging modules. */
6ed709fe
AJ		 922 [PM2800_MOD_30V_10A] = { { 0, 30, 0.0075, 2, 4 }, { 0, 10, 0.0025, 2, 4 }, { 0, 60 } },
923 [PM2800_MOD_60V_5A] = { { 0, 60, 0.015, 2, 3 }, { 0, 5, 0.00125, 2, 5 }, { 0, 60 } },
924 [PM2800_MOD_60V_10A] = { { 0, 60, 0.015, 2, 3 }, { 0, 10, 0.0025, 2, 5 }, { 0, 120 } },
c3eadb07 925 /* Linear modules. */
6ed709fe
AJ		 926 [PM2800_MOD_8V_15A] = { { 0, 8, 0.002, 3, 3 }, { -15, 15, 0.00375, 3, 5 }, { 0, 120 } },
927 [PM2800_MOD_60V_2A] = { { 0, 60, 0.015, 2, 3 }, { -2, 2, 0.0005, 3, 4 }, { 0, 120 } },
928 [PM2800_MOD_120V_1A] = { { 0, 120, 0.030, 2, 2 }, { -1, 1, 0.00025, 3, 5 }, { 0, 120 } },
c3eadb07
BV		 929};
930
329733d9 931static const struct philips_pm2800_model {
c3eadb07
BV		 932 unsigned int chassis;
933 unsigned int num_modules;
934 unsigned int set;
935 unsigned int modules[3];
936} philips_pm2800_matrix[] = {
937 /* Autoranging chassis. */
938 { 1, 1, 0, { PM2800_MOD_30V_10A, 0, 0 } },
939 { 1, 1, 1, { PM2800_MOD_60V_5A, 0, 0 } },
940 { 1, 2, 0, { PM2800_MOD_30V_10A, PM2800_MOD_30V_10A, 0 } },
941 { 1, 2, 1, { PM2800_MOD_60V_5A, PM2800_MOD_60V_5A, 0 } },
942 { 1, 2, 2, { PM2800_MOD_30V_10A, PM2800_MOD_60V_5A, 0 } },
943 { 1, 2, 3, { PM2800_MOD_30V_10A, PM2800_MOD_60V_10A, 0 } },
944 { 1, 2, 4, { PM2800_MOD_60V_5A, PM2800_MOD_60V_10A, 0 } },
945 { 1, 3, 0, { PM2800_MOD_30V_10A, PM2800_MOD_30V_10A, PM2800_MOD_30V_10A } },
946 { 1, 3, 1, { PM2800_MOD_60V_5A, PM2800_MOD_60V_5A, PM2800_MOD_60V_5A } },
947 { 1, 3, 2, { PM2800_MOD_30V_10A, PM2800_MOD_30V_10A, PM2800_MOD_60V_5A } },
948 { 1, 3, 3, { PM2800_MOD_30V_10A, PM2800_MOD_60V_5A, PM2800_MOD_60V_5A } },
949 /* Linear chassis. */
950 { 3, 1, 0, { PM2800_MOD_60V_2A, 0, 0 } },
951 { 3, 1, 1, { PM2800_MOD_120V_1A, 0, 0 } },
952 { 3, 1, 2, { PM2800_MOD_8V_15A, 0, 0 } },
953 { 3, 2, 0, { PM2800_MOD_60V_2A, 0, 0 } },
954 { 3, 2, 1, { PM2800_MOD_120V_1A, 0, 0 } },
955 { 3, 2, 2, { PM2800_MOD_60V_2A, PM2800_MOD_120V_1A, 0 } },
956 { 3, 2, 3, { PM2800_MOD_8V_15A, PM2800_MOD_8V_15A, 0 } },
957};
958
329733d9 959static const char *philips_pm2800_names[] = { "1", "2", "3" };
c3eadb07
BV		 960
961static int philips_pm2800_probe_channels(struct sr_dev_inst *sdi,
962 struct sr_scpi_hw_info *hw_info,
963 struct channel_spec **channels, unsigned int *num_channels,
964 struct channel_group_spec **channel_groups, unsigned int *num_channel_groups)
965{
329733d9
UH		 966 const struct philips_pm2800_model *model;
967 const struct philips_pm2800_module_spec *spec;
c3eadb07
BV		 968 unsigned int chassis, num_modules, set, module, m, i;
969
970 (void)sdi;
971
972 /*
973 * The model number as reported by *IDN? looks like e.g. PM2813/11,
974 * Where "PM28" is fixed, followed by the chassis code (1 = autoranging,
975 * 3 = linear series) and the number of modules: 1-3 for autoranging,
976 * 1-2 for linear.
977 * After the slash, the first digit denotes the module set. The
978 * digit after that denotes front (5) or rear (1) binding posts.
979 */
980 chassis = hw_info->model[4] - 0x30;
981 num_modules = hw_info->model[5] - 0x30;
982 set = hw_info->model[7] - 0x30;
983 for (m = 0; m < ARRAY_SIZE(philips_pm2800_matrix); m++) {
984 model = &philips_pm2800_matrix[m];
985 if (model->chassis == chassis && model->num_modules == num_modules
986 && model->set == set)
987 break;
988 }
989 if (m == ARRAY_SIZE(philips_pm2800_matrix)) {
990 sr_dbg("Model %s not found in matrix.", hw_info->model);
991 return SR_ERR;
992 }
993
994 sr_dbg("Found %d output channel%s:", num_modules, num_modules > 1 ? "s" : "");
995 *channels = g_malloc0(sizeof(struct channel_spec) * num_modules);
996 *channel_groups = g_malloc0(sizeof(struct channel_group_spec) * num_modules);
997 for (i = 0; i < num_modules; i++) {
998 module = model->modules[i];
999 spec = &philips_pm2800_module_specs[module];
6ed709fe 1000 sr_dbg("output %d: %.0f - %.0fV, %.0f - %.0fA, %.0f - %.0fW", i + 1,
c3eadb07 1001 spec->voltage[0], spec->voltage[1],
6ed709fe 1002 spec->current[0], spec->current[1],
d9251a2c 1003 spec->power[0], spec->power[1]);
329733d9 1004 (*channels)[i].name = (char *)philips_pm2800_names[i];
bcee1299 1005 memcpy(&((*channels)[i].voltage), spec, sizeof(double) * 15);
329733d9 1006 (*channel_groups)[i].name = (char *)philips_pm2800_names[i];
c3eadb07
BV		 1007 (*channel_groups)[i].channel_index_mask = 1 << i;
1008 (*channel_groups)[i].features = PPS_OTP | PPS_OVP | PPS_OCP;
f2bbcc33 1009 (*channel_groups)[i].mqflags = SR_MQFLAG_DC;
c3eadb07
BV		 1010 }
1011 *num_channels = *num_channel_groups = num_modules;
1012
1013 return SR_OK;
1014}
1015
8cb5affe 1016static const struct scpi_command philips_pm2800_cmd[] = {
c3eadb07
BV		 1017 { SCPI_CMD_SELECT_CHANNEL, ":INST:NSEL %s" },
1018 { SCPI_CMD_GET_MEAS_VOLTAGE, ":MEAS:VOLT?" },
1019 { SCPI_CMD_GET_MEAS_CURRENT, ":MEAS:CURR?" },
1020 { SCPI_CMD_GET_VOLTAGE_TARGET, ":SOUR:VOLT?" },
1021 { SCPI_CMD_SET_VOLTAGE_TARGET, ":SOUR:VOLT %.6f" },
1022 { SCPI_CMD_GET_CURRENT_LIMIT, ":SOUR:CURR?" },
1023 { SCPI_CMD_SET_CURRENT_LIMIT, ":SOUR:CURR %.6f" },
1024 { SCPI_CMD_GET_OUTPUT_ENABLED, ":OUTP?" },
1025 { SCPI_CMD_SET_OUTPUT_ENABLE, ":OUTP ON" },
1026 { SCPI_CMD_SET_OUTPUT_DISABLE, ":OUTP OFF" },
1027 { SCPI_CMD_GET_OUTPUT_REGULATION, ":SOUR:FUNC:MODE?" },
1028 { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_ACTIVE, ":SOUR:VOLT:PROT:TRIP?" },
1029 { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_THRESHOLD, ":SOUR:VOLT:PROT:LEV?" },
1030 { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_THRESHOLD, ":SOUR:VOLT:PROT:LEV %.6f" },
1031 { SCPI_CMD_GET_OVER_CURRENT_PROTECTION_ENABLED, ":SOUR:CURR:PROT:STAT?" },
1032 { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_ENABLE, ":SOUR:CURR:PROT:STAT ON" },
1033 { SCPI_CMD_SET_OVER_CURRENT_PROTECTION_DISABLE, ":SOUR:CURR:PROT:STAT OFF" },
1034 { SCPI_CMD_GET_OVER_CURRENT_PROTECTION_ACTIVE, ":SOUR:CURR:PROT:TRIP?" },
91ef511d 1035 ALL_ZERO
c3eadb07
BV		 1036};
1037
81eb36d6
MS		 1038static const uint32_t rs_hmc8043_devopts[] = {
1039 SR_CONF_CONTINUOUS,
88e4daa9
ML		 1040 SR_CONF_LIMIT_SAMPLES | SR_CONF_GET | SR_CONF_SET,
1041 SR_CONF_LIMIT_MSEC | SR_CONF_GET | SR_CONF_SET,
81eb36d6
MS		 1042};
1043
1044static const uint32_t rs_hmc8043_devopts_cg[] = {
1045 SR_CONF_OVER_VOLTAGE_PROTECTION_ENABLED | SR_CONF_GET | SR_CONF_SET,
1046 SR_CONF_OVER_VOLTAGE_PROTECTION_ACTIVE | SR_CONF_GET,
1047 SR_CONF_OVER_VOLTAGE_PROTECTION_THRESHOLD | SR_CONF_GET | SR_CONF_SET,
1048 SR_CONF_VOLTAGE | SR_CONF_GET,
1049 SR_CONF_VOLTAGE_TARGET | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
1050 SR_CONF_CURRENT | SR_CONF_GET,
1051 SR_CONF_CURRENT_LIMIT | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
1052 SR_CONF_ENABLED | SR_CONF_GET | SR_CONF_SET,
1053};
1054
1055static const struct channel_spec rs_hmc8043_ch[] = {
49a468ed
FS		 1056 { "1", { 0, 32.050, 0.001, 3, 4 }, { 0.001, 3, 0.001, 3, 4 }, { 0, 0, 0, 0, 4 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS },
1057 { "2", { 0, 32.050, 0.001, 3, 4 }, { 0.001, 3, 0.001, 3, 4 }, { 0, 0, 0, 0, 4 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS },
1058 { "3", { 0, 32.050, 0.001, 3, 4 }, { 0.001, 3, 0.001, 3, 4 }, { 0, 0, 0, 0, 4 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS },
81eb36d6
MS		 1059};
1060
1061static const struct channel_group_spec rs_hmc8043_cg[] = {
f2bbcc33
FS		 1062 { "1", CH_IDX(0), PPS_OVP, SR_MQFLAG_DC },
1063 { "2", CH_IDX(1), PPS_OVP, SR_MQFLAG_DC },
1064 { "3", CH_IDX(2), PPS_OVP, SR_MQFLAG_DC },
81eb36d6
MS		 1065};
1066
1067static const struct scpi_command rs_hmc8043_cmd[] = {
1068 { SCPI_CMD_SELECT_CHANNEL, "INST:NSEL %s" },
1069 { SCPI_CMD_GET_MEAS_VOLTAGE, "MEAS:VOLT?" },
1070 { SCPI_CMD_GET_MEAS_CURRENT, "MEAS:CURR?" },
1071 { SCPI_CMD_GET_VOLTAGE_TARGET, "VOLT?" },
1072 { SCPI_CMD_SET_VOLTAGE_TARGET, "VOLT %.6f" },
1073 { SCPI_CMD_GET_CURRENT_LIMIT, "CURR?" },
1074 { SCPI_CMD_SET_CURRENT_LIMIT, "CURR %.6f" },
1075 { SCPI_CMD_GET_OUTPUT_ENABLED, "OUTP?" },
1076 { SCPI_CMD_SET_OUTPUT_ENABLE, "OUTP ON" },
1077 { SCPI_CMD_SET_OUTPUT_DISABLE, "OUTP OFF" },
1078 { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_ACTIVE, "VOLT:PROT:TRIP?" },
1079 { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_THRESHOLD, "VOLT:PROT:LEV?" },
1080 { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_THRESHOLD, "VOLT:PROT:LEV %.6f" },
1081 { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_ENABLED, "VOLT:PROT:STAT?" },
1082 { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_ENABLE, "VOLT:PROT:STAT ON" },
1083 { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_DISABLE, "VOLT:PROT:STAT OFF" },
1084 ALL_ZERO
1085};
1086
bd5f0a14
FS		 1087static const uint32_t rs_hmp4040_devopts[] = {
1088 SR_CONF_CONTINUOUS,
1089 SR_CONF_LIMIT_SAMPLES | SR_CONF_GET | SR_CONF_SET,
1090 SR_CONF_LIMIT_MSEC | SR_CONF_GET | SR_CONF_SET,
1091};
1092
1093static const uint32_t rs_hmp4040_devopts_cg[] = {
1094 SR_CONF_OVER_VOLTAGE_PROTECTION_ENABLED | SR_CONF_GET,
1095 SR_CONF_OVER_VOLTAGE_PROTECTION_ACTIVE | SR_CONF_GET,
1096 SR_CONF_OVER_VOLTAGE_PROTECTION_THRESHOLD | SR_CONF_GET | SR_CONF_SET,
1097 SR_CONF_VOLTAGE | SR_CONF_GET,
1098 SR_CONF_VOLTAGE_TARGET | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
1099 SR_CONF_CURRENT | SR_CONF_GET,
1100 SR_CONF_CURRENT_LIMIT | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
1101 SR_CONF_ENABLED | SR_CONF_GET | SR_CONF_SET,
1102 SR_CONF_OVER_TEMPERATURE_PROTECTION_ACTIVE | SR_CONF_GET,
1103 SR_CONF_REGULATION | SR_CONF_GET,
1104};
1105
1c5d5905
GS		 1106static const struct channel_spec rs_hmp2020_ch[] = {
1107 { "1", { 0, 32.050, 0.001, 3, 4 }, { 0.001, 10.01, 0.0002, 3, 4 }, { 0, 0, 0, 0, 4 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS },
1108 { "2", { 0, 32.050, 0.001, 3, 4 }, { 0.001, 5.01, 0.0001, 3, 4 }, { 0, 0, 0, 0, 4 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS },
1109};
1110
1111static const struct channel_spec rs_hmp2030_ch[] = {
1112 { "1", { 0, 32.050, 0.001, 3, 4 }, { 0.001, 5.01, 0.0001, 3, 4 }, { 0, 0, 0, 0, 4 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS },
1113 { "2", { 0, 32.050, 0.001, 3, 4 }, { 0.001, 5.01, 0.0001, 3, 4 }, { 0, 0, 0, 0, 4 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS },
1114 { "3", { 0, 32.050, 0.001, 3, 4 }, { 0.001, 5.01, 0.0001, 3, 4 }, { 0, 0, 0, 0, 4 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS },
1115};
1116
bd5f0a14 1117static const struct channel_spec rs_hmp4040_ch[] = {
7320ce5e
GS		 1118 { "1", { 0, 32.050, 0.001, 3, 4 }, { 0.001, 10.01, 0.0002, 3, 4 }, { 0, 0, 0, 0, 4 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS },
1119 { "2", { 0, 32.050, 0.001, 3, 4 }, { 0.001, 10.01, 0.0002, 3, 4 }, { 0, 0, 0, 0, 4 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS },
1120 { "3", { 0, 32.050, 0.001, 3, 4 }, { 0.001, 10.01, 0.0002, 3, 4 }, { 0, 0, 0, 0, 4 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS },
1121 { "4", { 0, 32.050, 0.001, 3, 4 }, { 0.001, 10.01, 0.0002, 3, 4 }, { 0, 0, 0, 0, 4 }, FREQ_DC_ONLY, NO_OVP_LIMITS, NO_OCP_LIMITS },
bd5f0a14
FS		 1122};
1123
1124static const struct channel_group_spec rs_hmp4040_cg[] = {
1125 { "1", CH_IDX(0), PPS_OVP | PPS_OTP, SR_MQFLAG_DC },
1126 { "2", CH_IDX(1), PPS_OVP | PPS_OTP, SR_MQFLAG_DC },
1127 { "3", CH_IDX(2), PPS_OVP | PPS_OTP, SR_MQFLAG_DC },
1128 { "4", CH_IDX(3), PPS_OVP | PPS_OTP, SR_MQFLAG_DC },
1129};
1130
1131/*
1132 * Developer's note: Currently unused device commands. Some of them
1133 * are not in use because SCPI_CMD codes are not defined yet.
1134 * OUTP:GEN
1135 * VOLT? MAX, CURR? MAX
1136 * VOLT:PROT:CLE (could set SR_CONF_OVER_VOLTAGE_PROTECTION_ACTIVE)
1137 * VOLT:PROT:MODE
1138 * FUSE:STAT, FUSE:TRIP?, FUSE:LINK, FUSE:UNL
1139 * ARB:...
1140 * SYST:LOC, SYST:REM, SYST:RWL, SYST:MIX
1141 * SYST:BEEP:IMM
1142 */
1143static const struct scpi_command rs_hmp4040_cmd[] = {
f403cb9d
GS		 1144 { SCPI_CMD_REMOTE, "SYST:REM" },
1145 { SCPI_CMD_LOCAL, "SYST:LOC" },
bd5f0a14
FS		 1146 { SCPI_CMD_SELECT_CHANNEL, "INST:NSEL %s" },
1147 { SCPI_CMD_GET_MEAS_VOLTAGE, "MEAS:VOLT?" },
1148 { SCPI_CMD_GET_MEAS_CURRENT, "MEAS:CURR?" },
1149 { SCPI_CMD_GET_VOLTAGE_TARGET, "VOLT?" },
1150 { SCPI_CMD_SET_VOLTAGE_TARGET, "VOLT %.6f" },
1151 { SCPI_CMD_GET_CURRENT_LIMIT, "CURR?" },
1152 { SCPI_CMD_SET_CURRENT_LIMIT, "CURR %.6f" },
1153 { SCPI_CMD_GET_OUTPUT_ENABLED, "OUTP?" },
1154 { SCPI_CMD_SET_OUTPUT_ENABLE, "OUTP ON" },
1155 { SCPI_CMD_SET_OUTPUT_DISABLE, "OUTP OFF" },
1156 { SCPI_CMD_GET_OUTPUT_REGULATION, "STAT:QUES:INST:ISUM%s:COND?" },
1157 { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_ACTIVE, "VOLT:PROT:TRIP?" },
1158 { SCPI_CMD_GET_OVER_VOLTAGE_PROTECTION_THRESHOLD, "VOLT:PROT:LEV?" },
1159 { SCPI_CMD_SET_OVER_VOLTAGE_PROTECTION_THRESHOLD, "VOLT:PROT:LEV %.6f" },
1160 { SCPI_CMD_GET_OVER_TEMPERATURE_PROTECTION_ACTIVE, "STAT:QUES:INST:ISUM%s:COND?" },
1161 ALL_ZERO
1162};
1163
d4eabea8 1164SR_PRIV const struct scpi_pps pps_profiles[] = {
6cc93128 1165 /* Agilent N5763A */
5e7377f4 1166 { "Agilent", "N5763A", SCPI_DIALECT_UNKNOWN, 0,
6cc93128
AG		 1167 ARRAY_AND_SIZE(agilent_n5700a_devopts),
1168 ARRAY_AND_SIZE(agilent_n5700a_devopts_cg),
1169 ARRAY_AND_SIZE(agilent_n5763a_ch),
1170 ARRAY_AND_SIZE(agilent_n5700a_cg),
1171 agilent_n5700a_cmd,
1172 .probe_channels = NULL,
fd243315 1173 .init_acquisition = NULL,
7e66bf05 1174 .update_status = NULL,
6cc93128 1175 },
ca314e06 1176
5c9e56c9 1177 /* Agilent N5767A */
5e7377f4 1178 { "Agilent", "N5767A", SCPI_DIALECT_UNKNOWN, 0,
5c9e56c9
AG		 1179 ARRAY_AND_SIZE(agilent_n5700a_devopts),
1180 ARRAY_AND_SIZE(agilent_n5700a_devopts_cg),
1181 ARRAY_AND_SIZE(agilent_n5767a_ch),
6cc93128 1182 ARRAY_AND_SIZE(agilent_n5700a_cg),
91ef511d 1183 agilent_n5700a_cmd,
5c9e56c9 1184 .probe_channels = NULL,
fd243315 1185 .init_acquisition = NULL,
7e66bf05 1186 .update_status = NULL,
5c9e56c9 1187 },
ca314e06 1188
c3bfb959 1189 /* BK Precision 9310 */
5e7377f4 1190 { "BK", "^9130$", SCPI_DIALECT_UNKNOWN, 0,
c3bfb959
MW		 1191 ARRAY_AND_SIZE(bk_9130_devopts),
1192 ARRAY_AND_SIZE(bk_9130_devopts_cg),
1193 ARRAY_AND_SIZE(bk_9130_ch),
1194 ARRAY_AND_SIZE(bk_9130_cg),
1195 bk_9130_cmd,
1196 .probe_channels = NULL,
fd243315 1197 .init_acquisition = NULL,
7e66bf05 1198 .update_status = NULL,
c3bfb959
MW		 1199 },
1200
4ee1e2f3 1201 /* Chroma 61604 */
5e7377f4 1202 { "Chroma", "61604", SCPI_DIALECT_UNKNOWN, 0,
4ee1e2f3
AG		 1203 ARRAY_AND_SIZE(chroma_61604_devopts),
1204 ARRAY_AND_SIZE(chroma_61604_devopts_cg),
1205 ARRAY_AND_SIZE(chroma_61604_ch),
1206 ARRAY_AND_SIZE(chroma_61604_cg),
91ef511d 1207 chroma_61604_cmd,
4ee1e2f3 1208 .probe_channels = NULL,
fd243315 1209 .init_acquisition = NULL,
7e66bf05 1210 .update_status = NULL,
4ee1e2f3 1211 },
ca314e06 1212
5281993e 1213 /* Chroma 62000 series */
5e7377f4 1214 { "Chroma", "620[0-9]{2}P-[0-9]{2,3}-[0-9]{1,3}", SCPI_DIALECT_UNKNOWN, 0,
5281993e
AG		 1215 ARRAY_AND_SIZE(chroma_62000_devopts),
1216 ARRAY_AND_SIZE(chroma_62000_devopts_cg),
9a5185c7
AG		 1217 NULL, 0,
1218 NULL, 0,
91ef511d 1219 chroma_62000_cmd,
9a5185c7 1220 .probe_channels = chroma_62000p_probe_channels,
fd243315 1221 .init_acquisition = NULL,
7e66bf05 1222 .update_status = NULL,
5281993e 1223 },
ca314e06 1224
5ce427c7
FS		 1225 /*
1226 * This entry is for testing the HP COMP language with a HP 6632B power
1227 * supply switched to the COMP language ("SYST:LANG COMP"). When used,
1228 * disable the entry for the HP 6632B below!
1229 */
1230 /*
1231 { "HP", "6632B", SCPI_DIALECT_HP_COMP, 0,
1232 ARRAY_AND_SIZE(hp_6630a_devopts),
1233 ARRAY_AND_SIZE(hp_6630a_devopts_cg),
1234 ARRAY_AND_SIZE(hp_6632a_ch),
1235 ARRAY_AND_SIZE(hp_6630a_cg),
1236 hp_6630a_cmd,
1237 .probe_channels = NULL,
fd243315 1238 hp_6630a_init_acquisition,
5ce427c7
FS		 1239 hp_6630a_update_status,
1240 },
1241 */
1242
1243 /* HP 6632A */
1244 { "HP", "6632A", SCPI_DIALECT_HP_COMP, 0,
1245 ARRAY_AND_SIZE(hp_6630a_devopts),
1246 ARRAY_AND_SIZE(hp_6630a_devopts_cg),
1247 ARRAY_AND_SIZE(hp_6632a_ch),
1248 ARRAY_AND_SIZE(hp_6630a_cg),
1249 hp_6630a_cmd,
1250 .probe_channels = NULL,
fd243315 1251 hp_6630a_init_acquisition,
5ce427c7
FS		 1252 hp_6630a_update_status,
1253 },
1254
e76a3575 1255 /* HP 6633A */
5e7377f4 1256 { "HP", "6633A", SCPI_DIALECT_HP_COMP, 0,
e76a3575 1257 ARRAY_AND_SIZE(hp_6630a_devopts),
7c517d02 1258 ARRAY_AND_SIZE(hp_6630a_devopts_cg),
e76a3575 1259 ARRAY_AND_SIZE(hp_6633a_ch),
dbc519f7 1260 ARRAY_AND_SIZE(hp_6630a_cg),
e76a3575
AG		 1261 hp_6630a_cmd,
1262 .probe_channels = NULL,
fd243315 1263 hp_6630a_init_acquisition,
fdf03652 1264 hp_6630a_update_status,
e76a3575
AG		 1265 },
1266
5ce427c7
FS		 1267 /* HP 6634A */
1268 { "HP", "6634A", SCPI_DIALECT_HP_COMP, 0,
1269 ARRAY_AND_SIZE(hp_6630a_devopts),
1270 ARRAY_AND_SIZE(hp_6630a_devopts_cg),
1271 ARRAY_AND_SIZE(hp_6634a_ch),
1272 ARRAY_AND_SIZE(hp_6630a_cg),
1273 hp_6630a_cmd,
1274 .probe_channels = NULL,
fd243315 1275 hp_6630a_init_acquisition,
5ce427c7
FS		 1276 hp_6630a_update_status,
1277 },
1278
1279 /* HP 6611C */
1280 { "HP", "6611C", SCPI_DIALECT_HP_66XXB, PPS_OTP,
1281 ARRAY_AND_SIZE(hp_6630b_devopts),
1282 ARRAY_AND_SIZE(hp_6630b_devopts_cg),
1283 ARRAY_AND_SIZE(hp_6611c_ch),
1284 ARRAY_AND_SIZE(hp_6630b_cg),
1285 hp_6630b_cmd,
1286 .probe_channels = NULL,
fd243315 1287 hp_6630b_init_acquisition,
5ce427c7
FS		 1288 hp_6630b_update_status,
1289 },
1290
1291 /* HP 6612C */
1292 { "HP", "6612C", SCPI_DIALECT_HP_66XXB, PPS_OTP,
1293 ARRAY_AND_SIZE(hp_6630b_devopts),
1294 ARRAY_AND_SIZE(hp_6630b_devopts_cg),
1295 ARRAY_AND_SIZE(hp_6612c_ch),
1296 ARRAY_AND_SIZE(hp_6630b_cg),
1297 hp_6630b_cmd,
1298 .probe_channels = NULL,
fd243315 1299 hp_6630b_init_acquisition,
5ce427c7
FS		 1300 hp_6630b_update_status,
1301 },
1302
1303 /* HP 6613C */
1304 { "HP", "6613C", SCPI_DIALECT_HP_66XXB, PPS_OTP,
1305 ARRAY_AND_SIZE(hp_6630b_devopts),
1306 ARRAY_AND_SIZE(hp_6630b_devopts_cg),
1307 ARRAY_AND_SIZE(hp_6613c_ch),
1308 ARRAY_AND_SIZE(hp_6630b_cg),
1309 hp_6630b_cmd,
1310 .probe_channels = NULL,
fd243315 1311 hp_6630b_init_acquisition,
5ce427c7
FS		 1312 hp_6630b_update_status,
1313 },
1314
1315 /* HP 6614C */
1316 { "HP", "6614C", SCPI_DIALECT_HP_66XXB, PPS_OTP,
1317 ARRAY_AND_SIZE(hp_6630b_devopts),
1318 ARRAY_AND_SIZE(hp_6630b_devopts_cg),
1319 ARRAY_AND_SIZE(hp_6614c_ch),
1320 ARRAY_AND_SIZE(hp_6630b_cg),
1321 hp_6630b_cmd,
1322 .probe_channels = NULL,
fd243315 1323 hp_6630b_init_acquisition,
5ce427c7
FS		 1324 hp_6630b_update_status,
1325 },
1326
a61c8cce 1327 /* HP 6631B */
3d1aa50f 1328 { "HP", "6631B", SCPI_DIALECT_HP_66XXB, PPS_OTP,
a61c8cce
FS		 1329 ARRAY_AND_SIZE(hp_6630b_devopts),
1330 ARRAY_AND_SIZE(hp_6630b_devopts_cg),
1331 ARRAY_AND_SIZE(hp_6631b_ch),
dbc519f7 1332 ARRAY_AND_SIZE(hp_6630b_cg),
a61c8cce
FS		 1333 hp_6630b_cmd,
1334 .probe_channels = NULL,
fd243315 1335 hp_6630b_init_acquisition,
fe4bb774 1336 hp_6630b_update_status,
a61c8cce
FS		 1337 },
1338
bc4a2a46 1339 /* HP 6632B */
3d1aa50f 1340 { "HP", "6632B", SCPI_DIALECT_HP_66XXB, PPS_OTP,
a61c8cce
FS		 1341 ARRAY_AND_SIZE(hp_6630b_devopts),
1342 ARRAY_AND_SIZE(hp_6630b_devopts_cg),
bc4a2a46 1343 ARRAY_AND_SIZE(hp_6632b_ch),
dbc519f7 1344 ARRAY_AND_SIZE(hp_6630b_cg),
a61c8cce
FS		 1345 hp_6630b_cmd,
1346 .probe_channels = NULL,
fd243315 1347 hp_6630b_init_acquisition,
fe4bb774 1348 hp_6630b_update_status,
a61c8cce
FS		 1349 },
1350
0b0f40d8
MW		 1351 /* HP 66312A */
1352 { "HP", "66312A", SCPI_DIALECT_HP_66XXB, PPS_OTP,
1353 ARRAY_AND_SIZE(hp_6630b_devopts),
1354 ARRAY_AND_SIZE(hp_6630b_devopts_cg),
1355 ARRAY_AND_SIZE(hp_66312a_ch),
1356 ARRAY_AND_SIZE(hp_6630b_cg),
1357 hp_6630b_cmd,
1358 .probe_channels = NULL,
1359 hp_6630b_init_acquisition,
1360 hp_6630b_update_status,
1361 },
1362
a61c8cce 1363 /* HP 66332A */
3d1aa50f 1364 { "HP", "66332A", SCPI_DIALECT_HP_66XXB, PPS_OTP,
a61c8cce
FS		 1365 ARRAY_AND_SIZE(hp_6630b_devopts),
1366 ARRAY_AND_SIZE(hp_6630b_devopts_cg),
1367 ARRAY_AND_SIZE(hp_66332a_ch),
dbc519f7 1368 ARRAY_AND_SIZE(hp_6630b_cg),
a61c8cce
FS		 1369 hp_6630b_cmd,
1370 .probe_channels = NULL,
fd243315 1371 hp_6630b_init_acquisition,
fe4bb774 1372 hp_6630b_update_status,
a61c8cce
FS		 1373 },
1374
1375 /* HP 6633B */
3d1aa50f 1376 { "HP", "6633B", SCPI_DIALECT_HP_66XXB, PPS_OTP,
a61c8cce
FS		 1377 ARRAY_AND_SIZE(hp_6630b_devopts),
1378 ARRAY_AND_SIZE(hp_6630b_devopts_cg),
1379 ARRAY_AND_SIZE(hp_6633b_ch),
dbc519f7 1380 ARRAY_AND_SIZE(hp_6630b_cg),
a61c8cce
FS		 1381 hp_6630b_cmd,
1382 .probe_channels = NULL,
fd243315 1383 hp_6630b_init_acquisition,
fe4bb774 1384 hp_6630b_update_status,
a61c8cce
FS		 1385 },
1386
1387 /* HP 6634B */
3d1aa50f 1388 { "HP", "6634B", SCPI_DIALECT_HP_66XXB, PPS_OTP,
a61c8cce
FS		 1389 ARRAY_AND_SIZE(hp_6630b_devopts),
1390 ARRAY_AND_SIZE(hp_6630b_devopts_cg),
1391 ARRAY_AND_SIZE(hp_6634b_ch),
dbc519f7 1392 ARRAY_AND_SIZE(hp_6630b_cg),
a61c8cce 1393 hp_6630b_cmd,
c3eadb07 1394 .probe_channels = NULL,
fd243315 1395 hp_6630b_init_acquisition,
fe4bb774 1396 hp_6630b_update_status,
bc4a2a46
BV		 1397 },
1398
319fe9ce 1399 /* Rigol DP700 series */
5e7377f4 1400 { "Rigol", "^DP711$", SCPI_DIALECT_UNKNOWN, 0,
319fe9ce
UH		 1401 ARRAY_AND_SIZE(rigol_dp700_devopts),
1402 ARRAY_AND_SIZE(rigol_dp700_devopts_cg),
1403 ARRAY_AND_SIZE(rigol_dp711_ch),
1404 ARRAY_AND_SIZE(rigol_dp700_cg),
1405 rigol_dp700_cmd,
1406 .probe_channels = NULL,
fd243315 1407 .init_acquisition = NULL,
7e66bf05 1408 .update_status = NULL,
319fe9ce 1409 },
5e7377f4 1410 { "Rigol", "^DP712$", SCPI_DIALECT_UNKNOWN, 0,
319fe9ce
UH		 1411 ARRAY_AND_SIZE(rigol_dp700_devopts),
1412 ARRAY_AND_SIZE(rigol_dp700_devopts_cg),
1413 ARRAY_AND_SIZE(rigol_dp712_ch),
1414 ARRAY_AND_SIZE(rigol_dp700_cg),
1415 rigol_dp700_cmd,
1416 .probe_channels = NULL,
fd243315 1417 .init_acquisition = NULL,
7e66bf05 1418 .update_status = NULL,
319fe9ce
UH		 1419 },
1420
d4eabea8 1421 /* Rigol DP800 series */
5e7377f4 1422 { "Rigol", "^DP821A$", SCPI_DIALECT_UNKNOWN, PPS_OTP,
cfcdf576
ML		 1423 ARRAY_AND_SIZE(rigol_dp800_devopts),
1424 ARRAY_AND_SIZE(rigol_dp800_devopts_cg),
1425 ARRAY_AND_SIZE(rigol_dp821a_ch),
1426 ARRAY_AND_SIZE(rigol_dp820_cg),
91ef511d 1427 rigol_dp800_cmd,
cfcdf576 1428 .probe_channels = NULL,
fd243315 1429 .init_acquisition = NULL,
7e66bf05 1430 .update_status = NULL,
cfcdf576 1431 },
5e7377f4 1432 { "Rigol", "^DP831A$", SCPI_DIALECT_UNKNOWN, PPS_OTP,
3222ee10
BV		 1433 ARRAY_AND_SIZE(rigol_dp800_devopts),
1434 ARRAY_AND_SIZE(rigol_dp800_devopts_cg),
1435 ARRAY_AND_SIZE(rigol_dp831_ch),
cfcdf576 1436 ARRAY_AND_SIZE(rigol_dp830_cg),
91ef511d 1437 rigol_dp800_cmd,
c3eadb07 1438 .probe_channels = NULL,
fd243315 1439 .init_acquisition = NULL,
7e66bf05 1440 .update_status = NULL,
3222ee10 1441 },
5e7377f4 1442 { "Rigol", "^(DP832|DP832A)$", SCPI_DIALECT_UNKNOWN, PPS_OTP,
3222ee10
BV		 1443 ARRAY_AND_SIZE(rigol_dp800_devopts),
1444 ARRAY_AND_SIZE(rigol_dp800_devopts_cg),
1445 ARRAY_AND_SIZE(rigol_dp832_ch),
cfcdf576 1446 ARRAY_AND_SIZE(rigol_dp830_cg),
91ef511d 1447 rigol_dp800_cmd,
c3eadb07 1448 .probe_channels = NULL,
fd243315 1449 .init_acquisition = NULL,
7e66bf05 1450 .update_status = NULL,
c3eadb07
BV		 1451 },
1452
5433907e
PA		 1453 /* Owon P4000 series */
1454 { "OWON", "^P4305$", SCPI_DIALECT_UNKNOWN, 0,
1455 ARRAY_AND_SIZE(owon_p4000_devopts),
1456 ARRAY_AND_SIZE(owon_p4000_devopts_cg),
1457 ARRAY_AND_SIZE(owon_p4305_ch),
1458 ARRAY_AND_SIZE(owon_p4000_cg),
1459 owon_p4000_cmd,
1460 .probe_channels = NULL,
1461 .init_acquisition = NULL,
1462 .update_status = NULL,
1463 },
1464 { "OWON", "^P4603$", SCPI_DIALECT_UNKNOWN, 0,
1465 ARRAY_AND_SIZE(owon_p4000_devopts),
1466 ARRAY_AND_SIZE(owon_p4000_devopts_cg),
1467 ARRAY_AND_SIZE(owon_p4603_ch),
1468 ARRAY_AND_SIZE(owon_p4000_cg),
1469 owon_p4000_cmd,
1470 .probe_channels = NULL,
1471 .init_acquisition = NULL,
1472 .update_status = NULL,
1473 },
1474
c3eadb07 1475 /* Philips/Fluke PM2800 series */
5e7377f4 1476 { "Philips", "^PM28[13][123]/[01234]{1,2}$", SCPI_DIALECT_PHILIPS, 0,
9d9cf1c4 1477 ARRAY_AND_SIZE(philips_pm2800_devopts),
c3eadb07
BV		 1478 ARRAY_AND_SIZE(philips_pm2800_devopts_cg),
1479 NULL, 0,
1480 NULL, 0,
91ef511d 1481 philips_pm2800_cmd,
c3eadb07 1482 philips_pm2800_probe_channels,
fd243315 1483 .init_acquisition = NULL,
7e66bf05 1484 .update_status = NULL,
d4eabea8 1485 },
81eb36d6
MS		 1486
1487 /* Rohde & Schwarz HMC8043 */
5e7377f4 1488 { "Rohde&Schwarz", "HMC8043", SCPI_DIALECT_UNKNOWN, 0,
81eb36d6
MS		 1489 ARRAY_AND_SIZE(rs_hmc8043_devopts),
1490 ARRAY_AND_SIZE(rs_hmc8043_devopts_cg),
1491 ARRAY_AND_SIZE(rs_hmc8043_ch),
1492 ARRAY_AND_SIZE(rs_hmc8043_cg),
1493 rs_hmc8043_cmd,
1494 .probe_channels = NULL,
fd243315 1495 .init_acquisition = NULL,
7e66bf05 1496 .update_status = NULL,
81eb36d6 1497 },
bd5f0a14
FS		 1498
1499 /* Hameg / Rohde&Schwarz HMP4000 series */
22f76e18
GS		 1500 /* TODO Match on regex, pass scpi_pps item to .probe_channels(). */
1501 { "HAMEG", "HMP4030", SCPI_DIALECT_HMP, 0,
1502 ARRAY_AND_SIZE(rs_hmp4040_devopts),
1503 ARRAY_AND_SIZE(rs_hmp4040_devopts_cg),
1504 rs_hmp4040_ch, 3,
1505 rs_hmp4040_cg, 3,
1506 rs_hmp4040_cmd,
1507 .probe_channels = NULL,
f403cb9d 1508 .init_acquisition = NULL,
22f76e18
GS		 1509 .update_status = NULL,
1510 },
bd5f0a14
FS		 1511 { "HAMEG", "HMP4040", SCPI_DIALECT_HMP, 0,
1512 ARRAY_AND_SIZE(rs_hmp4040_devopts),
1513 ARRAY_AND_SIZE(rs_hmp4040_devopts_cg),
1514 ARRAY_AND_SIZE(rs_hmp4040_ch),
1515 ARRAY_AND_SIZE(rs_hmp4040_cg),
1516 rs_hmp4040_cmd,
1517 .probe_channels = NULL,
f403cb9d 1518 .init_acquisition = NULL,
bd5f0a14
FS		 1519 .update_status = NULL,
1520 },
1c5d5905
GS		 1521 { "ROHDE&SCHWARZ", "HMP2020", SCPI_DIALECT_HMP, 0,
1522 ARRAY_AND_SIZE(rs_hmp4040_devopts),
1523 ARRAY_AND_SIZE(rs_hmp4040_devopts_cg),
1524 rs_hmp2020_ch, 2,
1525 rs_hmp4040_cg, 2,
1526 rs_hmp4040_cmd,
1527 .probe_channels = NULL,
1528 .init_acquisition = NULL,
1529 .update_status = NULL,
1530 },
1531 { "ROHDE&SCHWARZ", "HMP2030", SCPI_DIALECT_HMP, 0,
1532 ARRAY_AND_SIZE(rs_hmp4040_devopts),
1533 ARRAY_AND_SIZE(rs_hmp4040_devopts_cg),
1534 rs_hmp2030_ch, 3,
1535 rs_hmp4040_cg, 3,
1536 rs_hmp4040_cmd,
1537 .probe_channels = NULL,
1538 .init_acquisition = NULL,
1539 .update_status = NULL,
1540 },
22f76e18
GS		 1541 { "ROHDE&SCHWARZ", "HMP4030", SCPI_DIALECT_HMP, 0,
1542 ARRAY_AND_SIZE(rs_hmp4040_devopts),
1543 ARRAY_AND_SIZE(rs_hmp4040_devopts_cg),
1544 rs_hmp4040_ch, 3,
1545 rs_hmp4040_cg, 3,
1546 rs_hmp4040_cmd,
1547 .probe_channels = NULL,
f403cb9d 1548 .init_acquisition = NULL,
22f76e18
GS		 1549 .update_status = NULL,
1550 },
1551 { "ROHDE&SCHWARZ", "HMP4040", SCPI_DIALECT_HMP, 0,
1552 ARRAY_AND_SIZE(rs_hmp4040_devopts),
1553 ARRAY_AND_SIZE(rs_hmp4040_devopts_cg),
1554 ARRAY_AND_SIZE(rs_hmp4040_ch),
1555 ARRAY_AND_SIZE(rs_hmp4040_cg),
1556 rs_hmp4040_cmd,
1557 .probe_channels = NULL,
f403cb9d 1558 .init_acquisition = NULL,
22f76e18
GS		 1559 .update_status = NULL,
1560 },
d4eabea8 1561};
d4eabea8 1562
1beccaed 1563SR_PRIV unsigned int num_pps_profiles = ARRAY_SIZE(pps_profiles);
Hardware access and backend lib