]>
Commit | Line | Data |
---|---|---|
f2cd2deb FS |
1 | /* |
2 | * This file is part of the libsigrok project. | |
3 | * | |
7047acc8 | 4 | * Copyright (C) 2022 Gerhard Sittig <gerhard.sittig@gmx.net> |
f2cd2deb FS |
5 | * Copyright (C) 2020 Florian Schmidt <schmidt_florian@gmx.de> |
6 | * Copyright (C) 2013 Marcus Comstedt <marcus@mc.pp.se> | |
7 | * Copyright (C) 2013 Bert Vermeulen <bert@biot.com> | |
8 | * Copyright (C) 2012 Joel Holdsworth <joel@airwebreathe.org.uk> | |
9 | * | |
10 | * This program is free software: you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License as published by | |
12 | * the Free Software Foundation, either version 3 of the License, or | |
13 | * (at your option) any later version. | |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, | |
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | * GNU General Public License for more details. | |
19 | * | |
20 | * You should have received a copy of the GNU General Public License | |
21 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
22 | */ | |
23 | ||
24 | #include <config.h> | |
a7740b06 | 25 | |
f2cd2deb | 26 | #include <libsigrok/libsigrok.h> |
a7740b06 GS |
27 | #include <string.h> |
28 | ||
f2cd2deb FS |
29 | #include "libsigrok-internal.h" |
30 | #include "protocol.h" | |
31 | ||
d466f61c GS |
32 | /* USB PID dependent MCU firmware. Model dependent FPGA bitstream. */ |
33 | #define MCU_FWFILE_FMT "kingst-la-%04x.fw" | |
34 | #define FPGA_FWFILE_FMT "kingst-%s-fpga.bitstream" | |
35 | ||
36 | /* | |
69320ad3 | 37 | * List of known devices and their features. See @ref kingst_model |
d466f61c | 38 | * for the fields' type and meaning. Table is sorted by EEPROM magic. |
69320ad3 GS |
39 | * More specific items need to go first (additional byte[2/6]). Not |
40 | * all devices are covered by this driver implementation, but telling | |
41 | * users what was detected is considered useful. | |
d466f61c | 42 | * |
69320ad3 | 43 | * TODO Verify the identification of models that were not tested before. |
d466f61c GS |
44 | */ |
45 | static const struct kingst_model models[] = { | |
f49837a5 GS |
46 | { 0x02, 0x01, "LA2016", "la2016a1", SR_MHZ(200), 16, 1, 0, }, |
47 | { 0x02, 0x00, "LA2016", "la2016", SR_MHZ(200), 16, 1, 0, }, | |
48 | { 0x03, 0x01, "LA1016", "la1016a1", SR_MHZ(100), 16, 1, 0, }, | |
49 | { 0x03, 0x00, "LA1016", "la1016", SR_MHZ(100), 16, 1, 0, }, | |
50 | { 0x04, 0x00, "LA1010", "la1010a0", SR_MHZ(100), 16, 0, SR_MHZ(800), }, | |
51 | { 0x05, 0x00, "LA5016", "la5016a1", SR_MHZ(500), 16, 2, SR_MHZ(800), }, | |
52 | { 0x06, 0x00, "LA5032", "la5032a0", SR_MHZ(500), 32, 4, SR_MHZ(800), }, | |
53 | { 0x07, 0x00, "LA1010", "la1010a1", SR_MHZ(100), 16, 0, SR_MHZ(800), }, | |
54 | { 0x08, 0x00, "LA2016", "la2016a1", SR_MHZ(200), 16, 1, 0, }, | |
55 | { 0x09, 0x00, "LA1016", "la1016a1", SR_MHZ(100), 16, 1, 0, }, | |
56 | { 0x0a, 0x00, "LA1010", "la1010a2", SR_MHZ(100), 16, 0, SR_MHZ(800), }, | |
1776a197 GS |
57 | { 0x0c, 0x10, "LA5016", "la5016a2", SR_MHZ(500), 16, 2, SR_MHZ(800), }, |
58 | { 0x0c, 0x00, "LA5016", "la5016a2", SR_MHZ(500), 16, 2, SR_MHZ(800), }, | |
f49837a5 | 59 | { 0x41, 0x00, "LA5016", "la5016a1", SR_MHZ(500), 16, 2, SR_MHZ(800), }, |
d466f61c | 60 | }; |
f2cd2deb | 61 | |
96dc954e | 62 | /* USB vendor class control requests, executed by the Cypress FX2 MCU. */ |
84fe94bd | 63 | #define CMD_FPGA_ENABLE 0x10 |
96dc954e GS |
64 | #define CMD_FPGA_SPI 0x20 /* R/W access to FPGA registers via SPI. */ |
65 | #define CMD_BULK_START 0x30 /* Start sample data download via USB EP6 IN. */ | |
66 | #define CMD_BULK_RESET 0x38 /* Flush FIFO of FX2 USB EP6 IN. */ | |
67 | #define CMD_FPGA_INIT 0x50 /* Used before and after FPGA bitstream upload. */ | |
68 | #define CMD_KAUTH 0x60 /* Communicate to auth IC (U10). Not used. */ | |
69 | #define CMD_EEPROM 0xa2 /* R/W access to EEPROM content. */ | |
00849545 | 70 | |
42f6dd55 | 71 | /* |
96dc954e GS |
72 | * FPGA register addresses (base addresses when registers span multiple |
73 | * bytes, in that case data is kept in little endian format). Passed to | |
74 | * CMD_FPGA_SPI requests. The FX2 MCU transparently handles the detail | |
75 | * of SPI transfers encoding the read (1) or write (0) direction in the | |
76 | * MSB of the address field. There are some 60 byte-wide FPGA registers. | |
d6f89d4b GS |
77 | * |
78 | * Unfortunately the FPGA registers change their meaning between the | |
79 | * read and write directions of access, or exclusively provide one of | |
80 | * these directions and not the other. This is an arbitrary vendor's | |
81 | * choice, there is nothing which the sigrok driver could do about it. | |
82 | * Values written to registers typically cannot get read back, neither | |
83 | * verified after writing a configuration, nor queried upon startup for | |
84 | * automatic detection of the current configuration. Neither appear to | |
85 | * be there echo registers for presence and communication checks, nor | |
86 | * version identifying registers, as far as we know. | |
42f6dd55 | 87 | */ |
96dc954e GS |
88 | #define REG_RUN 0x00 /* Read capture status, write start capture. */ |
89 | #define REG_PWM_EN 0x02 /* User PWM channels on/off. */ | |
90 | #define REG_CAPT_MODE 0x03 /* Write 0x00 capture to SDRAM, 0x01 streaming. */ | |
c8aa9206 | 91 | #define REG_PIN_STATE 0x04 /* Read current pin state (real time display). */ |
96dc954e GS |
92 | #define REG_BULK 0x08 /* Write start addr, byte count to download samples. */ |
93 | #define REG_SAMPLING 0x10 /* Write capture config, read capture SDRAM location. */ | |
3ab60908 GS |
94 | #define REG_TRIGGER 0x20 /* Write level and edge trigger config. */ |
95 | #define REG_UNKNOWN_30 0x30 | |
96dc954e GS |
96 | #define REG_THRESHOLD 0x68 /* Write PWM config to setup input threshold DAC. */ |
97 | #define REG_PWM1 0x70 /* Write config for user PWM1. */ | |
98 | #define REG_PWM2 0x78 /* Write config for user PWM2. */ | |
f2cd2deb | 99 | |
972d191b GS |
100 | /* Bit patterns to write to REG_CAPT_MODE. */ |
101 | #define CAPTMODE_TO_RAM 0x00 | |
102 | #define CAPTMODE_STREAM 0x01 | |
103 | ||
852c7d14 GS |
104 | /* Bit patterns to write to REG_RUN, setup run mode. */ |
105 | #define RUNMODE_HALT 0x00 | |
106 | #define RUNMODE_RUN 0x03 | |
107 | ||
b711fd8e GS |
108 | /* Bit patterns when reading from REG_RUN, get run state. */ |
109 | #define RUNSTATE_IDLE_BIT (1UL << 0) | |
110 | #define RUNSTATE_DRAM_BIT (1UL << 1) | |
111 | #define RUNSTATE_TRGD_BIT (1UL << 2) | |
112 | #define RUNSTATE_POST_BIT (1UL << 3) | |
113 | ||
f2cd2deb | 114 | static int ctrl_in(const struct sr_dev_inst *sdi, |
1ed93110 GS |
115 | uint8_t bRequest, uint16_t wValue, uint16_t wIndex, |
116 | void *data, uint16_t wLength) | |
f2cd2deb FS |
117 | { |
118 | struct sr_usb_dev_inst *usb; | |
119 | int ret; | |
120 | ||
121 | usb = sdi->conn; | |
122 | ||
411ad77c GS |
123 | ret = libusb_control_transfer(usb->devhdl, |
124 | LIBUSB_REQUEST_TYPE_VENDOR | LIBUSB_ENDPOINT_IN, | |
125 | bRequest, wValue, wIndex, data, wLength, | |
126 | DEFAULT_TIMEOUT_MS); | |
127 | if (ret != wLength) { | |
91f73872 GS |
128 | sr_dbg("USB ctrl in: %d bytes, req %d val %#x idx %d: %s.", |
129 | wLength, bRequest, wValue, wIndex, | |
130 | libusb_error_name(ret)); | |
131 | sr_err("Cannot read %d bytes from USB: %s.", | |
132 | wLength, libusb_error_name(ret)); | |
286b3e13 | 133 | return SR_ERR_IO; |
f2cd2deb FS |
134 | } |
135 | ||
136 | return SR_OK; | |
137 | } | |
138 | ||
139 | static int ctrl_out(const struct sr_dev_inst *sdi, | |
1ed93110 GS |
140 | uint8_t bRequest, uint16_t wValue, uint16_t wIndex, |
141 | void *data, uint16_t wLength) | |
f2cd2deb FS |
142 | { |
143 | struct sr_usb_dev_inst *usb; | |
144 | int ret; | |
145 | ||
146 | usb = sdi->conn; | |
147 | ||
411ad77c GS |
148 | ret = libusb_control_transfer(usb->devhdl, |
149 | LIBUSB_REQUEST_TYPE_VENDOR | LIBUSB_ENDPOINT_OUT, | |
150 | bRequest, wValue, wIndex, data, wLength, | |
151 | DEFAULT_TIMEOUT_MS); | |
152 | if (ret != wLength) { | |
91f73872 GS |
153 | sr_dbg("USB ctrl out: %d bytes, req %d val %#x idx %d: %s.", |
154 | wLength, bRequest, wValue, wIndex, | |
155 | libusb_error_name(ret)); | |
156 | sr_err("Cannot write %d bytes to USB: %s.", | |
157 | wLength, libusb_error_name(ret)); | |
286b3e13 | 158 | return SR_ERR_IO; |
f2cd2deb FS |
159 | } |
160 | ||
161 | return SR_OK; | |
162 | } | |
163 | ||
33020165 GS |
164 | /* HACK Experiment to spot FPGA registers of interest. */ |
165 | static void la2016_dump_fpga_registers(const struct sr_dev_inst *sdi, | |
166 | const char *caption, size_t reg_lower, size_t reg_upper) | |
167 | { | |
168 | static const size_t dump_chunk_len = 16; | |
169 | ||
170 | size_t rdlen; | |
171 | uint8_t rdbuf[0x80 - 0x00]; /* Span all FPGA registers. */ | |
172 | const uint8_t *rdptr; | |
173 | int ret; | |
174 | size_t dump_addr, indent, dump_len; | |
175 | GString *txt; | |
176 | ||
177 | if (sr_log_loglevel_get() < SR_LOG_SPEW) | |
178 | return; | |
179 | ||
180 | if (!reg_lower && !reg_upper) { | |
181 | reg_lower = 0; | |
182 | reg_upper = sizeof(rdbuf); | |
183 | } | |
184 | if (reg_upper - reg_lower > sizeof(rdbuf)) | |
185 | reg_upper = sizeof(rdbuf) - reg_lower; | |
186 | ||
187 | rdlen = reg_upper - reg_lower; | |
188 | ret = ctrl_in(sdi, CMD_FPGA_SPI, reg_lower, 0, rdbuf, rdlen); | |
189 | if (ret != SR_OK) { | |
190 | sr_err("Cannot get registers space."); | |
191 | return; | |
192 | } | |
193 | rdptr = rdbuf; | |
194 | ||
195 | sr_spew("FPGA registers dump: %s", caption ? : "for fun"); | |
196 | dump_addr = reg_lower; | |
197 | while (rdlen) { | |
198 | dump_len = rdlen; | |
199 | indent = dump_addr % dump_chunk_len; | |
200 | if (dump_len > dump_chunk_len) | |
201 | dump_len = dump_chunk_len; | |
202 | if (dump_len + indent > dump_chunk_len) | |
203 | dump_len = dump_chunk_len - indent; | |
204 | txt = sr_hexdump_new(rdptr, dump_len); | |
205 | sr_spew(" %04zx %*s%s", | |
206 | dump_addr, (int)(3 * indent), "", txt->str); | |
207 | sr_hexdump_free(txt); | |
208 | dump_addr += dump_len; | |
209 | rdptr += dump_len; | |
210 | rdlen -= dump_len; | |
211 | } | |
212 | } | |
213 | ||
d6f89d4b GS |
214 | /* |
215 | * Check the necessity for FPGA bitstream upload, because another upload | |
216 | * would take some 600ms which is undesirable after program startup. Try | |
217 | * to access some FPGA registers and check the values' plausibility. The | |
218 | * check should fail on the safe side, request another upload when in | |
219 | * doubt. A positive response (the request to continue operation with the | |
220 | * currently active bitstream) should be conservative. Accessing multiple | |
221 | * registers is considered cheap compared to the cost of bitstream upload. | |
222 | * | |
223 | * It helps though that both the vendor software and the sigrok driver | |
224 | * use the same bundle of MCU firmware and FPGA bitstream for any of the | |
225 | * supported models. We don't expect to successfully communicate to the | |
226 | * device yet disagree on its protocol. Ideally we would access version | |
227 | * identifying registers for improved robustness, but are not aware of | |
228 | * any. A bitstream reload can always be forced by a power cycle. | |
229 | */ | |
230 | static int check_fpga_bitstream(const struct sr_dev_inst *sdi) | |
231 | { | |
232 | uint8_t init_rsp; | |
3ab60908 | 233 | uint8_t buff[REG_PWM_EN - REG_RUN]; /* Larger of REG_RUN, REG_PWM_EN. */ |
d6f89d4b GS |
234 | int ret; |
235 | uint16_t run_state; | |
236 | uint8_t pwm_en; | |
237 | size_t read_len; | |
d6f89d4b GS |
238 | const uint8_t *rdptr; |
239 | ||
240 | sr_dbg("Checking operation of the FPGA bitstream."); | |
33020165 | 241 | la2016_dump_fpga_registers(sdi, "bitstream check", 0, 0); |
d6f89d4b | 242 | |
852c7d14 | 243 | init_rsp = ~0; |
d6f89d4b GS |
244 | ret = ctrl_in(sdi, CMD_FPGA_INIT, 0x00, 0, &init_rsp, sizeof(init_rsp)); |
245 | if (ret != SR_OK || init_rsp != 0) { | |
246 | sr_dbg("FPGA init query failed, or unexpected response."); | |
247 | return SR_ERR_IO; | |
248 | } | |
249 | ||
250 | read_len = sizeof(run_state); | |
251 | ret = ctrl_in(sdi, CMD_FPGA_SPI, REG_RUN, 0, buff, read_len); | |
252 | if (ret != SR_OK) { | |
253 | sr_dbg("FPGA register access failed (run state)."); | |
254 | return SR_ERR_IO; | |
255 | } | |
256 | rdptr = buff; | |
257 | run_state = read_u16le_inc(&rdptr); | |
258 | sr_spew("FPGA register: run state 0x%04x.", run_state); | |
259 | if (run_state && (run_state & 0x3) != 0x1) { | |
260 | sr_dbg("Unexpected FPGA register content (run state)."); | |
261 | return SR_ERR_DATA; | |
262 | } | |
263 | if (run_state && (run_state & ~0xf) != 0x85e0) { | |
264 | sr_dbg("Unexpected FPGA register content (run state)."); | |
265 | return SR_ERR_DATA; | |
266 | } | |
267 | ||
268 | read_len = sizeof(pwm_en); | |
269 | ret = ctrl_in(sdi, CMD_FPGA_SPI, REG_PWM_EN, 0, buff, read_len); | |
270 | if (ret != SR_OK) { | |
271 | sr_dbg("FPGA register access failed (PWM enable)."); | |
272 | return SR_ERR_IO; | |
273 | } | |
274 | rdptr = buff; | |
275 | pwm_en = read_u8_inc(&rdptr); | |
276 | sr_spew("FPGA register: PWM enable 0x%02x.", pwm_en); | |
277 | if ((pwm_en & 0x3) != 0x0) { | |
278 | sr_dbg("Unexpected FPGA register content (PWM enable)."); | |
279 | return SR_ERR_DATA; | |
280 | } | |
281 | ||
282 | sr_info("Could re-use current FPGA bitstream. No upload required."); | |
283 | return SR_OK; | |
284 | } | |
285 | ||
1ed93110 GS |
286 | static int upload_fpga_bitstream(const struct sr_dev_inst *sdi, |
287 | const char *bitstream_fname) | |
f2cd2deb FS |
288 | { |
289 | struct drv_context *drvc; | |
290 | struct sr_usb_dev_inst *usb; | |
291 | struct sr_resource bitstream; | |
b0d0131e | 292 | uint32_t bitstream_size; |
c3d40037 HK |
293 | uint8_t buffer[sizeof(uint32_t)]; |
294 | uint8_t *wrptr; | |
f2cd2deb | 295 | uint8_t block[4096]; |
3f48ab02 FS |
296 | int len, act_len; |
297 | unsigned int pos; | |
f2cd2deb | 298 | int ret; |
b0d0131e | 299 | unsigned int zero_pad_to; |
f2cd2deb FS |
300 | |
301 | drvc = sdi->driver->context; | |
302 | usb = sdi->conn; | |
303 | ||
9de389b1 | 304 | sr_info("Uploading FPGA bitstream '%s'.", bitstream_fname); |
f2cd2deb | 305 | |
411ad77c GS |
306 | ret = sr_resource_open(drvc->sr_ctx, &bitstream, |
307 | SR_RESOURCE_FIRMWARE, bitstream_fname); | |
f2cd2deb | 308 | if (ret != SR_OK) { |
91f73872 | 309 | sr_err("Cannot find FPGA bitstream %s.", bitstream_fname); |
f2cd2deb FS |
310 | return ret; |
311 | } | |
312 | ||
b0d0131e | 313 | bitstream_size = (uint32_t)bitstream.size; |
c3d40037 | 314 | wrptr = buffer; |
b0d0131e | 315 | write_u32le_inc(&wrptr, bitstream_size); |
411ad77c GS |
316 | ret = ctrl_out(sdi, CMD_FPGA_INIT, 0x00, 0, buffer, wrptr - buffer); |
317 | if (ret != SR_OK) { | |
91f73872 | 318 | sr_err("Cannot initiate FPGA bitstream upload."); |
f2cd2deb FS |
319 | sr_resource_close(drvc->sr_ctx, &bitstream); |
320 | return ret; | |
321 | } | |
b0d0131e GS |
322 | zero_pad_to = bitstream_size; |
323 | zero_pad_to += LA2016_EP2_PADDING - 1; | |
324 | zero_pad_to /= LA2016_EP2_PADDING; | |
325 | zero_pad_to *= LA2016_EP2_PADDING; | |
f2cd2deb FS |
326 | |
327 | pos = 0; | |
328 | while (1) { | |
3f48ab02 | 329 | if (pos < bitstream.size) { |
411ad77c GS |
330 | len = (int)sr_resource_read(drvc->sr_ctx, &bitstream, |
331 | block, sizeof(block)); | |
3f48ab02 | 332 | if (len < 0) { |
91f73872 | 333 | sr_err("Cannot read FPGA bitstream."); |
3f48ab02 | 334 | sr_resource_close(drvc->sr_ctx, &bitstream); |
286b3e13 | 335 | return SR_ERR_IO; |
3f48ab02 FS |
336 | } |
337 | } else { | |
96dc954e | 338 | /* Zero-pad until 'zero_pad_to'. */ |
3f48ab02 FS |
339 | len = zero_pad_to - pos; |
340 | if ((unsigned)len > sizeof(block)) | |
341 | len = sizeof(block); | |
342 | memset(&block, 0, len); | |
f2cd2deb FS |
343 | } |
344 | if (len == 0) | |
345 | break; | |
346 | ||
852c7d14 | 347 | ret = libusb_bulk_transfer(usb->devhdl, USB_EP_FPGA_BITSTREAM, |
1ed93110 | 348 | &block[0], len, &act_len, DEFAULT_TIMEOUT_MS); |
f2cd2deb | 349 | if (ret != 0) { |
91f73872 GS |
350 | sr_dbg("Cannot write FPGA bitstream, block %#x len %d: %s.", |
351 | pos, (int)len, libusb_error_name(ret)); | |
286b3e13 | 352 | ret = SR_ERR_IO; |
f2cd2deb FS |
353 | break; |
354 | } | |
355 | if (act_len != len) { | |
91f73872 GS |
356 | sr_dbg("Short write for FPGA bitstream, block %#x len %d: got %d.", |
357 | pos, (int)len, act_len); | |
286b3e13 | 358 | ret = SR_ERR_IO; |
f2cd2deb FS |
359 | break; |
360 | } | |
361 | pos += len; | |
362 | } | |
363 | sr_resource_close(drvc->sr_ctx, &bitstream); | |
5eb1b63d | 364 | if (ret != SR_OK) |
f2cd2deb | 365 | return ret; |
91f73872 GS |
366 | sr_info("FPGA bitstream upload (%" PRIu64 " bytes) done.", |
367 | bitstream.size); | |
f2cd2deb | 368 | |
d6f89d4b GS |
369 | return SR_OK; |
370 | } | |
371 | ||
372 | static int enable_fpga_bitstream(const struct sr_dev_inst *sdi) | |
373 | { | |
374 | int ret; | |
411ad77c | 375 | uint8_t resp; |
d6f89d4b | 376 | |
411ad77c GS |
377 | ret = ctrl_in(sdi, CMD_FPGA_INIT, 0x00, 0, &resp, sizeof(resp)); |
378 | if (ret != SR_OK) { | |
91f73872 | 379 | sr_err("Cannot read response after FPGA bitstream upload."); |
f2cd2deb FS |
380 | return ret; |
381 | } | |
411ad77c | 382 | if (resp != 0) { |
91f73872 | 383 | sr_err("Unexpected FPGA bitstream upload response, got 0x%02x, want 0.", |
411ad77c | 384 | resp); |
286b3e13 | 385 | return SR_ERR_DATA; |
3f48ab02 | 386 | } |
852c7d14 | 387 | g_usleep(30 * 1000); |
f2cd2deb | 388 | |
411ad77c GS |
389 | ret = ctrl_out(sdi, CMD_FPGA_ENABLE, 0x01, 0, NULL, 0); |
390 | if (ret != SR_OK) { | |
91f73872 | 391 | sr_err("Cannot enable FPGA after bitstream upload."); |
f2cd2deb FS |
392 | return ret; |
393 | } | |
852c7d14 | 394 | g_usleep(40 * 1000); |
d6f89d4b | 395 | |
f2cd2deb FS |
396 | return SR_OK; |
397 | } | |
398 | ||
399 | static int set_threshold_voltage(const struct sr_dev_inst *sdi, float voltage) | |
400 | { | |
f2cd2deb | 401 | int ret; |
1ed93110 | 402 | uint16_t duty_R79, duty_R56; |
3ab60908 | 403 | uint8_t buf[REG_PWM1 - REG_THRESHOLD]; /* Width of REG_THRESHOLD. */ |
f2ad79d1 KG |
404 | uint8_t *wrptr; |
405 | ||
96dc954e | 406 | /* Clamp threshold setting to valid range for LA2016. */ |
c35baf6e GS |
407 | if (voltage > LA2016_THR_VOLTAGE_MAX) { |
408 | voltage = LA2016_THR_VOLTAGE_MAX; | |
409 | } else if (voltage < -LA2016_THR_VOLTAGE_MAX) { | |
410 | voltage = -LA2016_THR_VOLTAGE_MAX; | |
f2ad79d1 KG |
411 | } |
412 | ||
413 | /* | |
96dc954e GS |
414 | * Two PWM output channels feed one DAC which generates a bias |
415 | * voltage, which offsets the input probe's voltage level, and | |
416 | * in combination with the FPGA pins' fixed threshold result in | |
417 | * a programmable input threshold from the user's perspective. | |
418 | * The PWM outputs can be seen on R79 and R56 respectively, the | |
419 | * frequency is 100kHz and the duty cycle varies. The R79 PWM | |
420 | * uses three discrete settings. The R56 PWM varies with desired | |
421 | * thresholds and depends on the R79 PWM configuration. See the | |
422 | * schematics comments which discuss the formulae. | |
f2ad79d1 KG |
423 | */ |
424 | if (voltage >= 2.9) { | |
96dc954e | 425 | duty_R79 = 0; /* PWM off (0V). */ |
f2ad79d1 | 426 | duty_R56 = (uint16_t)(302 * voltage - 363); |
c34f4a89 | 427 | } else if (voltage > -0.4) { |
96dc954e | 428 | duty_R79 = 0x00f2; /* 25% duty cycle. */ |
f2ad79d1 | 429 | duty_R56 = (uint16_t)(302 * voltage + 121); |
c34f4a89 GS |
430 | } else { |
431 | duty_R79 = 0x02d7; /* 72% duty cycle. */ | |
432 | duty_R56 = (uint16_t)(302 * voltage + 1090); | |
f2ad79d1 KG |
433 | } |
434 | ||
96dc954e | 435 | /* Clamp duty register values to sensible limits. */ |
f2ad79d1 KG |
436 | if (duty_R56 < 10) { |
437 | duty_R56 = 10; | |
1ed93110 | 438 | } else if (duty_R56 > 1100) { |
f2ad79d1 KG |
439 | duty_R56 = 1100; |
440 | } | |
441 | ||
91f73872 GS |
442 | sr_dbg("Set threshold voltage %.2fV.", voltage); |
443 | sr_dbg("Duty cycle values: R56 0x%04x, R79 0x%04x.", duty_R56, duty_R79); | |
f2ad79d1 KG |
444 | |
445 | wrptr = buf; | |
446 | write_u16le_inc(&wrptr, duty_R56); | |
447 | write_u16le_inc(&wrptr, duty_R79); | |
448 | ||
449 | ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_THRESHOLD, 0, buf, wrptr - buf); | |
f2cd2deb | 450 | if (ret != SR_OK) { |
91f73872 | 451 | sr_err("Cannot set threshold voltage %.2fV.", voltage); |
f2cd2deb FS |
452 | return ret; |
453 | } | |
f2cd2deb FS |
454 | |
455 | return SR_OK; | |
456 | } | |
457 | ||
08a49848 GS |
458 | /* |
459 | * Communicates a channel's configuration to the device after the | |
460 | * parameters may have changed. Configuration of one channel may | |
461 | * interfere with other channels since they share FPGA registers. | |
462 | */ | |
463 | static int set_pwm_config(const struct sr_dev_inst *sdi, size_t idx) | |
f2cd2deb | 464 | { |
08a49848 | 465 | static uint8_t reg_bases[] = { REG_PWM1, REG_PWM2, }; |
86d77b75 | 466 | |
f2cd2deb | 467 | struct dev_context *devc; |
08a49848 GS |
468 | struct pwm_setting *params; |
469 | uint8_t reg_base; | |
470 | double val_f; | |
471 | uint32_t val_u; | |
472 | uint32_t period, duty; | |
473 | size_t ch; | |
f2cd2deb | 474 | int ret; |
08a49848 GS |
475 | uint8_t enable_all, enable_cfg, reg_val; |
476 | uint8_t buf[REG_PWM2 - REG_PWM1]; /* Width of one REG_PWMx. */ | |
c3d40037 | 477 | uint8_t *wrptr; |
f2cd2deb FS |
478 | |
479 | devc = sdi->priv; | |
08a49848 GS |
480 | if (idx >= ARRAY_SIZE(devc->pwm_setting)) |
481 | return SR_ERR_ARG; | |
482 | params = &devc->pwm_setting[idx]; | |
483 | if (idx >= ARRAY_SIZE(reg_bases)) | |
484 | return SR_ERR_ARG; | |
485 | reg_base = reg_bases[idx]; | |
f2cd2deb | 486 | |
08a49848 GS |
487 | /* |
488 | * Map application's specs to hardware register values. Do math | |
489 | * in floating point initially, but convert to u32 eventually. | |
490 | */ | |
491 | sr_dbg("PWM config, app spec, ch %zu, en %d, freq %.1f, duty %.1f.", | |
492 | idx, params->enabled ? 1 : 0, params->freq, params->duty); | |
493 | val_f = PWM_CLOCK; | |
494 | val_f /= params->freq; | |
495 | val_u = val_f; | |
496 | period = val_u; | |
497 | val_f = period; | |
498 | val_f *= params->duty; | |
499 | val_f /= 100.0; | |
500 | val_f += 0.5; | |
501 | val_u = val_f; | |
502 | duty = val_u; | |
503 | sr_dbg("PWM config, reg 0x%04x, freq %u, duty %u.", | |
504 | (unsigned)reg_base, (unsigned)period, (unsigned)duty); | |
505 | ||
506 | /* Get the "enabled" state of all supported PWM channels. */ | |
507 | enable_all = 0; | |
508 | for (ch = 0; ch < ARRAY_SIZE(devc->pwm_setting); ch++) { | |
509 | if (!devc->pwm_setting[ch].enabled) | |
510 | continue; | |
511 | enable_all |= 1U << ch; | |
f2cd2deb | 512 | } |
08a49848 GS |
513 | enable_cfg = 1U << idx; |
514 | sr_spew("PWM config, enable all 0x%02hhx, cfg 0x%02hhx.", | |
515 | enable_all, enable_cfg); | |
f2cd2deb | 516 | |
08a49848 GS |
517 | /* |
518 | * Disable the to-get-configured channel before its parameters | |
519 | * will change. Or disable and exit when the channel is supposed | |
520 | * to get turned off. | |
521 | */ | |
522 | sr_spew("PWM config, disabling before param change."); | |
523 | reg_val = enable_all & ~enable_cfg; | |
524 | ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_PWM_EN, 0, | |
525 | ®_val, sizeof(reg_val)); | |
f2cd2deb | 526 | if (ret != SR_OK) { |
08a49848 | 527 | sr_err("Cannot adjust PWM enabled state."); |
f2cd2deb FS |
528 | return ret; |
529 | } | |
08a49848 GS |
530 | if (!params->enabled) |
531 | return SR_OK; | |
86d77b75 | 532 | |
08a49848 GS |
533 | /* Write register values to device. */ |
534 | sr_spew("PWM config, sending new parameters."); | |
535 | wrptr = buf; | |
536 | write_u32le_inc(&wrptr, period); | |
537 | write_u32le_inc(&wrptr, duty); | |
538 | ret = ctrl_out(sdi, CMD_FPGA_SPI, reg_base, 0, buf, wrptr - buf); | |
539 | if (ret != SR_OK) { | |
540 | sr_err("Cannot change PWM parameters."); | |
f2cd2deb | 541 | return ret; |
08a49848 | 542 | } |
f2cd2deb | 543 | |
08a49848 GS |
544 | /* Enable configured channel after write completion. */ |
545 | sr_spew("PWM config, enabling after param change."); | |
546 | reg_val = enable_all | enable_cfg; | |
547 | ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_PWM_EN, 0, | |
548 | ®_val, sizeof(reg_val)); | |
549 | if (ret != SR_OK) { | |
550 | sr_err("Cannot adjust PWM enabled state."); | |
f2cd2deb | 551 | return ret; |
08a49848 | 552 | } |
f2cd2deb FS |
553 | |
554 | return SR_OK; | |
555 | } | |
556 | ||
0fbb464b GS |
557 | /* |
558 | * Determine the number of enabled channels as well as their bitmask | |
559 | * representation. Derive data here which later simplifies processing | |
560 | * of raw capture data memory content in streaming mode. | |
561 | */ | |
562 | static void la2016_prepare_stream(const struct sr_dev_inst *sdi) | |
ea436ba7 | 563 | { |
0fbb464b GS |
564 | struct dev_context *devc; |
565 | struct stream_state_t *stream; | |
566 | size_t channel_mask; | |
ea436ba7 GS |
567 | GSList *l; |
568 | struct sr_channel *ch; | |
569 | ||
0fbb464b GS |
570 | devc = sdi->priv; |
571 | stream = &devc->stream; | |
572 | memset(stream, 0, sizeof(*stream)); | |
573 | ||
574 | stream->enabled_count = 0; | |
ea436ba7 GS |
575 | for (l = sdi->channels; l; l = l->next) { |
576 | ch = l->data; | |
577 | if (ch->type != SR_CHANNEL_LOGIC) | |
578 | continue; | |
579 | if (!ch->enabled) | |
580 | continue; | |
0fbb464b GS |
581 | channel_mask = 1UL << ch->index; |
582 | stream->enabled_mask |= channel_mask; | |
583 | stream->channel_masks[stream->enabled_count++] = channel_mask; | |
ea436ba7 | 584 | } |
0fbb464b | 585 | stream->channel_index = 0; |
ea436ba7 GS |
586 | } |
587 | ||
0fbb464b GS |
588 | /* |
589 | * This routine configures the set of enabled channels, as well as the | |
590 | * trigger condition (if one was specified). Also prepares the capture | |
591 | * data processing in stream mode, where the memory layout dramatically | |
592 | * differs from normal mode. | |
593 | */ | |
f2cd2deb FS |
594 | static int set_trigger_config(const struct sr_dev_inst *sdi) |
595 | { | |
596 | struct dev_context *devc; | |
597 | struct sr_trigger *trigger; | |
edb13f41 | 598 | struct trigger_cfg { |
972d191b GS |
599 | uint32_t channels; /* Actually: Enabled channels? */ |
600 | uint32_t enabled; /* Actually: Triggering channels? */ | |
edb13f41 GS |
601 | uint32_t level; |
602 | uint32_t high_or_falling; | |
603 | } cfg; | |
f2cd2deb FS |
604 | GSList *stages; |
605 | GSList *channel; | |
606 | struct sr_trigger_stage *stage1; | |
607 | struct sr_trigger_match *match; | |
4276ca94 | 608 | uint32_t ch_mask; |
f2cd2deb | 609 | int ret; |
3ab60908 | 610 | uint8_t buf[REG_UNKNOWN_30 - REG_TRIGGER]; /* Width of REG_TRIGGER. */ |
c3d40037 | 611 | uint8_t *wrptr; |
f2cd2deb FS |
612 | |
613 | devc = sdi->priv; | |
f2cd2deb | 614 | |
0fbb464b | 615 | la2016_prepare_stream(sdi); |
f2cd2deb | 616 | |
0fbb464b GS |
617 | memset(&cfg, 0, sizeof(cfg)); |
618 | cfg.channels = devc->stream.enabled_mask; | |
619 | if (!cfg.channels) { | |
620 | sr_err("Need at least one enabled logic channel."); | |
621 | return SR_ERR_ARG; | |
622 | } | |
623 | trigger = sr_session_trigger_get(sdi->session); | |
f2cd2deb FS |
624 | if (trigger && trigger->stages) { |
625 | stages = trigger->stages; | |
626 | stage1 = stages->data; | |
627 | if (stages->next) { | |
628 | sr_err("Only one trigger stage supported for now."); | |
286b3e13 | 629 | return SR_ERR_ARG; |
f2cd2deb FS |
630 | } |
631 | channel = stage1->matches; | |
632 | while (channel) { | |
633 | match = channel->data; | |
cf057ac4 | 634 | ch_mask = 1UL << match->channel->index; |
f2cd2deb FS |
635 | |
636 | switch (match->match) { | |
637 | case SR_TRIGGER_ZERO: | |
638 | cfg.level |= ch_mask; | |
639 | cfg.high_or_falling &= ~ch_mask; | |
640 | break; | |
641 | case SR_TRIGGER_ONE: | |
642 | cfg.level |= ch_mask; | |
643 | cfg.high_or_falling |= ch_mask; | |
644 | break; | |
645 | case SR_TRIGGER_RISING: | |
646 | if ((cfg.enabled & ~cfg.level)) { | |
91f73872 | 647 | sr_err("Device only supports one edge trigger."); |
286b3e13 | 648 | return SR_ERR_ARG; |
f2cd2deb FS |
649 | } |
650 | cfg.level &= ~ch_mask; | |
651 | cfg.high_or_falling &= ~ch_mask; | |
652 | break; | |
653 | case SR_TRIGGER_FALLING: | |
654 | if ((cfg.enabled & ~cfg.level)) { | |
91f73872 | 655 | sr_err("Device only supports one edge trigger."); |
286b3e13 | 656 | return SR_ERR_ARG; |
f2cd2deb FS |
657 | } |
658 | cfg.level &= ~ch_mask; | |
659 | cfg.high_or_falling |= ch_mask; | |
660 | break; | |
661 | default: | |
91f73872 | 662 | sr_err("Unknown trigger condition."); |
286b3e13 | 663 | return SR_ERR_ARG; |
f2cd2deb FS |
664 | } |
665 | cfg.enabled |= ch_mask; | |
666 | channel = channel->next; | |
667 | } | |
668 | } | |
91f73872 | 669 | sr_dbg("Set trigger config: " |
972d191b | 670 | "enabled-channels 0x%04x, triggering-channels 0x%04x, " |
91f73872 GS |
671 | "level-triggered 0x%04x, high/falling 0x%04x.", |
672 | cfg.channels, cfg.enabled, cfg.level, cfg.high_or_falling); | |
f2cd2deb | 673 | |
0fbb464b GS |
674 | /* |
675 | * Don't configure hardware trigger parameters in streaming mode | |
676 | * or when the device lacks local memory. Yet the above dump of | |
677 | * derived parameters from user specs is considered valueable. | |
678 | * | |
679 | * TODO Add support for soft triggers when hardware triggers in | |
680 | * the device are not used or are not available at all. | |
681 | */ | |
682 | if (!devc->model->memory_bits || devc->continuous) { | |
683 | if (!devc->model->memory_bits) | |
684 | sr_dbg("Device without memory. No hardware triggers."); | |
685 | else if (devc->continuous) | |
686 | sr_dbg("Streaming mode. No hardware triggers."); | |
687 | cfg.enabled = 0; | |
688 | cfg.level = 0; | |
689 | cfg.high_or_falling = 0; | |
690 | } | |
691 | ||
cf057ac4 | 692 | devc->trigger_involved = cfg.enabled != 0; |
f2cd2deb | 693 | |
c3d40037 HK |
694 | wrptr = buf; |
695 | write_u32le_inc(&wrptr, cfg.channels); | |
696 | write_u32le_inc(&wrptr, cfg.enabled); | |
697 | write_u32le_inc(&wrptr, cfg.level); | |
698 | write_u32le_inc(&wrptr, cfg.high_or_falling); | |
852c7d14 GS |
699 | /* TODO |
700 | * Comment on this literal 16. Origin, meaning? Cannot be the | |
701 | * register offset, nor the transfer length. Is it a channels | |
702 | * count that is relevant for 16 and 32 channel models? Is it | |
703 | * an obsolete experiment? | |
704 | */ | |
42f6dd55 | 705 | ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_TRIGGER, 16, buf, wrptr - buf); |
f2cd2deb | 706 | if (ret != SR_OK) { |
91f73872 | 707 | sr_err("Cannot setup trigger configuration."); |
f2cd2deb FS |
708 | return ret; |
709 | } | |
710 | ||
711 | return SR_OK; | |
712 | } | |
713 | ||
0fbb464b GS |
714 | /* |
715 | * This routine communicates the sample configuration to the device: | |
716 | * Total samples count and samplerate, pre-trigger configuration. | |
717 | */ | |
f2cd2deb FS |
718 | static int set_sample_config(const struct sr_dev_inst *sdi) |
719 | { | |
720 | struct dev_context *devc; | |
40a0db1e | 721 | uint64_t baseclock; |
d8fbfcd9 | 722 | uint64_t min_samplerate, eff_samplerate; |
0fbb464b | 723 | uint64_t stream_bandwidth; |
adab4d91 | 724 | uint16_t divider_u16; |
a38f0f5e | 725 | uint64_t limit_samples; |
adab4d91 GS |
726 | uint64_t pre_trigger_samples; |
727 | uint64_t pre_trigger_memory; | |
728 | uint8_t buf[REG_TRIGGER - REG_SAMPLING]; /* Width of REG_SAMPLING. */ | |
c3d40037 | 729 | uint8_t *wrptr; |
adab4d91 | 730 | int ret; |
f2cd2deb FS |
731 | |
732 | devc = sdi->priv; | |
f2cd2deb | 733 | |
cafcfe63 GS |
734 | /* |
735 | * The base clock need not be identical to the maximum samplerate, | |
736 | * and differs between models. The 500MHz devices even use a base | |
737 | * clock of 800MHz, and communicate divider 1 to the hardware to | |
738 | * configure the 500MHz samplerate. This allows them to operate at | |
739 | * a 200MHz samplerate which uses divider 4. | |
740 | */ | |
edc0b015 | 741 | if (devc->samplerate > devc->model->samplerate) { |
91f73872 | 742 | sr_err("Too high a sample rate: %" PRIu64 ".", |
edc0b015 | 743 | devc->samplerate); |
ea436ba7 GS |
744 | return SR_ERR_ARG; |
745 | } | |
40a0db1e GS |
746 | baseclock = devc->model->baseclock; |
747 | if (!baseclock) | |
748 | baseclock = devc->model->samplerate; | |
749 | min_samplerate = baseclock; | |
d8fbfcd9 | 750 | min_samplerate /= 65536; |
edc0b015 | 751 | if (devc->samplerate < min_samplerate) { |
ea436ba7 | 752 | sr_err("Too low a sample rate: %" PRIu64 ".", |
edc0b015 | 753 | devc->samplerate); |
ea436ba7 | 754 | return SR_ERR_ARG; |
f2cd2deb | 755 | } |
40a0db1e GS |
756 | divider_u16 = baseclock / devc->samplerate; |
757 | eff_samplerate = baseclock / divider_u16; | |
cafcfe63 GS |
758 | if (eff_samplerate > devc->model->samplerate) |
759 | eff_samplerate = devc->model->samplerate; | |
f2cd2deb | 760 | |
a38f0f5e GS |
761 | ret = sr_sw_limits_get_remain(&devc->sw_limits, |
762 | &limit_samples, NULL, NULL, NULL); | |
763 | if (ret != SR_OK) { | |
764 | sr_err("Cannot get acquisition limits."); | |
765 | return ret; | |
f2cd2deb | 766 | } |
a38f0f5e | 767 | if (limit_samples > LA2016_NUM_SAMPLES_MAX) { |
d8fbfcd9 GS |
768 | sr_warn("Too high a sample depth: %" PRIu64 ", capping.", |
769 | limit_samples); | |
770 | limit_samples = LA2016_NUM_SAMPLES_MAX; | |
a38f0f5e | 771 | } |
d8fbfcd9 GS |
772 | if (limit_samples == 0) { |
773 | limit_samples = LA2016_NUM_SAMPLES_MAX; | |
774 | sr_dbg("Passing %" PRIu64 " to HW for unlimited samples.", | |
775 | limit_samples); | |
ea436ba7 | 776 | } |
f2cd2deb | 777 | |
adab4d91 GS |
778 | /* |
779 | * The acquisition configuration communicates "pre-trigger" | |
780 | * specs in several formats. sigrok users provide a percentage | |
781 | * (0-100%), which translates to a pre-trigger samples count | |
782 | * (assuming that a total samples count limit was specified). | |
783 | * The device supports hardware compression, which depends on | |
784 | * slowly changing input data to be effective. Fast changing | |
785 | * input data may occupy more space in sample memory than its | |
786 | * uncompressed form would. This is why a third parameter can | |
787 | * limit the amount of sample memory to use for pre-trigger | |
788 | * data. Only the upper 24 bits of that memory size spec get | |
789 | * communicated to the device (written to its FPGA register). | |
790 | */ | |
0fbb464b GS |
791 | if (!devc->model->memory_bits) { |
792 | sr_dbg("Memory-less device, skipping pre-trigger config."); | |
793 | pre_trigger_samples = 0; | |
794 | pre_trigger_memory = 0; | |
795 | } else if (devc->trigger_involved) { | |
d8fbfcd9 GS |
796 | pre_trigger_samples = limit_samples; |
797 | pre_trigger_samples *= devc->capture_ratio; | |
798 | pre_trigger_samples /= 100; | |
799 | pre_trigger_memory = devc->model->memory_bits; | |
800 | pre_trigger_memory *= UINT64_C(1024 * 1024 * 1024); | |
801 | pre_trigger_memory /= 8; /* devc->model->channel_count ? */ | |
802 | pre_trigger_memory *= devc->capture_ratio; | |
803 | pre_trigger_memory /= 100; | |
804 | } else { | |
805 | sr_dbg("No trigger setup, skipping pre-trigger config."); | |
0fbb464b | 806 | pre_trigger_samples = 0; |
d8fbfcd9 GS |
807 | pre_trigger_memory = 0; |
808 | } | |
809 | /* Ensure non-zero value after LSB shift out in HW reg. */ | |
0fbb464b | 810 | if (pre_trigger_memory < 0x100) |
d8fbfcd9 | 811 | pre_trigger_memory = 0x100; |
f2cd2deb | 812 | |
0fbb464b GS |
813 | sr_dbg("Set sample config: %" PRIu64 "kHz (div %" PRIu16 "), %" PRIu64 " samples.", |
814 | eff_samplerate / SR_KHZ(1), divider_u16, limit_samples); | |
adab4d91 GS |
815 | sr_dbg("Capture ratio %" PRIu64 "%%, count %" PRIu64 ", mem %" PRIu64 ".", |
816 | devc->capture_ratio, pre_trigger_samples, pre_trigger_memory); | |
f2cd2deb | 817 | |
0fbb464b GS |
818 | if (devc->continuous) { |
819 | stream_bandwidth = eff_samplerate; | |
820 | stream_bandwidth *= devc->stream.enabled_count; | |
821 | sr_dbg("Streaming: channel count %zu, product %" PRIu64 ".", | |
822 | devc->stream.enabled_count, stream_bandwidth); | |
823 | stream_bandwidth /= 1000 * 1000; | |
824 | if (stream_bandwidth >= LA2016_STREAM_MBPS_MAX) { | |
825 | sr_warn("High USB stream bandwidth: %" PRIu64 "Mbps.", | |
826 | stream_bandwidth); | |
827 | } | |
828 | if (stream_bandwidth < LA2016_STREAM_PUSH_THR) { | |
829 | sr_dbg("Streaming: low Mbps, suggest periodic flush."); | |
830 | devc->stream.flush_period_ms = LA2016_STREAM_PUSH_IVAL; | |
831 | } | |
832 | } | |
833 | ||
b1a17c1a GS |
834 | /* |
835 | * The acquisition configuration occupies a total of 16 bytes: | |
836 | * - A 34bit total samples count limit (up to 10 billions) that | |
837 | * is kept in a 40bit register. | |
838 | * - A 34bit pre-trigger samples count limit (up to 10 billions) | |
839 | * in another 40bit register. | |
840 | * - A 32bit pre-trigger memory space limit (in bytes) of which | |
841 | * the upper 24bits are kept in an FPGA register. | |
842 | * - A 16bit clock divider which gets applied to the maximum | |
843 | * samplerate of the device. | |
844 | * - An 8bit register of unknown meaning. Currently always 0. | |
845 | */ | |
c3d40037 | 846 | wrptr = buf; |
a38f0f5e | 847 | write_u40le_inc(&wrptr, limit_samples); |
b1a17c1a GS |
848 | write_u40le_inc(&wrptr, pre_trigger_samples); |
849 | write_u24le_inc(&wrptr, pre_trigger_memory >> 8); | |
adab4d91 | 850 | write_u16le_inc(&wrptr, divider_u16); |
0d8e1ffc | 851 | write_u8_inc(&wrptr, 0); |
42f6dd55 | 852 | ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_SAMPLING, 0, buf, wrptr - buf); |
f2cd2deb | 853 | if (ret != SR_OK) { |
91f73872 | 854 | sr_err("Cannot setup acquisition configuration."); |
f2cd2deb FS |
855 | return ret; |
856 | } | |
857 | ||
858 | return SR_OK; | |
859 | } | |
860 | ||
96dc954e GS |
861 | /* |
862 | * FPGA register REG_RUN holds the run state (u16le format). Bit fields | |
863 | * of interest: | |
864 | * bit 0: value 1 = idle | |
865 | * bit 1: value 1 = writing to SDRAM | |
866 | * bit 2: value 0 = waiting for trigger, 1 = trigger seen | |
867 | * bit 3: value 0 = pretrigger sampling, 1 = posttrigger sampling | |
868 | * The meaning of other bit fields is unknown. | |
7601dca7 | 869 | * |
96dc954e | 870 | * Typical values in order of appearance during execution: |
b711fd8e GS |
871 | * 0x85e1: idle, no acquisition pending |
872 | * IDLE set, TRGD don't care, POST don't care; DRAM don't care | |
873 | * "In idle state." Takes precedence over all others. | |
96dc954e GS |
874 | * 0x85e2: pre-sampling, samples before the trigger position, |
875 | * when capture ratio > 0% | |
b711fd8e GS |
876 | * IDLE clear, TRGD clear, POST clear; DRAM don't care |
877 | * "Not idle any more, no post yet, not triggered yet." | |
96dc954e GS |
878 | * 0x85ea: pre-sampling complete, now waiting for the trigger |
879 | * (whilst sampling continuously) | |
b711fd8e GS |
880 | * IDLE clear, TRGD clear, POST set; DRAM don't care |
881 | * "Post set thus after pre, not triggered yet" | |
96dc954e | 882 | * 0x85ee: trigger seen, capturing post-trigger samples, running |
b711fd8e GS |
883 | * IDLE clear, TRGD set, POST set; DRAM don't care |
884 | * "Triggered and in post, not idle yet." | |
96dc954e | 885 | * 0x85ed: idle |
b711fd8e GS |
886 | * IDLE set, TRGD don't care, POST don't care; DRAM don't care |
887 | * "In idle state." TRGD/POST don't care, same meaning as above. | |
f2cd2deb | 888 | */ |
b711fd8e GS |
889 | static const uint16_t runstate_mask_idle = RUNSTATE_IDLE_BIT; |
890 | static const uint16_t runstate_patt_idle = RUNSTATE_IDLE_BIT; | |
891 | static const uint16_t runstate_mask_step = | |
892 | RUNSTATE_IDLE_BIT | RUNSTATE_TRGD_BIT | RUNSTATE_POST_BIT; | |
893 | static const uint16_t runstate_patt_pre_trig = 0; | |
894 | static const uint16_t runstate_patt_wait_trig = RUNSTATE_POST_BIT; | |
895 | static const uint16_t runstate_patt_post_trig = | |
896 | RUNSTATE_TRGD_BIT | RUNSTATE_POST_BIT; | |
897 | ||
f2cd2deb FS |
898 | static uint16_t run_state(const struct sr_dev_inst *sdi) |
899 | { | |
21d68fd9 GS |
900 | static uint16_t previous_state; |
901 | ||
f2cd2deb | 902 | int ret; |
21d68fd9 | 903 | uint16_t state; |
3ab60908 | 904 | uint8_t buff[REG_PWM_EN - REG_RUN]; /* Width of REG_RUN. */ |
21d68fd9 GS |
905 | const uint8_t *rdptr; |
906 | const char *label; | |
f2cd2deb | 907 | |
411ad77c GS |
908 | ret = ctrl_in(sdi, CMD_FPGA_SPI, REG_RUN, 0, buff, sizeof(state)); |
909 | if (ret != SR_OK) { | |
91f73872 | 910 | sr_err("Cannot read run state."); |
f2cd2deb FS |
911 | return ret; |
912 | } | |
21d68fd9 GS |
913 | rdptr = buff; |
914 | state = read_u16le_inc(&rdptr); | |
7601dca7 | 915 | |
96dc954e GS |
916 | /* |
917 | * Avoid flooding the log, only dump values as they change. | |
918 | * The routine is called about every 50ms. | |
7601dca7 | 919 | */ |
b711fd8e GS |
920 | if (state == previous_state) |
921 | return state; | |
922 | ||
923 | previous_state = state; | |
924 | label = NULL; | |
925 | if ((state & runstate_mask_idle) == runstate_patt_idle) | |
926 | label = "idle"; | |
927 | if ((state & runstate_mask_step) == runstate_patt_pre_trig) | |
928 | label = "pre-trigger sampling"; | |
929 | if ((state & runstate_mask_step) == runstate_patt_wait_trig) | |
930 | label = "sampling, waiting for trigger"; | |
931 | if ((state & runstate_mask_step) == runstate_patt_post_trig) | |
932 | label = "post-trigger sampling"; | |
933 | if (label && *label) | |
934 | sr_dbg("Run state: 0x%04x (%s).", state, label); | |
935 | else | |
936 | sr_dbg("Run state: 0x%04x.", state); | |
f2cd2deb FS |
937 | |
938 | return state; | |
939 | } | |
940 | ||
7a38cdf7 | 941 | static gboolean la2016_is_idle(const struct sr_dev_inst *sdi) |
c34f4a89 GS |
942 | { |
943 | uint16_t state; | |
944 | ||
945 | state = run_state(sdi); | |
b711fd8e | 946 | if ((state & runstate_mask_idle) == runstate_patt_idle) |
7a38cdf7 | 947 | return TRUE; |
c34f4a89 | 948 | |
7a38cdf7 | 949 | return FALSE; |
c34f4a89 GS |
950 | } |
951 | ||
952 | static int set_run_mode(const struct sr_dev_inst *sdi, uint8_t mode) | |
f2cd2deb FS |
953 | { |
954 | int ret; | |
955 | ||
411ad77c GS |
956 | ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_RUN, 0, &mode, sizeof(mode)); |
957 | if (ret != SR_OK) { | |
c34f4a89 | 958 | sr_err("Cannot configure run mode %d.", mode); |
f2cd2deb FS |
959 | return ret; |
960 | } | |
961 | ||
962 | return SR_OK; | |
963 | } | |
964 | ||
965 | static int get_capture_info(const struct sr_dev_inst *sdi) | |
966 | { | |
967 | struct dev_context *devc; | |
968 | int ret; | |
3ab60908 | 969 | uint8_t buf[REG_TRIGGER - REG_SAMPLING]; /* Width of REG_SAMPLING. */ |
c3d40037 | 970 | const uint8_t *rdptr; |
f2cd2deb FS |
971 | |
972 | devc = sdi->priv; | |
973 | ||
411ad77c GS |
974 | ret = ctrl_in(sdi, CMD_FPGA_SPI, REG_SAMPLING, 0, buf, sizeof(buf)); |
975 | if (ret != SR_OK) { | |
91f73872 | 976 | sr_err("Cannot read capture info."); |
f2cd2deb FS |
977 | return ret; |
978 | } | |
c3d40037 HK |
979 | |
980 | rdptr = buf; | |
981 | devc->info.n_rep_packets = read_u32le_inc(&rdptr); | |
982 | devc->info.n_rep_packets_before_trigger = read_u32le_inc(&rdptr); | |
983 | devc->info.write_pos = read_u32le_inc(&rdptr); | |
f2cd2deb | 984 | |
cf057ac4 | 985 | sr_dbg("Capture info: n_rep_packets: 0x%08x/%d, before_trigger: 0x%08x/%d, write_pos: 0x%08x/%d.", |
1ed93110 GS |
986 | devc->info.n_rep_packets, devc->info.n_rep_packets, |
987 | devc->info.n_rep_packets_before_trigger, | |
988 | devc->info.n_rep_packets_before_trigger, | |
989 | devc->info.write_pos, devc->info.write_pos); | |
f2cd2deb | 990 | |
038e65c1 GS |
991 | if (devc->info.n_rep_packets % devc->packets_per_chunk) { |
992 | sr_warn("Unexpected packets count %lu, not a multiple of %lu.", | |
852c7d14 | 993 | (unsigned long)devc->info.n_rep_packets, |
038e65c1 | 994 | (unsigned long)devc->packets_per_chunk); |
91f73872 | 995 | } |
f2cd2deb FS |
996 | |
997 | return SR_OK; | |
998 | } | |
999 | ||
d466f61c | 1000 | SR_PRIV int la2016_upload_firmware(const struct sr_dev_inst *sdi, |
91aa0f04 | 1001 | struct sr_context *sr_ctx, libusb_device *dev, gboolean skip_upload) |
f2cd2deb | 1002 | { |
d466f61c | 1003 | struct dev_context *devc; |
91aa0f04 GS |
1004 | uint16_t pid; |
1005 | char *fw; | |
d466f61c GS |
1006 | int ret; |
1007 | ||
1008 | devc = sdi ? sdi->priv : NULL; | |
91aa0f04 GS |
1009 | if (!devc || !devc->usb_pid) |
1010 | return SR_ERR_ARG; | |
1011 | pid = devc->usb_pid; | |
d466f61c | 1012 | |
91aa0f04 GS |
1013 | fw = g_strdup_printf(MCU_FWFILE_FMT, pid); |
1014 | sr_info("USB PID %04hx, MCU firmware '%s'.", pid, fw); | |
1015 | devc->mcu_firmware = g_strdup(fw); | |
d466f61c | 1016 | |
91aa0f04 GS |
1017 | if (skip_upload) |
1018 | ret = SR_OK; | |
1019 | else | |
1020 | ret = ezusb_upload_firmware(sr_ctx, dev, USB_CONFIGURATION, fw); | |
1021 | g_free(fw); | |
1022 | if (ret != SR_OK) | |
d466f61c | 1023 | return ret; |
d466f61c GS |
1024 | |
1025 | return SR_OK; | |
f2cd2deb FS |
1026 | } |
1027 | ||
1291ea43 GS |
1028 | static void LIBUSB_CALL receive_transfer(struct libusb_transfer *xfer); |
1029 | ||
796ce0bf GS |
1030 | static void la2016_usbxfer_release_cb(gpointer p) |
1031 | { | |
1032 | struct libusb_transfer *xfer; | |
1033 | ||
1034 | xfer = p; | |
1035 | g_free(xfer->buffer); | |
1036 | libusb_free_transfer(xfer); | |
1037 | } | |
1038 | ||
1291ea43 GS |
1039 | static int la2016_usbxfer_release(const struct sr_dev_inst *sdi) |
1040 | { | |
1041 | struct dev_context *devc; | |
1291ea43 GS |
1042 | |
1043 | devc = sdi ? sdi->priv : NULL; | |
1044 | if (!devc) | |
1045 | return SR_ERR_ARG; | |
1046 | ||
1047 | /* Release all USB transfers. */ | |
796ce0bf GS |
1048 | g_slist_free_full(devc->transfers, la2016_usbxfer_release_cb); |
1049 | devc->transfers = NULL; | |
1291ea43 GS |
1050 | |
1051 | return SR_OK; | |
1052 | } | |
1053 | ||
1054 | static int la2016_usbxfer_allocate(const struct sr_dev_inst *sdi) | |
1055 | { | |
1056 | struct dev_context *devc; | |
796ce0bf | 1057 | size_t bufsize, xfercount; |
1291ea43 GS |
1058 | uint8_t *buffer; |
1059 | struct libusb_transfer *xfer; | |
1060 | ||
1061 | devc = sdi ? sdi->priv : NULL; | |
1062 | if (!devc) | |
1063 | return SR_ERR_ARG; | |
1064 | ||
1065 | /* Transfers were already allocated before? */ | |
796ce0bf | 1066 | if (devc->transfers) |
1291ea43 GS |
1067 | return SR_OK; |
1068 | ||
1069 | /* | |
1070 | * Allocate all USB transfers and their buffers. Arrange for a | |
1071 | * buffer size which is within the device's capabilities, and | |
1072 | * is a multiple of the USB endpoint's size, to make use of the | |
1073 | * RAW_IO performance feature. | |
1074 | * | |
1075 | * Implementation detail: The LA2016_USB_BUFSZ value happens | |
1076 | * to match all those constraints. No additional arithmetics is | |
1077 | * required in this location. | |
1078 | */ | |
1079 | bufsize = LA2016_USB_BUFSZ; | |
796ce0bf GS |
1080 | xfercount = LA2016_USB_XFER_COUNT; |
1081 | while (xfercount--) { | |
1082 | buffer = g_try_malloc(bufsize); | |
1083 | if (!buffer) { | |
1084 | sr_err("Cannot allocate USB transfer buffer."); | |
1085 | return SR_ERR_MALLOC; | |
1086 | } | |
1087 | xfer = libusb_alloc_transfer(0); | |
1088 | if (!xfer) { | |
1089 | sr_err("Cannot allocate USB transfer."); | |
1090 | g_free(buffer); | |
1091 | return SR_ERR_MALLOC; | |
1092 | } | |
1093 | xfer->buffer = buffer; | |
1094 | devc->transfers = g_slist_append(devc->transfers, xfer); | |
1291ea43 | 1095 | } |
1291ea43 GS |
1096 | devc->transfer_bufsize = bufsize; |
1097 | ||
1098 | return SR_OK; | |
1099 | } | |
1100 | ||
1101 | static int la2016_usbxfer_cancel_all(const struct sr_dev_inst *sdi) | |
1102 | { | |
1103 | struct dev_context *devc; | |
796ce0bf | 1104 | GSList *l; |
1291ea43 GS |
1105 | struct libusb_transfer *xfer; |
1106 | ||
1107 | devc = sdi ? sdi->priv : NULL; | |
1108 | if (!devc) | |
1109 | return SR_ERR_ARG; | |
1110 | ||
1111 | /* Unconditionally cancel the transfer. Ignore errors. */ | |
796ce0bf GS |
1112 | for (l = devc->transfers; l; l = l->next) { |
1113 | xfer = l->data; | |
1114 | if (!xfer) | |
1115 | continue; | |
1291ea43 | 1116 | libusb_cancel_transfer(xfer); |
796ce0bf | 1117 | } |
1291ea43 GS |
1118 | |
1119 | return SR_OK; | |
1120 | } | |
1121 | ||
1122 | static int la2016_usbxfer_resubmit(const struct sr_dev_inst *sdi, | |
1123 | struct libusb_transfer *xfer) | |
1124 | { | |
1125 | struct dev_context *devc; | |
1126 | struct sr_usb_dev_inst *usb; | |
1127 | libusb_transfer_cb_fn cb; | |
1128 | int ret; | |
1129 | ||
1130 | devc = sdi ? sdi->priv : NULL; | |
1131 | usb = sdi ? sdi->conn : NULL; | |
1132 | if (!devc || !usb) | |
1133 | return SR_ERR_ARG; | |
1134 | ||
1135 | if (!xfer) | |
1136 | return SR_ERR_ARG; | |
1137 | ||
1138 | cb = receive_transfer; | |
1139 | libusb_fill_bulk_transfer(xfer, usb->devhdl, | |
1140 | USB_EP_CAPTURE_DATA | LIBUSB_ENDPOINT_IN, | |
1141 | xfer->buffer, devc->transfer_bufsize, | |
1142 | cb, (void *)sdi, CAPTURE_TIMEOUT_MS); | |
1143 | ret = libusb_submit_transfer(xfer); | |
1144 | if (ret != 0) { | |
1145 | sr_err("Cannot submit USB transfer: %s.", | |
1146 | libusb_error_name(ret)); | |
1147 | return SR_ERR_IO; | |
1148 | } | |
1149 | ||
1150 | return SR_OK; | |
1151 | } | |
1152 | ||
1153 | static int la2016_usbxfer_submit_all(const struct sr_dev_inst *sdi) | |
1154 | { | |
1155 | struct dev_context *devc; | |
796ce0bf GS |
1156 | GSList *l; |
1157 | struct libusb_transfer *xfer; | |
1291ea43 GS |
1158 | int ret; |
1159 | ||
1160 | devc = sdi ? sdi->priv : NULL; | |
1161 | if (!devc) | |
1162 | return SR_ERR_ARG; | |
1163 | ||
796ce0bf GS |
1164 | for (l = devc->transfers; l; l = l->next) { |
1165 | xfer = l->data; | |
1166 | if (!xfer) | |
1167 | return SR_ERR_ARG; | |
1168 | ret = la2016_usbxfer_resubmit(sdi, xfer); | |
1169 | if (ret != SR_OK) | |
1170 | return ret; | |
1171 | } | |
1291ea43 GS |
1172 | |
1173 | return SR_OK; | |
1174 | } | |
1175 | ||
9270f8f4 GS |
1176 | SR_PRIV int la2016_setup_acquisition(const struct sr_dev_inst *sdi, |
1177 | double voltage) | |
f2cd2deb | 1178 | { |
0fbb464b | 1179 | struct dev_context *devc; |
f2cd2deb FS |
1180 | int ret; |
1181 | uint8_t cmd; | |
1182 | ||
0fbb464b GS |
1183 | devc = sdi->priv; |
1184 | ||
9270f8f4 | 1185 | ret = set_threshold_voltage(sdi, voltage); |
f2cd2deb FS |
1186 | if (ret != SR_OK) |
1187 | return ret; | |
1188 | ||
0fbb464b | 1189 | cmd = devc->continuous ? CAPTMODE_STREAM : CAPTMODE_TO_RAM; |
411ad77c GS |
1190 | ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_CAPT_MODE, 0, &cmd, sizeof(cmd)); |
1191 | if (ret != SR_OK) { | |
91f73872 | 1192 | sr_err("Cannot send command to stop sampling."); |
f2cd2deb FS |
1193 | return ret; |
1194 | } | |
1195 | ||
1196 | ret = set_trigger_config(sdi); | |
1197 | if (ret != SR_OK) | |
1198 | return ret; | |
1199 | ||
1200 | ret = set_sample_config(sdi); | |
1201 | if (ret != SR_OK) | |
1202 | return ret; | |
1203 | ||
1204 | return SR_OK; | |
1205 | } | |
1206 | ||
1207 | SR_PRIV int la2016_start_acquisition(const struct sr_dev_inst *sdi) | |
1208 | { | |
0fbb464b | 1209 | struct dev_context *devc; |
3ebc1cb2 GS |
1210 | int ret; |
1211 | ||
0fbb464b GS |
1212 | devc = sdi->priv; |
1213 | ||
1291ea43 GS |
1214 | ret = la2016_usbxfer_allocate(sdi); |
1215 | if (ret != SR_OK) | |
1216 | return ret; | |
1217 | ||
0fbb464b GS |
1218 | if (devc->continuous) { |
1219 | ret = ctrl_out(sdi, CMD_BULK_RESET, 0x00, 0, NULL, 0); | |
1220 | if (ret != SR_OK) | |
1221 | return ret; | |
1222 | ||
1223 | ret = la2016_usbxfer_submit_all(sdi); | |
1224 | if (ret != SR_OK) | |
1225 | return ret; | |
1226 | ||
1227 | /* | |
1228 | * Periodic receive callback will set runmode. This | |
1229 | * activity MUST be close to data reception, a pause | |
1230 | * between these steps breaks the stream's operation. | |
1231 | */ | |
1232 | } else { | |
1233 | ret = set_run_mode(sdi, RUNMODE_RUN); | |
1234 | if (ret != SR_OK) | |
1235 | return ret; | |
1236 | } | |
3ebc1cb2 GS |
1237 | |
1238 | return SR_OK; | |
f2cd2deb FS |
1239 | } |
1240 | ||
3ebc1cb2 | 1241 | static int la2016_stop_acquisition(const struct sr_dev_inst *sdi) |
f2cd2deb | 1242 | { |
0fbb464b | 1243 | struct dev_context *devc; |
3ebc1cb2 GS |
1244 | int ret; |
1245 | ||
852c7d14 | 1246 | ret = set_run_mode(sdi, RUNMODE_HALT); |
3ebc1cb2 GS |
1247 | if (ret != SR_OK) |
1248 | return ret; | |
1249 | ||
0fbb464b GS |
1250 | devc = sdi->priv; |
1251 | if (devc->continuous) | |
1252 | devc->download_finished = TRUE; | |
1253 | ||
3ebc1cb2 | 1254 | return SR_OK; |
f2cd2deb FS |
1255 | } |
1256 | ||
1257 | SR_PRIV int la2016_abort_acquisition(const struct sr_dev_inst *sdi) | |
1258 | { | |
3ebc1cb2 | 1259 | int ret; |
3ebc1cb2 GS |
1260 | |
1261 | ret = la2016_stop_acquisition(sdi); | |
1262 | if (ret != SR_OK) | |
1263 | return ret; | |
1264 | ||
1291ea43 | 1265 | (void)la2016_usbxfer_cancel_all(sdi); |
3ebc1cb2 GS |
1266 | |
1267 | return SR_OK; | |
f2cd2deb FS |
1268 | } |
1269 | ||
1291ea43 | 1270 | static int la2016_start_download(const struct sr_dev_inst *sdi) |
f2cd2deb FS |
1271 | { |
1272 | struct dev_context *devc; | |
f2cd2deb | 1273 | int ret; |
3ab60908 | 1274 | uint8_t wrbuf[REG_SAMPLING - REG_BULK]; /* Width of REG_BULK. */ |
c3d40037 | 1275 | uint8_t *wrptr; |
f2cd2deb FS |
1276 | |
1277 | devc = sdi->priv; | |
f2cd2deb | 1278 | |
411ad77c GS |
1279 | ret = get_capture_info(sdi); |
1280 | if (ret != SR_OK) | |
f2cd2deb FS |
1281 | return ret; |
1282 | ||
038e65c1 GS |
1283 | devc->n_transfer_packets_to_read = devc->info.n_rep_packets; |
1284 | devc->n_transfer_packets_to_read /= devc->packets_per_chunk; | |
1285 | devc->n_bytes_to_read = devc->n_transfer_packets_to_read; | |
2b7d35b4 | 1286 | devc->n_bytes_to_read *= devc->transfer_size; |
f2cd2deb FS |
1287 | devc->read_pos = devc->info.write_pos - devc->n_bytes_to_read; |
1288 | devc->n_reps_until_trigger = devc->info.n_rep_packets_before_trigger; | |
1289 | ||
91f73872 | 1290 | sr_dbg("Want to read %u xfer-packets starting from pos %" PRIu32 ".", |
1ed93110 | 1291 | devc->n_transfer_packets_to_read, devc->read_pos); |
f2cd2deb | 1292 | |
411ad77c GS |
1293 | ret = ctrl_out(sdi, CMD_BULK_RESET, 0x00, 0, NULL, 0); |
1294 | if (ret != SR_OK) { | |
91f73872 | 1295 | sr_err("Cannot reset USB bulk state."); |
f2cd2deb FS |
1296 | return ret; |
1297 | } | |
91f73872 GS |
1298 | sr_dbg("Will read from 0x%08lx, 0x%08x bytes.", |
1299 | (unsigned long)devc->read_pos, devc->n_bytes_to_read); | |
c3d40037 HK |
1300 | wrptr = wrbuf; |
1301 | write_u32le_inc(&wrptr, devc->read_pos); | |
1302 | write_u32le_inc(&wrptr, devc->n_bytes_to_read); | |
411ad77c GS |
1303 | ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_BULK, 0, wrbuf, wrptr - wrbuf); |
1304 | if (ret != SR_OK) { | |
91f73872 | 1305 | sr_err("Cannot send USB bulk config."); |
f2cd2deb FS |
1306 | return ret; |
1307 | } | |
1291ea43 GS |
1308 | |
1309 | ret = la2016_usbxfer_submit_all(sdi); | |
411ad77c | 1310 | if (ret != SR_OK) { |
1291ea43 | 1311 | sr_err("Cannot submit USB bulk transfers."); |
f2cd2deb FS |
1312 | return ret; |
1313 | } | |
1314 | ||
1291ea43 GS |
1315 | ret = ctrl_out(sdi, CMD_BULK_START, 0x00, 0, NULL, 0); |
1316 | if (ret != SR_OK) { | |
1317 | sr_err("Cannot start USB bulk transfers."); | |
1318 | return ret; | |
f2cd2deb FS |
1319 | } |
1320 | ||
1321 | return SR_OK; | |
1322 | } | |
1323 | ||
480efba2 | 1324 | /* |
92ca309f GS |
1325 | * A chunk of sample memory was received via USB. These chunks contain |
1326 | * transfers of 16 or 32 bytes each (model dependent size and layout). | |
1327 | * Transfers contain a number of packets (5 or 6 per transfer), which | |
1328 | * contain a number of samples (16 or 32 sampled pin values, and an | |
1329 | * 8bit repeat count for these sampled pin values). A sequence number | |
1330 | * follows the packets within the transfer, allows to detect missing or | |
1331 | * out of order reception. | |
1332 | * | |
1333 | * Memory layout for 16-channel models: | |
1334 | * - 16 bytes per transfer | |
1335 | * - 5x (u16 pins, and u8 count) | |
1336 | * - 1x u8 sequence number | |
1337 | * | |
1338 | * Memory layout for 32-channel models: | |
1339 | * - 32 bytes per transfer | |
1340 | * - 6x (u32 pins, and u8 count) | |
1341 | * - 2x u8 sequence number (inverted, and normal) | |
1342 | * | |
1343 | * This implementation silently ignores the (weak) sequence number. | |
480efba2 | 1344 | */ |
dfac9592 | 1345 | static void send_chunk(struct sr_dev_inst *sdi, |
c7d14e31 | 1346 | const uint8_t *data_buffer, size_t data_length) |
dfac9592 GS |
1347 | { |
1348 | struct dev_context *devc; | |
2b7d35b4 | 1349 | size_t num_xfers, num_pkts, num_seqs; |
dfac9592 | 1350 | const uint8_t *rp; |
4276ca94 | 1351 | uint32_t sample_value; |
480efba2 GS |
1352 | size_t repetitions; |
1353 | uint8_t sample_buff[sizeof(sample_value)]; | |
dfac9592 GS |
1354 | |
1355 | devc = sdi->priv; | |
1356 | ||
a38f0f5e GS |
1357 | /* Ignore incoming USB data after complete sample data download. */ |
1358 | if (devc->download_finished) | |
1359 | return; | |
dfac9592 | 1360 | |
cf057ac4 | 1361 | if (devc->trigger_involved && !devc->trigger_marked && devc->info.n_rep_packets_before_trigger == 0) { |
a38f0f5e | 1362 | feed_queue_logic_send_trigger(devc->feed_queue); |
cf057ac4 | 1363 | devc->trigger_marked = TRUE; |
dfac9592 GS |
1364 | } |
1365 | ||
c7d14e31 GS |
1366 | /* |
1367 | * Adjust the number of remaining bytes to read from the device | |
1368 | * before the processing of the currently received chunk affects | |
1369 | * the variable which holds the number of received bytes. | |
1370 | */ | |
1371 | if (data_length > devc->n_bytes_to_read) | |
1372 | devc->n_bytes_to_read = 0; | |
1373 | else | |
1374 | devc->n_bytes_to_read -= data_length; | |
1375 | ||
1376 | /* Process the received chunk of capture data. */ | |
4276ca94 | 1377 | sample_value = 0; |
c7d14e31 | 1378 | rp = data_buffer; |
2b7d35b4 | 1379 | num_xfers = data_length / devc->transfer_size; |
480efba2 | 1380 | while (num_xfers--) { |
038e65c1 | 1381 | num_pkts = devc->packets_per_chunk; |
480efba2 | 1382 | while (num_pkts--) { |
dfac9592 | 1383 | |
4276ca94 GS |
1384 | if (devc->model->channel_count == 32) |
1385 | sample_value = read_u32le_inc(&rp); | |
1386 | else if (devc->model->channel_count == 16) | |
1387 | sample_value = read_u16le_inc(&rp); | |
dfac9592 | 1388 | repetitions = read_u8_inc(&rp); |
dfac9592 | 1389 | |
dfac9592 | 1390 | devc->total_samples += repetitions; |
480efba2 | 1391 | |
4276ca94 | 1392 | write_u32le(sample_buff, sample_value); |
a38f0f5e GS |
1393 | feed_queue_logic_submit(devc->feed_queue, |
1394 | sample_buff, repetitions); | |
1395 | sr_sw_limits_update_samples_read(&devc->sw_limits, | |
1396 | repetitions); | |
480efba2 | 1397 | |
cf057ac4 GS |
1398 | if (devc->trigger_involved && !devc->trigger_marked) { |
1399 | if (!--devc->n_reps_until_trigger) { | |
a38f0f5e | 1400 | feed_queue_logic_send_trigger(devc->feed_queue); |
cf057ac4 | 1401 | devc->trigger_marked = TRUE; |
91f73872 | 1402 | sr_dbg("Trigger position after %" PRIu64 " samples, %.6fms.", |
1ed93110 | 1403 | devc->total_samples, |
edc0b015 | 1404 | (double)devc->total_samples / devc->samplerate * 1e3); |
dfac9592 GS |
1405 | } |
1406 | } | |
1407 | } | |
2b7d35b4 GS |
1408 | /* Skip the sequence number bytes. */ |
1409 | num_seqs = devc->sequence_size; | |
1410 | while (num_seqs--) | |
1411 | (void)read_u8_inc(&rp); | |
dfac9592 | 1412 | } |
a38f0f5e | 1413 | |
c7d14e31 GS |
1414 | /* |
1415 | * Check for several conditions which shall terminate the | |
1416 | * capture data download: When the amount of capture data in | |
1417 | * the device is exhausted. When the user specified samples | |
1418 | * count limit is reached. | |
1419 | */ | |
1420 | if (!devc->n_bytes_to_read) { | |
1421 | devc->download_finished = TRUE; | |
1422 | } else { | |
1423 | sr_dbg("%" PRIu32 " more bytes to download from the device.", | |
1424 | devc->n_bytes_to_read); | |
1425 | } | |
a38f0f5e GS |
1426 | if (!devc->download_finished && sr_sw_limits_check(&devc->sw_limits)) { |
1427 | sr_dbg("Acquisition limit reached."); | |
1428 | devc->download_finished = TRUE; | |
1429 | } | |
1430 | if (devc->download_finished) { | |
1431 | sr_dbg("Download finished, flushing session feed queue."); | |
1432 | feed_queue_logic_flush(devc->feed_queue); | |
dfac9592 | 1433 | } |
a38f0f5e | 1434 | sr_dbg("Total samples after chunk: %" PRIu64 ".", devc->total_samples); |
dfac9592 GS |
1435 | } |
1436 | ||
0fbb464b GS |
1437 | /* |
1438 | * Process a chunk of capture data in streaming mode. The memory layout | |
1439 | * is rather different from "normal mode" (see the send_chunk() routine | |
1440 | * above). In streaming mode data is not compressed, and memory cells | |
1441 | * neither contain raw sampled pin values at a given point in time. The | |
1442 | * memory content needs transformation. | |
92ca309f GS |
1443 | * |
1444 | * All enabled channels get iterated over. Disabled channels will not | |
1445 | * occupy space in the streamed sample data. Per channel chunk there is | |
1446 | * one 16bit entity which carries samples that were taken at different | |
1447 | * times. The least significant bit was sampled first, higher bits were | |
1448 | * sampled later. After all 16bit entities for all enabled channels | |
1449 | * were seen, the first enabled channel's next chunk follows. | |
0fbb464b GS |
1450 | * |
1451 | * Implementor's note: This routine is inspired by convert_sample_data() | |
1452 | * in the https://github.com/AlexUg/sigrok implementation. Which in turn | |
1453 | * appears to have been derived from the saleae-logic16 sigrok driver. | |
1454 | * The code is phrased conservatively to verify the layout as discussed | |
1455 | * above, performance was not a priority. Operation was verified with an | |
92ca309f GS |
1456 | * LA2016 device. The LA5032 reportedly shares the 16 samples per channel |
1457 | * layout, just round-robins through a potentially larger set of enabled | |
1458 | * channels before returning to the first of the channels. | |
0fbb464b GS |
1459 | */ |
1460 | static void stream_data(struct sr_dev_inst *sdi, | |
1461 | const uint8_t *data_buffer, size_t data_length) | |
1462 | { | |
1463 | struct dev_context *devc; | |
1464 | struct stream_state_t *stream; | |
1465 | size_t bit_count; | |
1466 | const uint8_t *rp; | |
1467 | uint32_t sample_value; | |
1468 | uint8_t sample_buff[sizeof(sample_value)]; | |
1469 | size_t bit_idx; | |
1470 | uint32_t ch_mask; | |
1471 | ||
1472 | devc = sdi->priv; | |
1473 | stream = &devc->stream; | |
1474 | ||
1475 | /* Ignore incoming USB data after complete sample data download. */ | |
1476 | if (devc->download_finished) | |
1477 | return; | |
1478 | sr_dbg("Stream mode, got another chunk: %p, length %zu.", | |
1479 | data_buffer, data_length); | |
1480 | ||
1481 | /* TODO Add soft trigger support when in stream mode? */ | |
1482 | ||
4c1bfdf3 GS |
1483 | /* All channels' chunks carry 16 samples for one channel. */ |
1484 | bit_count = 16; | |
1485 | data_length /= sizeof(uint16_t); | |
1486 | ||
0fbb464b GS |
1487 | rp = data_buffer; |
1488 | sample_value = 0; | |
1489 | while (data_length--) { | |
1490 | /* Get another entity. */ | |
4c1bfdf3 | 1491 | sample_value = read_u16le_inc(&rp); |
0fbb464b GS |
1492 | |
1493 | /* Map the entity's bits to a channel's samples. */ | |
1494 | ch_mask = stream->channel_masks[stream->channel_index]; | |
1495 | for (bit_idx = 0; bit_idx < bit_count; bit_idx++) { | |
1496 | if (sample_value & (1UL << bit_idx)) | |
1497 | stream->sample_data[bit_idx] |= ch_mask; | |
1498 | } | |
1499 | ||
1500 | /* | |
1501 | * Advance to the next channel. Submit a block of | |
1502 | * samples when all channels' data was seen. | |
1503 | */ | |
1504 | stream->channel_index++; | |
1505 | if (stream->channel_index != stream->enabled_count) | |
1506 | continue; | |
1507 | for (bit_idx = 0; bit_idx < bit_count; bit_idx++) { | |
1508 | sample_value = stream->sample_data[bit_idx]; | |
1509 | write_u32le(sample_buff, sample_value); | |
1510 | feed_queue_logic_submit(devc->feed_queue, sample_buff, 1); | |
1511 | } | |
1512 | sr_sw_limits_update_samples_read(&devc->sw_limits, bit_count); | |
1513 | devc->total_samples += bit_count; | |
1514 | memset(stream->sample_data, 0, sizeof(stream->sample_data)); | |
1515 | stream->channel_index = 0; | |
1516 | } | |
1517 | ||
1518 | /* | |
1519 | * Need we count empty or failed USB transfers? This version | |
1520 | * doesn't, assumes that timeouts are perfectly legal because | |
1521 | * transfers are started early, and slow samplerates or trigger | |
1522 | * support in hardware are plausible causes for empty transfers. | |
1523 | * | |
1524 | * TODO Maybe a good condition would be (rather large) a timeout | |
1525 | * after a previous capture data chunk was seen? So that stalled | |
1526 | * streaming gets detected which _is_ an exceptional condition. | |
1527 | * We have observed these when "runmode" is set early but bulk | |
1528 | * transfers start late with a pause after setting the runmode. | |
1529 | */ | |
1530 | if (sr_sw_limits_check(&devc->sw_limits)) { | |
1531 | sr_dbg("Acquisition end reached (sw limits)."); | |
1532 | devc->download_finished = TRUE; | |
1533 | } | |
1534 | if (devc->download_finished) { | |
1535 | sr_dbg("Stream receive done, flushing session feed queue."); | |
1536 | feed_queue_logic_flush(devc->feed_queue); | |
1537 | } | |
1538 | sr_dbg("Total samples after chunk: %" PRIu64 ".", devc->total_samples); | |
1539 | } | |
1540 | ||
dfac9592 GS |
1541 | static void LIBUSB_CALL receive_transfer(struct libusb_transfer *transfer) |
1542 | { | |
1543 | struct sr_dev_inst *sdi; | |
1544 | struct dev_context *devc; | |
462a2f0a | 1545 | gboolean was_cancelled, device_gone; |
dfac9592 GS |
1546 | int ret; |
1547 | ||
1548 | sdi = transfer->user_data; | |
1549 | devc = sdi->priv; | |
dfac9592 | 1550 | |
1291ea43 | 1551 | was_cancelled = transfer->status == LIBUSB_TRANSFER_CANCELLED; |
462a2f0a | 1552 | device_gone = transfer->status == LIBUSB_TRANSFER_NO_DEVICE; |
dfac9592 | 1553 | sr_dbg("receive_transfer(): status %s received %d bytes.", |
1ed93110 | 1554 | libusb_error_name(transfer->status), transfer->actual_length); |
462a2f0a GS |
1555 | if (device_gone) { |
1556 | sr_warn("Lost communication to USB device."); | |
1557 | devc->download_finished = TRUE; | |
1558 | return; | |
1559 | } | |
1560 | ||
a38f0f5e GS |
1561 | /* |
1562 | * Implementation detail: A USB transfer timeout is not fatal | |
1563 | * here. We just process whatever was received, empty input is | |
1564 | * perfectly acceptable. Reaching (or exceeding) the sw limits | |
1565 | * or exhausting the device's captured data will complete the | |
1566 | * sample data download. | |
1567 | */ | |
0fbb464b GS |
1568 | if (devc->continuous) |
1569 | stream_data(sdi, transfer->buffer, transfer->actual_length); | |
1570 | else | |
1571 | send_chunk(sdi, transfer->buffer, transfer->actual_length); | |
c7d14e31 | 1572 | |
1291ea43 GS |
1573 | /* |
1574 | * Re-submit completed transfers (regardless of timeout or | |
1575 | * data reception), unless the transfer was cancelled when | |
1576 | * the acquisition was terminated or has completed. | |
1577 | */ | |
1578 | if (!was_cancelled && !devc->download_finished) { | |
1579 | ret = la2016_usbxfer_resubmit(sdi, transfer); | |
1580 | if (ret == SR_OK) | |
dfac9592 | 1581 | return; |
c7d14e31 | 1582 | devc->download_finished = TRUE; |
dfac9592 | 1583 | } |
dfac9592 GS |
1584 | } |
1585 | ||
1586 | SR_PRIV int la2016_receive_data(int fd, int revents, void *cb_data) | |
1587 | { | |
1588 | const struct sr_dev_inst *sdi; | |
1589 | struct dev_context *devc; | |
1590 | struct drv_context *drvc; | |
1591 | struct timeval tv; | |
a38f0f5e | 1592 | int ret; |
dfac9592 GS |
1593 | |
1594 | (void)fd; | |
1595 | (void)revents; | |
1596 | ||
1597 | sdi = cb_data; | |
1598 | devc = sdi->priv; | |
1599 | drvc = sdi->driver->context; | |
1600 | ||
0fbb464b GS |
1601 | /* Arrange for the start of stream mode when requested. */ |
1602 | if (devc->continuous && !devc->frame_begin_sent) { | |
1603 | sr_dbg("First receive callback in stream mode."); | |
1604 | devc->download_finished = FALSE; | |
1605 | devc->trigger_marked = FALSE; | |
1606 | devc->total_samples = 0; | |
1607 | ||
1608 | std_session_send_df_frame_begin(sdi); | |
1609 | devc->frame_begin_sent = TRUE; | |
1610 | ||
1611 | ret = set_run_mode(sdi, RUNMODE_RUN); | |
1612 | if (ret != SR_OK) { | |
1613 | sr_err("Cannot set 'runmode' to 'run'."); | |
1614 | return FALSE; | |
1615 | } | |
1616 | ||
1617 | ret = ctrl_out(sdi, CMD_BULK_START, 0x00, 0, NULL, 0); | |
1618 | if (ret != SR_OK) { | |
1619 | sr_err("Cannot start USB bulk transfers."); | |
1620 | return FALSE; | |
1621 | } | |
1622 | sr_dbg("Stream data reception initiated."); | |
1623 | } | |
1624 | ||
a38f0f5e GS |
1625 | /* |
1626 | * Wait for the acquisition to complete in hardware. | |
1627 | * Periodically check a potentially configured msecs timeout. | |
1628 | */ | |
0fbb464b | 1629 | if (!devc->continuous && !devc->completion_seen) { |
cf057ac4 | 1630 | if (!la2016_is_idle(sdi)) { |
a38f0f5e GS |
1631 | if (sr_sw_limits_check(&devc->sw_limits)) { |
1632 | devc->sw_limits.limit_msec = 0; | |
1633 | sr_dbg("Limit reached. Stopping acquisition."); | |
1634 | la2016_stop_acquisition(sdi); | |
1635 | } | |
96dc954e | 1636 | /* Not yet ready for sample data download. */ |
dfac9592 GS |
1637 | return TRUE; |
1638 | } | |
a38f0f5e GS |
1639 | sr_dbg("Acquisition completion seen (hardware)."); |
1640 | devc->sw_limits.limit_msec = 0; | |
cf057ac4 GS |
1641 | devc->completion_seen = TRUE; |
1642 | devc->download_finished = FALSE; | |
1643 | devc->trigger_marked = FALSE; | |
dfac9592 | 1644 | devc->total_samples = 0; |
a38f0f5e | 1645 | |
33020165 GS |
1646 | la2016_dump_fpga_registers(sdi, "acquisition complete", 0, 0); |
1647 | ||
a38f0f5e GS |
1648 | /* Initiate the download of acquired sample data. */ |
1649 | std_session_send_df_frame_begin(sdi); | |
96a405ab | 1650 | devc->frame_begin_sent = TRUE; |
1291ea43 | 1651 | ret = la2016_start_download(sdi); |
a38f0f5e | 1652 | if (ret != SR_OK) { |
91f73872 | 1653 | sr_err("Cannot start acquisition data download."); |
dfac9592 GS |
1654 | return FALSE; |
1655 | } | |
91f73872 | 1656 | sr_dbg("Acquisition data download started."); |
dfac9592 GS |
1657 | |
1658 | return TRUE; | |
1659 | } | |
1660 | ||
a38f0f5e | 1661 | /* Handle USB reception. Drives sample data download. */ |
1291ea43 | 1662 | memset(&tv, 0, sizeof(tv)); |
dfac9592 GS |
1663 | libusb_handle_events_timeout(drvc->sr_ctx->libusb_ctx, &tv); |
1664 | ||
0fbb464b GS |
1665 | /* |
1666 | * Periodically flush acquisition data in streaming mode. | |
1667 | * Without this nudge, previously received and accumulated data | |
1668 | * keeps sitting in queues and is not seen by applications. | |
1669 | */ | |
1670 | if (devc->continuous && devc->stream.flush_period_ms) { | |
1671 | uint64_t now, elapsed; | |
1672 | now = g_get_monotonic_time(); | |
1673 | if (!devc->stream.last_flushed) | |
1674 | devc->stream.last_flushed = now; | |
1675 | elapsed = now - devc->stream.last_flushed; | |
1676 | elapsed /= 1000; | |
1677 | if (elapsed >= devc->stream.flush_period_ms) { | |
1678 | sr_dbg("Stream mode, flushing."); | |
1679 | feed_queue_logic_flush(devc->feed_queue); | |
1680 | devc->stream.last_flushed = now; | |
1681 | } | |
1682 | } | |
1683 | ||
a38f0f5e | 1684 | /* Postprocess completion of sample data download. */ |
cf057ac4 | 1685 | if (devc->download_finished) { |
91f73872 | 1686 | sr_dbg("Download finished, post processing."); |
dfac9592 GS |
1687 | |
1688 | la2016_stop_acquisition(sdi); | |
a38f0f5e | 1689 | usb_source_remove(sdi->session, drvc->sr_ctx); |
1291ea43 GS |
1690 | |
1691 | la2016_usbxfer_cancel_all(sdi); | |
1692 | memset(&tv, 0, sizeof(tv)); | |
1693 | libusb_handle_events_timeout(drvc->sr_ctx->libusb_ctx, &tv); | |
dfac9592 | 1694 | |
a38f0f5e GS |
1695 | feed_queue_logic_flush(devc->feed_queue); |
1696 | feed_queue_logic_free(devc->feed_queue); | |
1697 | devc->feed_queue = NULL; | |
96a405ab GS |
1698 | if (devc->frame_begin_sent) { |
1699 | std_session_send_df_frame_end(sdi); | |
1700 | devc->frame_begin_sent = FALSE; | |
1701 | } | |
a38f0f5e GS |
1702 | std_session_send_df_end(sdi); |
1703 | ||
91f73872 | 1704 | sr_dbg("Download finished, done post processing."); |
dfac9592 GS |
1705 | } |
1706 | ||
1707 | return TRUE; | |
1708 | } | |
1709 | ||
d466f61c GS |
1710 | SR_PRIV int la2016_identify_device(const struct sr_dev_inst *sdi, |
1711 | gboolean show_message) | |
f2cd2deb | 1712 | { |
8b172e78 | 1713 | struct dev_context *devc; |
3ab60908 | 1714 | uint8_t buf[8]; /* Larger size of manuf date and device type magic. */ |
64172b16 | 1715 | size_t rdoff, rdlen; |
43d2e52f GS |
1716 | const uint8_t *rdptr; |
1717 | uint8_t date_yy, date_mm; | |
1718 | uint8_t dinv_yy, dinv_mm; | |
69320ad3 | 1719 | uint8_t magic, magic2; |
d466f61c GS |
1720 | size_t model_idx; |
1721 | const struct kingst_model *model; | |
9de389b1 | 1722 | int ret; |
f2cd2deb | 1723 | |
8b172e78 KG |
1724 | devc = sdi->priv; |
1725 | ||
96dc954e | 1726 | /* |
43d2e52f GS |
1727 | * Four EEPROM bytes at offset 0x20 are the manufacturing date, |
1728 | * year and month in BCD format, followed by inverted values for | |
1729 | * consistency checks. For example bytes 20 04 df fb translate | |
1730 | * to 2020-04. This information can help identify the vintage of | |
1731 | * devices when unknown magic numbers are seen. | |
9de389b1 | 1732 | */ |
64172b16 GS |
1733 | rdoff = 0x20; |
1734 | rdlen = 4 * sizeof(uint8_t); | |
1735 | ret = ctrl_in(sdi, CMD_EEPROM, rdoff, 0, buf, rdlen); | |
d466f61c | 1736 | if (ret != SR_OK && !show_message) { |
64172b16 | 1737 | /* Non-fatal weak attempt during probe. Not worth logging. */ |
d466f61c GS |
1738 | sr_dbg("Cannot access EEPROM."); |
1739 | return SR_ERR_IO; | |
1740 | } else if (ret != SR_OK) { | |
64172b16 | 1741 | /* Failed attempt in regular use. Non-fatal. Worth logging. */ |
43d2e52f | 1742 | sr_err("Cannot read manufacture date in EEPROM."); |
1ed93110 | 1743 | } else { |
64172b16 GS |
1744 | if (sr_log_loglevel_get() >= SR_LOG_SPEW) { |
1745 | GString *txt; | |
1746 | txt = sr_hexdump_new(buf, rdlen); | |
1747 | sr_spew("Manufacture date bytes %s.", txt->str); | |
1748 | sr_hexdump_free(txt); | |
1749 | } | |
43d2e52f GS |
1750 | rdptr = &buf[0]; |
1751 | date_yy = read_u8_inc(&rdptr); | |
1752 | date_mm = read_u8_inc(&rdptr); | |
1753 | dinv_yy = read_u8_inc(&rdptr); | |
1754 | dinv_mm = read_u8_inc(&rdptr); | |
1755 | sr_info("Manufacture date: 20%02hx-%02hx.", date_yy, date_mm); | |
1756 | if ((date_mm ^ dinv_mm) != 0xff || (date_yy ^ dinv_yy) != 0xff) | |
1757 | sr_warn("Manufacture date fails checksum test."); | |
f2cd2deb | 1758 | } |
f2cd2deb | 1759 | |
9de389b1 | 1760 | /* |
96dc954e GS |
1761 | * Several Kingst logic analyzer devices share the same USB VID |
1762 | * and PID. The product ID determines which MCU firmware to load. | |
1763 | * The MCU firmware provides access to EEPROM content which then | |
1764 | * allows to identify the device model. Which in turn determines | |
1765 | * which FPGA bitstream to load. Eight bytes at offset 0x08 are | |
1766 | * to get inspected. | |
9de389b1 | 1767 | * |
96dc954e GS |
1768 | * EEPROM content for model identification is kept redundantly |
1769 | * in memory. The values are stored in verbatim and in inverted | |
1770 | * form, multiple copies are kept at different offsets. Example | |
1771 | * data: | |
9de389b1 | 1772 | * |
96dc954e GS |
1773 | * magic 0x08 |
1774 | * | ~magic 0xf7 | |
1775 | * | | | |
1776 | * 08f7000008f710ef | |
1777 | * | | | |
1778 | * | ~magic backup | |
1779 | * magic backup | |
9de389b1 | 1780 | * |
96dc954e GS |
1781 | * Exclusively inspecting the magic byte appears to be sufficient, |
1782 | * other fields seem to be 'don't care'. | |
9de389b1 | 1783 | * |
96dc954e GS |
1784 | * magic 2 == LA2016 using "kingst-la2016-fpga.bitstream" |
1785 | * magic 3 == LA1016 using "kingst-la1016-fpga.bitstream" | |
1786 | * magic 8 == LA2016a using "kingst-la2016a1-fpga.bitstream" | |
1787 | * (latest v1.3.0 PCB, perhaps others) | |
1788 | * magic 9 == LA1016a using "kingst-la1016a1-fpga.bitstream" | |
1789 | * (latest v1.3.0 PCB, perhaps others) | |
9de389b1 | 1790 | * |
96dc954e GS |
1791 | * When EEPROM content does not match the hardware configuration |
1792 | * (the board layout), the software may load but yield incorrect | |
1793 | * results (like swapped channels). The FPGA bitstream itself | |
1794 | * will authenticate with IC U10 and fail when its capabilities | |
1795 | * do not match the hardware model. An LA1016 won't become a | |
1796 | * LA2016 by faking its EEPROM content. | |
9de389b1 | 1797 | */ |
d466f61c | 1798 | devc->identify_magic = 0; |
64172b16 GS |
1799 | rdoff = 0x08; |
1800 | rdlen = 8 * sizeof(uint8_t); | |
1801 | ret = ctrl_in(sdi, CMD_EEPROM, rdoff, 0, &buf, rdlen); | |
1802 | if (ret != SR_OK) { | |
91f73872 | 1803 | sr_err("Cannot read EEPROM device identifier bytes."); |
f2cd2deb FS |
1804 | return ret; |
1805 | } | |
64172b16 GS |
1806 | if (sr_log_loglevel_get() >= SR_LOG_SPEW) { |
1807 | GString *txt; | |
1808 | txt = sr_hexdump_new(buf, rdlen); | |
1809 | sr_spew("EEPROM magic bytes %s.", txt->str); | |
1810 | sr_hexdump_free(txt); | |
1811 | } | |
69320ad3 GS |
1812 | magic = 0; |
1813 | magic2 = 0; | |
1814 | if ((buf[0] ^ buf[1]) == 0xff && (buf[2] ^ buf[3]) == 0xff) { | |
1815 | /* Primary copy of magic passes complement check (4 bytes). */ | |
9de389b1 | 1816 | magic = buf[0]; |
69320ad3 | 1817 | magic2 = buf[2]; |
f49837a5 | 1818 | sr_dbg("Using primary magic 0x%hhx (0x%hhx).", magic, magic2); |
69320ad3 GS |
1819 | } else if ((buf[4] ^ buf[5]) == 0xff && (buf[6] ^ buf[7]) == 0xff) { |
1820 | /* Backup copy of magic passes complement check (4 bytes). */ | |
1821 | magic = buf[4]; | |
1822 | magic2 = buf[6]; | |
f49837a5 | 1823 | sr_dbg("Using secondary magic 0x%hhx (0x%hhx).", magic, magic2); |
69320ad3 GS |
1824 | } else if ((buf[0] ^ buf[1]) == 0xff) { |
1825 | /* Primary copy of magic passes complement check (2 bytes). */ | |
1826 | magic = buf[0]; | |
f49837a5 | 1827 | sr_dbg("Using primary magic 0x%hhx.", magic); |
43d2e52f | 1828 | } else if ((buf[4] ^ buf[5]) == 0xff) { |
69320ad3 | 1829 | /* Backup copy of magic passes complement check (2 bytes). */ |
9de389b1 | 1830 | magic = buf[4]; |
f49837a5 | 1831 | sr_dbg("Using secondary magic 0x%hhx.", magic); |
43d2e52f GS |
1832 | } else { |
1833 | sr_err("Cannot find consistent device type identification."); | |
f2cd2deb | 1834 | } |
d466f61c | 1835 | devc->identify_magic = magic; |
69320ad3 | 1836 | devc->identify_magic2 = magic2; |
9de389b1 | 1837 | |
d466f61c GS |
1838 | devc->model = NULL; |
1839 | for (model_idx = 0; model_idx < ARRAY_SIZE(models); model_idx++) { | |
1840 | model = &models[model_idx]; | |
1841 | if (model->magic != magic) | |
1842 | continue; | |
69320ad3 GS |
1843 | if (model->magic2 && model->magic2 != magic2) |
1844 | continue; | |
d466f61c | 1845 | devc->model = model; |
64172b16 GS |
1846 | sr_info("Model '%s', %zu channels, max %" PRIu64 "MHz.", |
1847 | model->name, model->channel_count, | |
1848 | model->samplerate / SR_MHZ(1)); | |
d466f61c GS |
1849 | devc->fpga_bitstream = g_strdup_printf(FPGA_FWFILE_FMT, |
1850 | model->fpga_stem); | |
d466f61c | 1851 | sr_info("FPGA bitstream file '%s'.", devc->fpga_bitstream); |
69320ad3 GS |
1852 | if (!model->channel_count) { |
1853 | sr_warn("Device lacks logic channels. Not supported."); | |
1854 | devc->model = NULL; | |
1855 | } | |
d6f89d4b GS |
1856 | break; |
1857 | } | |
d466f61c | 1858 | if (!devc->model) { |
91f73872 | 1859 | sr_err("Cannot identify as one of the supported models."); |
286b3e13 | 1860 | return SR_ERR_DATA; |
3f48ab02 | 1861 | } |
f2cd2deb | 1862 | |
d466f61c GS |
1863 | return SR_OK; |
1864 | } | |
1865 | ||
6d53e949 | 1866 | SR_PRIV int la2016_init_hardware(const struct sr_dev_inst *sdi) |
d466f61c GS |
1867 | { |
1868 | struct dev_context *devc; | |
1869 | const char *bitstream_fn; | |
1870 | int ret; | |
1871 | uint16_t state; | |
1872 | ||
1873 | devc = sdi->priv; | |
1874 | bitstream_fn = devc ? devc->fpga_bitstream : ""; | |
1875 | ||
1876 | ret = check_fpga_bitstream(sdi); | |
1877 | if (ret != SR_OK) { | |
d6f89d4b GS |
1878 | ret = upload_fpga_bitstream(sdi, bitstream_fn); |
1879 | if (ret != SR_OK) { | |
1880 | sr_err("Cannot upload FPGA bitstream."); | |
1881 | return ret; | |
1882 | } | |
1883 | } | |
1884 | ret = enable_fpga_bitstream(sdi); | |
9de389b1 | 1885 | if (ret != SR_OK) { |
d6f89d4b | 1886 | sr_err("Cannot enable FPGA bitstream after upload."); |
9de389b1 KG |
1887 | return ret; |
1888 | } | |
1889 | ||
f2cd2deb | 1890 | state = run_state(sdi); |
44947217 GS |
1891 | if ((state & 0xfff0) != 0x85e0) { |
1892 | sr_warn("Unexpected run state, want 0x85eX, got 0x%04x.", state); | |
9de389b1 | 1893 | } |
f2cd2deb | 1894 | |
6d53e949 GS |
1895 | ret = ctrl_out(sdi, CMD_BULK_RESET, 0x00, 0, NULL, 0); |
1896 | if (ret != SR_OK) { | |
91f73872 | 1897 | sr_err("Cannot reset USB bulk transfer."); |
f2cd2deb FS |
1898 | return ret; |
1899 | } | |
9de389b1 | 1900 | |
91f73872 | 1901 | sr_dbg("Device should be initialized."); |
f2cd2deb | 1902 | |
6d53e949 GS |
1903 | return SR_OK; |
1904 | } | |
1905 | ||
6d53e949 | 1906 | SR_PRIV int la2016_deinit_hardware(const struct sr_dev_inst *sdi) |
f2cd2deb FS |
1907 | { |
1908 | int ret; | |
1909 | ||
6d53e949 GS |
1910 | ret = ctrl_out(sdi, CMD_FPGA_ENABLE, 0x00, 0, NULL, 0); |
1911 | if (ret != SR_OK) { | |
91f73872 | 1912 | sr_err("Cannot deinitialize device's FPGA."); |
f2cd2deb FS |
1913 | return ret; |
1914 | } | |
1915 | ||
1916 | return SR_OK; | |
1917 | } | |
08a49848 | 1918 | |
1291ea43 GS |
1919 | SR_PRIV void la2016_release_resources(const struct sr_dev_inst *sdi) |
1920 | { | |
1921 | (void)la2016_usbxfer_release(sdi); | |
1922 | } | |
1923 | ||
08a49848 GS |
1924 | SR_PRIV int la2016_write_pwm_config(const struct sr_dev_inst *sdi, size_t idx) |
1925 | { | |
1926 | return set_pwm_config(sdi, idx); | |
1927 | } |