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f2cd2deb FS |
1 | /* |
2 | * This file is part of the libsigrok project. | |
3 | * | |
4 | * Copyright (C) 2020 Florian Schmidt <schmidt_florian@gmx.de> | |
5 | * Copyright (C) 2013 Marcus Comstedt <marcus@mc.pp.se> | |
6 | * Copyright (C) 2013 Bert Vermeulen <bert@biot.com> | |
7 | * Copyright (C) 2012 Joel Holdsworth <joel@airwebreathe.org.uk> | |
8 | * | |
9 | * This program is free software: you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License as published by | |
11 | * the Free Software Foundation, either version 3 of the License, or | |
12 | * (at your option) any later version. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
21 | */ | |
22 | ||
23 | #include <config.h> | |
a7740b06 | 24 | |
f2cd2deb | 25 | #include <libsigrok/libsigrok.h> |
a7740b06 GS |
26 | #include <string.h> |
27 | ||
f2cd2deb FS |
28 | #include "libsigrok-internal.h" |
29 | #include "protocol.h" | |
30 | ||
d466f61c GS |
31 | /* USB PID dependent MCU firmware. Model dependent FPGA bitstream. */ |
32 | #define MCU_FWFILE_FMT "kingst-la-%04x.fw" | |
33 | #define FPGA_FWFILE_FMT "kingst-%s-fpga.bitstream" | |
34 | ||
35 | /* | |
36 | * List of supported devices and their features. See @ref kingst_model | |
37 | * for the fields' type and meaning. Table is sorted by EEPROM magic. | |
38 | * | |
39 | * TODO | |
40 | * - Below LA1016 properties were guessed, need verification. | |
41 | * - Add LA5016 and LA5032 devices when their EEPROM magic is known. | |
42 | * - Does LA1010 fit the driver implementation? Samplerates vary with | |
43 | * channel counts, lack of local sample memory. Most probably not. | |
44 | */ | |
45 | static const struct kingst_model models[] = { | |
46 | { 2, "LA2016", "la2016", SR_MHZ(200), 16, 1, }, | |
47 | { 3, "LA1016", "la1016", SR_MHZ(100), 16, 1, }, | |
48 | { 8, "LA2016", "la2016a1", SR_MHZ(200), 16, 1, }, | |
49 | { 9, "LA1016", "la1016a1", SR_MHZ(100), 16, 1, }, | |
50 | }; | |
f2cd2deb | 51 | |
96dc954e | 52 | /* USB vendor class control requests, executed by the Cypress FX2 MCU. */ |
84fe94bd | 53 | #define CMD_FPGA_ENABLE 0x10 |
96dc954e GS |
54 | #define CMD_FPGA_SPI 0x20 /* R/W access to FPGA registers via SPI. */ |
55 | #define CMD_BULK_START 0x30 /* Start sample data download via USB EP6 IN. */ | |
56 | #define CMD_BULK_RESET 0x38 /* Flush FIFO of FX2 USB EP6 IN. */ | |
57 | #define CMD_FPGA_INIT 0x50 /* Used before and after FPGA bitstream upload. */ | |
58 | #define CMD_KAUTH 0x60 /* Communicate to auth IC (U10). Not used. */ | |
59 | #define CMD_EEPROM 0xa2 /* R/W access to EEPROM content. */ | |
00849545 | 60 | |
42f6dd55 | 61 | /* |
96dc954e GS |
62 | * FPGA register addresses (base addresses when registers span multiple |
63 | * bytes, in that case data is kept in little endian format). Passed to | |
64 | * CMD_FPGA_SPI requests. The FX2 MCU transparently handles the detail | |
65 | * of SPI transfers encoding the read (1) or write (0) direction in the | |
66 | * MSB of the address field. There are some 60 byte-wide FPGA registers. | |
d6f89d4b GS |
67 | * |
68 | * Unfortunately the FPGA registers change their meaning between the | |
69 | * read and write directions of access, or exclusively provide one of | |
70 | * these directions and not the other. This is an arbitrary vendor's | |
71 | * choice, there is nothing which the sigrok driver could do about it. | |
72 | * Values written to registers typically cannot get read back, neither | |
73 | * verified after writing a configuration, nor queried upon startup for | |
74 | * automatic detection of the current configuration. Neither appear to | |
75 | * be there echo registers for presence and communication checks, nor | |
76 | * version identifying registers, as far as we know. | |
42f6dd55 | 77 | */ |
96dc954e GS |
78 | #define REG_RUN 0x00 /* Read capture status, write start capture. */ |
79 | #define REG_PWM_EN 0x02 /* User PWM channels on/off. */ | |
80 | #define REG_CAPT_MODE 0x03 /* Write 0x00 capture to SDRAM, 0x01 streaming. */ | |
81 | #define REG_BULK 0x08 /* Write start addr, byte count to download samples. */ | |
82 | #define REG_SAMPLING 0x10 /* Write capture config, read capture SDRAM location. */ | |
3ab60908 GS |
83 | #define REG_TRIGGER 0x20 /* Write level and edge trigger config. */ |
84 | #define REG_UNKNOWN_30 0x30 | |
96dc954e GS |
85 | #define REG_THRESHOLD 0x68 /* Write PWM config to setup input threshold DAC. */ |
86 | #define REG_PWM1 0x70 /* Write config for user PWM1. */ | |
87 | #define REG_PWM2 0x78 /* Write config for user PWM2. */ | |
f2cd2deb | 88 | |
972d191b GS |
89 | /* Bit patterns to write to REG_CAPT_MODE. */ |
90 | #define CAPTMODE_TO_RAM 0x00 | |
91 | #define CAPTMODE_STREAM 0x01 | |
92 | ||
852c7d14 GS |
93 | /* Bit patterns to write to REG_RUN, setup run mode. */ |
94 | #define RUNMODE_HALT 0x00 | |
95 | #define RUNMODE_RUN 0x03 | |
96 | ||
b711fd8e GS |
97 | /* Bit patterns when reading from REG_RUN, get run state. */ |
98 | #define RUNSTATE_IDLE_BIT (1UL << 0) | |
99 | #define RUNSTATE_DRAM_BIT (1UL << 1) | |
100 | #define RUNSTATE_TRGD_BIT (1UL << 2) | |
101 | #define RUNSTATE_POST_BIT (1UL << 3) | |
102 | ||
f2cd2deb | 103 | static int ctrl_in(const struct sr_dev_inst *sdi, |
1ed93110 GS |
104 | uint8_t bRequest, uint16_t wValue, uint16_t wIndex, |
105 | void *data, uint16_t wLength) | |
f2cd2deb FS |
106 | { |
107 | struct sr_usb_dev_inst *usb; | |
108 | int ret; | |
109 | ||
110 | usb = sdi->conn; | |
111 | ||
411ad77c GS |
112 | ret = libusb_control_transfer(usb->devhdl, |
113 | LIBUSB_REQUEST_TYPE_VENDOR | LIBUSB_ENDPOINT_IN, | |
114 | bRequest, wValue, wIndex, data, wLength, | |
115 | DEFAULT_TIMEOUT_MS); | |
116 | if (ret != wLength) { | |
91f73872 GS |
117 | sr_dbg("USB ctrl in: %d bytes, req %d val %#x idx %d: %s.", |
118 | wLength, bRequest, wValue, wIndex, | |
119 | libusb_error_name(ret)); | |
120 | sr_err("Cannot read %d bytes from USB: %s.", | |
121 | wLength, libusb_error_name(ret)); | |
286b3e13 | 122 | return SR_ERR_IO; |
f2cd2deb FS |
123 | } |
124 | ||
125 | return SR_OK; | |
126 | } | |
127 | ||
128 | static int ctrl_out(const struct sr_dev_inst *sdi, | |
1ed93110 GS |
129 | uint8_t bRequest, uint16_t wValue, uint16_t wIndex, |
130 | void *data, uint16_t wLength) | |
f2cd2deb FS |
131 | { |
132 | struct sr_usb_dev_inst *usb; | |
133 | int ret; | |
134 | ||
135 | usb = sdi->conn; | |
136 | ||
411ad77c GS |
137 | ret = libusb_control_transfer(usb->devhdl, |
138 | LIBUSB_REQUEST_TYPE_VENDOR | LIBUSB_ENDPOINT_OUT, | |
139 | bRequest, wValue, wIndex, data, wLength, | |
140 | DEFAULT_TIMEOUT_MS); | |
141 | if (ret != wLength) { | |
91f73872 GS |
142 | sr_dbg("USB ctrl out: %d bytes, req %d val %#x idx %d: %s.", |
143 | wLength, bRequest, wValue, wIndex, | |
144 | libusb_error_name(ret)); | |
145 | sr_err("Cannot write %d bytes to USB: %s.", | |
146 | wLength, libusb_error_name(ret)); | |
286b3e13 | 147 | return SR_ERR_IO; |
f2cd2deb FS |
148 | } |
149 | ||
150 | return SR_OK; | |
151 | } | |
152 | ||
d6f89d4b GS |
153 | /* |
154 | * Check the necessity for FPGA bitstream upload, because another upload | |
155 | * would take some 600ms which is undesirable after program startup. Try | |
156 | * to access some FPGA registers and check the values' plausibility. The | |
157 | * check should fail on the safe side, request another upload when in | |
158 | * doubt. A positive response (the request to continue operation with the | |
159 | * currently active bitstream) should be conservative. Accessing multiple | |
160 | * registers is considered cheap compared to the cost of bitstream upload. | |
161 | * | |
162 | * It helps though that both the vendor software and the sigrok driver | |
163 | * use the same bundle of MCU firmware and FPGA bitstream for any of the | |
164 | * supported models. We don't expect to successfully communicate to the | |
165 | * device yet disagree on its protocol. Ideally we would access version | |
166 | * identifying registers for improved robustness, but are not aware of | |
167 | * any. A bitstream reload can always be forced by a power cycle. | |
168 | */ | |
169 | static int check_fpga_bitstream(const struct sr_dev_inst *sdi) | |
170 | { | |
171 | uint8_t init_rsp; | |
3ab60908 | 172 | uint8_t buff[REG_PWM_EN - REG_RUN]; /* Larger of REG_RUN, REG_PWM_EN. */ |
d6f89d4b GS |
173 | int ret; |
174 | uint16_t run_state; | |
175 | uint8_t pwm_en; | |
176 | size_t read_len; | |
d6f89d4b GS |
177 | const uint8_t *rdptr; |
178 | ||
179 | sr_dbg("Checking operation of the FPGA bitstream."); | |
180 | ||
852c7d14 | 181 | init_rsp = ~0; |
d6f89d4b GS |
182 | ret = ctrl_in(sdi, CMD_FPGA_INIT, 0x00, 0, &init_rsp, sizeof(init_rsp)); |
183 | if (ret != SR_OK || init_rsp != 0) { | |
184 | sr_dbg("FPGA init query failed, or unexpected response."); | |
185 | return SR_ERR_IO; | |
186 | } | |
187 | ||
188 | read_len = sizeof(run_state); | |
189 | ret = ctrl_in(sdi, CMD_FPGA_SPI, REG_RUN, 0, buff, read_len); | |
190 | if (ret != SR_OK) { | |
191 | sr_dbg("FPGA register access failed (run state)."); | |
192 | return SR_ERR_IO; | |
193 | } | |
194 | rdptr = buff; | |
195 | run_state = read_u16le_inc(&rdptr); | |
196 | sr_spew("FPGA register: run state 0x%04x.", run_state); | |
197 | if (run_state && (run_state & 0x3) != 0x1) { | |
198 | sr_dbg("Unexpected FPGA register content (run state)."); | |
199 | return SR_ERR_DATA; | |
200 | } | |
201 | if (run_state && (run_state & ~0xf) != 0x85e0) { | |
202 | sr_dbg("Unexpected FPGA register content (run state)."); | |
203 | return SR_ERR_DATA; | |
204 | } | |
205 | ||
206 | read_len = sizeof(pwm_en); | |
207 | ret = ctrl_in(sdi, CMD_FPGA_SPI, REG_PWM_EN, 0, buff, read_len); | |
208 | if (ret != SR_OK) { | |
209 | sr_dbg("FPGA register access failed (PWM enable)."); | |
210 | return SR_ERR_IO; | |
211 | } | |
212 | rdptr = buff; | |
213 | pwm_en = read_u8_inc(&rdptr); | |
214 | sr_spew("FPGA register: PWM enable 0x%02x.", pwm_en); | |
215 | if ((pwm_en & 0x3) != 0x0) { | |
216 | sr_dbg("Unexpected FPGA register content (PWM enable)."); | |
217 | return SR_ERR_DATA; | |
218 | } | |
219 | ||
220 | sr_info("Could re-use current FPGA bitstream. No upload required."); | |
221 | return SR_OK; | |
222 | } | |
223 | ||
1ed93110 GS |
224 | static int upload_fpga_bitstream(const struct sr_dev_inst *sdi, |
225 | const char *bitstream_fname) | |
f2cd2deb FS |
226 | { |
227 | struct drv_context *drvc; | |
228 | struct sr_usb_dev_inst *usb; | |
229 | struct sr_resource bitstream; | |
b0d0131e | 230 | uint32_t bitstream_size; |
c3d40037 HK |
231 | uint8_t buffer[sizeof(uint32_t)]; |
232 | uint8_t *wrptr; | |
f2cd2deb | 233 | uint8_t block[4096]; |
3f48ab02 FS |
234 | int len, act_len; |
235 | unsigned int pos; | |
f2cd2deb | 236 | int ret; |
b0d0131e | 237 | unsigned int zero_pad_to; |
f2cd2deb FS |
238 | |
239 | drvc = sdi->driver->context; | |
240 | usb = sdi->conn; | |
241 | ||
9de389b1 | 242 | sr_info("Uploading FPGA bitstream '%s'.", bitstream_fname); |
f2cd2deb | 243 | |
411ad77c GS |
244 | ret = sr_resource_open(drvc->sr_ctx, &bitstream, |
245 | SR_RESOURCE_FIRMWARE, bitstream_fname); | |
f2cd2deb | 246 | if (ret != SR_OK) { |
91f73872 | 247 | sr_err("Cannot find FPGA bitstream %s.", bitstream_fname); |
f2cd2deb FS |
248 | return ret; |
249 | } | |
250 | ||
b0d0131e | 251 | bitstream_size = (uint32_t)bitstream.size; |
c3d40037 | 252 | wrptr = buffer; |
b0d0131e | 253 | write_u32le_inc(&wrptr, bitstream_size); |
411ad77c GS |
254 | ret = ctrl_out(sdi, CMD_FPGA_INIT, 0x00, 0, buffer, wrptr - buffer); |
255 | if (ret != SR_OK) { | |
91f73872 | 256 | sr_err("Cannot initiate FPGA bitstream upload."); |
f2cd2deb FS |
257 | sr_resource_close(drvc->sr_ctx, &bitstream); |
258 | return ret; | |
259 | } | |
b0d0131e GS |
260 | zero_pad_to = bitstream_size; |
261 | zero_pad_to += LA2016_EP2_PADDING - 1; | |
262 | zero_pad_to /= LA2016_EP2_PADDING; | |
263 | zero_pad_to *= LA2016_EP2_PADDING; | |
f2cd2deb FS |
264 | |
265 | pos = 0; | |
266 | while (1) { | |
3f48ab02 | 267 | if (pos < bitstream.size) { |
411ad77c GS |
268 | len = (int)sr_resource_read(drvc->sr_ctx, &bitstream, |
269 | block, sizeof(block)); | |
3f48ab02 | 270 | if (len < 0) { |
91f73872 | 271 | sr_err("Cannot read FPGA bitstream."); |
3f48ab02 | 272 | sr_resource_close(drvc->sr_ctx, &bitstream); |
286b3e13 | 273 | return SR_ERR_IO; |
3f48ab02 FS |
274 | } |
275 | } else { | |
96dc954e | 276 | /* Zero-pad until 'zero_pad_to'. */ |
3f48ab02 FS |
277 | len = zero_pad_to - pos; |
278 | if ((unsigned)len > sizeof(block)) | |
279 | len = sizeof(block); | |
280 | memset(&block, 0, len); | |
f2cd2deb FS |
281 | } |
282 | if (len == 0) | |
283 | break; | |
284 | ||
852c7d14 | 285 | ret = libusb_bulk_transfer(usb->devhdl, USB_EP_FPGA_BITSTREAM, |
1ed93110 | 286 | &block[0], len, &act_len, DEFAULT_TIMEOUT_MS); |
f2cd2deb | 287 | if (ret != 0) { |
91f73872 GS |
288 | sr_dbg("Cannot write FPGA bitstream, block %#x len %d: %s.", |
289 | pos, (int)len, libusb_error_name(ret)); | |
286b3e13 | 290 | ret = SR_ERR_IO; |
f2cd2deb FS |
291 | break; |
292 | } | |
293 | if (act_len != len) { | |
91f73872 GS |
294 | sr_dbg("Short write for FPGA bitstream, block %#x len %d: got %d.", |
295 | pos, (int)len, act_len); | |
286b3e13 | 296 | ret = SR_ERR_IO; |
f2cd2deb FS |
297 | break; |
298 | } | |
299 | pos += len; | |
300 | } | |
301 | sr_resource_close(drvc->sr_ctx, &bitstream); | |
5eb1b63d | 302 | if (ret != SR_OK) |
f2cd2deb | 303 | return ret; |
91f73872 GS |
304 | sr_info("FPGA bitstream upload (%" PRIu64 " bytes) done.", |
305 | bitstream.size); | |
f2cd2deb | 306 | |
d6f89d4b GS |
307 | return SR_OK; |
308 | } | |
309 | ||
310 | static int enable_fpga_bitstream(const struct sr_dev_inst *sdi) | |
311 | { | |
312 | int ret; | |
411ad77c | 313 | uint8_t resp; |
d6f89d4b | 314 | |
411ad77c GS |
315 | ret = ctrl_in(sdi, CMD_FPGA_INIT, 0x00, 0, &resp, sizeof(resp)); |
316 | if (ret != SR_OK) { | |
91f73872 | 317 | sr_err("Cannot read response after FPGA bitstream upload."); |
f2cd2deb FS |
318 | return ret; |
319 | } | |
411ad77c | 320 | if (resp != 0) { |
91f73872 | 321 | sr_err("Unexpected FPGA bitstream upload response, got 0x%02x, want 0.", |
411ad77c | 322 | resp); |
286b3e13 | 323 | return SR_ERR_DATA; |
3f48ab02 | 324 | } |
852c7d14 | 325 | g_usleep(30 * 1000); |
f2cd2deb | 326 | |
411ad77c GS |
327 | ret = ctrl_out(sdi, CMD_FPGA_ENABLE, 0x01, 0, NULL, 0); |
328 | if (ret != SR_OK) { | |
91f73872 | 329 | sr_err("Cannot enable FPGA after bitstream upload."); |
f2cd2deb FS |
330 | return ret; |
331 | } | |
852c7d14 | 332 | g_usleep(40 * 1000); |
d6f89d4b | 333 | |
f2cd2deb FS |
334 | return SR_OK; |
335 | } | |
336 | ||
337 | static int set_threshold_voltage(const struct sr_dev_inst *sdi, float voltage) | |
338 | { | |
f2cd2deb | 339 | int ret; |
1ed93110 | 340 | uint16_t duty_R79, duty_R56; |
3ab60908 | 341 | uint8_t buf[REG_PWM1 - REG_THRESHOLD]; /* Width of REG_THRESHOLD. */ |
f2ad79d1 KG |
342 | uint8_t *wrptr; |
343 | ||
96dc954e | 344 | /* Clamp threshold setting to valid range for LA2016. */ |
c35baf6e GS |
345 | if (voltage > LA2016_THR_VOLTAGE_MAX) { |
346 | voltage = LA2016_THR_VOLTAGE_MAX; | |
347 | } else if (voltage < -LA2016_THR_VOLTAGE_MAX) { | |
348 | voltage = -LA2016_THR_VOLTAGE_MAX; | |
f2ad79d1 KG |
349 | } |
350 | ||
351 | /* | |
96dc954e GS |
352 | * Two PWM output channels feed one DAC which generates a bias |
353 | * voltage, which offsets the input probe's voltage level, and | |
354 | * in combination with the FPGA pins' fixed threshold result in | |
355 | * a programmable input threshold from the user's perspective. | |
356 | * The PWM outputs can be seen on R79 and R56 respectively, the | |
357 | * frequency is 100kHz and the duty cycle varies. The R79 PWM | |
358 | * uses three discrete settings. The R56 PWM varies with desired | |
359 | * thresholds and depends on the R79 PWM configuration. See the | |
360 | * schematics comments which discuss the formulae. | |
f2ad79d1 KG |
361 | */ |
362 | if (voltage >= 2.9) { | |
96dc954e | 363 | duty_R79 = 0; /* PWM off (0V). */ |
f2ad79d1 | 364 | duty_R56 = (uint16_t)(302 * voltage - 363); |
c34f4a89 | 365 | } else if (voltage > -0.4) { |
96dc954e | 366 | duty_R79 = 0x00f2; /* 25% duty cycle. */ |
f2ad79d1 | 367 | duty_R56 = (uint16_t)(302 * voltage + 121); |
c34f4a89 GS |
368 | } else { |
369 | duty_R79 = 0x02d7; /* 72% duty cycle. */ | |
370 | duty_R56 = (uint16_t)(302 * voltage + 1090); | |
f2ad79d1 KG |
371 | } |
372 | ||
96dc954e | 373 | /* Clamp duty register values to sensible limits. */ |
f2ad79d1 KG |
374 | if (duty_R56 < 10) { |
375 | duty_R56 = 10; | |
1ed93110 | 376 | } else if (duty_R56 > 1100) { |
f2ad79d1 KG |
377 | duty_R56 = 1100; |
378 | } | |
379 | ||
91f73872 GS |
380 | sr_dbg("Set threshold voltage %.2fV.", voltage); |
381 | sr_dbg("Duty cycle values: R56 0x%04x, R79 0x%04x.", duty_R56, duty_R79); | |
f2ad79d1 KG |
382 | |
383 | wrptr = buf; | |
384 | write_u16le_inc(&wrptr, duty_R56); | |
385 | write_u16le_inc(&wrptr, duty_R79); | |
386 | ||
387 | ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_THRESHOLD, 0, buf, wrptr - buf); | |
f2cd2deb | 388 | if (ret != SR_OK) { |
91f73872 | 389 | sr_err("Cannot set threshold voltage %.2fV.", voltage); |
f2cd2deb FS |
390 | return ret; |
391 | } | |
f2cd2deb FS |
392 | |
393 | return SR_OK; | |
394 | } | |
395 | ||
08a49848 GS |
396 | /* |
397 | * Communicates a channel's configuration to the device after the | |
398 | * parameters may have changed. Configuration of one channel may | |
399 | * interfere with other channels since they share FPGA registers. | |
400 | */ | |
401 | static int set_pwm_config(const struct sr_dev_inst *sdi, size_t idx) | |
f2cd2deb | 402 | { |
08a49848 | 403 | static uint8_t reg_bases[] = { REG_PWM1, REG_PWM2, }; |
86d77b75 | 404 | |
f2cd2deb | 405 | struct dev_context *devc; |
08a49848 GS |
406 | struct pwm_setting *params; |
407 | uint8_t reg_base; | |
408 | double val_f; | |
409 | uint32_t val_u; | |
410 | uint32_t period, duty; | |
411 | size_t ch; | |
f2cd2deb | 412 | int ret; |
08a49848 GS |
413 | uint8_t enable_all, enable_cfg, reg_val; |
414 | uint8_t buf[REG_PWM2 - REG_PWM1]; /* Width of one REG_PWMx. */ | |
c3d40037 | 415 | uint8_t *wrptr; |
f2cd2deb FS |
416 | |
417 | devc = sdi->priv; | |
08a49848 GS |
418 | if (idx >= ARRAY_SIZE(devc->pwm_setting)) |
419 | return SR_ERR_ARG; | |
420 | params = &devc->pwm_setting[idx]; | |
421 | if (idx >= ARRAY_SIZE(reg_bases)) | |
422 | return SR_ERR_ARG; | |
423 | reg_base = reg_bases[idx]; | |
f2cd2deb | 424 | |
08a49848 GS |
425 | /* |
426 | * Map application's specs to hardware register values. Do math | |
427 | * in floating point initially, but convert to u32 eventually. | |
428 | */ | |
429 | sr_dbg("PWM config, app spec, ch %zu, en %d, freq %.1f, duty %.1f.", | |
430 | idx, params->enabled ? 1 : 0, params->freq, params->duty); | |
431 | val_f = PWM_CLOCK; | |
432 | val_f /= params->freq; | |
433 | val_u = val_f; | |
434 | period = val_u; | |
435 | val_f = period; | |
436 | val_f *= params->duty; | |
437 | val_f /= 100.0; | |
438 | val_f += 0.5; | |
439 | val_u = val_f; | |
440 | duty = val_u; | |
441 | sr_dbg("PWM config, reg 0x%04x, freq %u, duty %u.", | |
442 | (unsigned)reg_base, (unsigned)period, (unsigned)duty); | |
443 | ||
444 | /* Get the "enabled" state of all supported PWM channels. */ | |
445 | enable_all = 0; | |
446 | for (ch = 0; ch < ARRAY_SIZE(devc->pwm_setting); ch++) { | |
447 | if (!devc->pwm_setting[ch].enabled) | |
448 | continue; | |
449 | enable_all |= 1U << ch; | |
f2cd2deb | 450 | } |
08a49848 GS |
451 | enable_cfg = 1U << idx; |
452 | sr_spew("PWM config, enable all 0x%02hhx, cfg 0x%02hhx.", | |
453 | enable_all, enable_cfg); | |
f2cd2deb | 454 | |
08a49848 GS |
455 | /* |
456 | * Disable the to-get-configured channel before its parameters | |
457 | * will change. Or disable and exit when the channel is supposed | |
458 | * to get turned off. | |
459 | */ | |
460 | sr_spew("PWM config, disabling before param change."); | |
461 | reg_val = enable_all & ~enable_cfg; | |
462 | ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_PWM_EN, 0, | |
463 | ®_val, sizeof(reg_val)); | |
f2cd2deb | 464 | if (ret != SR_OK) { |
08a49848 | 465 | sr_err("Cannot adjust PWM enabled state."); |
f2cd2deb FS |
466 | return ret; |
467 | } | |
08a49848 GS |
468 | if (!params->enabled) |
469 | return SR_OK; | |
86d77b75 | 470 | |
08a49848 GS |
471 | /* Write register values to device. */ |
472 | sr_spew("PWM config, sending new parameters."); | |
473 | wrptr = buf; | |
474 | write_u32le_inc(&wrptr, period); | |
475 | write_u32le_inc(&wrptr, duty); | |
476 | ret = ctrl_out(sdi, CMD_FPGA_SPI, reg_base, 0, buf, wrptr - buf); | |
477 | if (ret != SR_OK) { | |
478 | sr_err("Cannot change PWM parameters."); | |
f2cd2deb | 479 | return ret; |
08a49848 | 480 | } |
f2cd2deb | 481 | |
08a49848 GS |
482 | /* Enable configured channel after write completion. */ |
483 | sr_spew("PWM config, enabling after param change."); | |
484 | reg_val = enable_all | enable_cfg; | |
485 | ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_PWM_EN, 0, | |
486 | ®_val, sizeof(reg_val)); | |
487 | if (ret != SR_OK) { | |
488 | sr_err("Cannot adjust PWM enabled state."); | |
f2cd2deb | 489 | return ret; |
08a49848 | 490 | } |
f2cd2deb FS |
491 | |
492 | return SR_OK; | |
493 | } | |
494 | ||
4276ca94 | 495 | static uint32_t get_channels_mask(const struct sr_dev_inst *sdi) |
ea436ba7 | 496 | { |
4276ca94 | 497 | uint32_t channels; |
ea436ba7 GS |
498 | GSList *l; |
499 | struct sr_channel *ch; | |
500 | ||
501 | channels = 0; | |
502 | for (l = sdi->channels; l; l = l->next) { | |
503 | ch = l->data; | |
504 | if (ch->type != SR_CHANNEL_LOGIC) | |
505 | continue; | |
506 | if (!ch->enabled) | |
507 | continue; | |
508 | channels |= 1UL << ch->index; | |
509 | } | |
510 | ||
511 | return channels; | |
512 | } | |
513 | ||
f2cd2deb FS |
514 | static int set_trigger_config(const struct sr_dev_inst *sdi) |
515 | { | |
516 | struct dev_context *devc; | |
517 | struct sr_trigger *trigger; | |
edb13f41 | 518 | struct trigger_cfg { |
972d191b GS |
519 | uint32_t channels; /* Actually: Enabled channels? */ |
520 | uint32_t enabled; /* Actually: Triggering channels? */ | |
edb13f41 GS |
521 | uint32_t level; |
522 | uint32_t high_or_falling; | |
523 | } cfg; | |
f2cd2deb FS |
524 | GSList *stages; |
525 | GSList *channel; | |
526 | struct sr_trigger_stage *stage1; | |
527 | struct sr_trigger_match *match; | |
4276ca94 | 528 | uint32_t ch_mask; |
f2cd2deb | 529 | int ret; |
3ab60908 | 530 | uint8_t buf[REG_UNKNOWN_30 - REG_TRIGGER]; /* Width of REG_TRIGGER. */ |
c3d40037 | 531 | uint8_t *wrptr; |
f2cd2deb FS |
532 | |
533 | devc = sdi->priv; | |
534 | trigger = sr_session_trigger_get(sdi->session); | |
535 | ||
536 | memset(&cfg, 0, sizeof(cfg)); | |
537 | ||
ea436ba7 | 538 | cfg.channels = get_channels_mask(sdi); |
f2cd2deb FS |
539 | |
540 | if (trigger && trigger->stages) { | |
541 | stages = trigger->stages; | |
542 | stage1 = stages->data; | |
543 | if (stages->next) { | |
544 | sr_err("Only one trigger stage supported for now."); | |
286b3e13 | 545 | return SR_ERR_ARG; |
f2cd2deb FS |
546 | } |
547 | channel = stage1->matches; | |
548 | while (channel) { | |
549 | match = channel->data; | |
cf057ac4 | 550 | ch_mask = 1UL << match->channel->index; |
f2cd2deb FS |
551 | |
552 | switch (match->match) { | |
553 | case SR_TRIGGER_ZERO: | |
554 | cfg.level |= ch_mask; | |
555 | cfg.high_or_falling &= ~ch_mask; | |
556 | break; | |
557 | case SR_TRIGGER_ONE: | |
558 | cfg.level |= ch_mask; | |
559 | cfg.high_or_falling |= ch_mask; | |
560 | break; | |
561 | case SR_TRIGGER_RISING: | |
562 | if ((cfg.enabled & ~cfg.level)) { | |
91f73872 | 563 | sr_err("Device only supports one edge trigger."); |
286b3e13 | 564 | return SR_ERR_ARG; |
f2cd2deb FS |
565 | } |
566 | cfg.level &= ~ch_mask; | |
567 | cfg.high_or_falling &= ~ch_mask; | |
568 | break; | |
569 | case SR_TRIGGER_FALLING: | |
570 | if ((cfg.enabled & ~cfg.level)) { | |
91f73872 | 571 | sr_err("Device only supports one edge trigger."); |
286b3e13 | 572 | return SR_ERR_ARG; |
f2cd2deb FS |
573 | } |
574 | cfg.level &= ~ch_mask; | |
575 | cfg.high_or_falling |= ch_mask; | |
576 | break; | |
577 | default: | |
91f73872 | 578 | sr_err("Unknown trigger condition."); |
286b3e13 | 579 | return SR_ERR_ARG; |
f2cd2deb FS |
580 | } |
581 | cfg.enabled |= ch_mask; | |
582 | channel = channel->next; | |
583 | } | |
584 | } | |
91f73872 | 585 | sr_dbg("Set trigger config: " |
972d191b | 586 | "enabled-channels 0x%04x, triggering-channels 0x%04x, " |
91f73872 GS |
587 | "level-triggered 0x%04x, high/falling 0x%04x.", |
588 | cfg.channels, cfg.enabled, cfg.level, cfg.high_or_falling); | |
f2cd2deb | 589 | |
cf057ac4 | 590 | devc->trigger_involved = cfg.enabled != 0; |
f2cd2deb | 591 | |
c3d40037 HK |
592 | wrptr = buf; |
593 | write_u32le_inc(&wrptr, cfg.channels); | |
594 | write_u32le_inc(&wrptr, cfg.enabled); | |
595 | write_u32le_inc(&wrptr, cfg.level); | |
596 | write_u32le_inc(&wrptr, cfg.high_or_falling); | |
852c7d14 GS |
597 | /* TODO |
598 | * Comment on this literal 16. Origin, meaning? Cannot be the | |
599 | * register offset, nor the transfer length. Is it a channels | |
600 | * count that is relevant for 16 and 32 channel models? Is it | |
601 | * an obsolete experiment? | |
602 | */ | |
42f6dd55 | 603 | ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_TRIGGER, 16, buf, wrptr - buf); |
f2cd2deb | 604 | if (ret != SR_OK) { |
91f73872 | 605 | sr_err("Cannot setup trigger configuration."); |
f2cd2deb FS |
606 | return ret; |
607 | } | |
608 | ||
609 | return SR_OK; | |
610 | } | |
611 | ||
612 | static int set_sample_config(const struct sr_dev_inst *sdi) | |
613 | { | |
614 | struct dev_context *devc; | |
d8fbfcd9 | 615 | uint64_t min_samplerate, eff_samplerate; |
adab4d91 | 616 | uint16_t divider_u16; |
a38f0f5e | 617 | uint64_t limit_samples; |
adab4d91 GS |
618 | uint64_t pre_trigger_samples; |
619 | uint64_t pre_trigger_memory; | |
620 | uint8_t buf[REG_TRIGGER - REG_SAMPLING]; /* Width of REG_SAMPLING. */ | |
c3d40037 | 621 | uint8_t *wrptr; |
adab4d91 | 622 | int ret; |
f2cd2deb FS |
623 | |
624 | devc = sdi->priv; | |
f2cd2deb | 625 | |
edc0b015 | 626 | if (devc->samplerate > devc->model->samplerate) { |
91f73872 | 627 | sr_err("Too high a sample rate: %" PRIu64 ".", |
edc0b015 | 628 | devc->samplerate); |
ea436ba7 GS |
629 | return SR_ERR_ARG; |
630 | } | |
d8fbfcd9 GS |
631 | min_samplerate = devc->model->samplerate; |
632 | min_samplerate /= 65536; | |
edc0b015 | 633 | if (devc->samplerate < min_samplerate) { |
ea436ba7 | 634 | sr_err("Too low a sample rate: %" PRIu64 ".", |
edc0b015 | 635 | devc->samplerate); |
ea436ba7 | 636 | return SR_ERR_ARG; |
f2cd2deb | 637 | } |
edc0b015 | 638 | divider_u16 = devc->model->samplerate / devc->samplerate; |
d8fbfcd9 | 639 | eff_samplerate = devc->model->samplerate / divider_u16; |
f2cd2deb | 640 | |
a38f0f5e GS |
641 | ret = sr_sw_limits_get_remain(&devc->sw_limits, |
642 | &limit_samples, NULL, NULL, NULL); | |
643 | if (ret != SR_OK) { | |
644 | sr_err("Cannot get acquisition limits."); | |
645 | return ret; | |
f2cd2deb | 646 | } |
a38f0f5e | 647 | if (limit_samples > LA2016_NUM_SAMPLES_MAX) { |
d8fbfcd9 GS |
648 | sr_warn("Too high a sample depth: %" PRIu64 ", capping.", |
649 | limit_samples); | |
650 | limit_samples = LA2016_NUM_SAMPLES_MAX; | |
a38f0f5e | 651 | } |
d8fbfcd9 GS |
652 | if (limit_samples == 0) { |
653 | limit_samples = LA2016_NUM_SAMPLES_MAX; | |
654 | sr_dbg("Passing %" PRIu64 " to HW for unlimited samples.", | |
655 | limit_samples); | |
ea436ba7 | 656 | } |
f2cd2deb | 657 | |
adab4d91 GS |
658 | /* |
659 | * The acquisition configuration communicates "pre-trigger" | |
660 | * specs in several formats. sigrok users provide a percentage | |
661 | * (0-100%), which translates to a pre-trigger samples count | |
662 | * (assuming that a total samples count limit was specified). | |
663 | * The device supports hardware compression, which depends on | |
664 | * slowly changing input data to be effective. Fast changing | |
665 | * input data may occupy more space in sample memory than its | |
666 | * uncompressed form would. This is why a third parameter can | |
667 | * limit the amount of sample memory to use for pre-trigger | |
668 | * data. Only the upper 24 bits of that memory size spec get | |
669 | * communicated to the device (written to its FPGA register). | |
d8fbfcd9 GS |
670 | * |
671 | * TODO Determine whether the pre-trigger memory size gets | |
672 | * specified in samples or in bytes. A previous implementation | |
673 | * suggests bytes but this is suspicious when every other spec | |
674 | * is in terms of samples. | |
adab4d91 | 675 | */ |
d8fbfcd9 GS |
676 | if (devc->trigger_involved) { |
677 | pre_trigger_samples = limit_samples; | |
678 | pre_trigger_samples *= devc->capture_ratio; | |
679 | pre_trigger_samples /= 100; | |
680 | pre_trigger_memory = devc->model->memory_bits; | |
681 | pre_trigger_memory *= UINT64_C(1024 * 1024 * 1024); | |
682 | pre_trigger_memory /= 8; /* devc->model->channel_count ? */ | |
683 | pre_trigger_memory *= devc->capture_ratio; | |
684 | pre_trigger_memory /= 100; | |
685 | } else { | |
686 | sr_dbg("No trigger setup, skipping pre-trigger config."); | |
687 | pre_trigger_samples = 1; | |
688 | pre_trigger_memory = 0; | |
689 | } | |
690 | /* Ensure non-zero value after LSB shift out in HW reg. */ | |
691 | if (pre_trigger_memory < 0x100) { | |
692 | pre_trigger_memory = 0x100; | |
693 | } | |
f2cd2deb | 694 | |
adab4d91 | 695 | sr_dbg("Set sample config: %" PRIu64 "kHz, %" PRIu64 " samples.", |
d8fbfcd9 | 696 | eff_samplerate / SR_KHZ(1), limit_samples); |
adab4d91 GS |
697 | sr_dbg("Capture ratio %" PRIu64 "%%, count %" PRIu64 ", mem %" PRIu64 ".", |
698 | devc->capture_ratio, pre_trigger_samples, pre_trigger_memory); | |
f2cd2deb | 699 | |
b1a17c1a GS |
700 | /* |
701 | * The acquisition configuration occupies a total of 16 bytes: | |
702 | * - A 34bit total samples count limit (up to 10 billions) that | |
703 | * is kept in a 40bit register. | |
704 | * - A 34bit pre-trigger samples count limit (up to 10 billions) | |
705 | * in another 40bit register. | |
706 | * - A 32bit pre-trigger memory space limit (in bytes) of which | |
707 | * the upper 24bits are kept in an FPGA register. | |
708 | * - A 16bit clock divider which gets applied to the maximum | |
709 | * samplerate of the device. | |
710 | * - An 8bit register of unknown meaning. Currently always 0. | |
711 | */ | |
c3d40037 | 712 | wrptr = buf; |
a38f0f5e | 713 | write_u40le_inc(&wrptr, limit_samples); |
b1a17c1a GS |
714 | write_u40le_inc(&wrptr, pre_trigger_samples); |
715 | write_u24le_inc(&wrptr, pre_trigger_memory >> 8); | |
adab4d91 | 716 | write_u16le_inc(&wrptr, divider_u16); |
0d8e1ffc | 717 | write_u8_inc(&wrptr, 0); |
42f6dd55 | 718 | ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_SAMPLING, 0, buf, wrptr - buf); |
f2cd2deb | 719 | if (ret != SR_OK) { |
91f73872 | 720 | sr_err("Cannot setup acquisition configuration."); |
f2cd2deb FS |
721 | return ret; |
722 | } | |
723 | ||
724 | return SR_OK; | |
725 | } | |
726 | ||
96dc954e GS |
727 | /* |
728 | * FPGA register REG_RUN holds the run state (u16le format). Bit fields | |
729 | * of interest: | |
730 | * bit 0: value 1 = idle | |
731 | * bit 1: value 1 = writing to SDRAM | |
732 | * bit 2: value 0 = waiting for trigger, 1 = trigger seen | |
733 | * bit 3: value 0 = pretrigger sampling, 1 = posttrigger sampling | |
734 | * The meaning of other bit fields is unknown. | |
7601dca7 | 735 | * |
96dc954e | 736 | * Typical values in order of appearance during execution: |
b711fd8e GS |
737 | * 0x85e1: idle, no acquisition pending |
738 | * IDLE set, TRGD don't care, POST don't care; DRAM don't care | |
739 | * "In idle state." Takes precedence over all others. | |
96dc954e GS |
740 | * 0x85e2: pre-sampling, samples before the trigger position, |
741 | * when capture ratio > 0% | |
b711fd8e GS |
742 | * IDLE clear, TRGD clear, POST clear; DRAM don't care |
743 | * "Not idle any more, no post yet, not triggered yet." | |
96dc954e GS |
744 | * 0x85ea: pre-sampling complete, now waiting for the trigger |
745 | * (whilst sampling continuously) | |
b711fd8e GS |
746 | * IDLE clear, TRGD clear, POST set; DRAM don't care |
747 | * "Post set thus after pre, not triggered yet" | |
96dc954e | 748 | * 0x85ee: trigger seen, capturing post-trigger samples, running |
b711fd8e GS |
749 | * IDLE clear, TRGD set, POST set; DRAM don't care |
750 | * "Triggered and in post, not idle yet." | |
96dc954e | 751 | * 0x85ed: idle |
b711fd8e GS |
752 | * IDLE set, TRGD don't care, POST don't care; DRAM don't care |
753 | * "In idle state." TRGD/POST don't care, same meaning as above. | |
f2cd2deb | 754 | */ |
b711fd8e GS |
755 | static const uint16_t runstate_mask_idle = RUNSTATE_IDLE_BIT; |
756 | static const uint16_t runstate_patt_idle = RUNSTATE_IDLE_BIT; | |
757 | static const uint16_t runstate_mask_step = | |
758 | RUNSTATE_IDLE_BIT | RUNSTATE_TRGD_BIT | RUNSTATE_POST_BIT; | |
759 | static const uint16_t runstate_patt_pre_trig = 0; | |
760 | static const uint16_t runstate_patt_wait_trig = RUNSTATE_POST_BIT; | |
761 | static const uint16_t runstate_patt_post_trig = | |
762 | RUNSTATE_TRGD_BIT | RUNSTATE_POST_BIT; | |
763 | ||
f2cd2deb FS |
764 | static uint16_t run_state(const struct sr_dev_inst *sdi) |
765 | { | |
21d68fd9 GS |
766 | static uint16_t previous_state; |
767 | ||
f2cd2deb | 768 | int ret; |
21d68fd9 | 769 | uint16_t state; |
3ab60908 | 770 | uint8_t buff[REG_PWM_EN - REG_RUN]; /* Width of REG_RUN. */ |
21d68fd9 GS |
771 | const uint8_t *rdptr; |
772 | const char *label; | |
f2cd2deb | 773 | |
411ad77c GS |
774 | ret = ctrl_in(sdi, CMD_FPGA_SPI, REG_RUN, 0, buff, sizeof(state)); |
775 | if (ret != SR_OK) { | |
91f73872 | 776 | sr_err("Cannot read run state."); |
f2cd2deb FS |
777 | return ret; |
778 | } | |
21d68fd9 GS |
779 | rdptr = buff; |
780 | state = read_u16le_inc(&rdptr); | |
7601dca7 | 781 | |
96dc954e GS |
782 | /* |
783 | * Avoid flooding the log, only dump values as they change. | |
784 | * The routine is called about every 50ms. | |
7601dca7 | 785 | */ |
b711fd8e GS |
786 | if (state == previous_state) |
787 | return state; | |
788 | ||
789 | previous_state = state; | |
790 | label = NULL; | |
791 | if ((state & runstate_mask_idle) == runstate_patt_idle) | |
792 | label = "idle"; | |
793 | if ((state & runstate_mask_step) == runstate_patt_pre_trig) | |
794 | label = "pre-trigger sampling"; | |
795 | if ((state & runstate_mask_step) == runstate_patt_wait_trig) | |
796 | label = "sampling, waiting for trigger"; | |
797 | if ((state & runstate_mask_step) == runstate_patt_post_trig) | |
798 | label = "post-trigger sampling"; | |
799 | if (label && *label) | |
800 | sr_dbg("Run state: 0x%04x (%s).", state, label); | |
801 | else | |
802 | sr_dbg("Run state: 0x%04x.", state); | |
f2cd2deb FS |
803 | |
804 | return state; | |
805 | } | |
806 | ||
cf057ac4 | 807 | static int la2016_is_idle(const struct sr_dev_inst *sdi) |
c34f4a89 GS |
808 | { |
809 | uint16_t state; | |
810 | ||
811 | state = run_state(sdi); | |
b711fd8e | 812 | if ((state & runstate_mask_idle) == runstate_patt_idle) |
c34f4a89 GS |
813 | return 1; |
814 | ||
815 | return 0; | |
816 | } | |
817 | ||
818 | static int set_run_mode(const struct sr_dev_inst *sdi, uint8_t mode) | |
f2cd2deb FS |
819 | { |
820 | int ret; | |
821 | ||
411ad77c GS |
822 | ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_RUN, 0, &mode, sizeof(mode)); |
823 | if (ret != SR_OK) { | |
c34f4a89 | 824 | sr_err("Cannot configure run mode %d.", mode); |
f2cd2deb FS |
825 | return ret; |
826 | } | |
827 | ||
828 | return SR_OK; | |
829 | } | |
830 | ||
831 | static int get_capture_info(const struct sr_dev_inst *sdi) | |
832 | { | |
833 | struct dev_context *devc; | |
834 | int ret; | |
3ab60908 | 835 | uint8_t buf[REG_TRIGGER - REG_SAMPLING]; /* Width of REG_SAMPLING. */ |
c3d40037 | 836 | const uint8_t *rdptr; |
f2cd2deb FS |
837 | |
838 | devc = sdi->priv; | |
839 | ||
411ad77c GS |
840 | ret = ctrl_in(sdi, CMD_FPGA_SPI, REG_SAMPLING, 0, buf, sizeof(buf)); |
841 | if (ret != SR_OK) { | |
91f73872 | 842 | sr_err("Cannot read capture info."); |
f2cd2deb FS |
843 | return ret; |
844 | } | |
c3d40037 HK |
845 | |
846 | rdptr = buf; | |
847 | devc->info.n_rep_packets = read_u32le_inc(&rdptr); | |
848 | devc->info.n_rep_packets_before_trigger = read_u32le_inc(&rdptr); | |
849 | devc->info.write_pos = read_u32le_inc(&rdptr); | |
f2cd2deb | 850 | |
cf057ac4 | 851 | sr_dbg("Capture info: n_rep_packets: 0x%08x/%d, before_trigger: 0x%08x/%d, write_pos: 0x%08x/%d.", |
1ed93110 GS |
852 | devc->info.n_rep_packets, devc->info.n_rep_packets, |
853 | devc->info.n_rep_packets_before_trigger, | |
854 | devc->info.n_rep_packets_before_trigger, | |
855 | devc->info.write_pos, devc->info.write_pos); | |
f2cd2deb | 856 | |
038e65c1 GS |
857 | if (devc->info.n_rep_packets % devc->packets_per_chunk) { |
858 | sr_warn("Unexpected packets count %lu, not a multiple of %lu.", | |
852c7d14 | 859 | (unsigned long)devc->info.n_rep_packets, |
038e65c1 | 860 | (unsigned long)devc->packets_per_chunk); |
91f73872 | 861 | } |
f2cd2deb FS |
862 | |
863 | return SR_OK; | |
864 | } | |
865 | ||
d466f61c GS |
866 | SR_PRIV int la2016_upload_firmware(const struct sr_dev_inst *sdi, |
867 | struct sr_context *sr_ctx, libusb_device *dev, uint16_t product_id) | |
f2cd2deb | 868 | { |
d466f61c GS |
869 | struct dev_context *devc; |
870 | char *fw_file; | |
871 | int ret; | |
872 | ||
873 | devc = sdi ? sdi->priv : NULL; | |
874 | ||
875 | fw_file = g_strdup_printf(MCU_FWFILE_FMT, product_id); | |
876 | sr_info("USB PID %04hx, MCU firmware '%s'.", product_id, fw_file); | |
877 | ||
878 | ret = ezusb_upload_firmware(sr_ctx, dev, USB_CONFIGURATION, fw_file); | |
879 | if (ret != SR_OK) { | |
880 | g_free(fw_file); | |
881 | return ret; | |
882 | } | |
883 | ||
884 | if (devc) { | |
885 | devc->mcu_firmware = fw_file; | |
886 | fw_file = NULL; | |
887 | } | |
888 | g_free(fw_file); | |
889 | ||
890 | return SR_OK; | |
f2cd2deb FS |
891 | } |
892 | ||
9270f8f4 GS |
893 | SR_PRIV int la2016_setup_acquisition(const struct sr_dev_inst *sdi, |
894 | double voltage) | |
f2cd2deb | 895 | { |
f2cd2deb FS |
896 | int ret; |
897 | uint8_t cmd; | |
898 | ||
9270f8f4 | 899 | ret = set_threshold_voltage(sdi, voltage); |
f2cd2deb FS |
900 | if (ret != SR_OK) |
901 | return ret; | |
902 | ||
972d191b | 903 | cmd = CAPTMODE_TO_RAM; |
411ad77c GS |
904 | ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_CAPT_MODE, 0, &cmd, sizeof(cmd)); |
905 | if (ret != SR_OK) { | |
91f73872 | 906 | sr_err("Cannot send command to stop sampling."); |
f2cd2deb FS |
907 | return ret; |
908 | } | |
909 | ||
910 | ret = set_trigger_config(sdi); | |
911 | if (ret != SR_OK) | |
912 | return ret; | |
913 | ||
914 | ret = set_sample_config(sdi); | |
915 | if (ret != SR_OK) | |
916 | return ret; | |
917 | ||
918 | return SR_OK; | |
919 | } | |
920 | ||
921 | SR_PRIV int la2016_start_acquisition(const struct sr_dev_inst *sdi) | |
922 | { | |
3ebc1cb2 GS |
923 | int ret; |
924 | ||
852c7d14 | 925 | ret = set_run_mode(sdi, RUNMODE_RUN); |
3ebc1cb2 GS |
926 | if (ret != SR_OK) |
927 | return ret; | |
928 | ||
929 | return SR_OK; | |
f2cd2deb FS |
930 | } |
931 | ||
3ebc1cb2 | 932 | static int la2016_stop_acquisition(const struct sr_dev_inst *sdi) |
f2cd2deb | 933 | { |
3ebc1cb2 GS |
934 | int ret; |
935 | ||
852c7d14 | 936 | ret = set_run_mode(sdi, RUNMODE_HALT); |
3ebc1cb2 GS |
937 | if (ret != SR_OK) |
938 | return ret; | |
939 | ||
940 | return SR_OK; | |
f2cd2deb FS |
941 | } |
942 | ||
943 | SR_PRIV int la2016_abort_acquisition(const struct sr_dev_inst *sdi) | |
944 | { | |
3ebc1cb2 GS |
945 | int ret; |
946 | struct dev_context *devc; | |
947 | ||
948 | ret = la2016_stop_acquisition(sdi); | |
949 | if (ret != SR_OK) | |
950 | return ret; | |
951 | ||
952 | devc = sdi ? sdi->priv : NULL; | |
953 | if (devc && devc->transfer) | |
954 | libusb_cancel_transfer(devc->transfer); | |
955 | ||
956 | return SR_OK; | |
f2cd2deb FS |
957 | } |
958 | ||
cf057ac4 | 959 | static int la2016_start_download(const struct sr_dev_inst *sdi, |
1ed93110 | 960 | libusb_transfer_cb_fn cb) |
f2cd2deb FS |
961 | { |
962 | struct dev_context *devc; | |
963 | struct sr_usb_dev_inst *usb; | |
964 | int ret; | |
3ab60908 | 965 | uint8_t wrbuf[REG_SAMPLING - REG_BULK]; /* Width of REG_BULK. */ |
c3d40037 | 966 | uint8_t *wrptr; |
f2cd2deb FS |
967 | uint32_t to_read; |
968 | uint8_t *buffer; | |
969 | ||
970 | devc = sdi->priv; | |
971 | usb = sdi->conn; | |
972 | ||
411ad77c GS |
973 | ret = get_capture_info(sdi); |
974 | if (ret != SR_OK) | |
f2cd2deb FS |
975 | return ret; |
976 | ||
038e65c1 GS |
977 | devc->n_transfer_packets_to_read = devc->info.n_rep_packets; |
978 | devc->n_transfer_packets_to_read /= devc->packets_per_chunk; | |
979 | devc->n_bytes_to_read = devc->n_transfer_packets_to_read; | |
980 | devc->n_bytes_to_read *= TRANSFER_PACKET_LENGTH; | |
f2cd2deb FS |
981 | devc->read_pos = devc->info.write_pos - devc->n_bytes_to_read; |
982 | devc->n_reps_until_trigger = devc->info.n_rep_packets_before_trigger; | |
983 | ||
91f73872 | 984 | sr_dbg("Want to read %u xfer-packets starting from pos %" PRIu32 ".", |
1ed93110 | 985 | devc->n_transfer_packets_to_read, devc->read_pos); |
f2cd2deb | 986 | |
411ad77c GS |
987 | ret = ctrl_out(sdi, CMD_BULK_RESET, 0x00, 0, NULL, 0); |
988 | if (ret != SR_OK) { | |
91f73872 | 989 | sr_err("Cannot reset USB bulk state."); |
f2cd2deb FS |
990 | return ret; |
991 | } | |
91f73872 GS |
992 | sr_dbg("Will read from 0x%08lx, 0x%08x bytes.", |
993 | (unsigned long)devc->read_pos, devc->n_bytes_to_read); | |
c3d40037 HK |
994 | wrptr = wrbuf; |
995 | write_u32le_inc(&wrptr, devc->read_pos); | |
996 | write_u32le_inc(&wrptr, devc->n_bytes_to_read); | |
411ad77c GS |
997 | ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_BULK, 0, wrbuf, wrptr - wrbuf); |
998 | if (ret != SR_OK) { | |
91f73872 | 999 | sr_err("Cannot send USB bulk config."); |
f2cd2deb FS |
1000 | return ret; |
1001 | } | |
411ad77c GS |
1002 | ret = ctrl_out(sdi, CMD_BULK_START, 0x00, 0, NULL, 0); |
1003 | if (ret != SR_OK) { | |
91f73872 | 1004 | sr_err("Cannot unblock USB bulk transfers."); |
f2cd2deb FS |
1005 | return ret; |
1006 | } | |
1007 | ||
96dc954e GS |
1008 | /* |
1009 | * Pick a buffer size for all USB transfers. The buffer size | |
1010 | * must be a multiple of the endpoint packet size. And cannot | |
1011 | * exceed a maximum value. | |
1012 | */ | |
f2cd2deb | 1013 | to_read = devc->n_bytes_to_read; |
96dc954e GS |
1014 | if (to_read >= LA2016_USB_BUFSZ) /* Multiple transfers. */ |
1015 | to_read = LA2016_USB_BUFSZ; | |
418dfd7e GS |
1016 | to_read += LA2016_EP6_PKTSZ - 1; |
1017 | to_read /= LA2016_EP6_PKTSZ; | |
1018 | to_read *= LA2016_EP6_PKTSZ; | |
f2cd2deb FS |
1019 | buffer = g_try_malloc(to_read); |
1020 | if (!buffer) { | |
91f73872 GS |
1021 | sr_dbg("USB bulk transfer size %d bytes.", (int)to_read); |
1022 | sr_err("Cannot allocate buffer for USB bulk transfer."); | |
f2cd2deb FS |
1023 | return SR_ERR_MALLOC; |
1024 | } | |
1025 | ||
1026 | devc->transfer = libusb_alloc_transfer(0); | |
852c7d14 GS |
1027 | libusb_fill_bulk_transfer(devc->transfer, |
1028 | usb->devhdl, USB_EP_CAPTURE_DATA | LIBUSB_ENDPOINT_IN, | |
411ad77c | 1029 | buffer, to_read, cb, (void *)sdi, DEFAULT_TIMEOUT_MS); |
f2cd2deb | 1030 | |
411ad77c GS |
1031 | ret = libusb_submit_transfer(devc->transfer); |
1032 | if (ret != 0) { | |
91f73872 | 1033 | sr_err("Cannot submit USB transfer: %s.", libusb_error_name(ret)); |
f2cd2deb FS |
1034 | libusb_free_transfer(devc->transfer); |
1035 | devc->transfer = NULL; | |
1036 | g_free(buffer); | |
286b3e13 | 1037 | return SR_ERR_IO; |
f2cd2deb FS |
1038 | } |
1039 | ||
1040 | return SR_OK; | |
1041 | } | |
1042 | ||
480efba2 GS |
1043 | /* |
1044 | * A chunk (received via USB) contains a number of transfers (USB length | |
1045 | * divided by 16) which contain a number of packets (5 per transfer) which | |
1046 | * contain a number of samples (8bit repeat count per 16bit sample data). | |
1047 | */ | |
dfac9592 | 1048 | static void send_chunk(struct sr_dev_inst *sdi, |
480efba2 | 1049 | const uint8_t *packets, size_t num_xfers) |
dfac9592 GS |
1050 | { |
1051 | struct dev_context *devc; | |
480efba2 | 1052 | size_t num_pkts; |
dfac9592 | 1053 | const uint8_t *rp; |
4276ca94 | 1054 | uint32_t sample_value; |
480efba2 GS |
1055 | size_t repetitions; |
1056 | uint8_t sample_buff[sizeof(sample_value)]; | |
dfac9592 GS |
1057 | |
1058 | devc = sdi->priv; | |
1059 | ||
a38f0f5e GS |
1060 | /* Ignore incoming USB data after complete sample data download. */ |
1061 | if (devc->download_finished) | |
1062 | return; | |
dfac9592 | 1063 | |
cf057ac4 | 1064 | if (devc->trigger_involved && !devc->trigger_marked && devc->info.n_rep_packets_before_trigger == 0) { |
a38f0f5e | 1065 | feed_queue_logic_send_trigger(devc->feed_queue); |
cf057ac4 | 1066 | devc->trigger_marked = TRUE; |
dfac9592 GS |
1067 | } |
1068 | ||
4276ca94 | 1069 | sample_value = 0; |
dfac9592 | 1070 | rp = packets; |
480efba2 | 1071 | while (num_xfers--) { |
038e65c1 | 1072 | num_pkts = devc->packets_per_chunk; |
480efba2 | 1073 | while (num_pkts--) { |
dfac9592 | 1074 | |
4276ca94 GS |
1075 | /* TODO Verify 32channel layout. */ |
1076 | if (devc->model->channel_count == 32) | |
1077 | sample_value = read_u32le_inc(&rp); | |
1078 | else if (devc->model->channel_count == 16) | |
1079 | sample_value = read_u16le_inc(&rp); | |
dfac9592 | 1080 | repetitions = read_u8_inc(&rp); |
dfac9592 | 1081 | |
dfac9592 | 1082 | devc->total_samples += repetitions; |
480efba2 | 1083 | |
4276ca94 | 1084 | write_u32le(sample_buff, sample_value); |
a38f0f5e GS |
1085 | feed_queue_logic_submit(devc->feed_queue, |
1086 | sample_buff, repetitions); | |
1087 | sr_sw_limits_update_samples_read(&devc->sw_limits, | |
1088 | repetitions); | |
480efba2 | 1089 | |
cf057ac4 GS |
1090 | if (devc->trigger_involved && !devc->trigger_marked) { |
1091 | if (!--devc->n_reps_until_trigger) { | |
a38f0f5e | 1092 | feed_queue_logic_send_trigger(devc->feed_queue); |
cf057ac4 | 1093 | devc->trigger_marked = TRUE; |
91f73872 | 1094 | sr_dbg("Trigger position after %" PRIu64 " samples, %.6fms.", |
1ed93110 | 1095 | devc->total_samples, |
edc0b015 | 1096 | (double)devc->total_samples / devc->samplerate * 1e3); |
dfac9592 GS |
1097 | } |
1098 | } | |
1099 | } | |
1100 | (void)read_u8_inc(&rp); /* Skip sequence number. */ | |
1101 | } | |
a38f0f5e GS |
1102 | |
1103 | if (!devc->download_finished && sr_sw_limits_check(&devc->sw_limits)) { | |
1104 | sr_dbg("Acquisition limit reached."); | |
1105 | devc->download_finished = TRUE; | |
1106 | } | |
1107 | if (devc->download_finished) { | |
1108 | sr_dbg("Download finished, flushing session feed queue."); | |
1109 | feed_queue_logic_flush(devc->feed_queue); | |
dfac9592 | 1110 | } |
a38f0f5e | 1111 | sr_dbg("Total samples after chunk: %" PRIu64 ".", devc->total_samples); |
dfac9592 GS |
1112 | } |
1113 | ||
1114 | static void LIBUSB_CALL receive_transfer(struct libusb_transfer *transfer) | |
1115 | { | |
1116 | struct sr_dev_inst *sdi; | |
1117 | struct dev_context *devc; | |
1118 | struct sr_usb_dev_inst *usb; | |
a38f0f5e | 1119 | size_t num_xfers; |
dfac9592 GS |
1120 | int ret; |
1121 | ||
1122 | sdi = transfer->user_data; | |
1123 | devc = sdi->priv; | |
1124 | usb = sdi->conn; | |
1125 | ||
1126 | sr_dbg("receive_transfer(): status %s received %d bytes.", | |
1ed93110 | 1127 | libusb_error_name(transfer->status), transfer->actual_length); |
a38f0f5e GS |
1128 | /* |
1129 | * Implementation detail: A USB transfer timeout is not fatal | |
1130 | * here. We just process whatever was received, empty input is | |
1131 | * perfectly acceptable. Reaching (or exceeding) the sw limits | |
1132 | * or exhausting the device's captured data will complete the | |
1133 | * sample data download. | |
1134 | */ | |
1135 | num_xfers = transfer->actual_length / TRANSFER_PACKET_LENGTH; | |
1136 | send_chunk(sdi, transfer->buffer, num_xfers); | |
dfac9592 GS |
1137 | |
1138 | devc->n_bytes_to_read -= transfer->actual_length; | |
1139 | if (devc->n_bytes_to_read) { | |
1140 | uint32_t to_read = devc->n_bytes_to_read; | |
96dc954e GS |
1141 | /* |
1142 | * Determine read size for the next USB transfer. Make | |
1143 | * the buffer size a multiple of the endpoint packet | |
1144 | * size. Don't exceed a maximum value. | |
1145 | */ | |
dfac9592 GS |
1146 | if (to_read >= LA2016_USB_BUFSZ) |
1147 | to_read = LA2016_USB_BUFSZ; | |
418dfd7e GS |
1148 | to_read += LA2016_EP6_PKTSZ - 1; |
1149 | to_read /= LA2016_EP6_PKTSZ; | |
1150 | to_read *= LA2016_EP6_PKTSZ; | |
852c7d14 GS |
1151 | libusb_fill_bulk_transfer(transfer, |
1152 | usb->devhdl, USB_EP_CAPTURE_DATA | LIBUSB_ENDPOINT_IN, | |
1153 | transfer->buffer, to_read, | |
dfac9592 GS |
1154 | receive_transfer, (void *)sdi, DEFAULT_TIMEOUT_MS); |
1155 | ||
411ad77c GS |
1156 | ret = libusb_submit_transfer(transfer); |
1157 | if (ret == 0) | |
dfac9592 | 1158 | return; |
91f73872 GS |
1159 | sr_err("Cannot submit another USB transfer: %s.", |
1160 | libusb_error_name(ret)); | |
dfac9592 GS |
1161 | } |
1162 | ||
1163 | g_free(transfer->buffer); | |
1164 | libusb_free_transfer(transfer); | |
cf057ac4 | 1165 | devc->download_finished = TRUE; |
dfac9592 GS |
1166 | } |
1167 | ||
1168 | SR_PRIV int la2016_receive_data(int fd, int revents, void *cb_data) | |
1169 | { | |
1170 | const struct sr_dev_inst *sdi; | |
1171 | struct dev_context *devc; | |
1172 | struct drv_context *drvc; | |
1173 | struct timeval tv; | |
a38f0f5e | 1174 | int ret; |
dfac9592 GS |
1175 | |
1176 | (void)fd; | |
1177 | (void)revents; | |
1178 | ||
1179 | sdi = cb_data; | |
1180 | devc = sdi->priv; | |
1181 | drvc = sdi->driver->context; | |
1182 | ||
a38f0f5e GS |
1183 | /* |
1184 | * Wait for the acquisition to complete in hardware. | |
1185 | * Periodically check a potentially configured msecs timeout. | |
1186 | */ | |
cf057ac4 GS |
1187 | if (!devc->completion_seen) { |
1188 | if (!la2016_is_idle(sdi)) { | |
a38f0f5e GS |
1189 | if (sr_sw_limits_check(&devc->sw_limits)) { |
1190 | devc->sw_limits.limit_msec = 0; | |
1191 | sr_dbg("Limit reached. Stopping acquisition."); | |
1192 | la2016_stop_acquisition(sdi); | |
1193 | } | |
96dc954e | 1194 | /* Not yet ready for sample data download. */ |
dfac9592 GS |
1195 | return TRUE; |
1196 | } | |
a38f0f5e GS |
1197 | sr_dbg("Acquisition completion seen (hardware)."); |
1198 | devc->sw_limits.limit_msec = 0; | |
cf057ac4 GS |
1199 | devc->completion_seen = TRUE; |
1200 | devc->download_finished = FALSE; | |
1201 | devc->trigger_marked = FALSE; | |
dfac9592 | 1202 | devc->total_samples = 0; |
a38f0f5e GS |
1203 | |
1204 | /* Initiate the download of acquired sample data. */ | |
1205 | std_session_send_df_frame_begin(sdi); | |
1206 | ret = la2016_start_download(sdi, receive_transfer); | |
1207 | if (ret != SR_OK) { | |
91f73872 | 1208 | sr_err("Cannot start acquisition data download."); |
dfac9592 GS |
1209 | return FALSE; |
1210 | } | |
91f73872 | 1211 | sr_dbg("Acquisition data download started."); |
dfac9592 GS |
1212 | |
1213 | return TRUE; | |
1214 | } | |
1215 | ||
a38f0f5e | 1216 | /* Handle USB reception. Drives sample data download. */ |
dfac9592 GS |
1217 | tv.tv_sec = tv.tv_usec = 0; |
1218 | libusb_handle_events_timeout(drvc->sr_ctx->libusb_ctx, &tv); | |
1219 | ||
a38f0f5e | 1220 | /* Postprocess completion of sample data download. */ |
cf057ac4 | 1221 | if (devc->download_finished) { |
91f73872 | 1222 | sr_dbg("Download finished, post processing."); |
dfac9592 GS |
1223 | |
1224 | la2016_stop_acquisition(sdi); | |
a38f0f5e | 1225 | usb_source_remove(sdi->session, drvc->sr_ctx); |
dfac9592 GS |
1226 | devc->transfer = NULL; |
1227 | ||
a38f0f5e GS |
1228 | feed_queue_logic_flush(devc->feed_queue); |
1229 | feed_queue_logic_free(devc->feed_queue); | |
1230 | devc->feed_queue = NULL; | |
1231 | std_session_send_df_frame_end(sdi); | |
1232 | std_session_send_df_end(sdi); | |
1233 | ||
91f73872 | 1234 | sr_dbg("Download finished, done post processing."); |
dfac9592 GS |
1235 | } |
1236 | ||
1237 | return TRUE; | |
1238 | } | |
1239 | ||
d466f61c GS |
1240 | SR_PRIV int la2016_identify_device(const struct sr_dev_inst *sdi, |
1241 | gboolean show_message) | |
f2cd2deb | 1242 | { |
8b172e78 | 1243 | struct dev_context *devc; |
3ab60908 | 1244 | uint8_t buf[8]; /* Larger size of manuf date and device type magic. */ |
64172b16 | 1245 | size_t rdoff, rdlen; |
43d2e52f GS |
1246 | const uint8_t *rdptr; |
1247 | uint8_t date_yy, date_mm; | |
1248 | uint8_t dinv_yy, dinv_mm; | |
9de389b1 | 1249 | uint8_t magic; |
d466f61c GS |
1250 | size_t model_idx; |
1251 | const struct kingst_model *model; | |
9de389b1 | 1252 | int ret; |
f2cd2deb | 1253 | |
8b172e78 KG |
1254 | devc = sdi->priv; |
1255 | ||
96dc954e | 1256 | /* |
43d2e52f GS |
1257 | * Four EEPROM bytes at offset 0x20 are the manufacturing date, |
1258 | * year and month in BCD format, followed by inverted values for | |
1259 | * consistency checks. For example bytes 20 04 df fb translate | |
1260 | * to 2020-04. This information can help identify the vintage of | |
1261 | * devices when unknown magic numbers are seen. | |
9de389b1 | 1262 | */ |
64172b16 GS |
1263 | rdoff = 0x20; |
1264 | rdlen = 4 * sizeof(uint8_t); | |
1265 | ret = ctrl_in(sdi, CMD_EEPROM, rdoff, 0, buf, rdlen); | |
d466f61c | 1266 | if (ret != SR_OK && !show_message) { |
64172b16 | 1267 | /* Non-fatal weak attempt during probe. Not worth logging. */ |
d466f61c GS |
1268 | sr_dbg("Cannot access EEPROM."); |
1269 | return SR_ERR_IO; | |
1270 | } else if (ret != SR_OK) { | |
64172b16 | 1271 | /* Failed attempt in regular use. Non-fatal. Worth logging. */ |
43d2e52f | 1272 | sr_err("Cannot read manufacture date in EEPROM."); |
1ed93110 | 1273 | } else { |
64172b16 GS |
1274 | if (sr_log_loglevel_get() >= SR_LOG_SPEW) { |
1275 | GString *txt; | |
1276 | txt = sr_hexdump_new(buf, rdlen); | |
1277 | sr_spew("Manufacture date bytes %s.", txt->str); | |
1278 | sr_hexdump_free(txt); | |
1279 | } | |
43d2e52f GS |
1280 | rdptr = &buf[0]; |
1281 | date_yy = read_u8_inc(&rdptr); | |
1282 | date_mm = read_u8_inc(&rdptr); | |
1283 | dinv_yy = read_u8_inc(&rdptr); | |
1284 | dinv_mm = read_u8_inc(&rdptr); | |
1285 | sr_info("Manufacture date: 20%02hx-%02hx.", date_yy, date_mm); | |
1286 | if ((date_mm ^ dinv_mm) != 0xff || (date_yy ^ dinv_yy) != 0xff) | |
1287 | sr_warn("Manufacture date fails checksum test."); | |
f2cd2deb | 1288 | } |
f2cd2deb | 1289 | |
9de389b1 | 1290 | /* |
96dc954e GS |
1291 | * Several Kingst logic analyzer devices share the same USB VID |
1292 | * and PID. The product ID determines which MCU firmware to load. | |
1293 | * The MCU firmware provides access to EEPROM content which then | |
1294 | * allows to identify the device model. Which in turn determines | |
1295 | * which FPGA bitstream to load. Eight bytes at offset 0x08 are | |
1296 | * to get inspected. | |
9de389b1 | 1297 | * |
96dc954e GS |
1298 | * EEPROM content for model identification is kept redundantly |
1299 | * in memory. The values are stored in verbatim and in inverted | |
1300 | * form, multiple copies are kept at different offsets. Example | |
1301 | * data: | |
9de389b1 | 1302 | * |
96dc954e GS |
1303 | * magic 0x08 |
1304 | * | ~magic 0xf7 | |
1305 | * | | | |
1306 | * 08f7000008f710ef | |
1307 | * | | | |
1308 | * | ~magic backup | |
1309 | * magic backup | |
9de389b1 | 1310 | * |
96dc954e GS |
1311 | * Exclusively inspecting the magic byte appears to be sufficient, |
1312 | * other fields seem to be 'don't care'. | |
9de389b1 | 1313 | * |
96dc954e GS |
1314 | * magic 2 == LA2016 using "kingst-la2016-fpga.bitstream" |
1315 | * magic 3 == LA1016 using "kingst-la1016-fpga.bitstream" | |
1316 | * magic 8 == LA2016a using "kingst-la2016a1-fpga.bitstream" | |
1317 | * (latest v1.3.0 PCB, perhaps others) | |
1318 | * magic 9 == LA1016a using "kingst-la1016a1-fpga.bitstream" | |
1319 | * (latest v1.3.0 PCB, perhaps others) | |
9de389b1 | 1320 | * |
96dc954e GS |
1321 | * When EEPROM content does not match the hardware configuration |
1322 | * (the board layout), the software may load but yield incorrect | |
1323 | * results (like swapped channels). The FPGA bitstream itself | |
1324 | * will authenticate with IC U10 and fail when its capabilities | |
1325 | * do not match the hardware model. An LA1016 won't become a | |
1326 | * LA2016 by faking its EEPROM content. | |
9de389b1 | 1327 | */ |
d466f61c | 1328 | devc->identify_magic = 0; |
64172b16 GS |
1329 | rdoff = 0x08; |
1330 | rdlen = 8 * sizeof(uint8_t); | |
1331 | ret = ctrl_in(sdi, CMD_EEPROM, rdoff, 0, &buf, rdlen); | |
1332 | if (ret != SR_OK) { | |
91f73872 | 1333 | sr_err("Cannot read EEPROM device identifier bytes."); |
f2cd2deb FS |
1334 | return ret; |
1335 | } | |
64172b16 GS |
1336 | if (sr_log_loglevel_get() >= SR_LOG_SPEW) { |
1337 | GString *txt; | |
1338 | txt = sr_hexdump_new(buf, rdlen); | |
1339 | sr_spew("EEPROM magic bytes %s.", txt->str); | |
1340 | sr_hexdump_free(txt); | |
1341 | } | |
43d2e52f | 1342 | if ((buf[0] ^ buf[1]) == 0xff) { |
96dc954e | 1343 | /* Primary copy of magic passes complement check. */ |
9de389b1 | 1344 | magic = buf[0]; |
64172b16 | 1345 | sr_dbg("Using primary magic, value %d.", (int)magic); |
43d2e52f | 1346 | } else if ((buf[4] ^ buf[5]) == 0xff) { |
96dc954e | 1347 | /* Backup copy of magic passes complement check. */ |
9de389b1 | 1348 | magic = buf[4]; |
64172b16 | 1349 | sr_dbg("Using backup magic, value %d.", (int)magic); |
43d2e52f GS |
1350 | } else { |
1351 | sr_err("Cannot find consistent device type identification."); | |
1352 | magic = 0; | |
f2cd2deb | 1353 | } |
d466f61c | 1354 | devc->identify_magic = magic; |
9de389b1 | 1355 | |
d466f61c GS |
1356 | devc->model = NULL; |
1357 | for (model_idx = 0; model_idx < ARRAY_SIZE(models); model_idx++) { | |
1358 | model = &models[model_idx]; | |
1359 | if (model->magic != magic) | |
1360 | continue; | |
1361 | devc->model = model; | |
64172b16 GS |
1362 | sr_info("Model '%s', %zu channels, max %" PRIu64 "MHz.", |
1363 | model->name, model->channel_count, | |
1364 | model->samplerate / SR_MHZ(1)); | |
d466f61c GS |
1365 | devc->fpga_bitstream = g_strdup_printf(FPGA_FWFILE_FMT, |
1366 | model->fpga_stem); | |
d466f61c | 1367 | sr_info("FPGA bitstream file '%s'.", devc->fpga_bitstream); |
d6f89d4b GS |
1368 | break; |
1369 | } | |
d466f61c | 1370 | if (!devc->model) { |
91f73872 | 1371 | sr_err("Cannot identify as one of the supported models."); |
286b3e13 | 1372 | return SR_ERR_DATA; |
3f48ab02 | 1373 | } |
f2cd2deb | 1374 | |
d466f61c GS |
1375 | return SR_OK; |
1376 | } | |
1377 | ||
6d53e949 | 1378 | SR_PRIV int la2016_init_hardware(const struct sr_dev_inst *sdi) |
d466f61c GS |
1379 | { |
1380 | struct dev_context *devc; | |
1381 | const char *bitstream_fn; | |
1382 | int ret; | |
1383 | uint16_t state; | |
1384 | ||
1385 | devc = sdi->priv; | |
1386 | bitstream_fn = devc ? devc->fpga_bitstream : ""; | |
1387 | ||
1388 | ret = check_fpga_bitstream(sdi); | |
1389 | if (ret != SR_OK) { | |
d6f89d4b GS |
1390 | ret = upload_fpga_bitstream(sdi, bitstream_fn); |
1391 | if (ret != SR_OK) { | |
1392 | sr_err("Cannot upload FPGA bitstream."); | |
1393 | return ret; | |
1394 | } | |
1395 | } | |
1396 | ret = enable_fpga_bitstream(sdi); | |
9de389b1 | 1397 | if (ret != SR_OK) { |
d6f89d4b | 1398 | sr_err("Cannot enable FPGA bitstream after upload."); |
9de389b1 KG |
1399 | return ret; |
1400 | } | |
1401 | ||
f2cd2deb | 1402 | state = run_state(sdi); |
9de389b1 | 1403 | if (state != 0x85e9) { |
91f73872 | 1404 | sr_warn("Unexpected run state, want 0x85e9, got 0x%04x.", state); |
9de389b1 | 1405 | } |
f2cd2deb | 1406 | |
6d53e949 GS |
1407 | ret = ctrl_out(sdi, CMD_BULK_RESET, 0x00, 0, NULL, 0); |
1408 | if (ret != SR_OK) { | |
91f73872 | 1409 | sr_err("Cannot reset USB bulk transfer."); |
f2cd2deb FS |
1410 | return ret; |
1411 | } | |
9de389b1 | 1412 | |
91f73872 | 1413 | sr_dbg("Device should be initialized."); |
f2cd2deb | 1414 | |
6d53e949 GS |
1415 | return SR_OK; |
1416 | } | |
1417 | ||
6d53e949 | 1418 | SR_PRIV int la2016_deinit_hardware(const struct sr_dev_inst *sdi) |
f2cd2deb FS |
1419 | { |
1420 | int ret; | |
1421 | ||
6d53e949 GS |
1422 | ret = ctrl_out(sdi, CMD_FPGA_ENABLE, 0x00, 0, NULL, 0); |
1423 | if (ret != SR_OK) { | |
91f73872 | 1424 | sr_err("Cannot deinitialize device's FPGA."); |
f2cd2deb FS |
1425 | return ret; |
1426 | } | |
1427 | ||
1428 | return SR_OK; | |
1429 | } | |
08a49848 GS |
1430 | |
1431 | SR_PRIV int la2016_write_pwm_config(const struct sr_dev_inst *sdi, size_t idx) | |
1432 | { | |
1433 | return set_pwm_config(sdi, idx); | |
1434 | } |