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f2cd2deb FS |
1 | /* |
2 | * This file is part of the libsigrok project. | |
3 | * | |
4 | * Copyright (C) 2020 Florian Schmidt <schmidt_florian@gmx.de> | |
5 | * Copyright (C) 2013 Marcus Comstedt <marcus@mc.pp.se> | |
6 | * Copyright (C) 2013 Bert Vermeulen <bert@biot.com> | |
7 | * Copyright (C) 2012 Joel Holdsworth <joel@airwebreathe.org.uk> | |
8 | * | |
9 | * This program is free software: you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License as published by | |
11 | * the Free Software Foundation, either version 3 of the License, or | |
12 | * (at your option) any later version. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
21 | */ | |
22 | ||
23 | #include <config.h> | |
a7740b06 | 24 | |
f2cd2deb | 25 | #include <libsigrok/libsigrok.h> |
a7740b06 GS |
26 | #include <string.h> |
27 | ||
f2cd2deb FS |
28 | #include "libsigrok-internal.h" |
29 | #include "protocol.h" | |
30 | ||
f2cd2deb | 31 | #define UC_FIRMWARE "kingst-la-%04x.fw" |
9de389b1 KG |
32 | #define FPGA_FW_LA2016 "kingst-la2016-fpga.bitstream" |
33 | #define FPGA_FW_LA2016A "kingst-la2016a1-fpga.bitstream" | |
8b172e78 KG |
34 | #define FPGA_FW_LA1016 "kingst-la1016-fpga.bitstream" |
35 | #define FPGA_FW_LA1016A "kingst-la1016a1-fpga.bitstream" | |
f2cd2deb | 36 | |
8b172e78 KG |
37 | #define MAX_SAMPLE_RATE_LA2016 SR_MHZ(200) |
38 | #define MAX_SAMPLE_RATE_LA1016 SR_MHZ(100) | |
e9430410 GS |
39 | #define MAX_SAMPLE_DEPTH 10e9 |
40 | #define MAX_PWM_FREQ SR_MHZ(20) | |
41 | #define PWM_CLOCK SR_MHZ(200) /* 200MHz for both LA2016 and LA1016 */ | |
f2cd2deb | 42 | |
96dc954e | 43 | /* USB vendor class control requests, executed by the Cypress FX2 MCU. */ |
84fe94bd | 44 | #define CMD_FPGA_ENABLE 0x10 |
96dc954e GS |
45 | #define CMD_FPGA_SPI 0x20 /* R/W access to FPGA registers via SPI. */ |
46 | #define CMD_BULK_START 0x30 /* Start sample data download via USB EP6 IN. */ | |
47 | #define CMD_BULK_RESET 0x38 /* Flush FIFO of FX2 USB EP6 IN. */ | |
48 | #define CMD_FPGA_INIT 0x50 /* Used before and after FPGA bitstream upload. */ | |
49 | #define CMD_KAUTH 0x60 /* Communicate to auth IC (U10). Not used. */ | |
50 | #define CMD_EEPROM 0xa2 /* R/W access to EEPROM content. */ | |
00849545 | 51 | |
42f6dd55 | 52 | /* |
96dc954e GS |
53 | * FPGA register addresses (base addresses when registers span multiple |
54 | * bytes, in that case data is kept in little endian format). Passed to | |
55 | * CMD_FPGA_SPI requests. The FX2 MCU transparently handles the detail | |
56 | * of SPI transfers encoding the read (1) or write (0) direction in the | |
57 | * MSB of the address field. There are some 60 byte-wide FPGA registers. | |
d6f89d4b GS |
58 | * |
59 | * Unfortunately the FPGA registers change their meaning between the | |
60 | * read and write directions of access, or exclusively provide one of | |
61 | * these directions and not the other. This is an arbitrary vendor's | |
62 | * choice, there is nothing which the sigrok driver could do about it. | |
63 | * Values written to registers typically cannot get read back, neither | |
64 | * verified after writing a configuration, nor queried upon startup for | |
65 | * automatic detection of the current configuration. Neither appear to | |
66 | * be there echo registers for presence and communication checks, nor | |
67 | * version identifying registers, as far as we know. | |
42f6dd55 | 68 | */ |
96dc954e GS |
69 | #define REG_RUN 0x00 /* Read capture status, write start capture. */ |
70 | #define REG_PWM_EN 0x02 /* User PWM channels on/off. */ | |
71 | #define REG_CAPT_MODE 0x03 /* Write 0x00 capture to SDRAM, 0x01 streaming. */ | |
72 | #define REG_BULK 0x08 /* Write start addr, byte count to download samples. */ | |
73 | #define REG_SAMPLING 0x10 /* Write capture config, read capture SDRAM location. */ | |
74 | #define REG_TRIGGER 0x20 /* write level and edge trigger config. */ | |
75 | #define REG_THRESHOLD 0x68 /* Write PWM config to setup input threshold DAC. */ | |
76 | #define REG_PWM1 0x70 /* Write config for user PWM1. */ | |
77 | #define REG_PWM2 0x78 /* Write config for user PWM2. */ | |
f2cd2deb FS |
78 | |
79 | static int ctrl_in(const struct sr_dev_inst *sdi, | |
1ed93110 GS |
80 | uint8_t bRequest, uint16_t wValue, uint16_t wIndex, |
81 | void *data, uint16_t wLength) | |
f2cd2deb FS |
82 | { |
83 | struct sr_usb_dev_inst *usb; | |
84 | int ret; | |
85 | ||
86 | usb = sdi->conn; | |
87 | ||
88 | if ((ret = libusb_control_transfer( | |
89 | usb->devhdl, LIBUSB_REQUEST_TYPE_VENDOR | LIBUSB_ENDPOINT_IN, | |
90 | bRequest, wValue, wIndex, (unsigned char *)data, wLength, | |
91 | DEFAULT_TIMEOUT_MS)) != wLength) { | |
91f73872 GS |
92 | sr_dbg("USB ctrl in: %d bytes, req %d val %#x idx %d: %s.", |
93 | wLength, bRequest, wValue, wIndex, | |
94 | libusb_error_name(ret)); | |
95 | sr_err("Cannot read %d bytes from USB: %s.", | |
96 | wLength, libusb_error_name(ret)); | |
f2cd2deb FS |
97 | return SR_ERR; |
98 | } | |
99 | ||
100 | return SR_OK; | |
101 | } | |
102 | ||
103 | static int ctrl_out(const struct sr_dev_inst *sdi, | |
1ed93110 GS |
104 | uint8_t bRequest, uint16_t wValue, uint16_t wIndex, |
105 | void *data, uint16_t wLength) | |
f2cd2deb FS |
106 | { |
107 | struct sr_usb_dev_inst *usb; | |
108 | int ret; | |
109 | ||
110 | usb = sdi->conn; | |
111 | ||
112 | if ((ret = libusb_control_transfer( | |
113 | usb->devhdl, LIBUSB_REQUEST_TYPE_VENDOR | LIBUSB_ENDPOINT_OUT, | |
114 | bRequest, wValue, wIndex, (unsigned char*)data, wLength, | |
115 | DEFAULT_TIMEOUT_MS)) != wLength) { | |
91f73872 GS |
116 | sr_dbg("USB ctrl out: %d bytes, req %d val %#x idx %d: %s.", |
117 | wLength, bRequest, wValue, wIndex, | |
118 | libusb_error_name(ret)); | |
119 | sr_err("Cannot write %d bytes to USB: %s.", | |
120 | wLength, libusb_error_name(ret)); | |
f2cd2deb FS |
121 | return SR_ERR; |
122 | } | |
123 | ||
124 | return SR_OK; | |
125 | } | |
126 | ||
d6f89d4b GS |
127 | /* |
128 | * Check the necessity for FPGA bitstream upload, because another upload | |
129 | * would take some 600ms which is undesirable after program startup. Try | |
130 | * to access some FPGA registers and check the values' plausibility. The | |
131 | * check should fail on the safe side, request another upload when in | |
132 | * doubt. A positive response (the request to continue operation with the | |
133 | * currently active bitstream) should be conservative. Accessing multiple | |
134 | * registers is considered cheap compared to the cost of bitstream upload. | |
135 | * | |
136 | * It helps though that both the vendor software and the sigrok driver | |
137 | * use the same bundle of MCU firmware and FPGA bitstream for any of the | |
138 | * supported models. We don't expect to successfully communicate to the | |
139 | * device yet disagree on its protocol. Ideally we would access version | |
140 | * identifying registers for improved robustness, but are not aware of | |
141 | * any. A bitstream reload can always be forced by a power cycle. | |
142 | */ | |
143 | static int check_fpga_bitstream(const struct sr_dev_inst *sdi) | |
144 | { | |
145 | uint8_t init_rsp; | |
146 | int ret; | |
147 | uint16_t run_state; | |
148 | uint8_t pwm_en; | |
149 | size_t read_len; | |
150 | uint8_t buff[sizeof(run_state)]; | |
151 | const uint8_t *rdptr; | |
152 | ||
153 | sr_dbg("Checking operation of the FPGA bitstream."); | |
154 | ||
155 | init_rsp = 0xff; | |
156 | ret = ctrl_in(sdi, CMD_FPGA_INIT, 0x00, 0, &init_rsp, sizeof(init_rsp)); | |
157 | if (ret != SR_OK || init_rsp != 0) { | |
158 | sr_dbg("FPGA init query failed, or unexpected response."); | |
159 | return SR_ERR_IO; | |
160 | } | |
161 | ||
162 | read_len = sizeof(run_state); | |
163 | ret = ctrl_in(sdi, CMD_FPGA_SPI, REG_RUN, 0, buff, read_len); | |
164 | if (ret != SR_OK) { | |
165 | sr_dbg("FPGA register access failed (run state)."); | |
166 | return SR_ERR_IO; | |
167 | } | |
168 | rdptr = buff; | |
169 | run_state = read_u16le_inc(&rdptr); | |
170 | sr_spew("FPGA register: run state 0x%04x.", run_state); | |
171 | if (run_state && (run_state & 0x3) != 0x1) { | |
172 | sr_dbg("Unexpected FPGA register content (run state)."); | |
173 | return SR_ERR_DATA; | |
174 | } | |
175 | if (run_state && (run_state & ~0xf) != 0x85e0) { | |
176 | sr_dbg("Unexpected FPGA register content (run state)."); | |
177 | return SR_ERR_DATA; | |
178 | } | |
179 | ||
180 | read_len = sizeof(pwm_en); | |
181 | ret = ctrl_in(sdi, CMD_FPGA_SPI, REG_PWM_EN, 0, buff, read_len); | |
182 | if (ret != SR_OK) { | |
183 | sr_dbg("FPGA register access failed (PWM enable)."); | |
184 | return SR_ERR_IO; | |
185 | } | |
186 | rdptr = buff; | |
187 | pwm_en = read_u8_inc(&rdptr); | |
188 | sr_spew("FPGA register: PWM enable 0x%02x.", pwm_en); | |
189 | if ((pwm_en & 0x3) != 0x0) { | |
190 | sr_dbg("Unexpected FPGA register content (PWM enable)."); | |
191 | return SR_ERR_DATA; | |
192 | } | |
193 | ||
194 | sr_info("Could re-use current FPGA bitstream. No upload required."); | |
195 | return SR_OK; | |
196 | } | |
197 | ||
1ed93110 GS |
198 | static int upload_fpga_bitstream(const struct sr_dev_inst *sdi, |
199 | const char *bitstream_fname) | |
f2cd2deb FS |
200 | { |
201 | struct drv_context *drvc; | |
202 | struct sr_usb_dev_inst *usb; | |
203 | struct sr_resource bitstream; | |
b0d0131e | 204 | uint32_t bitstream_size; |
c3d40037 HK |
205 | uint8_t buffer[sizeof(uint32_t)]; |
206 | uint8_t *wrptr; | |
f2cd2deb | 207 | uint8_t block[4096]; |
3f48ab02 FS |
208 | int len, act_len; |
209 | unsigned int pos; | |
f2cd2deb | 210 | int ret; |
b0d0131e | 211 | unsigned int zero_pad_to; |
f2cd2deb FS |
212 | |
213 | drvc = sdi->driver->context; | |
214 | usb = sdi->conn; | |
215 | ||
9de389b1 | 216 | sr_info("Uploading FPGA bitstream '%s'.", bitstream_fname); |
f2cd2deb | 217 | |
9de389b1 | 218 | ret = sr_resource_open(drvc->sr_ctx, &bitstream, SR_RESOURCE_FIRMWARE, bitstream_fname); |
f2cd2deb | 219 | if (ret != SR_OK) { |
91f73872 | 220 | sr_err("Cannot find FPGA bitstream %s.", bitstream_fname); |
f2cd2deb FS |
221 | return ret; |
222 | } | |
223 | ||
b0d0131e | 224 | bitstream_size = (uint32_t)bitstream.size; |
c3d40037 | 225 | wrptr = buffer; |
b0d0131e | 226 | write_u32le_inc(&wrptr, bitstream_size); |
00849545 | 227 | if ((ret = ctrl_out(sdi, CMD_FPGA_INIT, 0x00, 0, buffer, wrptr - buffer)) != SR_OK) { |
91f73872 | 228 | sr_err("Cannot initiate FPGA bitstream upload."); |
f2cd2deb FS |
229 | sr_resource_close(drvc->sr_ctx, &bitstream); |
230 | return ret; | |
231 | } | |
b0d0131e GS |
232 | zero_pad_to = bitstream_size; |
233 | zero_pad_to += LA2016_EP2_PADDING - 1; | |
234 | zero_pad_to /= LA2016_EP2_PADDING; | |
235 | zero_pad_to *= LA2016_EP2_PADDING; | |
f2cd2deb FS |
236 | |
237 | pos = 0; | |
238 | while (1) { | |
3f48ab02 FS |
239 | if (pos < bitstream.size) { |
240 | len = (int)sr_resource_read(drvc->sr_ctx, &bitstream, &block, sizeof(block)); | |
241 | if (len < 0) { | |
91f73872 | 242 | sr_err("Cannot read FPGA bitstream."); |
3f48ab02 FS |
243 | sr_resource_close(drvc->sr_ctx, &bitstream); |
244 | return SR_ERR; | |
245 | } | |
246 | } else { | |
96dc954e | 247 | /* Zero-pad until 'zero_pad_to'. */ |
3f48ab02 FS |
248 | len = zero_pad_to - pos; |
249 | if ((unsigned)len > sizeof(block)) | |
250 | len = sizeof(block); | |
251 | memset(&block, 0, len); | |
f2cd2deb FS |
252 | } |
253 | if (len == 0) | |
254 | break; | |
255 | ||
1ed93110 GS |
256 | ret = libusb_bulk_transfer(usb->devhdl, 2, |
257 | &block[0], len, &act_len, DEFAULT_TIMEOUT_MS); | |
f2cd2deb | 258 | if (ret != 0) { |
91f73872 GS |
259 | sr_dbg("Cannot write FPGA bitstream, block %#x len %d: %s.", |
260 | pos, (int)len, libusb_error_name(ret)); | |
f2cd2deb FS |
261 | ret = SR_ERR; |
262 | break; | |
263 | } | |
264 | if (act_len != len) { | |
91f73872 GS |
265 | sr_dbg("Short write for FPGA bitstream, block %#x len %d: got %d.", |
266 | pos, (int)len, act_len); | |
f2cd2deb FS |
267 | ret = SR_ERR; |
268 | break; | |
269 | } | |
270 | pos += len; | |
271 | } | |
272 | sr_resource_close(drvc->sr_ctx, &bitstream); | |
273 | if (ret != 0) | |
274 | return ret; | |
91f73872 GS |
275 | sr_info("FPGA bitstream upload (%" PRIu64 " bytes) done.", |
276 | bitstream.size); | |
f2cd2deb | 277 | |
d6f89d4b GS |
278 | return SR_OK; |
279 | } | |
280 | ||
281 | static int enable_fpga_bitstream(const struct sr_dev_inst *sdi) | |
282 | { | |
283 | int ret; | |
284 | uint8_t cmd_resp; | |
285 | ||
00849545 | 286 | if ((ret = ctrl_in(sdi, CMD_FPGA_INIT, 0x00, 0, &cmd_resp, sizeof(cmd_resp))) != SR_OK) { |
91f73872 | 287 | sr_err("Cannot read response after FPGA bitstream upload."); |
f2cd2deb FS |
288 | return ret; |
289 | } | |
3f48ab02 | 290 | if (cmd_resp != 0) { |
91f73872 GS |
291 | sr_err("Unexpected FPGA bitstream upload response, got 0x%02x, want 0.", |
292 | cmd_resp); | |
3f48ab02 FS |
293 | return SR_ERR; |
294 | } | |
3f48ab02 | 295 | g_usleep(30000); |
f2cd2deb | 296 | |
00849545 | 297 | if ((ret = ctrl_out(sdi, CMD_FPGA_ENABLE, 0x01, 0, NULL, 0)) != SR_OK) { |
91f73872 | 298 | sr_err("Cannot enable FPGA after bitstream upload."); |
f2cd2deb FS |
299 | return ret; |
300 | } | |
3f48ab02 | 301 | g_usleep(40000); |
d6f89d4b | 302 | |
f2cd2deb FS |
303 | return SR_OK; |
304 | } | |
305 | ||
306 | static int set_threshold_voltage(const struct sr_dev_inst *sdi, float voltage) | |
307 | { | |
308 | struct dev_context *devc; | |
f2cd2deb FS |
309 | int ret; |
310 | ||
311 | devc = sdi->priv; | |
f2cd2deb | 312 | |
1ed93110 | 313 | uint16_t duty_R79, duty_R56; |
f2ad79d1 KG |
314 | uint8_t buf[2 * sizeof(uint16_t)]; |
315 | uint8_t *wrptr; | |
316 | ||
96dc954e | 317 | /* Clamp threshold setting to valid range for LA2016. */ |
f2ad79d1 KG |
318 | if (voltage > 4.0) { |
319 | voltage = 4.0; | |
1ed93110 | 320 | } else if (voltage < -4.0) { |
f2ad79d1 KG |
321 | voltage = -4.0; |
322 | } | |
323 | ||
324 | /* | |
96dc954e GS |
325 | * Two PWM output channels feed one DAC which generates a bias |
326 | * voltage, which offsets the input probe's voltage level, and | |
327 | * in combination with the FPGA pins' fixed threshold result in | |
328 | * a programmable input threshold from the user's perspective. | |
329 | * The PWM outputs can be seen on R79 and R56 respectively, the | |
330 | * frequency is 100kHz and the duty cycle varies. The R79 PWM | |
331 | * uses three discrete settings. The R56 PWM varies with desired | |
332 | * thresholds and depends on the R79 PWM configuration. See the | |
333 | * schematics comments which discuss the formulae. | |
f2ad79d1 KG |
334 | */ |
335 | if (voltage >= 2.9) { | |
96dc954e | 336 | duty_R79 = 0; /* PWM off (0V). */ |
f2ad79d1 | 337 | duty_R56 = (uint16_t)(302 * voltage - 363); |
1ed93110 | 338 | } else if (voltage <= -0.4) { |
96dc954e | 339 | duty_R79 = 0x02d7; /* 72% duty cycle. */ |
f2ad79d1 | 340 | duty_R56 = (uint16_t)(302 * voltage + 1090); |
1ed93110 | 341 | } else { |
96dc954e | 342 | duty_R79 = 0x00f2; /* 25% duty cycle. */ |
f2ad79d1 KG |
343 | duty_R56 = (uint16_t)(302 * voltage + 121); |
344 | } | |
345 | ||
96dc954e | 346 | /* Clamp duty register values to sensible limits. */ |
f2ad79d1 KG |
347 | if (duty_R56 < 10) { |
348 | duty_R56 = 10; | |
1ed93110 | 349 | } else if (duty_R56 > 1100) { |
f2ad79d1 KG |
350 | duty_R56 = 1100; |
351 | } | |
352 | ||
91f73872 GS |
353 | sr_dbg("Set threshold voltage %.2fV.", voltage); |
354 | sr_dbg("Duty cycle values: R56 0x%04x, R79 0x%04x.", duty_R56, duty_R79); | |
f2ad79d1 KG |
355 | |
356 | wrptr = buf; | |
357 | write_u16le_inc(&wrptr, duty_R56); | |
358 | write_u16le_inc(&wrptr, duty_R79); | |
359 | ||
360 | ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_THRESHOLD, 0, buf, wrptr - buf); | |
f2cd2deb | 361 | if (ret != SR_OK) { |
91f73872 | 362 | sr_err("Cannot set threshold voltage %.2fV.", voltage); |
f2cd2deb FS |
363 | return ret; |
364 | } | |
365 | devc->threshold_voltage = voltage; | |
366 | ||
367 | return SR_OK; | |
368 | } | |
369 | ||
370 | static int enable_pwm(const struct sr_dev_inst *sdi, uint8_t p1, uint8_t p2) | |
371 | { | |
372 | struct dev_context *devc; | |
373 | uint8_t cfg; | |
374 | int ret; | |
375 | ||
376 | devc = sdi->priv; | |
377 | cfg = 0; | |
378 | ||
379 | if (p1) cfg |= 1 << 0; | |
380 | if (p2) cfg |= 1 << 1; | |
381 | ||
91f73872 | 382 | sr_dbg("Set PWM enable %d %d. Config 0x%02x.", p1, p2, cfg); |
42f6dd55 | 383 | ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_PWM_EN, 0, &cfg, sizeof(cfg)); |
f2cd2deb | 384 | if (ret != SR_OK) { |
91f73872 | 385 | sr_err("Cannot setup PWM enabled state."); |
f2cd2deb FS |
386 | return ret; |
387 | } | |
388 | devc->pwm_setting[0].enabled = (p1) ? 1 : 0; | |
389 | devc->pwm_setting[1].enabled = (p2) ? 1 : 0; | |
390 | ||
391 | return SR_OK; | |
392 | } | |
393 | ||
1ed93110 GS |
394 | static int set_pwm(const struct sr_dev_inst *sdi, uint8_t which, |
395 | float freq, float duty) | |
f2cd2deb | 396 | { |
42f6dd55 | 397 | int CTRL_PWM[] = { REG_PWM1, REG_PWM2 }; |
f2cd2deb FS |
398 | struct dev_context *devc; |
399 | pwm_setting_dev_t cfg; | |
400 | pwm_setting_t *setting; | |
401 | int ret; | |
c3d40037 HK |
402 | uint8_t buf[2 * sizeof(uint32_t)]; |
403 | uint8_t *wrptr; | |
f2cd2deb FS |
404 | |
405 | devc = sdi->priv; | |
406 | ||
407 | if (which < 1 || which > 2) { | |
91f73872 | 408 | sr_err("Invalid PWM channel: %d.", which); |
f2cd2deb FS |
409 | return SR_ERR; |
410 | } | |
411 | if (freq > MAX_PWM_FREQ) { | |
91f73872 | 412 | sr_err("Too high a PWM frequency: %.1f.", freq); |
f2cd2deb FS |
413 | return SR_ERR; |
414 | } | |
415 | if (duty > 100 || duty < 0) { | |
91f73872 | 416 | sr_err("Invalid PWM duty cycle: %f.", duty); |
f2cd2deb FS |
417 | return SR_ERR; |
418 | } | |
419 | ||
420 | cfg.period = (uint32_t)(PWM_CLOCK / freq); | |
421 | cfg.duty = (uint32_t)(0.5f + (cfg.period * duty / 100.)); | |
91f73872 | 422 | sr_dbg("Set PWM%d period %d, duty %d.", which, cfg.period, cfg.duty); |
f2cd2deb | 423 | |
c3d40037 HK |
424 | wrptr = buf; |
425 | write_u32le_inc(&wrptr, cfg.period); | |
426 | write_u32le_inc(&wrptr, cfg.duty); | |
00849545 | 427 | ret = ctrl_out(sdi, CMD_FPGA_SPI, CTRL_PWM[which - 1], 0, buf, wrptr - buf); |
f2cd2deb | 428 | if (ret != SR_OK) { |
91f73872 GS |
429 | sr_err("Cannot setup PWM%d configuration %d %d.", |
430 | which, cfg.period, cfg.duty); | |
f2cd2deb FS |
431 | return ret; |
432 | } | |
433 | setting = &devc->pwm_setting[which - 1]; | |
434 | setting->freq = freq; | |
435 | setting->duty = duty; | |
f2cd2deb FS |
436 | |
437 | return SR_OK; | |
438 | } | |
439 | ||
440 | static int set_defaults(const struct sr_dev_inst *sdi) | |
441 | { | |
442 | struct dev_context *devc; | |
443 | int ret; | |
444 | ||
445 | devc = sdi->priv; | |
446 | ||
447 | devc->capture_ratio = 5; /* percent */ | |
448 | devc->cur_channels = 0xffff; | |
449 | devc->limit_samples = 5000000; | |
8b172e78 | 450 | devc->cur_samplerate = SR_MHZ(100); |
f2cd2deb FS |
451 | |
452 | ret = set_threshold_voltage(sdi, devc->threshold_voltage); | |
453 | if (ret) | |
454 | return ret; | |
455 | ||
456 | ret = enable_pwm(sdi, 0, 0); | |
457 | if (ret) | |
458 | return ret; | |
459 | ||
460 | ret = set_pwm(sdi, 1, 1e3, 50); | |
461 | if (ret) | |
462 | return ret; | |
463 | ||
464 | ret = set_pwm(sdi, 2, 100e3, 50); | |
465 | if (ret) | |
466 | return ret; | |
467 | ||
468 | ret = enable_pwm(sdi, 1, 1); | |
469 | if (ret) | |
470 | return ret; | |
471 | ||
472 | return SR_OK; | |
473 | } | |
474 | ||
475 | static int set_trigger_config(const struct sr_dev_inst *sdi) | |
476 | { | |
477 | struct dev_context *devc; | |
478 | struct sr_trigger *trigger; | |
479 | trigger_cfg_t cfg; | |
480 | GSList *stages; | |
481 | GSList *channel; | |
482 | struct sr_trigger_stage *stage1; | |
483 | struct sr_trigger_match *match; | |
484 | uint16_t ch_mask; | |
485 | int ret; | |
c3d40037 HK |
486 | uint8_t buf[4 * sizeof(uint32_t)]; |
487 | uint8_t *wrptr; | |
f2cd2deb FS |
488 | |
489 | devc = sdi->priv; | |
490 | trigger = sr_session_trigger_get(sdi->session); | |
491 | ||
492 | memset(&cfg, 0, sizeof(cfg)); | |
493 | ||
494 | cfg.channels = devc->cur_channels; | |
495 | ||
496 | if (trigger && trigger->stages) { | |
497 | stages = trigger->stages; | |
498 | stage1 = stages->data; | |
499 | if (stages->next) { | |
500 | sr_err("Only one trigger stage supported for now."); | |
501 | return SR_ERR; | |
502 | } | |
503 | channel = stage1->matches; | |
504 | while (channel) { | |
505 | match = channel->data; | |
506 | ch_mask = 1 << match->channel->index; | |
507 | ||
508 | switch (match->match) { | |
509 | case SR_TRIGGER_ZERO: | |
510 | cfg.level |= ch_mask; | |
511 | cfg.high_or_falling &= ~ch_mask; | |
512 | break; | |
513 | case SR_TRIGGER_ONE: | |
514 | cfg.level |= ch_mask; | |
515 | cfg.high_or_falling |= ch_mask; | |
516 | break; | |
517 | case SR_TRIGGER_RISING: | |
518 | if ((cfg.enabled & ~cfg.level)) { | |
91f73872 | 519 | sr_err("Device only supports one edge trigger."); |
f2cd2deb FS |
520 | return SR_ERR; |
521 | } | |
522 | cfg.level &= ~ch_mask; | |
523 | cfg.high_or_falling &= ~ch_mask; | |
524 | break; | |
525 | case SR_TRIGGER_FALLING: | |
526 | if ((cfg.enabled & ~cfg.level)) { | |
91f73872 | 527 | sr_err("Device only supports one edge trigger."); |
f2cd2deb FS |
528 | return SR_ERR; |
529 | } | |
530 | cfg.level &= ~ch_mask; | |
531 | cfg.high_or_falling |= ch_mask; | |
532 | break; | |
533 | default: | |
91f73872 | 534 | sr_err("Unknown trigger condition."); |
f2cd2deb FS |
535 | return SR_ERR; |
536 | } | |
537 | cfg.enabled |= ch_mask; | |
538 | channel = channel->next; | |
539 | } | |
540 | } | |
91f73872 GS |
541 | sr_dbg("Set trigger config: " |
542 | "channels 0x%04x, trigger-enabled 0x%04x, " | |
543 | "level-triggered 0x%04x, high/falling 0x%04x.", | |
544 | cfg.channels, cfg.enabled, cfg.level, cfg.high_or_falling); | |
f2cd2deb FS |
545 | |
546 | devc->had_triggers_configured = cfg.enabled != 0; | |
547 | ||
c3d40037 HK |
548 | wrptr = buf; |
549 | write_u32le_inc(&wrptr, cfg.channels); | |
550 | write_u32le_inc(&wrptr, cfg.enabled); | |
551 | write_u32le_inc(&wrptr, cfg.level); | |
552 | write_u32le_inc(&wrptr, cfg.high_or_falling); | |
42f6dd55 | 553 | ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_TRIGGER, 16, buf, wrptr - buf); |
f2cd2deb | 554 | if (ret != SR_OK) { |
91f73872 | 555 | sr_err("Cannot setup trigger configuration."); |
f2cd2deb FS |
556 | return ret; |
557 | } | |
558 | ||
559 | return SR_OK; | |
560 | } | |
561 | ||
562 | static int set_sample_config(const struct sr_dev_inst *sdi) | |
563 | { | |
564 | struct dev_context *devc; | |
f2cd2deb | 565 | double clock_divisor; |
f2cd2deb FS |
566 | uint64_t total; |
567 | int ret; | |
c3d40037 HK |
568 | uint16_t divisor; |
569 | uint8_t buf[2 * sizeof(uint32_t) + 48 / 8 + sizeof(uint16_t)]; | |
570 | uint8_t *wrptr; | |
f2cd2deb FS |
571 | |
572 | devc = sdi->priv; | |
573 | total = 128 * 1024 * 1024; | |
574 | ||
8b172e78 | 575 | if (devc->cur_samplerate > devc->max_samplerate) { |
91f73872 GS |
576 | sr_err("Too high a sample rate: %" PRIu64 ".", |
577 | devc->cur_samplerate); | |
f2cd2deb FS |
578 | return SR_ERR; |
579 | } | |
580 | ||
8b172e78 | 581 | clock_divisor = devc->max_samplerate / (double)devc->cur_samplerate; |
f2cd2deb FS |
582 | if (clock_divisor > 0xffff) |
583 | clock_divisor = 0xffff; | |
c3d40037 | 584 | divisor = (uint16_t)(clock_divisor + 0.5); |
8b172e78 | 585 | devc->cur_samplerate = devc->max_samplerate / divisor; |
f2cd2deb FS |
586 | |
587 | if (devc->limit_samples > MAX_SAMPLE_DEPTH) { | |
91f73872 GS |
588 | sr_err("Too high a sample depth: %" PRIu64 ".", |
589 | devc->limit_samples); | |
f2cd2deb FS |
590 | return SR_ERR; |
591 | } | |
f2cd2deb FS |
592 | |
593 | devc->pre_trigger_size = (devc->capture_ratio * devc->limit_samples) / 100; | |
594 | ||
91f73872 GS |
595 | sr_dbg("Set sample config: %" PRIu64 "kHz, %" PRIu64 " samples, trigger-pos %" PRIu64 "%%.", |
596 | devc->cur_samplerate / 1000, | |
597 | devc->limit_samples, | |
598 | devc->capture_ratio); | |
f2cd2deb | 599 | |
c3d40037 HK |
600 | wrptr = buf; |
601 | write_u32le_inc(&wrptr, devc->limit_samples); | |
0d8e1ffc KG |
602 | write_u8_inc(&wrptr, 0); |
603 | write_u32le_inc(&wrptr, devc->pre_trigger_size); | |
96dc954e | 604 | write_u32le_inc(&wrptr, ((total * devc->capture_ratio) / 100) & 0xffffff00); |
0d8e1ffc KG |
605 | write_u16le_inc(&wrptr, divisor); |
606 | write_u8_inc(&wrptr, 0); | |
c3d40037 | 607 | |
42f6dd55 | 608 | ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_SAMPLING, 0, buf, wrptr - buf); |
f2cd2deb | 609 | if (ret != SR_OK) { |
91f73872 | 610 | sr_err("Cannot setup acquisition configuration."); |
f2cd2deb FS |
611 | return ret; |
612 | } | |
613 | ||
614 | return SR_OK; | |
615 | } | |
616 | ||
96dc954e GS |
617 | /* |
618 | * FPGA register REG_RUN holds the run state (u16le format). Bit fields | |
619 | * of interest: | |
620 | * bit 0: value 1 = idle | |
621 | * bit 1: value 1 = writing to SDRAM | |
622 | * bit 2: value 0 = waiting for trigger, 1 = trigger seen | |
623 | * bit 3: value 0 = pretrigger sampling, 1 = posttrigger sampling | |
624 | * The meaning of other bit fields is unknown. | |
7601dca7 | 625 | * |
96dc954e GS |
626 | * Typical values in order of appearance during execution: |
627 | * 0x85e2: pre-sampling, samples before the trigger position, | |
628 | * when capture ratio > 0% | |
629 | * 0x85ea: pre-sampling complete, now waiting for the trigger | |
630 | * (whilst sampling continuously) | |
631 | * 0x85ee: trigger seen, capturing post-trigger samples, running | |
632 | * 0x85ed: idle | |
f2cd2deb FS |
633 | */ |
634 | static uint16_t run_state(const struct sr_dev_inst *sdi) | |
635 | { | |
636 | uint16_t state; | |
84fe94bd | 637 | static uint16_t previous_state = 0; |
f2cd2deb FS |
638 | int ret; |
639 | ||
42f6dd55 | 640 | if ((ret = ctrl_in(sdi, CMD_FPGA_SPI, REG_RUN, 0, &state, sizeof(state))) != SR_OK) { |
91f73872 | 641 | sr_err("Cannot read run state."); |
f2cd2deb FS |
642 | return ret; |
643 | } | |
7601dca7 | 644 | |
96dc954e GS |
645 | /* |
646 | * Avoid flooding the log, only dump values as they change. | |
647 | * The routine is called about every 50ms. | |
7601dca7 | 648 | */ |
84fe94bd | 649 | if (state != previous_state) { |
7601dca7 | 650 | previous_state = state; |
84fe94bd | 651 | if ((state & 0x0003) == 0x01) { |
91f73872 | 652 | sr_dbg("Run state: 0x%04x (%s).", state, "idle"); |
1ed93110 | 653 | } else if ((state & 0x000f) == 0x02) { |
91f73872 GS |
654 | sr_dbg("Run state: 0x%04x (%s).", state, |
655 | "pre-trigger sampling"); | |
1ed93110 | 656 | } else if ((state & 0x000f) == 0x0a) { |
91f73872 GS |
657 | sr_dbg("Run state: 0x%04x (%s).", state, |
658 | "sampling, waiting for trigger"); | |
1ed93110 | 659 | } else if ((state & 0x000f) == 0x0e) { |
91f73872 GS |
660 | sr_dbg("Run state: 0x%04x (%s).", state, |
661 | "post-trigger sampling"); | |
1ed93110 | 662 | } else { |
91f73872 | 663 | sr_dbg("Run state: 0x%04x.", state); |
7601dca7 KG |
664 | } |
665 | } | |
f2cd2deb FS |
666 | |
667 | return state; | |
668 | } | |
669 | ||
670 | static int set_run_mode(const struct sr_dev_inst *sdi, uint8_t fast_blinking) | |
671 | { | |
672 | int ret; | |
673 | ||
42f6dd55 | 674 | if ((ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_RUN, 0, &fast_blinking, sizeof(fast_blinking))) != SR_OK) { |
91f73872 | 675 | sr_err("Cannot configure run mode %d.", fast_blinking); |
f2cd2deb FS |
676 | return ret; |
677 | } | |
678 | ||
679 | return SR_OK; | |
680 | } | |
681 | ||
682 | static int get_capture_info(const struct sr_dev_inst *sdi) | |
683 | { | |
684 | struct dev_context *devc; | |
685 | int ret; | |
c3d40037 HK |
686 | uint8_t buf[3 * sizeof(uint32_t)]; |
687 | const uint8_t *rdptr; | |
f2cd2deb FS |
688 | |
689 | devc = sdi->priv; | |
690 | ||
42f6dd55 | 691 | if ((ret = ctrl_in(sdi, CMD_FPGA_SPI, REG_SAMPLING, 0, buf, sizeof(buf))) != SR_OK) { |
91f73872 | 692 | sr_err("Cannot read capture info."); |
f2cd2deb FS |
693 | return ret; |
694 | } | |
c3d40037 HK |
695 | |
696 | rdptr = buf; | |
697 | devc->info.n_rep_packets = read_u32le_inc(&rdptr); | |
698 | devc->info.n_rep_packets_before_trigger = read_u32le_inc(&rdptr); | |
699 | devc->info.write_pos = read_u32le_inc(&rdptr); | |
f2cd2deb | 700 | |
91f73872 | 701 | sr_dbg("Capture info: n_rep_packets: 0x%08x/%d, before_trigger: 0x%08x/%d, write_pos: 0x%08x%d.", |
1ed93110 GS |
702 | devc->info.n_rep_packets, devc->info.n_rep_packets, |
703 | devc->info.n_rep_packets_before_trigger, | |
704 | devc->info.n_rep_packets_before_trigger, | |
705 | devc->info.write_pos, devc->info.write_pos); | |
f2cd2deb | 706 | |
91f73872 GS |
707 | if (devc->info.n_rep_packets % 5) { |
708 | sr_warn("Unexpected packets count %lu, not a multiple of 5.", | |
709 | (unsigned long)devc->info.n_rep_packets); | |
710 | } | |
f2cd2deb FS |
711 | |
712 | return SR_OK; | |
713 | } | |
714 | ||
1ed93110 GS |
715 | SR_PRIV int la2016_upload_firmware(struct sr_context *sr_ctx, |
716 | libusb_device *dev, uint16_t product_id) | |
f2cd2deb FS |
717 | { |
718 | char fw_file[1024]; | |
719 | snprintf(fw_file, sizeof(fw_file) - 1, UC_FIRMWARE, product_id); | |
40a0b2f4 | 720 | return ezusb_upload_firmware(sr_ctx, dev, USB_CONFIGURATION, fw_file); |
f2cd2deb FS |
721 | } |
722 | ||
723 | SR_PRIV int la2016_setup_acquisition(const struct sr_dev_inst *sdi) | |
724 | { | |
725 | struct dev_context *devc; | |
726 | int ret; | |
727 | uint8_t cmd; | |
728 | ||
729 | devc = sdi->priv; | |
730 | ||
731 | ret = set_threshold_voltage(sdi, devc->threshold_voltage); | |
732 | if (ret != SR_OK) | |
733 | return ret; | |
734 | ||
735 | cmd = 0; | |
42f6dd55 | 736 | if ((ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_CAPT_MODE, 0, &cmd, sizeof(cmd))) != SR_OK) { |
91f73872 | 737 | sr_err("Cannot send command to stop sampling."); |
f2cd2deb FS |
738 | return ret; |
739 | } | |
740 | ||
741 | ret = set_trigger_config(sdi); | |
742 | if (ret != SR_OK) | |
743 | return ret; | |
744 | ||
745 | ret = set_sample_config(sdi); | |
746 | if (ret != SR_OK) | |
747 | return ret; | |
748 | ||
749 | return SR_OK; | |
750 | } | |
751 | ||
752 | SR_PRIV int la2016_start_acquisition(const struct sr_dev_inst *sdi) | |
753 | { | |
3ebc1cb2 GS |
754 | int ret; |
755 | ||
756 | ret = set_run_mode(sdi, 3); | |
757 | if (ret != SR_OK) | |
758 | return ret; | |
759 | ||
760 | return SR_OK; | |
f2cd2deb FS |
761 | } |
762 | ||
3ebc1cb2 | 763 | static int la2016_stop_acquisition(const struct sr_dev_inst *sdi) |
f2cd2deb | 764 | { |
3ebc1cb2 GS |
765 | int ret; |
766 | ||
767 | ret = set_run_mode(sdi, 0); | |
768 | if (ret != SR_OK) | |
769 | return ret; | |
770 | ||
771 | return SR_OK; | |
f2cd2deb FS |
772 | } |
773 | ||
774 | SR_PRIV int la2016_abort_acquisition(const struct sr_dev_inst *sdi) | |
775 | { | |
3ebc1cb2 GS |
776 | int ret; |
777 | struct dev_context *devc; | |
778 | ||
779 | ret = la2016_stop_acquisition(sdi); | |
780 | if (ret != SR_OK) | |
781 | return ret; | |
782 | ||
783 | devc = sdi ? sdi->priv : NULL; | |
784 | if (devc && devc->transfer) | |
785 | libusb_cancel_transfer(devc->transfer); | |
786 | ||
787 | return SR_OK; | |
f2cd2deb FS |
788 | } |
789 | ||
3ebc1cb2 | 790 | static int la2016_has_triggered(const struct sr_dev_inst *sdi) |
f2cd2deb FS |
791 | { |
792 | uint16_t state; | |
793 | ||
794 | state = run_state(sdi); | |
795 | ||
796 | return (state & 0x3) == 1; | |
797 | } | |
798 | ||
1ed93110 GS |
799 | static int la2016_start_retrieval(const struct sr_dev_inst *sdi, |
800 | libusb_transfer_cb_fn cb) | |
f2cd2deb FS |
801 | { |
802 | struct dev_context *devc; | |
803 | struct sr_usb_dev_inst *usb; | |
804 | int ret; | |
c3d40037 HK |
805 | uint8_t wrbuf[2 * sizeof(uint32_t)]; |
806 | uint8_t *wrptr; | |
f2cd2deb FS |
807 | uint32_t to_read; |
808 | uint8_t *buffer; | |
809 | ||
810 | devc = sdi->priv; | |
811 | usb = sdi->conn; | |
812 | ||
813 | if ((ret = get_capture_info(sdi)) != SR_OK) | |
814 | return ret; | |
815 | ||
c3d40037 HK |
816 | devc->n_transfer_packets_to_read = devc->info.n_rep_packets / NUM_PACKETS_IN_CHUNK; |
817 | devc->n_bytes_to_read = devc->n_transfer_packets_to_read * TRANSFER_PACKET_LENGTH; | |
f2cd2deb FS |
818 | devc->read_pos = devc->info.write_pos - devc->n_bytes_to_read; |
819 | devc->n_reps_until_trigger = devc->info.n_rep_packets_before_trigger; | |
820 | ||
91f73872 | 821 | sr_dbg("Want to read %u xfer-packets starting from pos %" PRIu32 ".", |
1ed93110 | 822 | devc->n_transfer_packets_to_read, devc->read_pos); |
f2cd2deb | 823 | |
00849545 | 824 | if ((ret = ctrl_out(sdi, CMD_BULK_RESET, 0x00, 0, NULL, 0)) != SR_OK) { |
91f73872 | 825 | sr_err("Cannot reset USB bulk state."); |
f2cd2deb FS |
826 | return ret; |
827 | } | |
91f73872 GS |
828 | sr_dbg("Will read from 0x%08lx, 0x%08x bytes.", |
829 | (unsigned long)devc->read_pos, devc->n_bytes_to_read); | |
c3d40037 HK |
830 | wrptr = wrbuf; |
831 | write_u32le_inc(&wrptr, devc->read_pos); | |
832 | write_u32le_inc(&wrptr, devc->n_bytes_to_read); | |
42f6dd55 | 833 | if ((ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_BULK, 0, wrbuf, wrptr - wrbuf)) != SR_OK) { |
91f73872 | 834 | sr_err("Cannot send USB bulk config."); |
f2cd2deb FS |
835 | return ret; |
836 | } | |
00849545 | 837 | if ((ret = ctrl_out(sdi, CMD_BULK_START, 0x00, 0, NULL, 0)) != SR_OK) { |
91f73872 | 838 | sr_err("Cannot unblock USB bulk transfers."); |
f2cd2deb FS |
839 | return ret; |
840 | } | |
841 | ||
96dc954e GS |
842 | /* |
843 | * Pick a buffer size for all USB transfers. The buffer size | |
844 | * must be a multiple of the endpoint packet size. And cannot | |
845 | * exceed a maximum value. | |
846 | */ | |
f2cd2deb | 847 | to_read = devc->n_bytes_to_read; |
96dc954e GS |
848 | if (to_read >= LA2016_USB_BUFSZ) /* Multiple transfers. */ |
849 | to_read = LA2016_USB_BUFSZ; | |
850 | else /* One transfer. */ | |
e847645b | 851 | to_read = (to_read + (LA2016_EP6_PKTSZ-1)) & ~(LA2016_EP6_PKTSZ-1); |
f2cd2deb FS |
852 | buffer = g_try_malloc(to_read); |
853 | if (!buffer) { | |
91f73872 GS |
854 | sr_dbg("USB bulk transfer size %d bytes.", (int)to_read); |
855 | sr_err("Cannot allocate buffer for USB bulk transfer."); | |
f2cd2deb FS |
856 | return SR_ERR_MALLOC; |
857 | } | |
858 | ||
859 | devc->transfer = libusb_alloc_transfer(0); | |
860 | libusb_fill_bulk_transfer( | |
861 | devc->transfer, usb->devhdl, | |
862 | 0x86, buffer, to_read, | |
863 | cb, (void *)sdi, DEFAULT_TIMEOUT_MS); | |
864 | ||
865 | if ((ret = libusb_submit_transfer(devc->transfer)) != 0) { | |
91f73872 | 866 | sr_err("Cannot submit USB transfer: %s.", libusb_error_name(ret)); |
f2cd2deb FS |
867 | libusb_free_transfer(devc->transfer); |
868 | devc->transfer = NULL; | |
869 | g_free(buffer); | |
870 | return SR_ERR; | |
871 | } | |
872 | ||
873 | return SR_OK; | |
874 | } | |
875 | ||
dfac9592 GS |
876 | static void send_chunk(struct sr_dev_inst *sdi, |
877 | const uint8_t *packets, unsigned int num_tfers) | |
878 | { | |
879 | struct dev_context *devc; | |
880 | struct sr_datafeed_logic logic; | |
881 | struct sr_datafeed_packet sr_packet; | |
882 | unsigned int max_samples, n_samples, total_samples, free_n_samples; | |
883 | unsigned int i, j, k; | |
884 | int do_signal_trigger; | |
885 | uint16_t *wp; | |
886 | const uint8_t *rp; | |
887 | uint16_t state; | |
888 | uint8_t repetitions; | |
889 | ||
890 | devc = sdi->priv; | |
891 | ||
892 | logic.unitsize = 2; | |
893 | logic.data = devc->convbuffer; | |
894 | ||
895 | sr_packet.type = SR_DF_LOGIC; | |
896 | sr_packet.payload = &logic; | |
897 | ||
898 | max_samples = devc->convbuffer_size / 2; | |
899 | n_samples = 0; | |
900 | wp = (uint16_t *)devc->convbuffer; | |
901 | total_samples = 0; | |
902 | do_signal_trigger = 0; | |
903 | ||
904 | if (devc->had_triggers_configured && devc->reading_behind_trigger == 0 && devc->info.n_rep_packets_before_trigger == 0) { | |
905 | std_session_send_df_trigger(sdi); | |
906 | devc->reading_behind_trigger = 1; | |
907 | } | |
908 | ||
909 | rp = packets; | |
910 | for (i = 0; i < num_tfers; i++) { | |
911 | for (k = 0; k < NUM_PACKETS_IN_CHUNK; k++) { | |
912 | free_n_samples = max_samples - n_samples; | |
913 | if (free_n_samples < 256 || do_signal_trigger) { | |
914 | logic.length = n_samples * 2; | |
915 | sr_session_send(sdi, &sr_packet); | |
916 | n_samples = 0; | |
917 | wp = (uint16_t *)devc->convbuffer; | |
918 | if (do_signal_trigger) { | |
919 | std_session_send_df_trigger(sdi); | |
920 | do_signal_trigger = 0; | |
921 | } | |
922 | } | |
923 | ||
924 | state = read_u16le_inc(&rp); | |
925 | repetitions = read_u8_inc(&rp); | |
926 | for (j = 0; j < repetitions; j++) | |
927 | *wp++ = state; | |
928 | ||
929 | n_samples += repetitions; | |
930 | total_samples += repetitions; | |
931 | devc->total_samples += repetitions; | |
932 | if (!devc->reading_behind_trigger) { | |
933 | devc->n_reps_until_trigger--; | |
934 | if (devc->n_reps_until_trigger == 0) { | |
935 | devc->reading_behind_trigger = 1; | |
936 | do_signal_trigger = 1; | |
91f73872 | 937 | sr_dbg("Trigger position after %" PRIu64 " samples, %.6fms.", |
1ed93110 GS |
938 | devc->total_samples, |
939 | (double)devc->total_samples / devc->cur_samplerate * 1e3); | |
dfac9592 GS |
940 | } |
941 | } | |
942 | } | |
943 | (void)read_u8_inc(&rp); /* Skip sequence number. */ | |
944 | } | |
945 | if (n_samples) { | |
946 | logic.length = n_samples * 2; | |
947 | sr_session_send(sdi, &sr_packet); | |
948 | if (do_signal_trigger) { | |
949 | std_session_send_df_trigger(sdi); | |
950 | } | |
951 | } | |
91f73872 | 952 | sr_dbg("Send_chunk done after %u samples.", total_samples); |
dfac9592 GS |
953 | } |
954 | ||
955 | static void LIBUSB_CALL receive_transfer(struct libusb_transfer *transfer) | |
956 | { | |
957 | struct sr_dev_inst *sdi; | |
958 | struct dev_context *devc; | |
959 | struct sr_usb_dev_inst *usb; | |
960 | int ret; | |
961 | ||
962 | sdi = transfer->user_data; | |
963 | devc = sdi->priv; | |
964 | usb = sdi->conn; | |
965 | ||
966 | sr_dbg("receive_transfer(): status %s received %d bytes.", | |
1ed93110 | 967 | libusb_error_name(transfer->status), transfer->actual_length); |
dfac9592 GS |
968 | |
969 | if (transfer->status == LIBUSB_TRANSFER_TIMED_OUT) { | |
91f73872 | 970 | sr_err("USB bulk transfer timeout."); |
dfac9592 GS |
971 | devc->transfer_finished = 1; |
972 | } | |
973 | send_chunk(sdi, transfer->buffer, transfer->actual_length / TRANSFER_PACKET_LENGTH); | |
974 | ||
975 | devc->n_bytes_to_read -= transfer->actual_length; | |
976 | if (devc->n_bytes_to_read) { | |
977 | uint32_t to_read = devc->n_bytes_to_read; | |
96dc954e GS |
978 | /* |
979 | * Determine read size for the next USB transfer. Make | |
980 | * the buffer size a multiple of the endpoint packet | |
981 | * size. Don't exceed a maximum value. | |
982 | */ | |
dfac9592 GS |
983 | if (to_read >= LA2016_USB_BUFSZ) |
984 | to_read = LA2016_USB_BUFSZ; | |
96dc954e | 985 | else |
dfac9592 GS |
986 | to_read = (to_read + (LA2016_EP6_PKTSZ-1)) & ~(LA2016_EP6_PKTSZ-1); |
987 | libusb_fill_bulk_transfer( | |
988 | transfer, usb->devhdl, | |
989 | 0x86, transfer->buffer, to_read, | |
990 | receive_transfer, (void *)sdi, DEFAULT_TIMEOUT_MS); | |
991 | ||
992 | if ((ret = libusb_submit_transfer(transfer)) == 0) | |
993 | return; | |
91f73872 GS |
994 | sr_err("Cannot submit another USB transfer: %s.", |
995 | libusb_error_name(ret)); | |
dfac9592 GS |
996 | } |
997 | ||
998 | g_free(transfer->buffer); | |
999 | libusb_free_transfer(transfer); | |
1000 | devc->transfer_finished = 1; | |
1001 | } | |
1002 | ||
1003 | SR_PRIV int la2016_receive_data(int fd, int revents, void *cb_data) | |
1004 | { | |
1005 | const struct sr_dev_inst *sdi; | |
1006 | struct dev_context *devc; | |
1007 | struct drv_context *drvc; | |
1008 | struct timeval tv; | |
1009 | ||
1010 | (void)fd; | |
1011 | (void)revents; | |
1012 | ||
1013 | sdi = cb_data; | |
1014 | devc = sdi->priv; | |
1015 | drvc = sdi->driver->context; | |
1016 | ||
1017 | if (devc->have_trigger == 0) { | |
1018 | if (la2016_has_triggered(sdi) == 0) { | |
96dc954e | 1019 | /* Not yet ready for sample data download. */ |
dfac9592 GS |
1020 | return TRUE; |
1021 | } | |
1022 | devc->have_trigger = 1; | |
1023 | devc->transfer_finished = 0; | |
1024 | devc->reading_behind_trigger = 0; | |
1025 | devc->total_samples = 0; | |
96dc954e | 1026 | /* We can start downloading sample data. */ |
dfac9592 | 1027 | if (la2016_start_retrieval(sdi, receive_transfer) != SR_OK) { |
91f73872 | 1028 | sr_err("Cannot start acquisition data download."); |
dfac9592 GS |
1029 | return FALSE; |
1030 | } | |
91f73872 | 1031 | sr_dbg("Acquisition data download started."); |
dfac9592 GS |
1032 | std_session_send_df_frame_begin(sdi); |
1033 | ||
1034 | return TRUE; | |
1035 | } | |
1036 | ||
1037 | tv.tv_sec = tv.tv_usec = 0; | |
1038 | libusb_handle_events_timeout(drvc->sr_ctx->libusb_ctx, &tv); | |
1039 | ||
1040 | if (devc->transfer_finished) { | |
91f73872 | 1041 | sr_dbg("Download finished, post processing."); |
dfac9592 GS |
1042 | std_session_send_df_frame_end(sdi); |
1043 | ||
1044 | usb_source_remove(sdi->session, drvc->sr_ctx); | |
1045 | std_session_send_df_end(sdi); | |
1046 | ||
1047 | la2016_stop_acquisition(sdi); | |
1048 | ||
1049 | g_free(devc->convbuffer); | |
1050 | devc->convbuffer = NULL; | |
1051 | ||
1052 | devc->transfer = NULL; | |
1053 | ||
91f73872 | 1054 | sr_dbg("Download finished, done post processing."); |
dfac9592 GS |
1055 | } |
1056 | ||
1057 | return TRUE; | |
1058 | } | |
1059 | ||
f2cd2deb FS |
1060 | SR_PRIV int la2016_init_device(const struct sr_dev_inst *sdi) |
1061 | { | |
8b172e78 | 1062 | struct dev_context *devc; |
f2cd2deb | 1063 | uint16_t state; |
9de389b1 KG |
1064 | uint8_t buf[8]; |
1065 | int16_t purchase_date_bcd[2]; | |
1066 | uint8_t magic; | |
d6f89d4b | 1067 | const char *bitstream_fn; |
9de389b1 | 1068 | int ret; |
f2cd2deb | 1069 | |
8b172e78 KG |
1070 | devc = sdi->priv; |
1071 | ||
96dc954e GS |
1072 | /* |
1073 | * Four EEPROM bytes at offset 0x20 are purchase year and month | |
1074 | * in BCD format, with 16bit complemented checksum. For example | |
1075 | * 20 04 df fb translates to 2020-04. This can help identify the | |
1076 | * age of devices when unknown magic numbers are seen. | |
9de389b1 KG |
1077 | */ |
1078 | if ((ret = ctrl_in(sdi, CMD_EEPROM, 0x20, 0, purchase_date_bcd, sizeof(purchase_date_bcd))) != SR_OK) { | |
91f73872 | 1079 | sr_err("Cannot read purchase date in EEPROM."); |
1ed93110 | 1080 | } else { |
91f73872 GS |
1081 | sr_dbg("Purchase date: 20%02hx-%02hx.", |
1082 | (purchase_date_bcd[0]) & 0xff, | |
1083 | (purchase_date_bcd[0] >> 8) & 0xff); | |
84fe94bd | 1084 | if (purchase_date_bcd[0] != (0x0ffff & ~purchase_date_bcd[1])) { |
91f73872 | 1085 | sr_err("Purchase date fails checksum test."); |
9de389b1 | 1086 | } |
f2cd2deb | 1087 | } |
f2cd2deb | 1088 | |
9de389b1 | 1089 | /* |
96dc954e GS |
1090 | * Several Kingst logic analyzer devices share the same USB VID |
1091 | * and PID. The product ID determines which MCU firmware to load. | |
1092 | * The MCU firmware provides access to EEPROM content which then | |
1093 | * allows to identify the device model. Which in turn determines | |
1094 | * which FPGA bitstream to load. Eight bytes at offset 0x08 are | |
1095 | * to get inspected. | |
9de389b1 | 1096 | * |
96dc954e GS |
1097 | * EEPROM content for model identification is kept redundantly |
1098 | * in memory. The values are stored in verbatim and in inverted | |
1099 | * form, multiple copies are kept at different offsets. Example | |
1100 | * data: | |
9de389b1 | 1101 | * |
96dc954e GS |
1102 | * magic 0x08 |
1103 | * | ~magic 0xf7 | |
1104 | * | | | |
1105 | * 08f7000008f710ef | |
1106 | * | | | |
1107 | * | ~magic backup | |
1108 | * magic backup | |
9de389b1 | 1109 | * |
96dc954e GS |
1110 | * Exclusively inspecting the magic byte appears to be sufficient, |
1111 | * other fields seem to be 'don't care'. | |
9de389b1 | 1112 | * |
96dc954e GS |
1113 | * magic 2 == LA2016 using "kingst-la2016-fpga.bitstream" |
1114 | * magic 3 == LA1016 using "kingst-la1016-fpga.bitstream" | |
1115 | * magic 8 == LA2016a using "kingst-la2016a1-fpga.bitstream" | |
1116 | * (latest v1.3.0 PCB, perhaps others) | |
1117 | * magic 9 == LA1016a using "kingst-la1016a1-fpga.bitstream" | |
1118 | * (latest v1.3.0 PCB, perhaps others) | |
9de389b1 | 1119 | * |
96dc954e GS |
1120 | * When EEPROM content does not match the hardware configuration |
1121 | * (the board layout), the software may load but yield incorrect | |
1122 | * results (like swapped channels). The FPGA bitstream itself | |
1123 | * will authenticate with IC U10 and fail when its capabilities | |
1124 | * do not match the hardware model. An LA1016 won't become a | |
1125 | * LA2016 by faking its EEPROM content. | |
9de389b1 | 1126 | */ |
9de389b1 | 1127 | if ((ret = ctrl_in(sdi, CMD_EEPROM, 0x08, 0, &buf, sizeof(buf))) != SR_OK) { |
91f73872 | 1128 | sr_err("Cannot read EEPROM device identifier bytes."); |
f2cd2deb FS |
1129 | return ret; |
1130 | } | |
f2cd2deb | 1131 | |
9de389b1 | 1132 | magic = 0; |
96dc954e GS |
1133 | if (buf[0] == (0xff & ~buf[1])) { |
1134 | /* Primary copy of magic passes complement check. */ | |
9de389b1 | 1135 | magic = buf[0]; |
1ed93110 | 1136 | } else if (buf[4] == (0xff & ~buf[5])) { |
96dc954e | 1137 | /* Backup copy of magic passes complement check. */ |
91f73872 | 1138 | sr_dbg("Using backup copy of device type magic number."); |
9de389b1 | 1139 | magic = buf[4]; |
f2cd2deb FS |
1140 | } |
1141 | ||
91f73872 | 1142 | sr_dbg("Device type: magic number is %hhu.", magic); |
9de389b1 | 1143 | |
96dc954e | 1144 | /* Select the FPGA bitstream depending on the model. */ |
9de389b1 KG |
1145 | switch (magic) { |
1146 | case 2: | |
d6f89d4b | 1147 | bitstream_fn = FPGA_FW_LA2016; |
8b172e78 KG |
1148 | devc->max_samplerate = MAX_SAMPLE_RATE_LA2016; |
1149 | break; | |
1150 | case 3: | |
d6f89d4b | 1151 | bitstream_fn = FPGA_FW_LA1016; |
8b172e78 | 1152 | devc->max_samplerate = MAX_SAMPLE_RATE_LA1016; |
9de389b1 KG |
1153 | break; |
1154 | case 8: | |
d6f89d4b | 1155 | bitstream_fn = FPGA_FW_LA2016A; |
8b172e78 KG |
1156 | devc->max_samplerate = MAX_SAMPLE_RATE_LA2016; |
1157 | break; | |
1158 | case 9: | |
d6f89d4b | 1159 | bitstream_fn = FPGA_FW_LA1016A; |
8b172e78 | 1160 | devc->max_samplerate = MAX_SAMPLE_RATE_LA1016; |
9de389b1 KG |
1161 | break; |
1162 | default: | |
d6f89d4b GS |
1163 | bitstream_fn = NULL; |
1164 | break; | |
1165 | } | |
1166 | if (!bitstream_fn || !*bitstream_fn) { | |
91f73872 | 1167 | sr_err("Cannot identify as one of the supported models."); |
3f48ab02 FS |
1168 | return SR_ERR; |
1169 | } | |
f2cd2deb | 1170 | |
d6f89d4b GS |
1171 | if (check_fpga_bitstream(sdi) != SR_OK) { |
1172 | ret = upload_fpga_bitstream(sdi, bitstream_fn); | |
1173 | if (ret != SR_OK) { | |
1174 | sr_err("Cannot upload FPGA bitstream."); | |
1175 | return ret; | |
1176 | } | |
1177 | } | |
1178 | ret = enable_fpga_bitstream(sdi); | |
9de389b1 | 1179 | if (ret != SR_OK) { |
d6f89d4b | 1180 | sr_err("Cannot enable FPGA bitstream after upload."); |
9de389b1 KG |
1181 | return ret; |
1182 | } | |
1183 | ||
f2cd2deb | 1184 | state = run_state(sdi); |
9de389b1 | 1185 | if (state != 0x85e9) { |
91f73872 | 1186 | sr_warn("Unexpected run state, want 0x85e9, got 0x%04x.", state); |
9de389b1 | 1187 | } |
f2cd2deb | 1188 | |
00849545 | 1189 | if ((ret = ctrl_out(sdi, CMD_BULK_RESET, 0x00, 0, NULL, 0)) != SR_OK) { |
91f73872 | 1190 | sr_err("Cannot reset USB bulk transfer."); |
f2cd2deb FS |
1191 | return ret; |
1192 | } | |
9de389b1 | 1193 | |
91f73872 | 1194 | sr_dbg("Device should be initialized."); |
f2cd2deb FS |
1195 | |
1196 | return set_defaults(sdi); | |
1197 | } | |
1198 | ||
1199 | SR_PRIV int la2016_deinit_device(const struct sr_dev_inst *sdi) | |
1200 | { | |
1201 | int ret; | |
1202 | ||
00849545 | 1203 | if ((ret = ctrl_out(sdi, CMD_FPGA_ENABLE, 0x00, 0, NULL, 0)) != SR_OK) { |
91f73872 | 1204 | sr_err("Cannot deinitialize device's FPGA."); |
f2cd2deb FS |
1205 | return ret; |
1206 | } | |
1207 | ||
1208 | return SR_OK; | |
1209 | } |