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f2cd2deb FS |
1 | /* |
2 | * This file is part of the libsigrok project. | |
3 | * | |
4 | * Copyright (C) 2020 Florian Schmidt <schmidt_florian@gmx.de> | |
5 | * Copyright (C) 2013 Marcus Comstedt <marcus@mc.pp.se> | |
6 | * Copyright (C) 2013 Bert Vermeulen <bert@biot.com> | |
7 | * Copyright (C) 2012 Joel Holdsworth <joel@airwebreathe.org.uk> | |
8 | * | |
9 | * This program is free software: you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License as published by | |
11 | * the Free Software Foundation, either version 3 of the License, or | |
12 | * (at your option) any later version. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
21 | */ | |
22 | ||
23 | #include <config.h> | |
a7740b06 | 24 | |
f2cd2deb | 25 | #include <libsigrok/libsigrok.h> |
a7740b06 GS |
26 | #include <string.h> |
27 | ||
f2cd2deb FS |
28 | #include "libsigrok-internal.h" |
29 | #include "protocol.h" | |
30 | ||
d466f61c GS |
31 | /* USB PID dependent MCU firmware. Model dependent FPGA bitstream. */ |
32 | #define MCU_FWFILE_FMT "kingst-la-%04x.fw" | |
33 | #define FPGA_FWFILE_FMT "kingst-%s-fpga.bitstream" | |
34 | ||
35 | /* | |
36 | * List of supported devices and their features. See @ref kingst_model | |
37 | * for the fields' type and meaning. Table is sorted by EEPROM magic. | |
38 | * | |
39 | * TODO | |
40 | * - Below LA1016 properties were guessed, need verification. | |
41 | * - Add LA5016 and LA5032 devices when their EEPROM magic is known. | |
42 | * - Does LA1010 fit the driver implementation? Samplerates vary with | |
43 | * channel counts, lack of local sample memory. Most probably not. | |
44 | */ | |
45 | static const struct kingst_model models[] = { | |
46 | { 2, "LA2016", "la2016", SR_MHZ(200), 16, 1, }, | |
47 | { 3, "LA1016", "la1016", SR_MHZ(100), 16, 1, }, | |
48 | { 8, "LA2016", "la2016a1", SR_MHZ(200), 16, 1, }, | |
49 | { 9, "LA1016", "la1016a1", SR_MHZ(100), 16, 1, }, | |
50 | }; | |
f2cd2deb | 51 | |
96dc954e | 52 | /* USB vendor class control requests, executed by the Cypress FX2 MCU. */ |
84fe94bd | 53 | #define CMD_FPGA_ENABLE 0x10 |
96dc954e GS |
54 | #define CMD_FPGA_SPI 0x20 /* R/W access to FPGA registers via SPI. */ |
55 | #define CMD_BULK_START 0x30 /* Start sample data download via USB EP6 IN. */ | |
56 | #define CMD_BULK_RESET 0x38 /* Flush FIFO of FX2 USB EP6 IN. */ | |
57 | #define CMD_FPGA_INIT 0x50 /* Used before and after FPGA bitstream upload. */ | |
58 | #define CMD_KAUTH 0x60 /* Communicate to auth IC (U10). Not used. */ | |
59 | #define CMD_EEPROM 0xa2 /* R/W access to EEPROM content. */ | |
00849545 | 60 | |
42f6dd55 | 61 | /* |
96dc954e GS |
62 | * FPGA register addresses (base addresses when registers span multiple |
63 | * bytes, in that case data is kept in little endian format). Passed to | |
64 | * CMD_FPGA_SPI requests. The FX2 MCU transparently handles the detail | |
65 | * of SPI transfers encoding the read (1) or write (0) direction in the | |
66 | * MSB of the address field. There are some 60 byte-wide FPGA registers. | |
d6f89d4b GS |
67 | * |
68 | * Unfortunately the FPGA registers change their meaning between the | |
69 | * read and write directions of access, or exclusively provide one of | |
70 | * these directions and not the other. This is an arbitrary vendor's | |
71 | * choice, there is nothing which the sigrok driver could do about it. | |
72 | * Values written to registers typically cannot get read back, neither | |
73 | * verified after writing a configuration, nor queried upon startup for | |
74 | * automatic detection of the current configuration. Neither appear to | |
75 | * be there echo registers for presence and communication checks, nor | |
76 | * version identifying registers, as far as we know. | |
42f6dd55 | 77 | */ |
96dc954e GS |
78 | #define REG_RUN 0x00 /* Read capture status, write start capture. */ |
79 | #define REG_PWM_EN 0x02 /* User PWM channels on/off. */ | |
80 | #define REG_CAPT_MODE 0x03 /* Write 0x00 capture to SDRAM, 0x01 streaming. */ | |
81 | #define REG_BULK 0x08 /* Write start addr, byte count to download samples. */ | |
82 | #define REG_SAMPLING 0x10 /* Write capture config, read capture SDRAM location. */ | |
83 | #define REG_TRIGGER 0x20 /* write level and edge trigger config. */ | |
84 | #define REG_THRESHOLD 0x68 /* Write PWM config to setup input threshold DAC. */ | |
85 | #define REG_PWM1 0x70 /* Write config for user PWM1. */ | |
86 | #define REG_PWM2 0x78 /* Write config for user PWM2. */ | |
f2cd2deb | 87 | |
852c7d14 GS |
88 | /* Bit patterns to write to REG_RUN, setup run mode. */ |
89 | #define RUNMODE_HALT 0x00 | |
90 | #define RUNMODE_RUN 0x03 | |
91 | ||
b711fd8e GS |
92 | /* Bit patterns when reading from REG_RUN, get run state. */ |
93 | #define RUNSTATE_IDLE_BIT (1UL << 0) | |
94 | #define RUNSTATE_DRAM_BIT (1UL << 1) | |
95 | #define RUNSTATE_TRGD_BIT (1UL << 2) | |
96 | #define RUNSTATE_POST_BIT (1UL << 3) | |
97 | ||
f2cd2deb | 98 | static int ctrl_in(const struct sr_dev_inst *sdi, |
1ed93110 GS |
99 | uint8_t bRequest, uint16_t wValue, uint16_t wIndex, |
100 | void *data, uint16_t wLength) | |
f2cd2deb FS |
101 | { |
102 | struct sr_usb_dev_inst *usb; | |
103 | int ret; | |
104 | ||
105 | usb = sdi->conn; | |
106 | ||
411ad77c GS |
107 | ret = libusb_control_transfer(usb->devhdl, |
108 | LIBUSB_REQUEST_TYPE_VENDOR | LIBUSB_ENDPOINT_IN, | |
109 | bRequest, wValue, wIndex, data, wLength, | |
110 | DEFAULT_TIMEOUT_MS); | |
111 | if (ret != wLength) { | |
91f73872 GS |
112 | sr_dbg("USB ctrl in: %d bytes, req %d val %#x idx %d: %s.", |
113 | wLength, bRequest, wValue, wIndex, | |
114 | libusb_error_name(ret)); | |
115 | sr_err("Cannot read %d bytes from USB: %s.", | |
116 | wLength, libusb_error_name(ret)); | |
f2cd2deb FS |
117 | return SR_ERR; |
118 | } | |
119 | ||
120 | return SR_OK; | |
121 | } | |
122 | ||
123 | static int ctrl_out(const struct sr_dev_inst *sdi, | |
1ed93110 GS |
124 | uint8_t bRequest, uint16_t wValue, uint16_t wIndex, |
125 | void *data, uint16_t wLength) | |
f2cd2deb FS |
126 | { |
127 | struct sr_usb_dev_inst *usb; | |
128 | int ret; | |
129 | ||
130 | usb = sdi->conn; | |
131 | ||
411ad77c GS |
132 | ret = libusb_control_transfer(usb->devhdl, |
133 | LIBUSB_REQUEST_TYPE_VENDOR | LIBUSB_ENDPOINT_OUT, | |
134 | bRequest, wValue, wIndex, data, wLength, | |
135 | DEFAULT_TIMEOUT_MS); | |
136 | if (ret != wLength) { | |
91f73872 GS |
137 | sr_dbg("USB ctrl out: %d bytes, req %d val %#x idx %d: %s.", |
138 | wLength, bRequest, wValue, wIndex, | |
139 | libusb_error_name(ret)); | |
140 | sr_err("Cannot write %d bytes to USB: %s.", | |
141 | wLength, libusb_error_name(ret)); | |
f2cd2deb FS |
142 | return SR_ERR; |
143 | } | |
144 | ||
145 | return SR_OK; | |
146 | } | |
147 | ||
d6f89d4b GS |
148 | /* |
149 | * Check the necessity for FPGA bitstream upload, because another upload | |
150 | * would take some 600ms which is undesirable after program startup. Try | |
151 | * to access some FPGA registers and check the values' plausibility. The | |
152 | * check should fail on the safe side, request another upload when in | |
153 | * doubt. A positive response (the request to continue operation with the | |
154 | * currently active bitstream) should be conservative. Accessing multiple | |
155 | * registers is considered cheap compared to the cost of bitstream upload. | |
156 | * | |
157 | * It helps though that both the vendor software and the sigrok driver | |
158 | * use the same bundle of MCU firmware and FPGA bitstream for any of the | |
159 | * supported models. We don't expect to successfully communicate to the | |
160 | * device yet disagree on its protocol. Ideally we would access version | |
161 | * identifying registers for improved robustness, but are not aware of | |
162 | * any. A bitstream reload can always be forced by a power cycle. | |
163 | */ | |
164 | static int check_fpga_bitstream(const struct sr_dev_inst *sdi) | |
165 | { | |
166 | uint8_t init_rsp; | |
167 | int ret; | |
168 | uint16_t run_state; | |
169 | uint8_t pwm_en; | |
170 | size_t read_len; | |
171 | uint8_t buff[sizeof(run_state)]; | |
172 | const uint8_t *rdptr; | |
173 | ||
174 | sr_dbg("Checking operation of the FPGA bitstream."); | |
175 | ||
852c7d14 | 176 | init_rsp = ~0; |
d6f89d4b GS |
177 | ret = ctrl_in(sdi, CMD_FPGA_INIT, 0x00, 0, &init_rsp, sizeof(init_rsp)); |
178 | if (ret != SR_OK || init_rsp != 0) { | |
179 | sr_dbg("FPGA init query failed, or unexpected response."); | |
180 | return SR_ERR_IO; | |
181 | } | |
182 | ||
183 | read_len = sizeof(run_state); | |
184 | ret = ctrl_in(sdi, CMD_FPGA_SPI, REG_RUN, 0, buff, read_len); | |
185 | if (ret != SR_OK) { | |
186 | sr_dbg("FPGA register access failed (run state)."); | |
187 | return SR_ERR_IO; | |
188 | } | |
189 | rdptr = buff; | |
190 | run_state = read_u16le_inc(&rdptr); | |
191 | sr_spew("FPGA register: run state 0x%04x.", run_state); | |
192 | if (run_state && (run_state & 0x3) != 0x1) { | |
193 | sr_dbg("Unexpected FPGA register content (run state)."); | |
194 | return SR_ERR_DATA; | |
195 | } | |
196 | if (run_state && (run_state & ~0xf) != 0x85e0) { | |
197 | sr_dbg("Unexpected FPGA register content (run state)."); | |
198 | return SR_ERR_DATA; | |
199 | } | |
200 | ||
201 | read_len = sizeof(pwm_en); | |
202 | ret = ctrl_in(sdi, CMD_FPGA_SPI, REG_PWM_EN, 0, buff, read_len); | |
203 | if (ret != SR_OK) { | |
204 | sr_dbg("FPGA register access failed (PWM enable)."); | |
205 | return SR_ERR_IO; | |
206 | } | |
207 | rdptr = buff; | |
208 | pwm_en = read_u8_inc(&rdptr); | |
209 | sr_spew("FPGA register: PWM enable 0x%02x.", pwm_en); | |
210 | if ((pwm_en & 0x3) != 0x0) { | |
211 | sr_dbg("Unexpected FPGA register content (PWM enable)."); | |
212 | return SR_ERR_DATA; | |
213 | } | |
214 | ||
215 | sr_info("Could re-use current FPGA bitstream. No upload required."); | |
216 | return SR_OK; | |
217 | } | |
218 | ||
1ed93110 GS |
219 | static int upload_fpga_bitstream(const struct sr_dev_inst *sdi, |
220 | const char *bitstream_fname) | |
f2cd2deb FS |
221 | { |
222 | struct drv_context *drvc; | |
223 | struct sr_usb_dev_inst *usb; | |
224 | struct sr_resource bitstream; | |
b0d0131e | 225 | uint32_t bitstream_size; |
c3d40037 HK |
226 | uint8_t buffer[sizeof(uint32_t)]; |
227 | uint8_t *wrptr; | |
f2cd2deb | 228 | uint8_t block[4096]; |
3f48ab02 FS |
229 | int len, act_len; |
230 | unsigned int pos; | |
f2cd2deb | 231 | int ret; |
b0d0131e | 232 | unsigned int zero_pad_to; |
f2cd2deb FS |
233 | |
234 | drvc = sdi->driver->context; | |
235 | usb = sdi->conn; | |
236 | ||
9de389b1 | 237 | sr_info("Uploading FPGA bitstream '%s'.", bitstream_fname); |
f2cd2deb | 238 | |
411ad77c GS |
239 | ret = sr_resource_open(drvc->sr_ctx, &bitstream, |
240 | SR_RESOURCE_FIRMWARE, bitstream_fname); | |
f2cd2deb | 241 | if (ret != SR_OK) { |
91f73872 | 242 | sr_err("Cannot find FPGA bitstream %s.", bitstream_fname); |
f2cd2deb FS |
243 | return ret; |
244 | } | |
245 | ||
b0d0131e | 246 | bitstream_size = (uint32_t)bitstream.size; |
c3d40037 | 247 | wrptr = buffer; |
b0d0131e | 248 | write_u32le_inc(&wrptr, bitstream_size); |
411ad77c GS |
249 | ret = ctrl_out(sdi, CMD_FPGA_INIT, 0x00, 0, buffer, wrptr - buffer); |
250 | if (ret != SR_OK) { | |
91f73872 | 251 | sr_err("Cannot initiate FPGA bitstream upload."); |
f2cd2deb FS |
252 | sr_resource_close(drvc->sr_ctx, &bitstream); |
253 | return ret; | |
254 | } | |
b0d0131e GS |
255 | zero_pad_to = bitstream_size; |
256 | zero_pad_to += LA2016_EP2_PADDING - 1; | |
257 | zero_pad_to /= LA2016_EP2_PADDING; | |
258 | zero_pad_to *= LA2016_EP2_PADDING; | |
f2cd2deb FS |
259 | |
260 | pos = 0; | |
261 | while (1) { | |
3f48ab02 | 262 | if (pos < bitstream.size) { |
411ad77c GS |
263 | len = (int)sr_resource_read(drvc->sr_ctx, &bitstream, |
264 | block, sizeof(block)); | |
3f48ab02 | 265 | if (len < 0) { |
91f73872 | 266 | sr_err("Cannot read FPGA bitstream."); |
3f48ab02 FS |
267 | sr_resource_close(drvc->sr_ctx, &bitstream); |
268 | return SR_ERR; | |
269 | } | |
270 | } else { | |
96dc954e | 271 | /* Zero-pad until 'zero_pad_to'. */ |
3f48ab02 FS |
272 | len = zero_pad_to - pos; |
273 | if ((unsigned)len > sizeof(block)) | |
274 | len = sizeof(block); | |
275 | memset(&block, 0, len); | |
f2cd2deb FS |
276 | } |
277 | if (len == 0) | |
278 | break; | |
279 | ||
852c7d14 | 280 | ret = libusb_bulk_transfer(usb->devhdl, USB_EP_FPGA_BITSTREAM, |
1ed93110 | 281 | &block[0], len, &act_len, DEFAULT_TIMEOUT_MS); |
f2cd2deb | 282 | if (ret != 0) { |
91f73872 GS |
283 | sr_dbg("Cannot write FPGA bitstream, block %#x len %d: %s.", |
284 | pos, (int)len, libusb_error_name(ret)); | |
f2cd2deb FS |
285 | ret = SR_ERR; |
286 | break; | |
287 | } | |
288 | if (act_len != len) { | |
91f73872 GS |
289 | sr_dbg("Short write for FPGA bitstream, block %#x len %d: got %d.", |
290 | pos, (int)len, act_len); | |
f2cd2deb FS |
291 | ret = SR_ERR; |
292 | break; | |
293 | } | |
294 | pos += len; | |
295 | } | |
296 | sr_resource_close(drvc->sr_ctx, &bitstream); | |
5eb1b63d | 297 | if (ret != SR_OK) |
f2cd2deb | 298 | return ret; |
91f73872 GS |
299 | sr_info("FPGA bitstream upload (%" PRIu64 " bytes) done.", |
300 | bitstream.size); | |
f2cd2deb | 301 | |
d6f89d4b GS |
302 | return SR_OK; |
303 | } | |
304 | ||
305 | static int enable_fpga_bitstream(const struct sr_dev_inst *sdi) | |
306 | { | |
307 | int ret; | |
411ad77c | 308 | uint8_t resp; |
d6f89d4b | 309 | |
411ad77c GS |
310 | ret = ctrl_in(sdi, CMD_FPGA_INIT, 0x00, 0, &resp, sizeof(resp)); |
311 | if (ret != SR_OK) { | |
91f73872 | 312 | sr_err("Cannot read response after FPGA bitstream upload."); |
f2cd2deb FS |
313 | return ret; |
314 | } | |
411ad77c | 315 | if (resp != 0) { |
91f73872 | 316 | sr_err("Unexpected FPGA bitstream upload response, got 0x%02x, want 0.", |
411ad77c | 317 | resp); |
3f48ab02 FS |
318 | return SR_ERR; |
319 | } | |
852c7d14 | 320 | g_usleep(30 * 1000); |
f2cd2deb | 321 | |
411ad77c GS |
322 | ret = ctrl_out(sdi, CMD_FPGA_ENABLE, 0x01, 0, NULL, 0); |
323 | if (ret != SR_OK) { | |
91f73872 | 324 | sr_err("Cannot enable FPGA after bitstream upload."); |
f2cd2deb FS |
325 | return ret; |
326 | } | |
852c7d14 | 327 | g_usleep(40 * 1000); |
d6f89d4b | 328 | |
f2cd2deb FS |
329 | return SR_OK; |
330 | } | |
331 | ||
332 | static int set_threshold_voltage(const struct sr_dev_inst *sdi, float voltage) | |
333 | { | |
334 | struct dev_context *devc; | |
f2cd2deb | 335 | int ret; |
1ed93110 | 336 | uint16_t duty_R79, duty_R56; |
f2ad79d1 KG |
337 | uint8_t buf[2 * sizeof(uint16_t)]; |
338 | uint8_t *wrptr; | |
339 | ||
084d6b92 GS |
340 | devc = sdi->priv; |
341 | ||
96dc954e | 342 | /* Clamp threshold setting to valid range for LA2016. */ |
f2ad79d1 KG |
343 | if (voltage > 4.0) { |
344 | voltage = 4.0; | |
1ed93110 | 345 | } else if (voltage < -4.0) { |
f2ad79d1 KG |
346 | voltage = -4.0; |
347 | } | |
348 | ||
349 | /* | |
96dc954e GS |
350 | * Two PWM output channels feed one DAC which generates a bias |
351 | * voltage, which offsets the input probe's voltage level, and | |
352 | * in combination with the FPGA pins' fixed threshold result in | |
353 | * a programmable input threshold from the user's perspective. | |
354 | * The PWM outputs can be seen on R79 and R56 respectively, the | |
355 | * frequency is 100kHz and the duty cycle varies. The R79 PWM | |
356 | * uses three discrete settings. The R56 PWM varies with desired | |
357 | * thresholds and depends on the R79 PWM configuration. See the | |
358 | * schematics comments which discuss the formulae. | |
f2ad79d1 KG |
359 | */ |
360 | if (voltage >= 2.9) { | |
96dc954e | 361 | duty_R79 = 0; /* PWM off (0V). */ |
f2ad79d1 | 362 | duty_R56 = (uint16_t)(302 * voltage - 363); |
c34f4a89 | 363 | } else if (voltage > -0.4) { |
96dc954e | 364 | duty_R79 = 0x00f2; /* 25% duty cycle. */ |
f2ad79d1 | 365 | duty_R56 = (uint16_t)(302 * voltage + 121); |
c34f4a89 GS |
366 | } else { |
367 | duty_R79 = 0x02d7; /* 72% duty cycle. */ | |
368 | duty_R56 = (uint16_t)(302 * voltage + 1090); | |
f2ad79d1 KG |
369 | } |
370 | ||
96dc954e | 371 | /* Clamp duty register values to sensible limits. */ |
f2ad79d1 KG |
372 | if (duty_R56 < 10) { |
373 | duty_R56 = 10; | |
1ed93110 | 374 | } else if (duty_R56 > 1100) { |
f2ad79d1 KG |
375 | duty_R56 = 1100; |
376 | } | |
377 | ||
91f73872 GS |
378 | sr_dbg("Set threshold voltage %.2fV.", voltage); |
379 | sr_dbg("Duty cycle values: R56 0x%04x, R79 0x%04x.", duty_R56, duty_R79); | |
f2ad79d1 KG |
380 | |
381 | wrptr = buf; | |
382 | write_u16le_inc(&wrptr, duty_R56); | |
383 | write_u16le_inc(&wrptr, duty_R79); | |
384 | ||
385 | ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_THRESHOLD, 0, buf, wrptr - buf); | |
f2cd2deb | 386 | if (ret != SR_OK) { |
91f73872 | 387 | sr_err("Cannot set threshold voltage %.2fV.", voltage); |
f2cd2deb FS |
388 | return ret; |
389 | } | |
390 | devc->threshold_voltage = voltage; | |
391 | ||
392 | return SR_OK; | |
393 | } | |
394 | ||
86d77b75 | 395 | static int enable_pwm(const struct sr_dev_inst *sdi, gboolean p1, gboolean p2) |
f2cd2deb FS |
396 | { |
397 | struct dev_context *devc; | |
398 | uint8_t cfg; | |
399 | int ret; | |
400 | ||
401 | devc = sdi->priv; | |
f2cd2deb | 402 | |
86d77b75 GS |
403 | cfg = 0; |
404 | if (p1) | |
405 | cfg |= 1U << 0; | |
406 | if (p2) | |
407 | cfg |= 1U << 1; | |
91f73872 | 408 | sr_dbg("Set PWM enable %d %d. Config 0x%02x.", p1, p2, cfg); |
86d77b75 | 409 | |
42f6dd55 | 410 | ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_PWM_EN, 0, &cfg, sizeof(cfg)); |
f2cd2deb | 411 | if (ret != SR_OK) { |
91f73872 | 412 | sr_err("Cannot setup PWM enabled state."); |
f2cd2deb FS |
413 | return ret; |
414 | } | |
86d77b75 | 415 | |
f2cd2deb FS |
416 | devc->pwm_setting[0].enabled = (p1) ? 1 : 0; |
417 | devc->pwm_setting[1].enabled = (p2) ? 1 : 0; | |
418 | ||
419 | return SR_OK; | |
420 | } | |
421 | ||
86d77b75 | 422 | static int configure_pwm(const struct sr_dev_inst *sdi, uint8_t which, |
1ed93110 | 423 | float freq, float duty) |
f2cd2deb | 424 | { |
86d77b75 GS |
425 | static uint8_t ctrl_reg_tab[] = { REG_PWM1, REG_PWM2, }; |
426 | ||
f2cd2deb | 427 | struct dev_context *devc; |
86d77b75 GS |
428 | uint8_t ctrl_reg; |
429 | struct pwm_setting_dev cfg; | |
430 | struct pwm_setting *setting; | |
f2cd2deb | 431 | int ret; |
c3d40037 HK |
432 | uint8_t buf[2 * sizeof(uint32_t)]; |
433 | uint8_t *wrptr; | |
f2cd2deb FS |
434 | |
435 | devc = sdi->priv; | |
436 | ||
86d77b75 | 437 | if (which < 1 || which > ARRAY_SIZE(ctrl_reg_tab)) { |
91f73872 | 438 | sr_err("Invalid PWM channel: %d.", which); |
f2cd2deb FS |
439 | return SR_ERR; |
440 | } | |
86d77b75 | 441 | if (freq < 0 || freq > MAX_PWM_FREQ) { |
91f73872 | 442 | sr_err("Too high a PWM frequency: %.1f.", freq); |
f2cd2deb FS |
443 | return SR_ERR; |
444 | } | |
86d77b75 | 445 | if (duty < 0 || duty > 100) { |
91f73872 | 446 | sr_err("Invalid PWM duty cycle: %f.", duty); |
f2cd2deb FS |
447 | return SR_ERR; |
448 | } | |
449 | ||
86d77b75 | 450 | memset(&cfg, 0, sizeof(cfg)); |
f2cd2deb FS |
451 | cfg.period = (uint32_t)(PWM_CLOCK / freq); |
452 | cfg.duty = (uint32_t)(0.5f + (cfg.period * duty / 100.)); | |
91f73872 | 453 | sr_dbg("Set PWM%d period %d, duty %d.", which, cfg.period, cfg.duty); |
f2cd2deb | 454 | |
86d77b75 | 455 | ctrl_reg = ctrl_reg_tab[which - 1]; |
c3d40037 HK |
456 | wrptr = buf; |
457 | write_u32le_inc(&wrptr, cfg.period); | |
458 | write_u32le_inc(&wrptr, cfg.duty); | |
86d77b75 | 459 | ret = ctrl_out(sdi, CMD_FPGA_SPI, ctrl_reg, 0, buf, wrptr - buf); |
f2cd2deb | 460 | if (ret != SR_OK) { |
91f73872 GS |
461 | sr_err("Cannot setup PWM%d configuration %d %d.", |
462 | which, cfg.period, cfg.duty); | |
f2cd2deb FS |
463 | return ret; |
464 | } | |
86d77b75 | 465 | |
f2cd2deb FS |
466 | setting = &devc->pwm_setting[which - 1]; |
467 | setting->freq = freq; | |
468 | setting->duty = duty; | |
f2cd2deb FS |
469 | |
470 | return SR_OK; | |
471 | } | |
472 | ||
473 | static int set_defaults(const struct sr_dev_inst *sdi) | |
474 | { | |
475 | struct dev_context *devc; | |
476 | int ret; | |
477 | ||
478 | devc = sdi->priv; | |
479 | ||
f2cd2deb FS |
480 | ret = set_threshold_voltage(sdi, devc->threshold_voltage); |
481 | if (ret) | |
482 | return ret; | |
483 | ||
86d77b75 | 484 | ret = enable_pwm(sdi, FALSE, FALSE); |
f2cd2deb FS |
485 | if (ret) |
486 | return ret; | |
487 | ||
86d77b75 | 488 | ret = configure_pwm(sdi, 1, SR_KHZ(1), 50); |
f2cd2deb FS |
489 | if (ret) |
490 | return ret; | |
491 | ||
86d77b75 | 492 | ret = configure_pwm(sdi, 2, SR_KHZ(100), 50); |
f2cd2deb FS |
493 | if (ret) |
494 | return ret; | |
495 | ||
86d77b75 | 496 | ret = enable_pwm(sdi, TRUE, TRUE); |
f2cd2deb FS |
497 | if (ret) |
498 | return ret; | |
499 | ||
500 | return SR_OK; | |
501 | } | |
502 | ||
ea436ba7 GS |
503 | static uint16_t get_channels_mask(const struct sr_dev_inst *sdi) |
504 | { | |
505 | uint16_t channels; | |
506 | GSList *l; | |
507 | struct sr_channel *ch; | |
508 | ||
509 | channels = 0; | |
510 | for (l = sdi->channels; l; l = l->next) { | |
511 | ch = l->data; | |
512 | if (ch->type != SR_CHANNEL_LOGIC) | |
513 | continue; | |
514 | if (!ch->enabled) | |
515 | continue; | |
516 | channels |= 1UL << ch->index; | |
517 | } | |
518 | ||
519 | return channels; | |
520 | } | |
521 | ||
f2cd2deb FS |
522 | static int set_trigger_config(const struct sr_dev_inst *sdi) |
523 | { | |
524 | struct dev_context *devc; | |
525 | struct sr_trigger *trigger; | |
66f5f697 | 526 | struct trigger_cfg cfg; |
f2cd2deb FS |
527 | GSList *stages; |
528 | GSList *channel; | |
529 | struct sr_trigger_stage *stage1; | |
530 | struct sr_trigger_match *match; | |
531 | uint16_t ch_mask; | |
532 | int ret; | |
c3d40037 HK |
533 | uint8_t buf[4 * sizeof(uint32_t)]; |
534 | uint8_t *wrptr; | |
f2cd2deb FS |
535 | |
536 | devc = sdi->priv; | |
537 | trigger = sr_session_trigger_get(sdi->session); | |
538 | ||
539 | memset(&cfg, 0, sizeof(cfg)); | |
540 | ||
ea436ba7 | 541 | cfg.channels = get_channels_mask(sdi); |
f2cd2deb FS |
542 | |
543 | if (trigger && trigger->stages) { | |
544 | stages = trigger->stages; | |
545 | stage1 = stages->data; | |
546 | if (stages->next) { | |
547 | sr_err("Only one trigger stage supported for now."); | |
548 | return SR_ERR; | |
549 | } | |
550 | channel = stage1->matches; | |
551 | while (channel) { | |
552 | match = channel->data; | |
cf057ac4 | 553 | ch_mask = 1UL << match->channel->index; |
f2cd2deb FS |
554 | |
555 | switch (match->match) { | |
556 | case SR_TRIGGER_ZERO: | |
557 | cfg.level |= ch_mask; | |
558 | cfg.high_or_falling &= ~ch_mask; | |
559 | break; | |
560 | case SR_TRIGGER_ONE: | |
561 | cfg.level |= ch_mask; | |
562 | cfg.high_or_falling |= ch_mask; | |
563 | break; | |
564 | case SR_TRIGGER_RISING: | |
565 | if ((cfg.enabled & ~cfg.level)) { | |
91f73872 | 566 | sr_err("Device only supports one edge trigger."); |
f2cd2deb FS |
567 | return SR_ERR; |
568 | } | |
569 | cfg.level &= ~ch_mask; | |
570 | cfg.high_or_falling &= ~ch_mask; | |
571 | break; | |
572 | case SR_TRIGGER_FALLING: | |
573 | if ((cfg.enabled & ~cfg.level)) { | |
91f73872 | 574 | sr_err("Device only supports one edge trigger."); |
f2cd2deb FS |
575 | return SR_ERR; |
576 | } | |
577 | cfg.level &= ~ch_mask; | |
578 | cfg.high_or_falling |= ch_mask; | |
579 | break; | |
580 | default: | |
91f73872 | 581 | sr_err("Unknown trigger condition."); |
f2cd2deb FS |
582 | return SR_ERR; |
583 | } | |
584 | cfg.enabled |= ch_mask; | |
585 | channel = channel->next; | |
586 | } | |
587 | } | |
91f73872 GS |
588 | sr_dbg("Set trigger config: " |
589 | "channels 0x%04x, trigger-enabled 0x%04x, " | |
590 | "level-triggered 0x%04x, high/falling 0x%04x.", | |
591 | cfg.channels, cfg.enabled, cfg.level, cfg.high_or_falling); | |
f2cd2deb | 592 | |
cf057ac4 | 593 | devc->trigger_involved = cfg.enabled != 0; |
f2cd2deb | 594 | |
c3d40037 HK |
595 | wrptr = buf; |
596 | write_u32le_inc(&wrptr, cfg.channels); | |
597 | write_u32le_inc(&wrptr, cfg.enabled); | |
598 | write_u32le_inc(&wrptr, cfg.level); | |
599 | write_u32le_inc(&wrptr, cfg.high_or_falling); | |
852c7d14 GS |
600 | /* TODO |
601 | * Comment on this literal 16. Origin, meaning? Cannot be the | |
602 | * register offset, nor the transfer length. Is it a channels | |
603 | * count that is relevant for 16 and 32 channel models? Is it | |
604 | * an obsolete experiment? | |
605 | */ | |
42f6dd55 | 606 | ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_TRIGGER, 16, buf, wrptr - buf); |
f2cd2deb | 607 | if (ret != SR_OK) { |
91f73872 | 608 | sr_err("Cannot setup trigger configuration."); |
f2cd2deb FS |
609 | return ret; |
610 | } | |
611 | ||
612 | return SR_OK; | |
613 | } | |
614 | ||
615 | static int set_sample_config(const struct sr_dev_inst *sdi) | |
616 | { | |
617 | struct dev_context *devc; | |
d8fbfcd9 | 618 | uint64_t min_samplerate, eff_samplerate; |
adab4d91 | 619 | uint16_t divider_u16; |
a38f0f5e | 620 | uint64_t limit_samples; |
adab4d91 GS |
621 | uint64_t pre_trigger_samples; |
622 | uint64_t pre_trigger_memory; | |
623 | uint8_t buf[REG_TRIGGER - REG_SAMPLING]; /* Width of REG_SAMPLING. */ | |
c3d40037 | 624 | uint8_t *wrptr; |
adab4d91 | 625 | int ret; |
f2cd2deb FS |
626 | |
627 | devc = sdi->priv; | |
f2cd2deb | 628 | |
d466f61c | 629 | if (devc->cur_samplerate > devc->model->samplerate) { |
91f73872 GS |
630 | sr_err("Too high a sample rate: %" PRIu64 ".", |
631 | devc->cur_samplerate); | |
ea436ba7 GS |
632 | return SR_ERR_ARG; |
633 | } | |
d8fbfcd9 GS |
634 | min_samplerate = devc->model->samplerate; |
635 | min_samplerate /= 65536; | |
636 | if (devc->cur_samplerate < min_samplerate) { | |
ea436ba7 GS |
637 | sr_err("Too low a sample rate: %" PRIu64 ".", |
638 | devc->cur_samplerate); | |
639 | return SR_ERR_ARG; | |
f2cd2deb | 640 | } |
d8fbfcd9 GS |
641 | divider_u16 = devc->model->samplerate / devc->cur_samplerate; |
642 | eff_samplerate = devc->model->samplerate / divider_u16; | |
f2cd2deb | 643 | |
a38f0f5e GS |
644 | ret = sr_sw_limits_get_remain(&devc->sw_limits, |
645 | &limit_samples, NULL, NULL, NULL); | |
646 | if (ret != SR_OK) { | |
647 | sr_err("Cannot get acquisition limits."); | |
648 | return ret; | |
f2cd2deb | 649 | } |
a38f0f5e | 650 | if (limit_samples > LA2016_NUM_SAMPLES_MAX) { |
d8fbfcd9 GS |
651 | sr_warn("Too high a sample depth: %" PRIu64 ", capping.", |
652 | limit_samples); | |
653 | limit_samples = LA2016_NUM_SAMPLES_MAX; | |
a38f0f5e | 654 | } |
d8fbfcd9 GS |
655 | if (limit_samples == 0) { |
656 | limit_samples = LA2016_NUM_SAMPLES_MAX; | |
657 | sr_dbg("Passing %" PRIu64 " to HW for unlimited samples.", | |
658 | limit_samples); | |
ea436ba7 | 659 | } |
f2cd2deb | 660 | |
adab4d91 GS |
661 | /* |
662 | * The acquisition configuration communicates "pre-trigger" | |
663 | * specs in several formats. sigrok users provide a percentage | |
664 | * (0-100%), which translates to a pre-trigger samples count | |
665 | * (assuming that a total samples count limit was specified). | |
666 | * The device supports hardware compression, which depends on | |
667 | * slowly changing input data to be effective. Fast changing | |
668 | * input data may occupy more space in sample memory than its | |
669 | * uncompressed form would. This is why a third parameter can | |
670 | * limit the amount of sample memory to use for pre-trigger | |
671 | * data. Only the upper 24 bits of that memory size spec get | |
672 | * communicated to the device (written to its FPGA register). | |
d8fbfcd9 GS |
673 | * |
674 | * TODO Determine whether the pre-trigger memory size gets | |
675 | * specified in samples or in bytes. A previous implementation | |
676 | * suggests bytes but this is suspicious when every other spec | |
677 | * is in terms of samples. | |
adab4d91 | 678 | */ |
d8fbfcd9 GS |
679 | if (devc->trigger_involved) { |
680 | pre_trigger_samples = limit_samples; | |
681 | pre_trigger_samples *= devc->capture_ratio; | |
682 | pre_trigger_samples /= 100; | |
683 | pre_trigger_memory = devc->model->memory_bits; | |
684 | pre_trigger_memory *= UINT64_C(1024 * 1024 * 1024); | |
685 | pre_trigger_memory /= 8; /* devc->model->channel_count ? */ | |
686 | pre_trigger_memory *= devc->capture_ratio; | |
687 | pre_trigger_memory /= 100; | |
688 | } else { | |
689 | sr_dbg("No trigger setup, skipping pre-trigger config."); | |
690 | pre_trigger_samples = 1; | |
691 | pre_trigger_memory = 0; | |
692 | } | |
693 | /* Ensure non-zero value after LSB shift out in HW reg. */ | |
694 | if (pre_trigger_memory < 0x100) { | |
695 | pre_trigger_memory = 0x100; | |
696 | } | |
f2cd2deb | 697 | |
adab4d91 | 698 | sr_dbg("Set sample config: %" PRIu64 "kHz, %" PRIu64 " samples.", |
d8fbfcd9 | 699 | eff_samplerate / SR_KHZ(1), limit_samples); |
adab4d91 GS |
700 | sr_dbg("Capture ratio %" PRIu64 "%%, count %" PRIu64 ", mem %" PRIu64 ".", |
701 | devc->capture_ratio, pre_trigger_samples, pre_trigger_memory); | |
f2cd2deb | 702 | |
b1a17c1a GS |
703 | /* |
704 | * The acquisition configuration occupies a total of 16 bytes: | |
705 | * - A 34bit total samples count limit (up to 10 billions) that | |
706 | * is kept in a 40bit register. | |
707 | * - A 34bit pre-trigger samples count limit (up to 10 billions) | |
708 | * in another 40bit register. | |
709 | * - A 32bit pre-trigger memory space limit (in bytes) of which | |
710 | * the upper 24bits are kept in an FPGA register. | |
711 | * - A 16bit clock divider which gets applied to the maximum | |
712 | * samplerate of the device. | |
713 | * - An 8bit register of unknown meaning. Currently always 0. | |
714 | */ | |
c3d40037 | 715 | wrptr = buf; |
a38f0f5e | 716 | write_u40le_inc(&wrptr, limit_samples); |
b1a17c1a GS |
717 | write_u40le_inc(&wrptr, pre_trigger_samples); |
718 | write_u24le_inc(&wrptr, pre_trigger_memory >> 8); | |
adab4d91 | 719 | write_u16le_inc(&wrptr, divider_u16); |
0d8e1ffc | 720 | write_u8_inc(&wrptr, 0); |
42f6dd55 | 721 | ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_SAMPLING, 0, buf, wrptr - buf); |
f2cd2deb | 722 | if (ret != SR_OK) { |
91f73872 | 723 | sr_err("Cannot setup acquisition configuration."); |
f2cd2deb FS |
724 | return ret; |
725 | } | |
726 | ||
727 | return SR_OK; | |
728 | } | |
729 | ||
96dc954e GS |
730 | /* |
731 | * FPGA register REG_RUN holds the run state (u16le format). Bit fields | |
732 | * of interest: | |
733 | * bit 0: value 1 = idle | |
734 | * bit 1: value 1 = writing to SDRAM | |
735 | * bit 2: value 0 = waiting for trigger, 1 = trigger seen | |
736 | * bit 3: value 0 = pretrigger sampling, 1 = posttrigger sampling | |
737 | * The meaning of other bit fields is unknown. | |
7601dca7 | 738 | * |
96dc954e | 739 | * Typical values in order of appearance during execution: |
b711fd8e GS |
740 | * 0x85e1: idle, no acquisition pending |
741 | * IDLE set, TRGD don't care, POST don't care; DRAM don't care | |
742 | * "In idle state." Takes precedence over all others. | |
96dc954e GS |
743 | * 0x85e2: pre-sampling, samples before the trigger position, |
744 | * when capture ratio > 0% | |
b711fd8e GS |
745 | * IDLE clear, TRGD clear, POST clear; DRAM don't care |
746 | * "Not idle any more, no post yet, not triggered yet." | |
96dc954e GS |
747 | * 0x85ea: pre-sampling complete, now waiting for the trigger |
748 | * (whilst sampling continuously) | |
b711fd8e GS |
749 | * IDLE clear, TRGD clear, POST set; DRAM don't care |
750 | * "Post set thus after pre, not triggered yet" | |
96dc954e | 751 | * 0x85ee: trigger seen, capturing post-trigger samples, running |
b711fd8e GS |
752 | * IDLE clear, TRGD set, POST set; DRAM don't care |
753 | * "Triggered and in post, not idle yet." | |
96dc954e | 754 | * 0x85ed: idle |
b711fd8e GS |
755 | * IDLE set, TRGD don't care, POST don't care; DRAM don't care |
756 | * "In idle state." TRGD/POST don't care, same meaning as above. | |
f2cd2deb | 757 | */ |
b711fd8e GS |
758 | static const uint16_t runstate_mask_idle = RUNSTATE_IDLE_BIT; |
759 | static const uint16_t runstate_patt_idle = RUNSTATE_IDLE_BIT; | |
760 | static const uint16_t runstate_mask_step = | |
761 | RUNSTATE_IDLE_BIT | RUNSTATE_TRGD_BIT | RUNSTATE_POST_BIT; | |
762 | static const uint16_t runstate_patt_pre_trig = 0; | |
763 | static const uint16_t runstate_patt_wait_trig = RUNSTATE_POST_BIT; | |
764 | static const uint16_t runstate_patt_post_trig = | |
765 | RUNSTATE_TRGD_BIT | RUNSTATE_POST_BIT; | |
766 | ||
f2cd2deb FS |
767 | static uint16_t run_state(const struct sr_dev_inst *sdi) |
768 | { | |
21d68fd9 GS |
769 | static uint16_t previous_state; |
770 | ||
f2cd2deb | 771 | int ret; |
21d68fd9 GS |
772 | uint16_t state; |
773 | uint8_t buff[sizeof(state)]; | |
774 | const uint8_t *rdptr; | |
775 | const char *label; | |
f2cd2deb | 776 | |
411ad77c GS |
777 | ret = ctrl_in(sdi, CMD_FPGA_SPI, REG_RUN, 0, buff, sizeof(state)); |
778 | if (ret != SR_OK) { | |
91f73872 | 779 | sr_err("Cannot read run state."); |
f2cd2deb FS |
780 | return ret; |
781 | } | |
21d68fd9 GS |
782 | rdptr = buff; |
783 | state = read_u16le_inc(&rdptr); | |
7601dca7 | 784 | |
96dc954e GS |
785 | /* |
786 | * Avoid flooding the log, only dump values as they change. | |
787 | * The routine is called about every 50ms. | |
7601dca7 | 788 | */ |
b711fd8e GS |
789 | if (state == previous_state) |
790 | return state; | |
791 | ||
792 | previous_state = state; | |
793 | label = NULL; | |
794 | if ((state & runstate_mask_idle) == runstate_patt_idle) | |
795 | label = "idle"; | |
796 | if ((state & runstate_mask_step) == runstate_patt_pre_trig) | |
797 | label = "pre-trigger sampling"; | |
798 | if ((state & runstate_mask_step) == runstate_patt_wait_trig) | |
799 | label = "sampling, waiting for trigger"; | |
800 | if ((state & runstate_mask_step) == runstate_patt_post_trig) | |
801 | label = "post-trigger sampling"; | |
802 | if (label && *label) | |
803 | sr_dbg("Run state: 0x%04x (%s).", state, label); | |
804 | else | |
805 | sr_dbg("Run state: 0x%04x.", state); | |
f2cd2deb FS |
806 | |
807 | return state; | |
808 | } | |
809 | ||
cf057ac4 | 810 | static int la2016_is_idle(const struct sr_dev_inst *sdi) |
c34f4a89 GS |
811 | { |
812 | uint16_t state; | |
813 | ||
814 | state = run_state(sdi); | |
b711fd8e | 815 | if ((state & runstate_mask_idle) == runstate_patt_idle) |
c34f4a89 GS |
816 | return 1; |
817 | ||
818 | return 0; | |
819 | } | |
820 | ||
821 | static int set_run_mode(const struct sr_dev_inst *sdi, uint8_t mode) | |
f2cd2deb FS |
822 | { |
823 | int ret; | |
824 | ||
411ad77c GS |
825 | ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_RUN, 0, &mode, sizeof(mode)); |
826 | if (ret != SR_OK) { | |
c34f4a89 | 827 | sr_err("Cannot configure run mode %d.", mode); |
f2cd2deb FS |
828 | return ret; |
829 | } | |
830 | ||
831 | return SR_OK; | |
832 | } | |
833 | ||
834 | static int get_capture_info(const struct sr_dev_inst *sdi) | |
835 | { | |
836 | struct dev_context *devc; | |
837 | int ret; | |
c3d40037 HK |
838 | uint8_t buf[3 * sizeof(uint32_t)]; |
839 | const uint8_t *rdptr; | |
f2cd2deb FS |
840 | |
841 | devc = sdi->priv; | |
842 | ||
411ad77c GS |
843 | ret = ctrl_in(sdi, CMD_FPGA_SPI, REG_SAMPLING, 0, buf, sizeof(buf)); |
844 | if (ret != SR_OK) { | |
91f73872 | 845 | sr_err("Cannot read capture info."); |
f2cd2deb FS |
846 | return ret; |
847 | } | |
c3d40037 HK |
848 | |
849 | rdptr = buf; | |
850 | devc->info.n_rep_packets = read_u32le_inc(&rdptr); | |
851 | devc->info.n_rep_packets_before_trigger = read_u32le_inc(&rdptr); | |
852 | devc->info.write_pos = read_u32le_inc(&rdptr); | |
f2cd2deb | 853 | |
cf057ac4 | 854 | sr_dbg("Capture info: n_rep_packets: 0x%08x/%d, before_trigger: 0x%08x/%d, write_pos: 0x%08x/%d.", |
1ed93110 GS |
855 | devc->info.n_rep_packets, devc->info.n_rep_packets, |
856 | devc->info.n_rep_packets_before_trigger, | |
857 | devc->info.n_rep_packets_before_trigger, | |
858 | devc->info.write_pos, devc->info.write_pos); | |
f2cd2deb | 859 | |
852c7d14 GS |
860 | if (devc->info.n_rep_packets % NUM_PACKETS_IN_CHUNK) { |
861 | sr_warn("Unexpected packets count %lu, not a multiple of %d.", | |
862 | (unsigned long)devc->info.n_rep_packets, | |
863 | NUM_PACKETS_IN_CHUNK); | |
91f73872 | 864 | } |
f2cd2deb FS |
865 | |
866 | return SR_OK; | |
867 | } | |
868 | ||
d466f61c GS |
869 | SR_PRIV int la2016_upload_firmware(const struct sr_dev_inst *sdi, |
870 | struct sr_context *sr_ctx, libusb_device *dev, uint16_t product_id) | |
f2cd2deb | 871 | { |
d466f61c GS |
872 | struct dev_context *devc; |
873 | char *fw_file; | |
874 | int ret; | |
875 | ||
876 | devc = sdi ? sdi->priv : NULL; | |
877 | ||
878 | fw_file = g_strdup_printf(MCU_FWFILE_FMT, product_id); | |
879 | sr_info("USB PID %04hx, MCU firmware '%s'.", product_id, fw_file); | |
880 | ||
881 | ret = ezusb_upload_firmware(sr_ctx, dev, USB_CONFIGURATION, fw_file); | |
882 | if (ret != SR_OK) { | |
883 | g_free(fw_file); | |
884 | return ret; | |
885 | } | |
886 | ||
887 | if (devc) { | |
888 | devc->mcu_firmware = fw_file; | |
889 | fw_file = NULL; | |
890 | } | |
891 | g_free(fw_file); | |
892 | ||
893 | return SR_OK; | |
f2cd2deb FS |
894 | } |
895 | ||
896 | SR_PRIV int la2016_setup_acquisition(const struct sr_dev_inst *sdi) | |
897 | { | |
898 | struct dev_context *devc; | |
899 | int ret; | |
900 | uint8_t cmd; | |
901 | ||
902 | devc = sdi->priv; | |
903 | ||
904 | ret = set_threshold_voltage(sdi, devc->threshold_voltage); | |
905 | if (ret != SR_OK) | |
906 | return ret; | |
907 | ||
908 | cmd = 0; | |
411ad77c GS |
909 | ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_CAPT_MODE, 0, &cmd, sizeof(cmd)); |
910 | if (ret != SR_OK) { | |
91f73872 | 911 | sr_err("Cannot send command to stop sampling."); |
f2cd2deb FS |
912 | return ret; |
913 | } | |
914 | ||
915 | ret = set_trigger_config(sdi); | |
916 | if (ret != SR_OK) | |
917 | return ret; | |
918 | ||
919 | ret = set_sample_config(sdi); | |
920 | if (ret != SR_OK) | |
921 | return ret; | |
922 | ||
923 | return SR_OK; | |
924 | } | |
925 | ||
926 | SR_PRIV int la2016_start_acquisition(const struct sr_dev_inst *sdi) | |
927 | { | |
3ebc1cb2 GS |
928 | int ret; |
929 | ||
852c7d14 | 930 | ret = set_run_mode(sdi, RUNMODE_RUN); |
3ebc1cb2 GS |
931 | if (ret != SR_OK) |
932 | return ret; | |
933 | ||
934 | return SR_OK; | |
f2cd2deb FS |
935 | } |
936 | ||
3ebc1cb2 | 937 | static int la2016_stop_acquisition(const struct sr_dev_inst *sdi) |
f2cd2deb | 938 | { |
3ebc1cb2 GS |
939 | int ret; |
940 | ||
852c7d14 | 941 | ret = set_run_mode(sdi, RUNMODE_HALT); |
3ebc1cb2 GS |
942 | if (ret != SR_OK) |
943 | return ret; | |
944 | ||
945 | return SR_OK; | |
f2cd2deb FS |
946 | } |
947 | ||
948 | SR_PRIV int la2016_abort_acquisition(const struct sr_dev_inst *sdi) | |
949 | { | |
3ebc1cb2 GS |
950 | int ret; |
951 | struct dev_context *devc; | |
952 | ||
953 | ret = la2016_stop_acquisition(sdi); | |
954 | if (ret != SR_OK) | |
955 | return ret; | |
956 | ||
957 | devc = sdi ? sdi->priv : NULL; | |
958 | if (devc && devc->transfer) | |
959 | libusb_cancel_transfer(devc->transfer); | |
960 | ||
961 | return SR_OK; | |
f2cd2deb FS |
962 | } |
963 | ||
cf057ac4 | 964 | static int la2016_start_download(const struct sr_dev_inst *sdi, |
1ed93110 | 965 | libusb_transfer_cb_fn cb) |
f2cd2deb FS |
966 | { |
967 | struct dev_context *devc; | |
968 | struct sr_usb_dev_inst *usb; | |
969 | int ret; | |
c3d40037 HK |
970 | uint8_t wrbuf[2 * sizeof(uint32_t)]; |
971 | uint8_t *wrptr; | |
f2cd2deb FS |
972 | uint32_t to_read; |
973 | uint8_t *buffer; | |
974 | ||
975 | devc = sdi->priv; | |
976 | usb = sdi->conn; | |
977 | ||
411ad77c GS |
978 | ret = get_capture_info(sdi); |
979 | if (ret != SR_OK) | |
f2cd2deb FS |
980 | return ret; |
981 | ||
c3d40037 HK |
982 | devc->n_transfer_packets_to_read = devc->info.n_rep_packets / NUM_PACKETS_IN_CHUNK; |
983 | devc->n_bytes_to_read = devc->n_transfer_packets_to_read * TRANSFER_PACKET_LENGTH; | |
f2cd2deb FS |
984 | devc->read_pos = devc->info.write_pos - devc->n_bytes_to_read; |
985 | devc->n_reps_until_trigger = devc->info.n_rep_packets_before_trigger; | |
986 | ||
91f73872 | 987 | sr_dbg("Want to read %u xfer-packets starting from pos %" PRIu32 ".", |
1ed93110 | 988 | devc->n_transfer_packets_to_read, devc->read_pos); |
f2cd2deb | 989 | |
411ad77c GS |
990 | ret = ctrl_out(sdi, CMD_BULK_RESET, 0x00, 0, NULL, 0); |
991 | if (ret != SR_OK) { | |
91f73872 | 992 | sr_err("Cannot reset USB bulk state."); |
f2cd2deb FS |
993 | return ret; |
994 | } | |
91f73872 GS |
995 | sr_dbg("Will read from 0x%08lx, 0x%08x bytes.", |
996 | (unsigned long)devc->read_pos, devc->n_bytes_to_read); | |
c3d40037 HK |
997 | wrptr = wrbuf; |
998 | write_u32le_inc(&wrptr, devc->read_pos); | |
999 | write_u32le_inc(&wrptr, devc->n_bytes_to_read); | |
411ad77c GS |
1000 | ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_BULK, 0, wrbuf, wrptr - wrbuf); |
1001 | if (ret != SR_OK) { | |
91f73872 | 1002 | sr_err("Cannot send USB bulk config."); |
f2cd2deb FS |
1003 | return ret; |
1004 | } | |
411ad77c GS |
1005 | ret = ctrl_out(sdi, CMD_BULK_START, 0x00, 0, NULL, 0); |
1006 | if (ret != SR_OK) { | |
91f73872 | 1007 | sr_err("Cannot unblock USB bulk transfers."); |
f2cd2deb FS |
1008 | return ret; |
1009 | } | |
1010 | ||
96dc954e GS |
1011 | /* |
1012 | * Pick a buffer size for all USB transfers. The buffer size | |
1013 | * must be a multiple of the endpoint packet size. And cannot | |
1014 | * exceed a maximum value. | |
1015 | */ | |
f2cd2deb | 1016 | to_read = devc->n_bytes_to_read; |
96dc954e GS |
1017 | if (to_read >= LA2016_USB_BUFSZ) /* Multiple transfers. */ |
1018 | to_read = LA2016_USB_BUFSZ; | |
1019 | else /* One transfer. */ | |
e847645b | 1020 | to_read = (to_read + (LA2016_EP6_PKTSZ-1)) & ~(LA2016_EP6_PKTSZ-1); |
f2cd2deb FS |
1021 | buffer = g_try_malloc(to_read); |
1022 | if (!buffer) { | |
91f73872 GS |
1023 | sr_dbg("USB bulk transfer size %d bytes.", (int)to_read); |
1024 | sr_err("Cannot allocate buffer for USB bulk transfer."); | |
f2cd2deb FS |
1025 | return SR_ERR_MALLOC; |
1026 | } | |
1027 | ||
1028 | devc->transfer = libusb_alloc_transfer(0); | |
852c7d14 GS |
1029 | libusb_fill_bulk_transfer(devc->transfer, |
1030 | usb->devhdl, USB_EP_CAPTURE_DATA | LIBUSB_ENDPOINT_IN, | |
411ad77c | 1031 | buffer, to_read, cb, (void *)sdi, DEFAULT_TIMEOUT_MS); |
f2cd2deb | 1032 | |
411ad77c GS |
1033 | ret = libusb_submit_transfer(devc->transfer); |
1034 | if (ret != 0) { | |
91f73872 | 1035 | sr_err("Cannot submit USB transfer: %s.", libusb_error_name(ret)); |
f2cd2deb FS |
1036 | libusb_free_transfer(devc->transfer); |
1037 | devc->transfer = NULL; | |
1038 | g_free(buffer); | |
1039 | return SR_ERR; | |
1040 | } | |
1041 | ||
1042 | return SR_OK; | |
1043 | } | |
1044 | ||
480efba2 GS |
1045 | /* |
1046 | * A chunk (received via USB) contains a number of transfers (USB length | |
1047 | * divided by 16) which contain a number of packets (5 per transfer) which | |
1048 | * contain a number of samples (8bit repeat count per 16bit sample data). | |
1049 | */ | |
dfac9592 | 1050 | static void send_chunk(struct sr_dev_inst *sdi, |
480efba2 | 1051 | const uint8_t *packets, size_t num_xfers) |
dfac9592 GS |
1052 | { |
1053 | struct dev_context *devc; | |
480efba2 | 1054 | size_t num_pkts; |
dfac9592 | 1055 | const uint8_t *rp; |
480efba2 GS |
1056 | uint16_t sample_value; |
1057 | size_t repetitions; | |
1058 | uint8_t sample_buff[sizeof(sample_value)]; | |
dfac9592 GS |
1059 | |
1060 | devc = sdi->priv; | |
1061 | ||
a38f0f5e GS |
1062 | /* Ignore incoming USB data after complete sample data download. */ |
1063 | if (devc->download_finished) | |
1064 | return; | |
dfac9592 | 1065 | |
cf057ac4 | 1066 | if (devc->trigger_involved && !devc->trigger_marked && devc->info.n_rep_packets_before_trigger == 0) { |
a38f0f5e | 1067 | feed_queue_logic_send_trigger(devc->feed_queue); |
cf057ac4 | 1068 | devc->trigger_marked = TRUE; |
dfac9592 GS |
1069 | } |
1070 | ||
1071 | rp = packets; | |
480efba2 GS |
1072 | while (num_xfers--) { |
1073 | num_pkts = NUM_PACKETS_IN_CHUNK; | |
1074 | while (num_pkts--) { | |
dfac9592 | 1075 | |
480efba2 | 1076 | sample_value = read_u16le_inc(&rp); |
dfac9592 | 1077 | repetitions = read_u8_inc(&rp); |
dfac9592 | 1078 | |
dfac9592 | 1079 | devc->total_samples += repetitions; |
480efba2 GS |
1080 | |
1081 | write_u16le(sample_buff, sample_value); | |
a38f0f5e GS |
1082 | feed_queue_logic_submit(devc->feed_queue, |
1083 | sample_buff, repetitions); | |
1084 | sr_sw_limits_update_samples_read(&devc->sw_limits, | |
1085 | repetitions); | |
480efba2 | 1086 | |
cf057ac4 GS |
1087 | if (devc->trigger_involved && !devc->trigger_marked) { |
1088 | if (!--devc->n_reps_until_trigger) { | |
a38f0f5e | 1089 | feed_queue_logic_send_trigger(devc->feed_queue); |
cf057ac4 | 1090 | devc->trigger_marked = TRUE; |
91f73872 | 1091 | sr_dbg("Trigger position after %" PRIu64 " samples, %.6fms.", |
1ed93110 GS |
1092 | devc->total_samples, |
1093 | (double)devc->total_samples / devc->cur_samplerate * 1e3); | |
dfac9592 GS |
1094 | } |
1095 | } | |
1096 | } | |
1097 | (void)read_u8_inc(&rp); /* Skip sequence number. */ | |
1098 | } | |
a38f0f5e GS |
1099 | |
1100 | if (!devc->download_finished && sr_sw_limits_check(&devc->sw_limits)) { | |
1101 | sr_dbg("Acquisition limit reached."); | |
1102 | devc->download_finished = TRUE; | |
1103 | } | |
1104 | if (devc->download_finished) { | |
1105 | sr_dbg("Download finished, flushing session feed queue."); | |
1106 | feed_queue_logic_flush(devc->feed_queue); | |
dfac9592 | 1107 | } |
a38f0f5e | 1108 | sr_dbg("Total samples after chunk: %" PRIu64 ".", devc->total_samples); |
dfac9592 GS |
1109 | } |
1110 | ||
1111 | static void LIBUSB_CALL receive_transfer(struct libusb_transfer *transfer) | |
1112 | { | |
1113 | struct sr_dev_inst *sdi; | |
1114 | struct dev_context *devc; | |
1115 | struct sr_usb_dev_inst *usb; | |
a38f0f5e | 1116 | size_t num_xfers; |
dfac9592 GS |
1117 | int ret; |
1118 | ||
1119 | sdi = transfer->user_data; | |
1120 | devc = sdi->priv; | |
1121 | usb = sdi->conn; | |
1122 | ||
1123 | sr_dbg("receive_transfer(): status %s received %d bytes.", | |
1ed93110 | 1124 | libusb_error_name(transfer->status), transfer->actual_length); |
a38f0f5e GS |
1125 | /* |
1126 | * Implementation detail: A USB transfer timeout is not fatal | |
1127 | * here. We just process whatever was received, empty input is | |
1128 | * perfectly acceptable. Reaching (or exceeding) the sw limits | |
1129 | * or exhausting the device's captured data will complete the | |
1130 | * sample data download. | |
1131 | */ | |
1132 | num_xfers = transfer->actual_length / TRANSFER_PACKET_LENGTH; | |
1133 | send_chunk(sdi, transfer->buffer, num_xfers); | |
dfac9592 GS |
1134 | |
1135 | devc->n_bytes_to_read -= transfer->actual_length; | |
1136 | if (devc->n_bytes_to_read) { | |
1137 | uint32_t to_read = devc->n_bytes_to_read; | |
96dc954e GS |
1138 | /* |
1139 | * Determine read size for the next USB transfer. Make | |
1140 | * the buffer size a multiple of the endpoint packet | |
1141 | * size. Don't exceed a maximum value. | |
1142 | */ | |
dfac9592 GS |
1143 | if (to_read >= LA2016_USB_BUFSZ) |
1144 | to_read = LA2016_USB_BUFSZ; | |
96dc954e | 1145 | else |
dfac9592 | 1146 | to_read = (to_read + (LA2016_EP6_PKTSZ-1)) & ~(LA2016_EP6_PKTSZ-1); |
852c7d14 GS |
1147 | libusb_fill_bulk_transfer(transfer, |
1148 | usb->devhdl, USB_EP_CAPTURE_DATA | LIBUSB_ENDPOINT_IN, | |
1149 | transfer->buffer, to_read, | |
dfac9592 GS |
1150 | receive_transfer, (void *)sdi, DEFAULT_TIMEOUT_MS); |
1151 | ||
411ad77c GS |
1152 | ret = libusb_submit_transfer(transfer); |
1153 | if (ret == 0) | |
dfac9592 | 1154 | return; |
91f73872 GS |
1155 | sr_err("Cannot submit another USB transfer: %s.", |
1156 | libusb_error_name(ret)); | |
dfac9592 GS |
1157 | } |
1158 | ||
1159 | g_free(transfer->buffer); | |
1160 | libusb_free_transfer(transfer); | |
cf057ac4 | 1161 | devc->download_finished = TRUE; |
dfac9592 GS |
1162 | } |
1163 | ||
1164 | SR_PRIV int la2016_receive_data(int fd, int revents, void *cb_data) | |
1165 | { | |
1166 | const struct sr_dev_inst *sdi; | |
1167 | struct dev_context *devc; | |
1168 | struct drv_context *drvc; | |
1169 | struct timeval tv; | |
a38f0f5e | 1170 | int ret; |
dfac9592 GS |
1171 | |
1172 | (void)fd; | |
1173 | (void)revents; | |
1174 | ||
1175 | sdi = cb_data; | |
1176 | devc = sdi->priv; | |
1177 | drvc = sdi->driver->context; | |
1178 | ||
a38f0f5e GS |
1179 | /* |
1180 | * Wait for the acquisition to complete in hardware. | |
1181 | * Periodically check a potentially configured msecs timeout. | |
1182 | */ | |
cf057ac4 GS |
1183 | if (!devc->completion_seen) { |
1184 | if (!la2016_is_idle(sdi)) { | |
a38f0f5e GS |
1185 | if (sr_sw_limits_check(&devc->sw_limits)) { |
1186 | devc->sw_limits.limit_msec = 0; | |
1187 | sr_dbg("Limit reached. Stopping acquisition."); | |
1188 | la2016_stop_acquisition(sdi); | |
1189 | } | |
96dc954e | 1190 | /* Not yet ready for sample data download. */ |
dfac9592 GS |
1191 | return TRUE; |
1192 | } | |
a38f0f5e GS |
1193 | sr_dbg("Acquisition completion seen (hardware)."); |
1194 | devc->sw_limits.limit_msec = 0; | |
cf057ac4 GS |
1195 | devc->completion_seen = TRUE; |
1196 | devc->download_finished = FALSE; | |
1197 | devc->trigger_marked = FALSE; | |
dfac9592 | 1198 | devc->total_samples = 0; |
a38f0f5e GS |
1199 | |
1200 | /* Initiate the download of acquired sample data. */ | |
1201 | std_session_send_df_frame_begin(sdi); | |
1202 | ret = la2016_start_download(sdi, receive_transfer); | |
1203 | if (ret != SR_OK) { | |
91f73872 | 1204 | sr_err("Cannot start acquisition data download."); |
dfac9592 GS |
1205 | return FALSE; |
1206 | } | |
91f73872 | 1207 | sr_dbg("Acquisition data download started."); |
dfac9592 GS |
1208 | |
1209 | return TRUE; | |
1210 | } | |
1211 | ||
a38f0f5e | 1212 | /* Handle USB reception. Drives sample data download. */ |
dfac9592 GS |
1213 | tv.tv_sec = tv.tv_usec = 0; |
1214 | libusb_handle_events_timeout(drvc->sr_ctx->libusb_ctx, &tv); | |
1215 | ||
a38f0f5e | 1216 | /* Postprocess completion of sample data download. */ |
cf057ac4 | 1217 | if (devc->download_finished) { |
91f73872 | 1218 | sr_dbg("Download finished, post processing."); |
dfac9592 GS |
1219 | |
1220 | la2016_stop_acquisition(sdi); | |
a38f0f5e | 1221 | usb_source_remove(sdi->session, drvc->sr_ctx); |
dfac9592 GS |
1222 | devc->transfer = NULL; |
1223 | ||
a38f0f5e GS |
1224 | feed_queue_logic_flush(devc->feed_queue); |
1225 | feed_queue_logic_free(devc->feed_queue); | |
1226 | devc->feed_queue = NULL; | |
1227 | std_session_send_df_frame_end(sdi); | |
1228 | std_session_send_df_end(sdi); | |
1229 | ||
91f73872 | 1230 | sr_dbg("Download finished, done post processing."); |
dfac9592 GS |
1231 | } |
1232 | ||
1233 | return TRUE; | |
1234 | } | |
1235 | ||
d466f61c GS |
1236 | SR_PRIV int la2016_identify_device(const struct sr_dev_inst *sdi, |
1237 | gboolean show_message) | |
f2cd2deb | 1238 | { |
8b172e78 | 1239 | struct dev_context *devc; |
9de389b1 | 1240 | uint8_t buf[8]; |
64172b16 | 1241 | size_t rdoff, rdlen; |
43d2e52f GS |
1242 | const uint8_t *rdptr; |
1243 | uint8_t date_yy, date_mm; | |
1244 | uint8_t dinv_yy, dinv_mm; | |
9de389b1 | 1245 | uint8_t magic; |
d466f61c GS |
1246 | size_t model_idx; |
1247 | const struct kingst_model *model; | |
9de389b1 | 1248 | int ret; |
f2cd2deb | 1249 | |
8b172e78 KG |
1250 | devc = sdi->priv; |
1251 | ||
96dc954e | 1252 | /* |
43d2e52f GS |
1253 | * Four EEPROM bytes at offset 0x20 are the manufacturing date, |
1254 | * year and month in BCD format, followed by inverted values for | |
1255 | * consistency checks. For example bytes 20 04 df fb translate | |
1256 | * to 2020-04. This information can help identify the vintage of | |
1257 | * devices when unknown magic numbers are seen. | |
9de389b1 | 1258 | */ |
64172b16 GS |
1259 | rdoff = 0x20; |
1260 | rdlen = 4 * sizeof(uint8_t); | |
1261 | ret = ctrl_in(sdi, CMD_EEPROM, rdoff, 0, buf, rdlen); | |
d466f61c | 1262 | if (ret != SR_OK && !show_message) { |
64172b16 | 1263 | /* Non-fatal weak attempt during probe. Not worth logging. */ |
d466f61c GS |
1264 | sr_dbg("Cannot access EEPROM."); |
1265 | return SR_ERR_IO; | |
1266 | } else if (ret != SR_OK) { | |
64172b16 | 1267 | /* Failed attempt in regular use. Non-fatal. Worth logging. */ |
43d2e52f | 1268 | sr_err("Cannot read manufacture date in EEPROM."); |
1ed93110 | 1269 | } else { |
64172b16 GS |
1270 | if (sr_log_loglevel_get() >= SR_LOG_SPEW) { |
1271 | GString *txt; | |
1272 | txt = sr_hexdump_new(buf, rdlen); | |
1273 | sr_spew("Manufacture date bytes %s.", txt->str); | |
1274 | sr_hexdump_free(txt); | |
1275 | } | |
43d2e52f GS |
1276 | rdptr = &buf[0]; |
1277 | date_yy = read_u8_inc(&rdptr); | |
1278 | date_mm = read_u8_inc(&rdptr); | |
1279 | dinv_yy = read_u8_inc(&rdptr); | |
1280 | dinv_mm = read_u8_inc(&rdptr); | |
1281 | sr_info("Manufacture date: 20%02hx-%02hx.", date_yy, date_mm); | |
1282 | if ((date_mm ^ dinv_mm) != 0xff || (date_yy ^ dinv_yy) != 0xff) | |
1283 | sr_warn("Manufacture date fails checksum test."); | |
f2cd2deb | 1284 | } |
f2cd2deb | 1285 | |
9de389b1 | 1286 | /* |
96dc954e GS |
1287 | * Several Kingst logic analyzer devices share the same USB VID |
1288 | * and PID. The product ID determines which MCU firmware to load. | |
1289 | * The MCU firmware provides access to EEPROM content which then | |
1290 | * allows to identify the device model. Which in turn determines | |
1291 | * which FPGA bitstream to load. Eight bytes at offset 0x08 are | |
1292 | * to get inspected. | |
9de389b1 | 1293 | * |
96dc954e GS |
1294 | * EEPROM content for model identification is kept redundantly |
1295 | * in memory. The values are stored in verbatim and in inverted | |
1296 | * form, multiple copies are kept at different offsets. Example | |
1297 | * data: | |
9de389b1 | 1298 | * |
96dc954e GS |
1299 | * magic 0x08 |
1300 | * | ~magic 0xf7 | |
1301 | * | | | |
1302 | * 08f7000008f710ef | |
1303 | * | | | |
1304 | * | ~magic backup | |
1305 | * magic backup | |
9de389b1 | 1306 | * |
96dc954e GS |
1307 | * Exclusively inspecting the magic byte appears to be sufficient, |
1308 | * other fields seem to be 'don't care'. | |
9de389b1 | 1309 | * |
96dc954e GS |
1310 | * magic 2 == LA2016 using "kingst-la2016-fpga.bitstream" |
1311 | * magic 3 == LA1016 using "kingst-la1016-fpga.bitstream" | |
1312 | * magic 8 == LA2016a using "kingst-la2016a1-fpga.bitstream" | |
1313 | * (latest v1.3.0 PCB, perhaps others) | |
1314 | * magic 9 == LA1016a using "kingst-la1016a1-fpga.bitstream" | |
1315 | * (latest v1.3.0 PCB, perhaps others) | |
9de389b1 | 1316 | * |
96dc954e GS |
1317 | * When EEPROM content does not match the hardware configuration |
1318 | * (the board layout), the software may load but yield incorrect | |
1319 | * results (like swapped channels). The FPGA bitstream itself | |
1320 | * will authenticate with IC U10 and fail when its capabilities | |
1321 | * do not match the hardware model. An LA1016 won't become a | |
1322 | * LA2016 by faking its EEPROM content. | |
9de389b1 | 1323 | */ |
d466f61c | 1324 | devc->identify_magic = 0; |
64172b16 GS |
1325 | rdoff = 0x08; |
1326 | rdlen = 8 * sizeof(uint8_t); | |
1327 | ret = ctrl_in(sdi, CMD_EEPROM, rdoff, 0, &buf, rdlen); | |
1328 | if (ret != SR_OK) { | |
91f73872 | 1329 | sr_err("Cannot read EEPROM device identifier bytes."); |
f2cd2deb FS |
1330 | return ret; |
1331 | } | |
64172b16 GS |
1332 | if (sr_log_loglevel_get() >= SR_LOG_SPEW) { |
1333 | GString *txt; | |
1334 | txt = sr_hexdump_new(buf, rdlen); | |
1335 | sr_spew("EEPROM magic bytes %s.", txt->str); | |
1336 | sr_hexdump_free(txt); | |
1337 | } | |
43d2e52f | 1338 | if ((buf[0] ^ buf[1]) == 0xff) { |
96dc954e | 1339 | /* Primary copy of magic passes complement check. */ |
9de389b1 | 1340 | magic = buf[0]; |
64172b16 | 1341 | sr_dbg("Using primary magic, value %d.", (int)magic); |
43d2e52f | 1342 | } else if ((buf[4] ^ buf[5]) == 0xff) { |
96dc954e | 1343 | /* Backup copy of magic passes complement check. */ |
9de389b1 | 1344 | magic = buf[4]; |
64172b16 | 1345 | sr_dbg("Using backup magic, value %d.", (int)magic); |
43d2e52f GS |
1346 | } else { |
1347 | sr_err("Cannot find consistent device type identification."); | |
1348 | magic = 0; | |
f2cd2deb | 1349 | } |
d466f61c | 1350 | devc->identify_magic = magic; |
9de389b1 | 1351 | |
d466f61c GS |
1352 | devc->model = NULL; |
1353 | for (model_idx = 0; model_idx < ARRAY_SIZE(models); model_idx++) { | |
1354 | model = &models[model_idx]; | |
1355 | if (model->magic != magic) | |
1356 | continue; | |
1357 | devc->model = model; | |
64172b16 GS |
1358 | sr_info("Model '%s', %zu channels, max %" PRIu64 "MHz.", |
1359 | model->name, model->channel_count, | |
1360 | model->samplerate / SR_MHZ(1)); | |
d466f61c GS |
1361 | devc->fpga_bitstream = g_strdup_printf(FPGA_FWFILE_FMT, |
1362 | model->fpga_stem); | |
d466f61c | 1363 | sr_info("FPGA bitstream file '%s'.", devc->fpga_bitstream); |
d6f89d4b GS |
1364 | break; |
1365 | } | |
d466f61c | 1366 | if (!devc->model) { |
91f73872 | 1367 | sr_err("Cannot identify as one of the supported models."); |
3f48ab02 FS |
1368 | return SR_ERR; |
1369 | } | |
f2cd2deb | 1370 | |
d466f61c GS |
1371 | return SR_OK; |
1372 | } | |
1373 | ||
6d53e949 | 1374 | SR_PRIV int la2016_init_hardware(const struct sr_dev_inst *sdi) |
d466f61c GS |
1375 | { |
1376 | struct dev_context *devc; | |
1377 | const char *bitstream_fn; | |
1378 | int ret; | |
1379 | uint16_t state; | |
1380 | ||
1381 | devc = sdi->priv; | |
1382 | bitstream_fn = devc ? devc->fpga_bitstream : ""; | |
1383 | ||
1384 | ret = check_fpga_bitstream(sdi); | |
1385 | if (ret != SR_OK) { | |
d6f89d4b GS |
1386 | ret = upload_fpga_bitstream(sdi, bitstream_fn); |
1387 | if (ret != SR_OK) { | |
1388 | sr_err("Cannot upload FPGA bitstream."); | |
1389 | return ret; | |
1390 | } | |
1391 | } | |
1392 | ret = enable_fpga_bitstream(sdi); | |
9de389b1 | 1393 | if (ret != SR_OK) { |
d6f89d4b | 1394 | sr_err("Cannot enable FPGA bitstream after upload."); |
9de389b1 KG |
1395 | return ret; |
1396 | } | |
1397 | ||
f2cd2deb | 1398 | state = run_state(sdi); |
9de389b1 | 1399 | if (state != 0x85e9) { |
91f73872 | 1400 | sr_warn("Unexpected run state, want 0x85e9, got 0x%04x.", state); |
9de389b1 | 1401 | } |
f2cd2deb | 1402 | |
6d53e949 GS |
1403 | ret = ctrl_out(sdi, CMD_BULK_RESET, 0x00, 0, NULL, 0); |
1404 | if (ret != SR_OK) { | |
91f73872 | 1405 | sr_err("Cannot reset USB bulk transfer."); |
f2cd2deb FS |
1406 | return ret; |
1407 | } | |
9de389b1 | 1408 | |
91f73872 | 1409 | sr_dbg("Device should be initialized."); |
f2cd2deb | 1410 | |
6d53e949 GS |
1411 | return SR_OK; |
1412 | } | |
1413 | ||
1414 | SR_PRIV int la2016_init_params(const struct sr_dev_inst *sdi) | |
1415 | { | |
1416 | int ret; | |
1417 | ||
c34f4a89 GS |
1418 | ret = set_defaults(sdi); |
1419 | if (ret != SR_OK) | |
1420 | return ret; | |
1421 | ||
1422 | return SR_OK; | |
f2cd2deb FS |
1423 | } |
1424 | ||
6d53e949 | 1425 | SR_PRIV int la2016_deinit_hardware(const struct sr_dev_inst *sdi) |
f2cd2deb FS |
1426 | { |
1427 | int ret; | |
1428 | ||
6d53e949 GS |
1429 | ret = ctrl_out(sdi, CMD_FPGA_ENABLE, 0x00, 0, NULL, 0); |
1430 | if (ret != SR_OK) { | |
91f73872 | 1431 | sr_err("Cannot deinitialize device's FPGA."); |
f2cd2deb FS |
1432 | return ret; |
1433 | } | |
1434 | ||
1435 | return SR_OK; | |
1436 | } |