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6a25fa42 AZ |
1 | /* |
2 | * This file is part of the libsigrok project. | |
3 | * | |
5089a143 AZ |
4 | * Copyright (C) 2016 Andreas Zschunke <andreas.zschunke@gmx.net> |
5 | * Copyright (C) 2017 Andrej Valek <andy@skyrain.eu> | |
6 | * Copyright (C) 2017 Uwe Hermann <uwe@hermann-uwe.de> | |
6a25fa42 AZ |
7 | * |
8 | * This program is free software: you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation, either version 3 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
20 | */ | |
21 | ||
22 | #include <config.h> | |
23 | #include "protocol.h" | |
24 | ||
5089a143 AZ |
25 | #define USB_INTERFACE 0 |
26 | #define NUM_CHANNELS 32 | |
6a25fa42 | 27 | |
5089a143 AZ |
28 | static const uint32_t scanopts[] = { |
29 | SR_CONF_CONN, | |
30 | }; | |
31 | ||
32 | static const uint32_t drvopts[] = { | |
33 | SR_CONF_LOGIC_ANALYZER, | |
34 | }; | |
35 | ||
36 | static const uint32_t devopts[] = { | |
37 | SR_CONF_SAMPLERATE | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST, | |
3dc976fe | 38 | SR_CONF_CAPTURE_RATIO | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST, |
4b75f84c | 39 | SR_CONF_LIMIT_SAMPLES | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST, |
5089a143 AZ |
40 | SR_CONF_TRIGGER_MATCH | SR_CONF_LIST, |
41 | SR_CONF_CONN | SR_CONF_GET, | |
f49065c6 AV |
42 | SR_CONF_EXTERNAL_CLOCK | SR_CONF_GET | SR_CONF_SET, |
43 | SR_CONF_EXTERNAL_CLOCK_SOURCE | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST, | |
44 | SR_CONF_CLOCK_EDGE | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST, | |
45 | }; | |
46 | ||
47 | static const uint32_t devopts_fpga_zero[] = { | |
48 | SR_CONF_SAMPLERATE | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST, | |
49 | SR_CONF_CAPTURE_RATIO | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST, | |
50 | SR_CONF_LIMIT_SAMPLES | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST, | |
51 | SR_CONF_TRIGGER_MATCH | SR_CONF_LIST, | |
52 | SR_CONF_CONN | SR_CONF_GET, | |
2a801861 AV |
53 | }; |
54 | ||
55 | static const uint32_t devopts_cg[] = { | |
caad0024 | 56 | SR_CONF_VOLTAGE_THRESHOLD | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST, |
5089a143 AZ |
57 | }; |
58 | ||
cbc656e4 UH |
59 | static const char *cg_names[] = { |
60 | "A", "B", | |
61 | }; | |
62 | ||
f49065c6 AV |
63 | static const char *signal_edges[] = { |
64 | [H4032L_CLOCK_EDGE_TYPE_RISE] = "rising", | |
65 | [H4032L_CLOCK_EDGE_TYPE_FALL] = "falling", | |
66 | [H4032L_CLOCK_EDGE_TYPE_BOTH] = "both", | |
67 | }; | |
68 | ||
69 | static const char *ext_clock_sources[] = { | |
70 | [H4032L_EXT_CLOCK_SOURCE_CHANNEL_A] = "ACLK", | |
71 | [H4032L_EXT_CLOCK_SOURCE_CHANNEL_B] = "BCLK" | |
72 | }; | |
73 | ||
74 | static const uint8_t ext_clock_edges[2][3] = { | |
75 | { | |
76 | H4032L_CLOCK_EDGE_TYPE_RISE_A, | |
77 | H4032L_CLOCK_EDGE_TYPE_FALL_A, | |
78 | H4032L_CLOCK_EDGE_TYPE_BOTH_A | |
79 | }, | |
80 | { | |
81 | H4032L_CLOCK_EDGE_TYPE_RISE_B, | |
82 | H4032L_CLOCK_EDGE_TYPE_FALL_B, | |
83 | H4032L_CLOCK_EDGE_TYPE_BOTH_B | |
84 | } | |
85 | }; | |
86 | ||
5089a143 AZ |
87 | static const int32_t trigger_matches[] = { |
88 | SR_TRIGGER_ZERO, | |
89 | SR_TRIGGER_ONE, | |
90 | SR_TRIGGER_RISING, | |
91 | SR_TRIGGER_FALLING, | |
92 | SR_TRIGGER_EDGE, | |
93 | }; | |
94 | ||
95 | static const uint64_t samplerates[] = { | |
96 | SR_KHZ(1), | |
97 | SR_KHZ(2), | |
98 | SR_KHZ(4), | |
99 | SR_KHZ(8), | |
100 | SR_KHZ(16), | |
101 | SR_HZ(31250), | |
102 | SR_HZ(62500), | |
103 | SR_KHZ(125), | |
104 | SR_KHZ(250), | |
105 | SR_KHZ(500), | |
106 | SR_KHZ(625), | |
107 | SR_HZ(781250), | |
108 | SR_MHZ(1), | |
109 | SR_KHZ(1250), | |
110 | SR_HZ(1562500), | |
111 | SR_MHZ(2), | |
112 | SR_KHZ(2500), | |
113 | SR_KHZ(3125), | |
114 | SR_MHZ(4), | |
115 | SR_MHZ(5), | |
116 | SR_KHZ(6250), | |
117 | SR_MHZ(10), | |
118 | SR_KHZ(12500), | |
119 | SR_MHZ(20), | |
120 | SR_MHZ(25), | |
121 | SR_MHZ(40), | |
122 | SR_MHZ(50), | |
123 | SR_MHZ(80), | |
124 | SR_MHZ(100), | |
125 | SR_MHZ(160), | |
126 | SR_MHZ(200), | |
127 | SR_MHZ(320), | |
128 | SR_MHZ(400), | |
129 | }; | |
130 | ||
131 | static const uint64_t samplerates_hw[] = { | |
132 | SR_MHZ(100), | |
133 | SR_MHZ(50), | |
134 | SR_MHZ(25), | |
135 | SR_KHZ(12500), | |
136 | SR_KHZ(6250), | |
137 | SR_KHZ(3125), | |
138 | SR_HZ(1562500), | |
139 | SR_HZ(781250), | |
140 | SR_MHZ(80), | |
141 | SR_MHZ(40), | |
142 | SR_MHZ(20), | |
143 | SR_MHZ(10), | |
144 | SR_MHZ(5), | |
145 | SR_KHZ(2500), | |
146 | SR_KHZ(1250), | |
147 | SR_KHZ(625), | |
148 | SR_MHZ(4), | |
149 | SR_MHZ(2), | |
150 | SR_MHZ(1), | |
151 | SR_KHZ(500), | |
152 | SR_KHZ(250), | |
153 | SR_KHZ(125), | |
154 | SR_HZ(62500), | |
155 | SR_HZ(31250), | |
156 | SR_KHZ(16), | |
157 | SR_KHZ(8), | |
158 | SR_KHZ(4), | |
159 | SR_KHZ(2), | |
160 | SR_KHZ(1), | |
161 | 0, | |
162 | 0, | |
163 | 0, | |
164 | SR_MHZ(200), | |
165 | SR_MHZ(160), | |
166 | SR_MHZ(400), | |
167 | SR_MHZ(320), | |
168 | }; | |
169 | ||
3f34a402 | 170 | static struct sr_dev_driver hantek_4032l_driver_info; |
6a25fa42 AZ |
171 | |
172 | static GSList *scan(struct sr_dev_driver *di, GSList *options) | |
173 | { | |
5089a143 AZ |
174 | struct drv_context *drvc = di->context; |
175 | GSList *l, *devices, *conn_devices; | |
176 | libusb_device **devlist; | |
177 | struct libusb_device_descriptor des; | |
178 | const char *conn; | |
179 | int i; | |
180 | char connection_id[64]; | |
181 | struct sr_channel_group *cg; | |
182 | struct sr_dev_inst *sdi; | |
183 | struct sr_channel *ch; | |
6a25fa42 AZ |
184 | |
185 | devices = NULL; | |
5089a143 | 186 | conn_devices = NULL; |
6a25fa42 | 187 | drvc->instances = NULL; |
5089a143 AZ |
188 | conn = NULL; |
189 | ||
190 | for (l = options; l; l = l->next) { | |
191 | struct sr_config *src = l->data; | |
192 | if (src->key == SR_CONF_CONN) { | |
193 | conn = g_variant_get_string(src->data, NULL); | |
194 | break; | |
195 | } | |
196 | } | |
6a25fa42 | 197 | |
5089a143 AZ |
198 | if (conn) |
199 | conn_devices = sr_usb_find(drvc->sr_ctx->libusb_ctx, conn); | |
200 | else | |
201 | conn_devices = NULL; | |
202 | ||
203 | libusb_get_device_list(drvc->sr_ctx->libusb_ctx, &devlist); | |
204 | for (i = 0; devlist[i]; i++) { | |
205 | if (conn) { | |
206 | struct sr_usb_dev_inst *usb = NULL; | |
207 | for (l = conn_devices; l; l = l->next) { | |
208 | usb = l->data; | |
28f2d07f AV |
209 | if (usb->bus == libusb_get_bus_number(devlist[i]) && |
210 | usb->address == libusb_get_device_address(devlist[i])) | |
5089a143 AZ |
211 | break; |
212 | } | |
213 | if (!l) | |
214 | /* This device matched none of the ones that | |
215 | * matched the conn specification. */ | |
216 | continue; | |
217 | } | |
218 | ||
219 | libusb_get_device_descriptor(devlist[i], &des); | |
220 | ||
221 | if (des.idVendor != H4032L_USB_VENDOR || | |
222 | des.idProduct != H4032L_USB_PRODUCT) | |
223 | continue; | |
224 | ||
6c1a76d1 RT |
225 | if (usb_get_port_path(devlist[i], connection_id, sizeof(connection_id)) < 0) |
226 | continue; | |
5089a143 AZ |
227 | |
228 | sdi = g_malloc0(sizeof(struct sr_dev_inst)); | |
229 | sdi->driver = &hantek_4032l_driver_info; | |
230 | sdi->vendor = g_strdup("Hantek"); | |
231 | sdi->model = g_strdup("4032L"); | |
232 | sdi->connection_id = g_strdup(connection_id); | |
233 | ||
234 | struct sr_channel_group *channel_groups[2]; | |
235 | for (int j = 0; j < 2; j++) { | |
236 | cg = g_malloc0(sizeof(struct sr_channel_group)); | |
237 | cg->name = g_strdup_printf("%c", 'A' + j); | |
238 | channel_groups[j] = cg; | |
239 | sdi->channel_groups = g_slist_append(sdi->channel_groups, cg); | |
240 | } | |
241 | ||
242 | /* Assemble channel list and add channel to channel groups. */ | |
243 | for (int j = 0; j < NUM_CHANNELS; j++) { | |
244 | char channel_name[4]; | |
245 | sprintf(channel_name, "%c%d", 'A' + (j & 1), j / 2); | |
246 | ch = sr_channel_new(sdi, j, SR_CHANNEL_LOGIC, TRUE, channel_name); | |
247 | cg = channel_groups[j & 1]; | |
248 | cg->channels = g_slist_append(cg->channels, ch); | |
249 | } | |
250 | ||
251 | struct dev_context *devc = g_malloc0(sizeof(struct dev_context)); | |
252 | ||
253 | /* Initialize command packet. */ | |
254 | devc->cmd_pkt.magic = H4032L_CMD_PKT_MAGIC; | |
bf2a6eea | 255 | devc->cmd_pkt.sample_size = 16 * 1024; |
f49065c6 | 256 | devc->sample_rate = 0; |
5089a143 AZ |
257 | |
258 | devc->status = H4032L_STATUS_IDLE; | |
259 | ||
260 | devc->capture_ratio = 5; | |
f49065c6 AV |
261 | devc->external_clock = FALSE; |
262 | devc->clock_edge = H4032L_CLOCK_EDGE_TYPE_RISE; | |
263 | ||
ee1a7d2f AV |
264 | /* Create array of thresholds from min to max. */ |
265 | GVariant *thresholds = std_gvar_min_max_step_thresholds( | |
266 | H4032L_THR_VOLTAGE_MIN, H4032L_THR_VOLTAGE_MAX, | |
267 | H4032L_THR_VOLTAGE_STEP); | |
268 | /* Take default threshold value from array (FP workaround). */ | |
269 | g_variant_get_child(thresholds, H4032L_THR_VOLTAGE_DEFAULT, | |
270 | "(dd)", &devc->cur_threshold[0], &devc->cur_threshold[1]); | |
5089a143 | 271 | |
5089a143 AZ |
272 | sdi->priv = devc; |
273 | devices = g_slist_append(devices, sdi); | |
274 | ||
275 | sdi->status = SR_ST_INACTIVE; | |
276 | sdi->inst_type = SR_INST_USB; | |
277 | sdi->conn = sr_usb_dev_inst_new( | |
278 | libusb_get_bus_number(devlist[i]), | |
279 | libusb_get_device_address(devlist[i]), NULL); | |
280 | } | |
6a25fa42 | 281 | |
5089a143 AZ |
282 | g_slist_free_full(conn_devices, (GDestroyNotify)sr_usb_dev_inst_free); |
283 | libusb_free_device_list(devlist, 1); | |
6a25fa42 | 284 | |
5089a143 | 285 | return std_scan_complete(di, devices); |
6a25fa42 AZ |
286 | } |
287 | ||
288 | static int dev_open(struct sr_dev_inst *sdi) | |
289 | { | |
5089a143 AZ |
290 | struct sr_usb_dev_inst *usb = sdi->conn; |
291 | int ret; | |
6a25fa42 | 292 | |
5089a143 AZ |
293 | ret = h4032l_dev_open(sdi); |
294 | if (ret != SR_OK) { | |
295 | sr_err("Unable to open device."); | |
296 | return SR_ERR; | |
297 | } | |
6a25fa42 | 298 | |
5089a143 AZ |
299 | ret = libusb_claim_interface(usb->devhdl, USB_INTERFACE); |
300 | if (ret != 0) { | |
301 | switch (ret) { | |
302 | case LIBUSB_ERROR_BUSY: | |
303 | sr_err("Unable to claim USB interface. Another " | |
304 | "program or driver has already claimed it."); | |
305 | break; | |
306 | case LIBUSB_ERROR_NO_DEVICE: | |
307 | sr_err("Device has been disconnected."); | |
308 | break; | |
309 | default: | |
310 | sr_err("Unable to claim interface: %s.", | |
311 | libusb_error_name(ret)); | |
312 | break; | |
313 | } | |
314 | ||
315 | return SR_ERR; | |
316 | } | |
6a25fa42 | 317 | |
7a7afc00 AV |
318 | /* Get FPGA version. */ |
319 | if ((ret = h4032l_get_fpga_version(sdi)) != SR_OK) | |
320 | return ret; | |
321 | ||
6a25fa42 AZ |
322 | return SR_OK; |
323 | } | |
324 | ||
325 | static int dev_close(struct sr_dev_inst *sdi) | |
326 | { | |
5089a143 | 327 | struct sr_usb_dev_inst *usb; |
6a25fa42 | 328 | |
5089a143 | 329 | usb = sdi->conn; |
6a25fa42 | 330 | |
5089a143 AZ |
331 | if (!usb->devhdl) |
332 | return SR_ERR_BUG; | |
6a25fa42 | 333 | |
5089a143 AZ |
334 | sr_info("Closing device on %d.%d (logical) / %s (physical) interface %d.", |
335 | usb->bus, usb->address, sdi->connection_id, USB_INTERFACE); | |
336 | libusb_release_interface(usb->devhdl, USB_INTERFACE); | |
337 | libusb_close(usb->devhdl); | |
338 | usb->devhdl = NULL; | |
6a25fa42 AZ |
339 | |
340 | return SR_OK; | |
341 | } | |
342 | ||
343 | static int config_get(uint32_t key, GVariant **data, | |
344 | const struct sr_dev_inst *sdi, const struct sr_channel_group *cg) | |
345 | { | |
5089a143 AZ |
346 | struct dev_context *devc = sdi->priv; |
347 | struct sr_usb_dev_inst *usb; | |
cbc656e4 | 348 | int idx; |
6a25fa42 | 349 | |
6a25fa42 | 350 | switch (key) { |
caad0024 | 351 | case SR_CONF_VOLTAGE_THRESHOLD: |
61803a29 UH |
352 | if (!cg) |
353 | return SR_ERR_CHANNEL_GROUP; | |
cbc656e4 | 354 | if ((idx = std_str_idx_s(cg->name, ARRAY_AND_SIZE(cg_names))) < 0) |
61803a29 | 355 | return SR_ERR_CHANNEL_GROUP; |
cbc656e4 UH |
356 | *data = std_gvar_tuple_double( |
357 | devc->cur_threshold[idx], devc->cur_threshold[idx]); | |
caad0024 | 358 | break; |
5089a143 | 359 | case SR_CONF_SAMPLERATE: |
f49065c6 | 360 | *data = g_variant_new_uint64(samplerates_hw[devc->sample_rate]); |
5089a143 AZ |
361 | break; |
362 | case SR_CONF_CAPTURE_RATIO: | |
363 | *data = g_variant_new_uint64(devc->capture_ratio); | |
364 | break; | |
365 | case SR_CONF_LIMIT_SAMPLES: | |
366 | *data = g_variant_new_uint64(devc->cmd_pkt.sample_size); | |
367 | break; | |
f49065c6 AV |
368 | case SR_CONF_EXTERNAL_CLOCK: |
369 | *data = g_variant_new_boolean(devc->external_clock); | |
370 | break; | |
371 | case SR_CONF_EXTERNAL_CLOCK_SOURCE: | |
cbc656e4 | 372 | *data = g_variant_new_string(ext_clock_sources[devc->external_clock_source]); |
f49065c6 | 373 | break; |
5089a143 AZ |
374 | case SR_CONF_CONN: |
375 | if (!sdi || !(usb = sdi->conn)) | |
376 | return SR_ERR_ARG; | |
377 | *data = g_variant_new_printf("%d.%d", usb->bus, usb->address); | |
378 | break; | |
f49065c6 | 379 | case SR_CONF_CLOCK_EDGE: |
cbc656e4 | 380 | *data = g_variant_new_string(signal_edges[devc->clock_edge]); |
f49065c6 | 381 | break; |
6a25fa42 AZ |
382 | default: |
383 | return SR_ERR_NA; | |
384 | } | |
385 | ||
5089a143 | 386 | return SR_OK; |
6a25fa42 AZ |
387 | } |
388 | ||
389 | static int config_set(uint32_t key, GVariant *data, | |
390 | const struct sr_dev_inst *sdi, const struct sr_channel_group *cg) | |
391 | { | |
61803a29 | 392 | int idx; |
5089a143 AZ |
393 | struct dev_context *devc = sdi->priv; |
394 | struct h4032l_cmd_pkt *cmd_pkt = &devc->cmd_pkt; | |
7b9387b8 | 395 | uint64_t sample_rate, num_samples; |
cbc656e4 | 396 | double low, high; |
6a25fa42 | 397 | |
6a25fa42 | 398 | switch (key) { |
61803a29 UH |
399 | case SR_CONF_SAMPLERATE: |
400 | idx = 0; | |
401 | sample_rate = g_variant_get_uint64(data); | |
cbc656e4 | 402 | while (idx < (int)ARRAY_SIZE(samplerates_hw) && samplerates_hw[idx] != sample_rate) |
61803a29 UH |
403 | idx++; |
404 | if (idx == ARRAY_SIZE(samplerates_hw) || sample_rate == 0) { | |
405 | sr_err("Invalid sample rate."); | |
406 | return SR_ERR_SAMPLERATE; | |
3dc976fe | 407 | } |
61803a29 UH |
408 | devc->sample_rate = idx; |
409 | break; | |
410 | case SR_CONF_CAPTURE_RATIO: | |
583fc126 | 411 | devc->capture_ratio = g_variant_get_uint64(data); |
61803a29 UH |
412 | break; |
413 | case SR_CONF_LIMIT_SAMPLES: | |
7b9387b8 UH |
414 | num_samples = g_variant_get_uint64(data); |
415 | num_samples += 511; | |
416 | num_samples &= 0xfffffe00; | |
417 | if (num_samples < H4043L_NUM_SAMPLES_MIN || | |
418 | num_samples > H4032L_NUM_SAMPLES_MAX) { | |
61803a29 | 419 | sr_err("Invalid sample range 2k...64M: %" |
7b9387b8 | 420 | PRIu64 ".", num_samples); |
61803a29 | 421 | return SR_ERR; |
5089a143 | 422 | } |
7b9387b8 | 423 | cmd_pkt->sample_size = num_samples; |
61803a29 UH |
424 | break; |
425 | case SR_CONF_VOLTAGE_THRESHOLD: | |
426 | if (!cg) | |
427 | return SR_ERR_CHANNEL_GROUP; | |
cbc656e4 | 428 | if ((idx = std_str_idx_s(cg->name, ARRAY_AND_SIZE(cg_names))) < 0) |
61803a29 | 429 | return SR_ERR_CHANNEL_GROUP; |
cbc656e4 UH |
430 | g_variant_get(data, "(dd)", &low, &high); |
431 | devc->cur_threshold[idx] = (low + high) / 2.0; | |
61803a29 | 432 | break; |
f49065c6 AV |
433 | case SR_CONF_EXTERNAL_CLOCK: |
434 | devc->external_clock = g_variant_get_boolean(data); | |
435 | break; | |
436 | case SR_CONF_EXTERNAL_CLOCK_SOURCE: | |
437 | if ((idx = std_str_idx(data, ARRAY_AND_SIZE(ext_clock_sources))) < 0) | |
438 | return SR_ERR_ARG; | |
439 | devc->external_clock_source = idx; | |
440 | break; | |
441 | case SR_CONF_CLOCK_EDGE: | |
442 | if ((idx = std_str_idx(data, ARRAY_AND_SIZE(signal_edges))) < 0) | |
443 | return SR_ERR_ARG; | |
444 | devc->clock_edge = idx; | |
445 | break; | |
28f2d07f AV |
446 | default: |
447 | return SR_ERR_NA; | |
6a25fa42 AZ |
448 | } |
449 | ||
28f2d07f | 450 | return SR_OK; |
6a25fa42 AZ |
451 | } |
452 | ||
453 | static int config_list(uint32_t key, GVariant **data, | |
454 | const struct sr_dev_inst *sdi, const struct sr_channel_group *cg) | |
455 | { | |
f49065c6 AV |
456 | struct dev_context *devc = (sdi) ? sdi->priv : NULL; |
457 | ||
6a25fa42 | 458 | switch (key) { |
5089a143 AZ |
459 | case SR_CONF_SCAN_OPTIONS: |
460 | case SR_CONF_DEVICE_OPTIONS: | |
2a801861 AV |
461 | if (cg) { |
462 | *data = std_gvar_array_u32(ARRAY_AND_SIZE(devopts_cg)); | |
463 | break; | |
464 | } | |
f49065c6 AV |
465 | /* Disable external clock and edges for FPGA version 0. */ |
466 | if (devc && (!devc->fpga_version)) | |
467 | return STD_CONFIG_LIST(key, data, sdi, cg, scanopts, drvopts, devopts_fpga_zero); | |
5089a143 AZ |
468 | return STD_CONFIG_LIST(key, data, sdi, cg, scanopts, drvopts, devopts); |
469 | case SR_CONF_SAMPLERATE: | |
470 | *data = std_gvar_samplerates(ARRAY_AND_SIZE(samplerates)); | |
471 | break; | |
472 | case SR_CONF_TRIGGER_MATCH: | |
473 | *data = std_gvar_array_i32(ARRAY_AND_SIZE(trigger_matches)); | |
474 | break; | |
475 | case SR_CONF_VOLTAGE_THRESHOLD: | |
ee1a7d2f AV |
476 | *data = std_gvar_min_max_step_thresholds(H4032L_THR_VOLTAGE_MIN, |
477 | H4032L_THR_VOLTAGE_MAX, H4032L_THR_VOLTAGE_STEP); | |
5089a143 | 478 | break; |
4b75f84c AV |
479 | case SR_CONF_LIMIT_SAMPLES: |
480 | *data = std_gvar_tuple_u64(H4043L_NUM_SAMPLES_MIN, H4032L_NUM_SAMPLES_MAX); | |
481 | break; | |
f49065c6 AV |
482 | case SR_CONF_CLOCK_EDGE: |
483 | *data = g_variant_new_strv(ARRAY_AND_SIZE(signal_edges)); | |
484 | break; | |
485 | case SR_CONF_EXTERNAL_CLOCK_SOURCE: | |
486 | *data = g_variant_new_strv(ARRAY_AND_SIZE(ext_clock_sources)); | |
487 | break; | |
6a25fa42 AZ |
488 | default: |
489 | return SR_ERR_NA; | |
490 | } | |
491 | ||
5089a143 | 492 | return SR_OK; |
6a25fa42 AZ |
493 | } |
494 | ||
5089a143 | 495 | static int dev_acquisition_start(const struct sr_dev_inst *sdi) |
6a25fa42 | 496 | { |
5089a143 AZ |
497 | struct sr_dev_driver *di = sdi->driver; |
498 | struct drv_context *drvc = di->context; | |
499 | struct dev_context *devc = sdi->priv; | |
500 | struct sr_trigger *trigger = sr_session_trigger_get(sdi->session); | |
501 | struct h4032l_cmd_pkt *cmd_pkt = &devc->cmd_pkt; | |
502 | ||
28f2d07f | 503 | /* Initialize variables. */ |
a5b9880e | 504 | devc->acq_aborted = FALSE; |
2958315d | 505 | devc->submitted_transfers = 0; |
3dc976fe | 506 | devc->sent_samples = 0; |
a5b9880e | 507 | |
5089a143 AZ |
508 | /* Calculate packet ratio. */ |
509 | cmd_pkt->pre_trigger_size = (cmd_pkt->sample_size * devc->capture_ratio) / 100; | |
3dc976fe | 510 | devc->trigger_pos = cmd_pkt->pre_trigger_size; |
5089a143 | 511 | |
f49065c6 AV |
512 | /* Set clock edge, when external clock is enabled. */ |
513 | if (devc->external_clock) | |
514 | cmd_pkt->sample_rate = ext_clock_edges[devc->external_clock_source][devc->clock_edge]; | |
515 | else | |
516 | cmd_pkt->sample_rate = devc->sample_rate; | |
517 | ||
e6bb2984 | 518 | /* Set PWM channel values. */ |
2a801861 AV |
519 | devc->cmd_pkt.pwm_a = h4032l_voltage2pwm(devc->cur_threshold[0]); |
520 | devc->cmd_pkt.pwm_b = h4032l_voltage2pwm(devc->cur_threshold[1]); | |
caad0024 | 521 | |
5089a143 AZ |
522 | cmd_pkt->trig_flags.enable_trigger1 = 0; |
523 | cmd_pkt->trig_flags.enable_trigger2 = 0; | |
524 | cmd_pkt->trig_flags.trigger_and_logic = 0; | |
525 | ||
526 | if (trigger && trigger->stages) { | |
527 | GSList *stages = trigger->stages; | |
528 | struct sr_trigger_stage *stage1 = stages->data; | |
529 | if (stages->next) { | |
4868f15a | 530 | sr_err("Only one trigger stage supported for now."); |
5089a143 AZ |
531 | return SR_ERR; |
532 | } | |
533 | cmd_pkt->trig_flags.enable_trigger1 = 1; | |
534 | cmd_pkt->trigger[0].flags.edge_type = H4032L_TRIGGER_EDGE_TYPE_DISABLED; | |
535 | cmd_pkt->trigger[0].flags.data_range_enabled = 0; | |
536 | cmd_pkt->trigger[0].flags.time_range_enabled = 0; | |
537 | cmd_pkt->trigger[0].flags.combined_enabled = 0; | |
538 | cmd_pkt->trigger[0].flags.data_range_type = H4032L_TRIGGER_DATA_RANGE_TYPE_MAX; | |
539 | cmd_pkt->trigger[0].data_range_mask = 0; | |
540 | cmd_pkt->trigger[0].data_range_max = 0; | |
541 | ||
542 | /* Initialize range mask values. */ | |
543 | uint32_t range_mask = 0; | |
544 | uint32_t range_value = 0; | |
545 | ||
546 | GSList *channel = stage1->matches; | |
547 | while (channel) { | |
548 | struct sr_trigger_match *match = channel->data; | |
549 | ||
550 | switch (match->match) { | |
551 | case SR_TRIGGER_ZERO: | |
552 | range_mask |= (1 << match->channel->index); | |
553 | break; | |
554 | case SR_TRIGGER_ONE: | |
555 | range_mask |= (1 << match->channel->index); | |
556 | range_value |= (1 << match->channel->index); | |
557 | break; | |
558 | case SR_TRIGGER_RISING: | |
559 | if (cmd_pkt->trigger[0].flags.edge_type != H4032L_TRIGGER_EDGE_TYPE_DISABLED) { | |
4868f15a | 560 | sr_err("Only one trigger signal with fall/rising/edge allowed."); |
5089a143 AZ |
561 | return SR_ERR; |
562 | } | |
563 | cmd_pkt->trigger[0].flags.edge_type = H4032L_TRIGGER_EDGE_TYPE_RISE; | |
564 | cmd_pkt->trigger[0].flags.edge_signal = match->channel->index; | |
565 | break; | |
566 | case SR_TRIGGER_FALLING: | |
567 | if (cmd_pkt->trigger[0].flags.edge_type != H4032L_TRIGGER_EDGE_TYPE_DISABLED) { | |
4868f15a | 568 | sr_err("Only one trigger signal with fall/rising/edge allowed."); |
5089a143 AZ |
569 | return SR_ERR; |
570 | } | |
571 | cmd_pkt->trigger[0].flags.edge_type = H4032L_TRIGGER_EDGE_TYPE_FALL; | |
572 | cmd_pkt->trigger[0].flags.edge_signal = match->channel->index; | |
573 | break; | |
574 | case SR_TRIGGER_EDGE: | |
575 | if (cmd_pkt->trigger[0].flags.edge_type != H4032L_TRIGGER_EDGE_TYPE_DISABLED) { | |
4868f15a | 576 | sr_err("Only one trigger signal with fall/rising/edge allowed."); |
5089a143 AZ |
577 | return SR_ERR; |
578 | } | |
579 | cmd_pkt->trigger[0].flags.edge_type = H4032L_TRIGGER_EDGE_TYPE_TOGGLE; | |
580 | cmd_pkt->trigger[0].flags.edge_signal = match->channel->index; | |
581 | break; | |
582 | default: | |
4868f15a | 583 | sr_err("Unknown trigger value."); |
5089a143 AZ |
584 | return SR_ERR; |
585 | } | |
586 | ||
587 | channel = channel->next; | |
588 | } | |
589 | ||
80d34975 UH |
590 | cmd_pkt->trigger[0].flags.data_range_enabled = 1; |
591 | cmd_pkt->trigger[0].data_range_mask |= range_mask; | |
592 | cmd_pkt->trigger[0].data_range_max = range_value; | |
5089a143 | 593 | } |
6a25fa42 | 594 | |
74c4c174 | 595 | usb_source_add(sdi->session, drvc->sr_ctx, 1000, |
5089a143 | 596 | h4032l_receive_data, sdi->driver->context); |
6a25fa42 | 597 | |
5089a143 AZ |
598 | /* Start capturing. */ |
599 | return h4032l_start(sdi); | |
6a25fa42 AZ |
600 | } |
601 | ||
5089a143 | 602 | static int dev_acquisition_stop(struct sr_dev_inst *sdi) |
6a25fa42 | 603 | { |
2958315d AV |
604 | /* Stop capturing. */ |
605 | return h4032l_stop(sdi); | |
6a25fa42 AZ |
606 | } |
607 | ||
3f34a402 | 608 | static struct sr_dev_driver hantek_4032l_driver_info = { |
6a25fa42 | 609 | .name = "hantek-4032l", |
5089a143 | 610 | .longname = "Hantek 4032L", |
6a25fa42 | 611 | .api_version = 1, |
5089a143 AZ |
612 | .init = std_init, |
613 | .cleanup = std_cleanup, | |
6a25fa42 | 614 | .scan = scan, |
5089a143 AZ |
615 | .dev_list = std_dev_list, |
616 | .dev_clear = std_dev_clear, | |
6a25fa42 AZ |
617 | .config_get = config_get, |
618 | .config_set = config_set, | |
619 | .config_list = config_list, | |
620 | .dev_open = dev_open, | |
621 | .dev_close = dev_close, | |
622 | .dev_acquisition_start = dev_acquisition_start, | |
623 | .dev_acquisition_stop = dev_acquisition_stop, | |
624 | .context = NULL, | |
625 | }; | |
5089a143 | 626 | SR_REGISTER_DEV_DRIVER(hantek_4032l_driver_info); |