[libsigrok.git] / src / hardware / hantek-4032l / api.c

/*
 * This file is part of the libsigrok project.
 *
 * Copyright (C) 2016 Andreas Zschunke <andreas.zschunke@gmx.net>
 * Copyright (C) 2017 Andrej Valek <andy@skyrain.eu>
 * Copyright (C) 2017 Uwe Hermann <uwe@hermann-uwe.de>
 *
 * This program is free software: you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation, either version 3 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#include <config.h>
#include "protocol.h"

#define USB_INTERFACE 0
#define NUM_CHANNELS 32

static const uint32_t scanopts[] = {
	SR_CONF_CONN,
};

static const uint32_t drvopts[] = {
	SR_CONF_LOGIC_ANALYZER,
};

static const uint32_t devopts[] = {
	SR_CONF_SAMPLERATE | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
	SR_CONF_CAPTURE_RATIO | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
	SR_CONF_LIMIT_SAMPLES | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
	SR_CONF_TRIGGER_MATCH | SR_CONF_LIST,
	SR_CONF_CONN | SR_CONF_GET,
};

static const uint32_t devopts_cg[] = {
	SR_CONF_VOLTAGE_THRESHOLD | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
};

static const int32_t trigger_matches[] = {
	SR_TRIGGER_ZERO,
	SR_TRIGGER_ONE,
	SR_TRIGGER_RISING,
	SR_TRIGGER_FALLING,
	SR_TRIGGER_EDGE,
};

static const uint64_t samplerates[] = {
	SR_KHZ(1),
	SR_KHZ(2),
	SR_KHZ(4),
	SR_KHZ(8),
	SR_KHZ(16),
	SR_HZ(31250),
	SR_HZ(62500),
	SR_KHZ(125),
	SR_KHZ(250),
	SR_KHZ(500),
	SR_KHZ(625),
	SR_HZ(781250),
	SR_MHZ(1),
	SR_KHZ(1250),
	SR_HZ(1562500),
	SR_MHZ(2),
	SR_KHZ(2500),
	SR_KHZ(3125),
	SR_MHZ(4),
	SR_MHZ(5),
	SR_KHZ(6250),
	SR_MHZ(10),
	SR_KHZ(12500),
	SR_MHZ(20),
	SR_MHZ(25),
	SR_MHZ(40),
	SR_MHZ(50),
	SR_MHZ(80),
	SR_MHZ(100),
	SR_MHZ(160),
	SR_MHZ(200),
	SR_MHZ(320),
	SR_MHZ(400),
};

static const uint64_t samplerates_hw[] = {
	SR_MHZ(100),
	SR_MHZ(50),
	SR_MHZ(25),
	SR_KHZ(12500),
	SR_KHZ(6250),
	SR_KHZ(3125),
	SR_HZ(1562500),
	SR_HZ(781250),
	SR_MHZ(80),
	SR_MHZ(40),
	SR_MHZ(20),
	SR_MHZ(10),
	SR_MHZ(5),
	SR_KHZ(2500),
	SR_KHZ(1250),
	SR_KHZ(625),
	SR_MHZ(4),
	SR_MHZ(2),
	SR_MHZ(1),
	SR_KHZ(500),
	SR_KHZ(250),
	SR_KHZ(125),
	SR_HZ(62500),
	SR_HZ(31250),
	SR_KHZ(16),
	SR_KHZ(8),
	SR_KHZ(4),
	SR_KHZ(2),
	SR_KHZ(1),
	0,
	0,
	0,
	SR_MHZ(200),
	SR_MHZ(160),
	SR_MHZ(400),
	SR_MHZ(320),
};

SR_PRIV struct sr_dev_driver hantek_4032l_driver_info;

static GSList *scan(struct sr_dev_driver *di, GSList *options)
{
	struct drv_context *drvc = di->context;
	GSList *l, *devices, *conn_devices;
	libusb_device **devlist;
	struct libusb_device_descriptor des;
	const char *conn;
	int i;
	char connection_id[64];
	struct sr_channel_group *cg;
	struct sr_dev_inst *sdi;
	struct sr_channel *ch;

	devices = NULL;
	conn_devices = NULL;
	drvc->instances = NULL;
	conn = NULL;

	for (l = options; l; l = l->next) {
		struct sr_config *src = l->data;
		if (src->key == SR_CONF_CONN) {
			conn = g_variant_get_string(src->data, NULL);
			break;
		}
	}

	if (conn)
		conn_devices = sr_usb_find(drvc->sr_ctx->libusb_ctx, conn);
	else
		conn_devices = NULL;

	libusb_get_device_list(drvc->sr_ctx->libusb_ctx, &devlist);
	for (i = 0; devlist[i]; i++) {
		if (conn) {
			struct sr_usb_dev_inst *usb = NULL;
			for (l = conn_devices; l; l = l->next) {
				usb = l->data;
				if (usb->bus == libusb_get_bus_number(devlist[i]) &&
				    usb->address == libusb_get_device_address(devlist[i]))
					break;
			}
			if (!l)
				/* This device matched none of the ones that
				 * matched the conn specification. */
				continue;
		}

		libusb_get_device_descriptor(devlist[i], &des);

		if (des.idVendor != H4032L_USB_VENDOR ||
		    des.idProduct != H4032L_USB_PRODUCT)
			continue;

		if (usb_get_port_path(devlist[i], connection_id, sizeof(connection_id)) < 0)
			continue;

		sdi = g_malloc0(sizeof(struct sr_dev_inst));
		sdi->driver = &hantek_4032l_driver_info;
		sdi->vendor = g_strdup("Hantek");
		sdi->model = g_strdup("4032L");
		sdi->connection_id = g_strdup(connection_id);

		struct sr_channel_group *channel_groups[2];
		for (int j = 0; j < 2; j++) {
			cg = g_malloc0(sizeof(struct sr_channel_group));
			cg->name = g_strdup_printf("%c", 'A' + j);
			channel_groups[j] = cg;
			sdi->channel_groups = g_slist_append(sdi->channel_groups, cg);
		}

		/* Assemble channel list and add channel to channel groups. */
		for (int j = 0; j < NUM_CHANNELS; j++) {
			char channel_name[4];
			sprintf(channel_name, "%c%d", 'A' + (j & 1), j / 2);
			ch = sr_channel_new(sdi, j, SR_CHANNEL_LOGIC, TRUE, channel_name);
			cg = channel_groups[j & 1];
			cg->channels = g_slist_append(cg->channels, ch);
		}

		struct dev_context *devc = g_malloc0(sizeof(struct dev_context));

		/* Initialize command packet. */
		devc->cmd_pkt.magic = H4032L_CMD_PKT_MAGIC;
		devc->cmd_pkt.sample_size = 16384;

		devc->status = H4032L_STATUS_IDLE;

		devc->capture_ratio = 5;
		devc->cur_threshold[0] = 2.5;
		devc->cur_threshold[1] = 2.5;

		sdi->priv = devc;
		devices = g_slist_append(devices, sdi);

		sdi->status = SR_ST_INACTIVE;
		sdi->inst_type = SR_INST_USB;
		sdi->conn = sr_usb_dev_inst_new(
			libusb_get_bus_number(devlist[i]),
			libusb_get_device_address(devlist[i]), NULL);
	}

	g_slist_free_full(conn_devices, (GDestroyNotify)sr_usb_dev_inst_free);
	libusb_free_device_list(devlist, 1);

	return std_scan_complete(di, devices);
}

static int dev_open(struct sr_dev_inst *sdi)
{
	struct sr_usb_dev_inst *usb = sdi->conn;
	int ret;

	ret = h4032l_dev_open(sdi);
	if (ret != SR_OK) {
		sr_err("Unable to open device.");
		return SR_ERR;
	}

	ret = libusb_claim_interface(usb->devhdl, USB_INTERFACE);
	if (ret != 0) {
		switch (ret) {
		case LIBUSB_ERROR_BUSY:
			sr_err("Unable to claim USB interface. Another "
			       "program or driver has already claimed it.");
			break;
		case LIBUSB_ERROR_NO_DEVICE:
			sr_err("Device has been disconnected.");
			break;
		default:
			sr_err("Unable to claim interface: %s.",
			       libusb_error_name(ret));
			break;
		}

		return SR_ERR;
	}

	/* Get FPGA version. */
	if ((ret = h4032l_get_fpga_version(sdi)) != SR_OK)
		return ret;

	return SR_OK;
}

static int dev_close(struct sr_dev_inst *sdi)
{
	struct sr_usb_dev_inst *usb;

	usb = sdi->conn;

	if (!usb->devhdl)
		return SR_ERR_BUG;

	sr_info("Closing device on %d.%d (logical) / %s (physical) interface %d.",
		usb->bus, usb->address, sdi->connection_id, USB_INTERFACE);
	libusb_release_interface(usb->devhdl, USB_INTERFACE);
	libusb_close(usb->devhdl);
	usb->devhdl = NULL;

	return SR_OK;
}

static int config_get(uint32_t key, GVariant **data,
	const struct sr_dev_inst *sdi, const struct sr_channel_group *cg)
{
	struct dev_context *devc = sdi->priv;
	struct sr_usb_dev_inst *usb;

	switch (key) {
	case SR_CONF_VOLTAGE_THRESHOLD:
		if (cg) {
			if (!strcmp(cg->name, "A"))
				*data = std_gvar_tuple_double(
					devc->cur_threshold[0], devc->cur_threshold[0]);
			else if (!strcmp(cg->name, "B"))
				*data = std_gvar_tuple_double(
					devc->cur_threshold[1], devc->cur_threshold[1]);
			else
				return SR_ERR_CHANNEL_GROUP;
		}
		break;
	case SR_CONF_SAMPLERATE:
		*data = g_variant_new_uint64(samplerates_hw[devc->cmd_pkt.sample_rate]);
		break;
	case SR_CONF_CAPTURE_RATIO:
		*data = g_variant_new_uint64(devc->capture_ratio);
		break;
	case SR_CONF_LIMIT_SAMPLES:
		*data = g_variant_new_uint64(devc->cmd_pkt.sample_size);
		break;
	case SR_CONF_CONN:
		if (!sdi || !(usb = sdi->conn))
			return SR_ERR_ARG;
		*data = g_variant_new_printf("%d.%d", usb->bus, usb->address);
		break;
	default:
		return SR_ERR_NA;
	}

	return SR_OK;
}

static int config_set(uint32_t key, GVariant *data,
	const struct sr_dev_inst *sdi, const struct sr_channel_group *cg)
{
	struct dev_context *devc = sdi->priv;
	struct h4032l_cmd_pkt *cmd_pkt = &devc->cmd_pkt;

	switch (key) {
	case SR_CONF_SAMPLERATE: {
			uint64_t sample_rate = g_variant_get_uint64(data);
			uint8_t i = 0;
			while (i < ARRAY_SIZE(samplerates_hw) && samplerates_hw[i] != sample_rate)
				i++;

			if (i == ARRAY_SIZE(samplerates_hw) || sample_rate == 0) {
				sr_err("Invalid sample rate.");
				return SR_ERR_SAMPLERATE;
			}
			cmd_pkt->sample_rate = i;
			break;
		}
	case SR_CONF_CAPTURE_RATIO: {
			uint64_t capture_ratio = g_variant_get_uint64(data);
			if (capture_ratio > 99) {
				sr_err("Invalid capture ratio.");
				return SR_ERR;
			}
			devc->capture_ratio = capture_ratio;
			break;
		}
	case SR_CONF_LIMIT_SAMPLES: {
			uint64_t number_samples = g_variant_get_uint64(data);
			number_samples += 511;
			number_samples &= 0xfffffe00;
			if (number_samples < H4043L_NUM_SAMPLES_MIN ||
			    number_samples > H4032L_NUM_SAMPLES_MAX) {
				sr_err("Invalid sample range 2k...64M: %"
				       PRIu64 ".", number_samples);
				return SR_ERR;
			}
			cmd_pkt->sample_size = number_samples;
			break;
		}
	case SR_CONF_VOLTAGE_THRESHOLD: {
			double low, high;
			g_variant_get(data, "(dd)", &low, &high);
			double threshold = (low + high) / 2.0;
			if (cg) {
				if (!strcmp(cg->name, "A"))
					devc->cur_threshold[0] = threshold;
				else if (!strcmp(cg->name, "B"))
					devc->cur_threshold[1] = threshold;
				else
					return SR_ERR_CHANNEL_GROUP;
			}
			break;
		}
	default:
		return SR_ERR_NA;
	}

	return SR_OK;
}

static int config_list(uint32_t key, GVariant **data,
	const struct sr_dev_inst *sdi, const struct sr_channel_group *cg)
{
	switch (key) {
	case SR_CONF_SCAN_OPTIONS:
	case SR_CONF_DEVICE_OPTIONS:
		if (cg) {
			*data = std_gvar_array_u32(ARRAY_AND_SIZE(devopts_cg));
			break;
		}
		return STD_CONFIG_LIST(key, data, sdi, cg, scanopts, drvopts, devopts);
	case SR_CONF_SAMPLERATE:
		*data = std_gvar_samplerates(ARRAY_AND_SIZE(samplerates));
		break;
	case SR_CONF_TRIGGER_MATCH:
		*data = std_gvar_array_i32(ARRAY_AND_SIZE(trigger_matches));
		break;
	case SR_CONF_VOLTAGE_THRESHOLD:
		*data = std_gvar_min_max_step_thresholds(-6.0, 6.0, 0.1);
		break;
	case SR_CONF_LIMIT_SAMPLES:
		*data = std_gvar_tuple_u64(H4043L_NUM_SAMPLES_MIN, H4032L_NUM_SAMPLES_MAX);
		break;
	default:
		return SR_ERR_NA;
	}

	return SR_OK;
}

static int dev_acquisition_start(const struct sr_dev_inst *sdi)
{
	struct sr_dev_driver *di = sdi->driver;
	struct drv_context *drvc = di->context;
	struct dev_context *devc = sdi->priv;
	struct sr_trigger *trigger = sr_session_trigger_get(sdi->session);
	struct h4032l_cmd_pkt *cmd_pkt = &devc->cmd_pkt;

	/* Initialize variables. */
	devc->acq_aborted = FALSE;
	devc->submitted_transfers = 0;
	devc->sent_samples = 0;

	/* Calculate packet ratio. */
	cmd_pkt->pre_trigger_size = (cmd_pkt->sample_size * devc->capture_ratio) / 100;
	devc->trigger_pos = cmd_pkt->pre_trigger_size;

	/* Set pwm channel values. */
	devc->cmd_pkt.pwm_a = h4032l_voltage2pwm(devc->cur_threshold[0]);
	devc->cmd_pkt.pwm_b = h4032l_voltage2pwm(devc->cur_threshold[1]);

	cmd_pkt->trig_flags.enable_trigger1 = 0;
	cmd_pkt->trig_flags.enable_trigger2 = 0;
	cmd_pkt->trig_flags.trigger_and_logic = 0;

	if (trigger && trigger->stages) {
		GSList *stages = trigger->stages;
		struct sr_trigger_stage *stage1 = stages->data;
		if (stages->next) {
			sr_err("Only one trigger stage supported for now.");
			return SR_ERR;
		}
		cmd_pkt->trig_flags.enable_trigger1 = 1;
		cmd_pkt->trigger[0].flags.edge_type = H4032L_TRIGGER_EDGE_TYPE_DISABLED;
		cmd_pkt->trigger[0].flags.data_range_enabled = 0;
		cmd_pkt->trigger[0].flags.time_range_enabled = 0;
		cmd_pkt->trigger[0].flags.combined_enabled = 0;
		cmd_pkt->trigger[0].flags.data_range_type = H4032L_TRIGGER_DATA_RANGE_TYPE_MAX;
		cmd_pkt->trigger[0].data_range_mask = 0;
		cmd_pkt->trigger[0].data_range_max = 0;

		/* Initialize range mask values. */
		uint32_t range_mask = 0;
		uint32_t range_value = 0;

		GSList *channel = stage1->matches;
		while (channel) {
			struct sr_trigger_match *match = channel->data;

			switch (match->match) {
			case SR_TRIGGER_ZERO:
				range_mask |= (1 << match->channel->index);
				break;
			case SR_TRIGGER_ONE:
				range_mask |= (1 << match->channel->index);
				range_value |= (1 << match->channel->index);
				break;
			case SR_TRIGGER_RISING:
				if (cmd_pkt->trigger[0].flags.edge_type != H4032L_TRIGGER_EDGE_TYPE_DISABLED) {
					sr_err("Only one trigger signal with fall/rising/edge allowed.");
					return SR_ERR;
				}
				cmd_pkt->trigger[0].flags.edge_type = H4032L_TRIGGER_EDGE_TYPE_RISE;
				cmd_pkt->trigger[0].flags.edge_signal = match->channel->index;
				break;
			case SR_TRIGGER_FALLING:
				if (cmd_pkt->trigger[0].flags.edge_type != H4032L_TRIGGER_EDGE_TYPE_DISABLED) {
					sr_err("Only one trigger signal with fall/rising/edge allowed.");
					return SR_ERR;
				}
				cmd_pkt->trigger[0].flags.edge_type = H4032L_TRIGGER_EDGE_TYPE_FALL;
				cmd_pkt->trigger[0].flags.edge_signal = match->channel->index;
				break;
			case SR_TRIGGER_EDGE:
				if (cmd_pkt->trigger[0].flags.edge_type != H4032L_TRIGGER_EDGE_TYPE_DISABLED) {
					sr_err("Only one trigger signal with fall/rising/edge allowed.");
					return SR_ERR;
				}
				cmd_pkt->trigger[0].flags.edge_type = H4032L_TRIGGER_EDGE_TYPE_TOGGLE;
				cmd_pkt->trigger[0].flags.edge_signal = match->channel->index;
				break;
			default:
				sr_err("Unknown trigger value.");
				return SR_ERR;
			}

			channel = channel->next;
		}

		/* Compress range mask value and apply range settings. */
		if (range_mask) {
			cmd_pkt->trigger[0].flags.data_range_enabled = 1;
			cmd_pkt->trigger[0].data_range_mask |= (range_mask);

			uint32_t new_range_value = 0;
			uint32_t bit_mask = 1;
			while (range_mask) {
				if ((range_mask & 1) != 0) {
					new_range_value <<= 1;
					if ((range_value & 1) != 0)
						new_range_value |= bit_mask;
					bit_mask <<= 1;
				}
				range_mask >>= 1;
				range_value >>= 1;
			}
			cmd_pkt->trigger[0].data_range_max |= range_value;
		}
	}

	usb_source_add(sdi->session, drvc->sr_ctx, 1000,
		h4032l_receive_data, sdi->driver->context);

	/* Start capturing. */
	return h4032l_start(sdi);
}

static int dev_acquisition_stop(struct sr_dev_inst *sdi)
{
	/* Stop capturing. */
	return h4032l_stop(sdi);
}

SR_PRIV struct sr_dev_driver hantek_4032l_driver_info = {
	.name = "hantek-4032l",
	.longname = "Hantek 4032L",
	.api_version = 1,
	.init = std_init,
	.cleanup = std_cleanup,
	.scan = scan,
	.dev_list = std_dev_list,
	.dev_clear = std_dev_clear,
	.config_get = config_get,
	.config_set = config_set,
	.config_list = config_list,
	.dev_open = dev_open,
	.dev_close = dev_close,
	.dev_acquisition_start = dev_acquisition_start,
	.dev_acquisition_stop = dev_acquisition_stop,
	.context = NULL,
};
SR_REGISTER_DEV_DRIVER(hantek_4032l_driver_info);
Commit	Line	Data
6a25fa42 AZ	1	/*
	2	* This file is part of the libsigrok project.
	3	*
5089a143 AZ	4	* Copyright (C) 2016 Andreas Zschunke <andreas.zschunke@gmx.net>
	5	* Copyright (C) 2017 Andrej Valek <andy@skyrain.eu>
	6	* Copyright (C) 2017 Uwe Hermann <uwe@hermann-uwe.de>
6a25fa42 AZ	7	*
	8	* This program is free software: you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License as published by
	10	* the Free Software Foundation, either version 3 of the License, or
	11	* (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program. If not, see <http://www.gnu.org/licenses/>.
	20	*/
	21
	22	#include <config.h>
	23	#include "protocol.h"
	24
5089a143 AZ	25	#define USB_INTERFACE 0
5089a143 AZ	26	#define NUM_CHANNELS 32
6a25fa42	27
5089a143 AZ	28	static const uint32_t scanopts[] = {
	29	SR_CONF_CONN,
	30	};
	31
	32	static const uint32_t drvopts[] = {
	33	SR_CONF_LOGIC_ANALYZER,
	34	};
	35
	36	static const uint32_t devopts[] = {
	37	SR_CONF_SAMPLERATE \| SR_CONF_GET \| SR_CONF_SET \| SR_CONF_LIST,
3dc976fe	38	SR_CONF_CAPTURE_RATIO \| SR_CONF_GET \| SR_CONF_SET \| SR_CONF_LIST,
4b75f84c	39	SR_CONF_LIMIT_SAMPLES \| SR_CONF_GET \| SR_CONF_SET \| SR_CONF_LIST,
5089a143 AZ	40	SR_CONF_TRIGGER_MATCH \| SR_CONF_LIST,
5089a143 AZ	41	SR_CONF_CONN \| SR_CONF_GET,
2a801861 AV	42	};
	43
	44	static const uint32_t devopts_cg[] = {
caad0024	45	SR_CONF_VOLTAGE_THRESHOLD \| SR_CONF_GET \| SR_CONF_SET \| SR_CONF_LIST,
5089a143 AZ	46	};
	47
	48	static const int32_t trigger_matches[] = {
	49	SR_TRIGGER_ZERO,
	50	SR_TRIGGER_ONE,
	51	SR_TRIGGER_RISING,
	52	SR_TRIGGER_FALLING,
	53	SR_TRIGGER_EDGE,
	54	};
	55
	56	static const uint64_t samplerates[] = {
	57	SR_KHZ(1),
	58	SR_KHZ(2),
	59	SR_KHZ(4),
	60	SR_KHZ(8),
	61	SR_KHZ(16),
	62	SR_HZ(31250),
	63	SR_HZ(62500),
	64	SR_KHZ(125),
	65	SR_KHZ(250),
	66	SR_KHZ(500),
	67	SR_KHZ(625),
	68	SR_HZ(781250),
	69	SR_MHZ(1),
	70	SR_KHZ(1250),
	71	SR_HZ(1562500),
	72	SR_MHZ(2),
	73	SR_KHZ(2500),
	74	SR_KHZ(3125),
	75	SR_MHZ(4),
	76	SR_MHZ(5),
	77	SR_KHZ(6250),
	78	SR_MHZ(10),
	79	SR_KHZ(12500),
	80	SR_MHZ(20),
	81	SR_MHZ(25),
	82	SR_MHZ(40),
	83	SR_MHZ(50),
	84	SR_MHZ(80),
	85	SR_MHZ(100),
	86	SR_MHZ(160),
	87	SR_MHZ(200),
	88	SR_MHZ(320),
	89	SR_MHZ(400),
	90	};
	91
	92	static const uint64_t samplerates_hw[] = {
	93	SR_MHZ(100),
	94	SR_MHZ(50),
	95	SR_MHZ(25),
	96	SR_KHZ(12500),
	97	SR_KHZ(6250),
	98	SR_KHZ(3125),
	99	SR_HZ(1562500),
	100	SR_HZ(781250),
	101	SR_MHZ(80),
	102	SR_MHZ(40),
	103	SR_MHZ(20),
	104	SR_MHZ(10),
	105	SR_MHZ(5),
	106	SR_KHZ(2500),
	107	SR_KHZ(1250),
	108	SR_KHZ(625),
	109	SR_MHZ(4),
110	SR_MHZ(2),
111	SR_MHZ(1),
112	SR_KHZ(500),
113	SR_KHZ(250),
114	SR_KHZ(125),
115	SR_HZ(62500),
116	SR_HZ(31250),
117	SR_KHZ(16),
118	SR_KHZ(8),
119	SR_KHZ(4),
120	SR_KHZ(2),
121	SR_KHZ(1),
122	0,
123	0,
124	0,
125	SR_MHZ(200),
126	SR_MHZ(160),
127	SR_MHZ(400),
128	SR_MHZ(320),
129	};
130
131	SR_PRIV struct sr_dev_driver hantek_4032l_driver_info;
6a25fa42 AZ	132
	133	static GSList scan(struct sr_dev_driver di, GSList *options)
	134	{
5089a143 AZ	135	struct drv_context *drvc = di->context;
	136	GSList l, devices, *conn_devices;
	137	libusb_device **devlist;
	138	struct libusb_device_descriptor des;
	139	const char *conn;
	140	int i;
	141	char connection_id[64];
	142	struct sr_channel_group *cg;
	143	struct sr_dev_inst *sdi;
	144	struct sr_channel *ch;
6a25fa42 AZ	145
6a25fa42 AZ	146	devices = NULL;
5089a143	147	conn_devices = NULL;
6a25fa42	148	drvc->instances = NULL;
5089a143 AZ	149	conn = NULL;
	150
	151	for (l = options; l; l = l->next) {
	152	struct sr_config *src = l->data;
	153	if (src->key == SR_CONF_CONN) {
	154	conn = g_variant_get_string(src->data, NULL);
	155	break;
	156	}
	157	}
6a25fa42	158
5089a143 AZ	159	if (conn)
	160	conn_devices = sr_usb_find(drvc->sr_ctx->libusb_ctx, conn);
	161	else
	162	conn_devices = NULL;
	163
	164	libusb_get_device_list(drvc->sr_ctx->libusb_ctx, &devlist);
	165	for (i = 0; devlist[i]; i++) {
	166	if (conn) {
	167	struct sr_usb_dev_inst *usb = NULL;
	168	for (l = conn_devices; l; l = l->next) {
	169	usb = l->data;
28f2d07f AV	170	if (usb->bus == libusb_get_bus_number(devlist[i]) &&
28f2d07f AV	171	usb->address == libusb_get_device_address(devlist[i]))
5089a143 AZ	172	break;
	173	}
	174	if (!l)
	175	/* This device matched none of the ones that
	176	* matched the conn specification. */
	177	continue;
	178	}
	179
	180	libusb_get_device_descriptor(devlist[i], &des);
	181
	182	if (des.idVendor != H4032L_USB_VENDOR \|\|
	183	des.idProduct != H4032L_USB_PRODUCT)
	184	continue;
	185
6c1a76d1 RT	186	if (usb_get_port_path(devlist[i], connection_id, sizeof(connection_id)) < 0)
6c1a76d1 RT	187	continue;
5089a143 AZ	188
	189	sdi = g_malloc0(sizeof(struct sr_dev_inst));
	190	sdi->driver = &hantek_4032l_driver_info;
	191	sdi->vendor = g_strdup("Hantek");
	192	sdi->model = g_strdup("4032L");
	193	sdi->connection_id = g_strdup(connection_id);
	194
	195	struct sr_channel_group *channel_groups[2];
	196	for (int j = 0; j < 2; j++) {
	197	cg = g_malloc0(sizeof(struct sr_channel_group));
	198	cg->name = g_strdup_printf("%c", 'A' + j);
	199	channel_groups[j] = cg;
	200	sdi->channel_groups = g_slist_append(sdi->channel_groups, cg);
	201	}
	202
	203	/* Assemble channel list and add channel to channel groups. */
	204	for (int j = 0; j < NUM_CHANNELS; j++) {
	205	char channel_name[4];
	206	sprintf(channel_name, "%c%d", 'A' + (j & 1), j / 2);
	207	ch = sr_channel_new(sdi, j, SR_CHANNEL_LOGIC, TRUE, channel_name);
	208	cg = channel_groups[j & 1];
	209	cg->channels = g_slist_append(cg->channels, ch);
	210	}
	211
	212	struct dev_context *devc = g_malloc0(sizeof(struct dev_context));
	213
	214	/* Initialize command packet. */
	215	devc->cmd_pkt.magic = H4032L_CMD_PKT_MAGIC;
5089a143	216	devc->cmd_pkt.sample_size = 16384;
5089a143 AZ	217
	218	devc->status = H4032L_STATUS_IDLE;
	219
	220	devc->capture_ratio = 5;
2a801861 AV	221	devc->cur_threshold[0] = 2.5;
2a801861 AV	222	devc->cur_threshold[1] = 2.5;
5089a143	223
5089a143 AZ	224	sdi->priv = devc;
	225	devices = g_slist_append(devices, sdi);
	226
	227	sdi->status = SR_ST_INACTIVE;
	228	sdi->inst_type = SR_INST_USB;
	229	sdi->conn = sr_usb_dev_inst_new(
	230	libusb_get_bus_number(devlist[i]),
	231	libusb_get_device_address(devlist[i]), NULL);
	232	}
6a25fa42	233
5089a143 AZ	234	g_slist_free_full(conn_devices, (GDestroyNotify)sr_usb_dev_inst_free);
5089a143 AZ	235	libusb_free_device_list(devlist, 1);
6a25fa42	236
5089a143	237	return std_scan_complete(di, devices);
6a25fa42 AZ	238	}
	239
	240	static int dev_open(struct sr_dev_inst *sdi)
	241	{
5089a143 AZ	242	struct sr_usb_dev_inst *usb = sdi->conn;
5089a143 AZ	243	int ret;
6a25fa42	244
5089a143 AZ	245	ret = h4032l_dev_open(sdi);
	246	if (ret != SR_OK) {
	247	sr_err("Unable to open device.");
	248	return SR_ERR;
	249	}
6a25fa42	250
5089a143 AZ	251	ret = libusb_claim_interface(usb->devhdl, USB_INTERFACE);
	252	if (ret != 0) {
	253	switch (ret) {
	254	case LIBUSB_ERROR_BUSY:
	255	sr_err("Unable to claim USB interface. Another "
	256	"program or driver has already claimed it.");
	257	break;
	258	case LIBUSB_ERROR_NO_DEVICE:
	259	sr_err("Device has been disconnected.");
	260	break;
	261	default:
	262	sr_err("Unable to claim interface: %s.",
	263	libusb_error_name(ret));
	264	break;
	265	}
	266
	267	return SR_ERR;
	268	}
6a25fa42	269
7a7afc00 AV	270	/* Get FPGA version. */
	271	if ((ret = h4032l_get_fpga_version(sdi)) != SR_OK)
	272	return ret;
	273
6a25fa42 AZ	274	return SR_OK;
	275	}
	276
	277	static int dev_close(struct sr_dev_inst *sdi)
	278	{
5089a143	279	struct sr_usb_dev_inst *usb;
6a25fa42	280
5089a143	281	usb = sdi->conn;
6a25fa42	282
5089a143 AZ	283	if (!usb->devhdl)
5089a143 AZ	284	return SR_ERR_BUG;
6a25fa42	285
5089a143 AZ	286	sr_info("Closing device on %d.%d (logical) / %s (physical) interface %d.",
	287	usb->bus, usb->address, sdi->connection_id, USB_INTERFACE);
	288	libusb_release_interface(usb->devhdl, USB_INTERFACE);
	289	libusb_close(usb->devhdl);
	290	usb->devhdl = NULL;
6a25fa42 AZ	291
	292	return SR_OK;
	293	}
	294
	295	static int config_get(uint32_t key, GVariant **data,
	296	const struct sr_dev_inst sdi, const struct sr_channel_group cg)
	297	{
5089a143 AZ	298	struct dev_context *devc = sdi->priv;
5089a143 AZ	299	struct sr_usb_dev_inst *usb;
6a25fa42	300
6a25fa42	301	switch (key) {
caad0024	302	case SR_CONF_VOLTAGE_THRESHOLD:
2a801861 AV	303	if (cg) {
	304	if (!strcmp(cg->name, "A"))
	305	*data = std_gvar_tuple_double(
	306	devc->cur_threshold[0], devc->cur_threshold[0]);
	307	else if (!strcmp(cg->name, "B"))
	308	*data = std_gvar_tuple_double(
	309	devc->cur_threshold[1], devc->cur_threshold[1]);
	310	else
	311	return SR_ERR_CHANNEL_GROUP;
	312	}
caad0024	313	break;
5089a143 AZ	314	case SR_CONF_SAMPLERATE:
	315	*data = g_variant_new_uint64(samplerates_hw[devc->cmd_pkt.sample_rate]);
	316	break;
	317	case SR_CONF_CAPTURE_RATIO:
	318	*data = g_variant_new_uint64(devc->capture_ratio);
	319	break;
	320	case SR_CONF_LIMIT_SAMPLES:
	321	*data = g_variant_new_uint64(devc->cmd_pkt.sample_size);
	322	break;
	323	case SR_CONF_CONN:
	324	if (!sdi \|\| !(usb = sdi->conn))
	325	return SR_ERR_ARG;
	326	*data = g_variant_new_printf("%d.%d", usb->bus, usb->address);
	327	break;
6a25fa42 AZ	328	default:
	329	return SR_ERR_NA;
	330	}
	331
5089a143	332	return SR_OK;
6a25fa42 AZ	333	}
	334
	335	static int config_set(uint32_t key, GVariant *data,
	336	const struct sr_dev_inst sdi, const struct sr_channel_group cg)
	337	{
5089a143 AZ	338	struct dev_context *devc = sdi->priv;
5089a143 AZ	339	struct h4032l_cmd_pkt *cmd_pkt = &devc->cmd_pkt;
6a25fa42	340
6a25fa42	341	switch (key) {
5089a143 AZ	342	case SR_CONF_SAMPLERATE: {
	343	uint64_t sample_rate = g_variant_get_uint64(data);
	344	uint8_t i = 0;
	345	while (i < ARRAY_SIZE(samplerates_hw) && samplerates_hw[i] != sample_rate)
	346	i++;
	347
	348	if (i == ARRAY_SIZE(samplerates_hw) \|\| sample_rate == 0) {
4868f15a	349	sr_err("Invalid sample rate.");
5089a143 AZ	350	return SR_ERR_SAMPLERATE;
	351	}
	352	cmd_pkt->sample_rate = i;
28f2d07f	353	break;
5089a143	354	}
3dc976fe AV	355	case SR_CONF_CAPTURE_RATIO: {
	356	uint64_t capture_ratio = g_variant_get_uint64(data);
	357	if (capture_ratio > 99) {
	358	sr_err("Invalid capture ratio.");
	359	return SR_ERR;
	360	}
	361	devc->capture_ratio = capture_ratio;
	362	break;
	363	}
5089a143 AZ	364	case SR_CONF_LIMIT_SAMPLES: {
	365	uint64_t number_samples = g_variant_get_uint64(data);
	366	number_samples += 511;
	367	number_samples &= 0xfffffe00;
4b75f84c AV	368	if (number_samples < H4043L_NUM_SAMPLES_MIN \|\|
4b75f84c AV	369	number_samples > H4032L_NUM_SAMPLES_MAX) {
4868f15a UH	370	sr_err("Invalid sample range 2k...64M: %"
4868f15a UH	371	PRIu64 ".", number_samples);
5089a143 AZ	372	return SR_ERR;
	373	}
	374	cmd_pkt->sample_size = number_samples;
28f2d07f	375	break;
5089a143 AZ	376	}
5089a143 AZ	377	case SR_CONF_VOLTAGE_THRESHOLD: {
caad0024 AV	378	double low, high;
caad0024 AV	379	g_variant_get(data, "(dd)", &low, &high);
2a801861 AV	380	double threshold = (low + high) / 2.0;
	381	if (cg) {
	382	if (!strcmp(cg->name, "A"))
	383	devc->cur_threshold[0] = threshold;
	384	else if (!strcmp(cg->name, "B"))
	385	devc->cur_threshold[1] = threshold;
	386	else
	387	return SR_ERR_CHANNEL_GROUP;
	388	}
28f2d07f	389	break;
5089a143	390	}
28f2d07f AV	391	default:
28f2d07f AV	392	return SR_ERR_NA;
6a25fa42 AZ	393	}
6a25fa42 AZ	394
28f2d07f	395	return SR_OK;
6a25fa42 AZ	396	}
	397
	398	static int config_list(uint32_t key, GVariant **data,
	399	const struct sr_dev_inst sdi, const struct sr_channel_group cg)
	400	{
6a25fa42	401	switch (key) {
5089a143 AZ	402	case SR_CONF_SCAN_OPTIONS:
5089a143 AZ	403	case SR_CONF_DEVICE_OPTIONS:
2a801861 AV	404	if (cg) {
	405	*data = std_gvar_array_u32(ARRAY_AND_SIZE(devopts_cg));
	406	break;
	407	}
5089a143 AZ	408	return STD_CONFIG_LIST(key, data, sdi, cg, scanopts, drvopts, devopts);
	409	case SR_CONF_SAMPLERATE:
	410	*data = std_gvar_samplerates(ARRAY_AND_SIZE(samplerates));
	411	break;
	412	case SR_CONF_TRIGGER_MATCH:
	413	*data = std_gvar_array_i32(ARRAY_AND_SIZE(trigger_matches));
	414	break;
	415	case SR_CONF_VOLTAGE_THRESHOLD:
caad0024	416	*data = std_gvar_min_max_step_thresholds(-6.0, 6.0, 0.1);
5089a143	417	break;
4b75f84c AV	418	case SR_CONF_LIMIT_SAMPLES:
	419	*data = std_gvar_tuple_u64(H4043L_NUM_SAMPLES_MIN, H4032L_NUM_SAMPLES_MAX);
	420	break;
6a25fa42 AZ	421	default:
	422	return SR_ERR_NA;
	423	}
	424
5089a143	425	return SR_OK;
6a25fa42 AZ	426	}
6a25fa42 AZ	427
5089a143	428	static int dev_acquisition_start(const struct sr_dev_inst *sdi)
6a25fa42	429	{
5089a143 AZ	430	struct sr_dev_driver *di = sdi->driver;
	431	struct drv_context *drvc = di->context;
	432	struct dev_context *devc = sdi->priv;
	433	struct sr_trigger *trigger = sr_session_trigger_get(sdi->session);
	434	struct h4032l_cmd_pkt *cmd_pkt = &devc->cmd_pkt;
	435
28f2d07f	436	/* Initialize variables. */
a5b9880e	437	devc->acq_aborted = FALSE;
2958315d	438	devc->submitted_transfers = 0;
3dc976fe	439	devc->sent_samples = 0;
a5b9880e	440
5089a143 AZ	441	/* Calculate packet ratio. */
5089a143 AZ	442	cmd_pkt->pre_trigger_size = (cmd_pkt->sample_size * devc->capture_ratio) / 100;
3dc976fe	443	devc->trigger_pos = cmd_pkt->pre_trigger_size;
5089a143	444
caad0024	445	/* Set pwm channel values. */
2a801861 AV	446	devc->cmd_pkt.pwm_a = h4032l_voltage2pwm(devc->cur_threshold[0]);
2a801861 AV	447	devc->cmd_pkt.pwm_b = h4032l_voltage2pwm(devc->cur_threshold[1]);
caad0024	448
5089a143 AZ	449	cmd_pkt->trig_flags.enable_trigger1 = 0;
	450	cmd_pkt->trig_flags.enable_trigger2 = 0;
	451	cmd_pkt->trig_flags.trigger_and_logic = 0;
	452
	453	if (trigger && trigger->stages) {
	454	GSList *stages = trigger->stages;
	455	struct sr_trigger_stage *stage1 = stages->data;
	456	if (stages->next) {
4868f15a	457	sr_err("Only one trigger stage supported for now.");
5089a143 AZ	458	return SR_ERR;
	459	}
	460	cmd_pkt->trig_flags.enable_trigger1 = 1;
	461	cmd_pkt->trigger[0].flags.edge_type = H4032L_TRIGGER_EDGE_TYPE_DISABLED;
	462	cmd_pkt->trigger[0].flags.data_range_enabled = 0;
	463	cmd_pkt->trigger[0].flags.time_range_enabled = 0;
	464	cmd_pkt->trigger[0].flags.combined_enabled = 0;
	465	cmd_pkt->trigger[0].flags.data_range_type = H4032L_TRIGGER_DATA_RANGE_TYPE_MAX;
	466	cmd_pkt->trigger[0].data_range_mask = 0;
	467	cmd_pkt->trigger[0].data_range_max = 0;
	468
	469	/* Initialize range mask values. */
	470	uint32_t range_mask = 0;
	471	uint32_t range_value = 0;
	472
	473	GSList *channel = stage1->matches;
	474	while (channel) {
	475	struct sr_trigger_match *match = channel->data;
	476
	477	switch (match->match) {
	478	case SR_TRIGGER_ZERO:
	479	range_mask \|= (1 << match->channel->index);
	480	break;
	481	case SR_TRIGGER_ONE:
	482	range_mask \|= (1 << match->channel->index);
	483	range_value \|= (1 << match->channel->index);
	484	break;
	485	case SR_TRIGGER_RISING:
	486	if (cmd_pkt->trigger[0].flags.edge_type != H4032L_TRIGGER_EDGE_TYPE_DISABLED) {
4868f15a	487	sr_err("Only one trigger signal with fall/rising/edge allowed.");
5089a143 AZ	488	return SR_ERR;
	489	}
	490	cmd_pkt->trigger[0].flags.edge_type = H4032L_TRIGGER_EDGE_TYPE_RISE;
	491	cmd_pkt->trigger[0].flags.edge_signal = match->channel->index;
	492	break;
	493	case SR_TRIGGER_FALLING:
	494	if (cmd_pkt->trigger[0].flags.edge_type != H4032L_TRIGGER_EDGE_TYPE_DISABLED) {
4868f15a	495	sr_err("Only one trigger signal with fall/rising/edge allowed.");
5089a143 AZ	496	return SR_ERR;
	497	}
	498	cmd_pkt->trigger[0].flags.edge_type = H4032L_TRIGGER_EDGE_TYPE_FALL;
	499	cmd_pkt->trigger[0].flags.edge_signal = match->channel->index;
	500	break;
	501	case SR_TRIGGER_EDGE:
	502	if (cmd_pkt->trigger[0].flags.edge_type != H4032L_TRIGGER_EDGE_TYPE_DISABLED) {
4868f15a	503	sr_err("Only one trigger signal with fall/rising/edge allowed.");
5089a143 AZ	504	return SR_ERR;
	505	}
	506	cmd_pkt->trigger[0].flags.edge_type = H4032L_TRIGGER_EDGE_TYPE_TOGGLE;
	507	cmd_pkt->trigger[0].flags.edge_signal = match->channel->index;
	508	break;
	509	default:
4868f15a	510	sr_err("Unknown trigger value.");
5089a143 AZ	511	return SR_ERR;
	512	}
	513
	514	channel = channel->next;
	515	}
	516
	517	/* Compress range mask value and apply range settings. */
	518	if (range_mask) {
	519	cmd_pkt->trigger[0].flags.data_range_enabled = 1;
	520	cmd_pkt->trigger[0].data_range_mask \|= (range_mask);
	521
	522	uint32_t new_range_value = 0;
	523	uint32_t bit_mask = 1;
	524	while (range_mask) {
	525	if ((range_mask & 1) != 0) {
	526	new_range_value <<= 1;
	527	if ((range_value & 1) != 0)
	528	new_range_value \|= bit_mask;
	529	bit_mask <<= 1;
	530	}
	531	range_mask >>= 1;
	532	range_value >>= 1;
	533	}
	534	cmd_pkt->trigger[0].data_range_max \|= range_value;
	535	}
	536	}
6a25fa42	537
74c4c174	538	usb_source_add(sdi->session, drvc->sr_ctx, 1000,
5089a143	539	h4032l_receive_data, sdi->driver->context);
6a25fa42	540
5089a143 AZ	541	/* Start capturing. */
5089a143 AZ	542	return h4032l_start(sdi);
6a25fa42 AZ	543	}
6a25fa42 AZ	544
5089a143	545	static int dev_acquisition_stop(struct sr_dev_inst *sdi)
6a25fa42	546	{
2958315d AV	547	/* Stop capturing. */
2958315d AV	548	return h4032l_stop(sdi);
6a25fa42 AZ	549	}
	550
	551	SR_PRIV struct sr_dev_driver hantek_4032l_driver_info = {
	552	.name = "hantek-4032l",
5089a143	553	.longname = "Hantek 4032L",
6a25fa42	554	.api_version = 1,
5089a143 AZ	555	.init = std_init,
5089a143 AZ	556	.cleanup = std_cleanup,
6a25fa42	557	.scan = scan,
5089a143 AZ	558	.dev_list = std_dev_list,
5089a143 AZ	559	.dev_clear = std_dev_clear,
6a25fa42 AZ	560	.config_get = config_get,
	561	.config_set = config_set,
	562	.config_list = config_list,
	563	.dev_open = dev_open,
	564	.dev_close = dev_close,
	565	.dev_acquisition_start = dev_acquisition_start,
	566	.dev_acquisition_stop = dev_acquisition_stop,
	567	.context = NULL,
	568	};
5089a143	569	SR_REGISTER_DEV_DRIVER(hantek_4032l_driver_info);