[libsigrok.git] / src / hardware / hantek-4032l / api.c

/*
 * This file is part of the libsigrok project.
 *
 * Copyright (C) 2016 Andreas Zschunke <andreas.zschunke@gmx.net>
 * Copyright (C) 2017 Andrej Valek <andy@skyrain.eu>
 * Copyright (C) 2017 Uwe Hermann <uwe@hermann-uwe.de>
 *
 * This program is free software: you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation, either version 3 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#include <config.h>
#include "protocol.h"

#define USB_INTERFACE 0
#define NUM_CHANNELS 32

static const uint32_t scanopts[] = {
	SR_CONF_CONN,
};

static const uint32_t drvopts[] = {
	SR_CONF_LOGIC_ANALYZER,
};

static const uint32_t devopts[] = {
	SR_CONF_SAMPLERATE | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
	SR_CONF_CAPTURE_RATIO | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
	SR_CONF_LIMIT_SAMPLES | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
	SR_CONF_TRIGGER_MATCH | SR_CONF_LIST,
	SR_CONF_CONN | SR_CONF_GET,
	SR_CONF_EXTERNAL_CLOCK | SR_CONF_GET | SR_CONF_SET,
	SR_CONF_EXTERNAL_CLOCK_SOURCE | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
	SR_CONF_CLOCK_EDGE | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
};

static const uint32_t devopts_fpga_zero[] = {
	SR_CONF_SAMPLERATE | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
	SR_CONF_CAPTURE_RATIO | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
	SR_CONF_LIMIT_SAMPLES | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
	SR_CONF_TRIGGER_MATCH | SR_CONF_LIST,
	SR_CONF_CONN | SR_CONF_GET,
};

static const uint32_t devopts_cg[] = {
	SR_CONF_VOLTAGE_THRESHOLD | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
};

static const char *signal_edges[] = {
	[H4032L_CLOCK_EDGE_TYPE_RISE] = "rising",
	[H4032L_CLOCK_EDGE_TYPE_FALL] = "falling",
	[H4032L_CLOCK_EDGE_TYPE_BOTH] = "both",
};

static const char *ext_clock_sources[] = {
	[H4032L_EXT_CLOCK_SOURCE_CHANNEL_A] = "ACLK",
	[H4032L_EXT_CLOCK_SOURCE_CHANNEL_B] = "BCLK"
};

static const uint8_t ext_clock_edges[2][3] = {
	{
		H4032L_CLOCK_EDGE_TYPE_RISE_A,
		H4032L_CLOCK_EDGE_TYPE_FALL_A,
		H4032L_CLOCK_EDGE_TYPE_BOTH_A
	},
	{
		H4032L_CLOCK_EDGE_TYPE_RISE_B,
		H4032L_CLOCK_EDGE_TYPE_FALL_B,
		H4032L_CLOCK_EDGE_TYPE_BOTH_B
	}
};

static const int32_t trigger_matches[] = {
	SR_TRIGGER_ZERO,
	SR_TRIGGER_ONE,
	SR_TRIGGER_RISING,
	SR_TRIGGER_FALLING,
	SR_TRIGGER_EDGE,
};

static const uint64_t samplerates[] = {
	SR_KHZ(1),
	SR_KHZ(2),
	SR_KHZ(4),
	SR_KHZ(8),
	SR_KHZ(16),
	SR_HZ(31250),
	SR_HZ(62500),
	SR_KHZ(125),
	SR_KHZ(250),
	SR_KHZ(500),
	SR_KHZ(625),
	SR_HZ(781250),
	SR_MHZ(1),
	SR_KHZ(1250),
	SR_HZ(1562500),
	SR_MHZ(2),
	SR_KHZ(2500),
	SR_KHZ(3125),
	SR_MHZ(4),
	SR_MHZ(5),
	SR_KHZ(6250),
	SR_MHZ(10),
	SR_KHZ(12500),
	SR_MHZ(20),
	SR_MHZ(25),
	SR_MHZ(40),
	SR_MHZ(50),
	SR_MHZ(80),
	SR_MHZ(100),
	SR_MHZ(160),
	SR_MHZ(200),
	SR_MHZ(320),
	SR_MHZ(400),
};

static const uint64_t samplerates_hw[] = {
	SR_MHZ(100),
	SR_MHZ(50),
	SR_MHZ(25),
	SR_KHZ(12500),
	SR_KHZ(6250),
	SR_KHZ(3125),
	SR_HZ(1562500),
	SR_HZ(781250),
	SR_MHZ(80),
	SR_MHZ(40),
	SR_MHZ(20),
	SR_MHZ(10),
	SR_MHZ(5),
	SR_KHZ(2500),
	SR_KHZ(1250),
	SR_KHZ(625),
	SR_MHZ(4),
	SR_MHZ(2),
	SR_MHZ(1),
	SR_KHZ(500),
	SR_KHZ(250),
	SR_KHZ(125),
	SR_HZ(62500),
	SR_HZ(31250),
	SR_KHZ(16),
	SR_KHZ(8),
	SR_KHZ(4),
	SR_KHZ(2),
	SR_KHZ(1),
	0,
	0,
	0,
	SR_MHZ(200),
	SR_MHZ(160),
	SR_MHZ(400),
	SR_MHZ(320),
};

SR_PRIV struct sr_dev_driver hantek_4032l_driver_info;

static GSList *scan(struct sr_dev_driver *di, GSList *options)
{
	struct drv_context *drvc = di->context;
	GSList *l, *devices, *conn_devices;
	libusb_device **devlist;
	struct libusb_device_descriptor des;
	const char *conn;
	int i;
	char connection_id[64];
	struct sr_channel_group *cg;
	struct sr_dev_inst *sdi;
	struct sr_channel *ch;

	devices = NULL;
	conn_devices = NULL;
	drvc->instances = NULL;
	conn = NULL;

	for (l = options; l; l = l->next) {
		struct sr_config *src = l->data;
		if (src->key == SR_CONF_CONN) {
			conn = g_variant_get_string(src->data, NULL);
			break;
		}
	}

	if (conn)
		conn_devices = sr_usb_find(drvc->sr_ctx->libusb_ctx, conn);
	else
		conn_devices = NULL;

	libusb_get_device_list(drvc->sr_ctx->libusb_ctx, &devlist);
	for (i = 0; devlist[i]; i++) {
		if (conn) {
			struct sr_usb_dev_inst *usb = NULL;
			for (l = conn_devices; l; l = l->next) {
				usb = l->data;
				if (usb->bus == libusb_get_bus_number(devlist[i]) &&
				    usb->address == libusb_get_device_address(devlist[i]))
					break;
			}
			if (!l)
				/* This device matched none of the ones that
				 * matched the conn specification. */
				continue;
		}

		libusb_get_device_descriptor(devlist[i], &des);

		if (des.idVendor != H4032L_USB_VENDOR ||
		    des.idProduct != H4032L_USB_PRODUCT)
			continue;

		if (usb_get_port_path(devlist[i], connection_id, sizeof(connection_id)) < 0)
			continue;

		sdi = g_malloc0(sizeof(struct sr_dev_inst));
		sdi->driver = &hantek_4032l_driver_info;
		sdi->vendor = g_strdup("Hantek");
		sdi->model = g_strdup("4032L");
		sdi->connection_id = g_strdup(connection_id);

		struct sr_channel_group *channel_groups[2];
		for (int j = 0; j < 2; j++) {
			cg = g_malloc0(sizeof(struct sr_channel_group));
			cg->name = g_strdup_printf("%c", 'A' + j);
			channel_groups[j] = cg;
			sdi->channel_groups = g_slist_append(sdi->channel_groups, cg);
		}

		/* Assemble channel list and add channel to channel groups. */
		for (int j = 0; j < NUM_CHANNELS; j++) {
			char channel_name[4];
			sprintf(channel_name, "%c%d", 'A' + (j & 1), j / 2);
			ch = sr_channel_new(sdi, j, SR_CHANNEL_LOGIC, TRUE, channel_name);
			cg = channel_groups[j & 1];
			cg->channels = g_slist_append(cg->channels, ch);
		}

		struct dev_context *devc = g_malloc0(sizeof(struct dev_context));

		/* Initialize command packet. */
		devc->cmd_pkt.magic = H4032L_CMD_PKT_MAGIC;
		devc->cmd_pkt.sample_size = 16384;
		devc->sample_rate = 0;

		devc->status = H4032L_STATUS_IDLE;

		devc->capture_ratio = 5;
		devc->external_clock = FALSE;
		devc->clock_edge = H4032L_CLOCK_EDGE_TYPE_RISE;

		devc->cur_threshold[0] = 2.5;
		devc->cur_threshold[1] = 2.5;

		sdi->priv = devc;
		devices = g_slist_append(devices, sdi);

		sdi->status = SR_ST_INACTIVE;
		sdi->inst_type = SR_INST_USB;
		sdi->conn = sr_usb_dev_inst_new(
			libusb_get_bus_number(devlist[i]),
			libusb_get_device_address(devlist[i]), NULL);
	}

	g_slist_free_full(conn_devices, (GDestroyNotify)sr_usb_dev_inst_free);
	libusb_free_device_list(devlist, 1);

	return std_scan_complete(di, devices);
}

static int dev_open(struct sr_dev_inst *sdi)
{
	struct sr_usb_dev_inst *usb = sdi->conn;
	int ret;

	ret = h4032l_dev_open(sdi);
	if (ret != SR_OK) {
		sr_err("Unable to open device.");
		return SR_ERR;
	}

	ret = libusb_claim_interface(usb->devhdl, USB_INTERFACE);
	if (ret != 0) {
		switch (ret) {
		case LIBUSB_ERROR_BUSY:
			sr_err("Unable to claim USB interface. Another "
			       "program or driver has already claimed it.");
			break;
		case LIBUSB_ERROR_NO_DEVICE:
			sr_err("Device has been disconnected.");
			break;
		default:
			sr_err("Unable to claim interface: %s.",
			       libusb_error_name(ret));
			break;
		}

		return SR_ERR;
	}

	/* Get FPGA version. */
	if ((ret = h4032l_get_fpga_version(sdi)) != SR_OK)
		return ret;

	return SR_OK;
}

static int dev_close(struct sr_dev_inst *sdi)
{
	struct sr_usb_dev_inst *usb;

	usb = sdi->conn;

	if (!usb->devhdl)
		return SR_ERR_BUG;

	sr_info("Closing device on %d.%d (logical) / %s (physical) interface %d.",
		usb->bus, usb->address, sdi->connection_id, USB_INTERFACE);
	libusb_release_interface(usb->devhdl, USB_INTERFACE);
	libusb_close(usb->devhdl);
	usb->devhdl = NULL;

	return SR_OK;
}

static int config_get(uint32_t key, GVariant **data,
	const struct sr_dev_inst *sdi, const struct sr_channel_group *cg)
{
	struct dev_context *devc = sdi->priv;
	struct sr_usb_dev_inst *usb;
	unsigned int idx;

	switch (key) {
	case SR_CONF_VOLTAGE_THRESHOLD:
		if (cg) {
			if (!strcmp(cg->name, "A"))
				*data = std_gvar_tuple_double(
					devc->cur_threshold[0], devc->cur_threshold[0]);
			else if (!strcmp(cg->name, "B"))
				*data = std_gvar_tuple_double(
					devc->cur_threshold[1], devc->cur_threshold[1]);
			else
				return SR_ERR_CHANNEL_GROUP;
		}
		break;
	case SR_CONF_SAMPLERATE:
		*data = g_variant_new_uint64(samplerates_hw[devc->sample_rate]);
		break;
	case SR_CONF_CAPTURE_RATIO:
		*data = g_variant_new_uint64(devc->capture_ratio);
		break;
	case SR_CONF_LIMIT_SAMPLES:
		*data = g_variant_new_uint64(devc->cmd_pkt.sample_size);
		break;
	case SR_CONF_EXTERNAL_CLOCK:
		*data = g_variant_new_boolean(devc->external_clock);
		break;
	case SR_CONF_EXTERNAL_CLOCK_SOURCE:
		idx = devc->external_clock_source;
		if (idx >= ARRAY_SIZE(ext_clock_sources))
			return SR_ERR_BUG;
		*data = g_variant_new_string(ext_clock_sources[idx]);
		break;
	case SR_CONF_CONN:
		if (!sdi || !(usb = sdi->conn))
			return SR_ERR_ARG;
		*data = g_variant_new_printf("%d.%d", usb->bus, usb->address);
		break;
	case SR_CONF_CLOCK_EDGE:
		idx = devc->clock_edge;
		if (idx >= ARRAY_SIZE(signal_edges))
			return SR_ERR_BUG;
		*data = g_variant_new_string(signal_edges[idx]);
		break;
	default:
		return SR_ERR_NA;
	}

	return SR_OK;
}

static int config_set(uint32_t key, GVariant *data,
	const struct sr_dev_inst *sdi, const struct sr_channel_group *cg)
{
	struct dev_context *devc = sdi->priv;
	struct h4032l_cmd_pkt *cmd_pkt = &devc->cmd_pkt;
	int idx;

	switch (key) {
	case SR_CONF_SAMPLERATE: {
			uint64_t sample_rate = g_variant_get_uint64(data);
			uint8_t i = 0;
			while (i < ARRAY_SIZE(samplerates_hw) && samplerates_hw[i] != sample_rate)
				i++;

			if (i == ARRAY_SIZE(samplerates_hw) || sample_rate == 0) {
				sr_err("Invalid sample rate.");
				return SR_ERR_SAMPLERATE;
			}
			devc->sample_rate = i;
			break;
		}
	case SR_CONF_CAPTURE_RATIO: {
			uint64_t capture_ratio = g_variant_get_uint64(data);
			if (capture_ratio > 99) {
				sr_err("Invalid capture ratio.");
				return SR_ERR;
			}
			devc->capture_ratio = capture_ratio;
			break;
		}
	case SR_CONF_LIMIT_SAMPLES: {
			uint64_t number_samples = g_variant_get_uint64(data);
			number_samples += 511;
			number_samples &= 0xfffffe00;
			if (number_samples < H4043L_NUM_SAMPLES_MIN ||
			    number_samples > H4032L_NUM_SAMPLES_MAX) {
				sr_err("Invalid sample range 2k...64M: %"
				       PRIu64 ".", number_samples);
				return SR_ERR;
			}
			cmd_pkt->sample_size = number_samples;
			break;
		}
	case SR_CONF_VOLTAGE_THRESHOLD: {
			double low, high;
			g_variant_get(data, "(dd)", &low, &high);
			double threshold = (low + high) / 2.0;
			if (cg) {
				if (!strcmp(cg->name, "A"))
					devc->cur_threshold[0] = threshold;
				else if (!strcmp(cg->name, "B"))
					devc->cur_threshold[1] = threshold;
				else
					return SR_ERR_CHANNEL_GROUP;
			}
			break;
		}
	case SR_CONF_EXTERNAL_CLOCK:
		devc->external_clock = g_variant_get_boolean(data);
		break;
	case SR_CONF_EXTERNAL_CLOCK_SOURCE:
		if ((idx = std_str_idx(data, ARRAY_AND_SIZE(ext_clock_sources))) < 0)
			return SR_ERR_ARG;
		devc->external_clock_source = idx;
		break;
	case SR_CONF_CLOCK_EDGE:
		if ((idx = std_str_idx(data, ARRAY_AND_SIZE(signal_edges))) < 0)
			return SR_ERR_ARG;
		devc->clock_edge = idx;
		break;
	default:
		return SR_ERR_NA;
	}

	return SR_OK;
}

static int config_list(uint32_t key, GVariant **data,
	const struct sr_dev_inst *sdi, const struct sr_channel_group *cg)
{

	struct dev_context *devc = (sdi) ? sdi->priv : NULL;

	switch (key) {
	case SR_CONF_SCAN_OPTIONS:
	case SR_CONF_DEVICE_OPTIONS:
		if (cg) {
			*data = std_gvar_array_u32(ARRAY_AND_SIZE(devopts_cg));
			break;
		}
		/* Disable external clock and edges for FPGA version 0. */
		if (devc && (!devc->fpga_version))
			return STD_CONFIG_LIST(key, data, sdi, cg, scanopts, drvopts, devopts_fpga_zero);
		return STD_CONFIG_LIST(key, data, sdi, cg, scanopts, drvopts, devopts);
	case SR_CONF_SAMPLERATE:
		*data = std_gvar_samplerates(ARRAY_AND_SIZE(samplerates));
		break;
	case SR_CONF_TRIGGER_MATCH:
		*data = std_gvar_array_i32(ARRAY_AND_SIZE(trigger_matches));
		break;
	case SR_CONF_VOLTAGE_THRESHOLD:
		*data = std_gvar_min_max_step_thresholds(-6.0, 6.0, 0.1);
		break;
	case SR_CONF_LIMIT_SAMPLES:
		*data = std_gvar_tuple_u64(H4043L_NUM_SAMPLES_MIN, H4032L_NUM_SAMPLES_MAX);
		break;
	case SR_CONF_CLOCK_EDGE:
		*data = g_variant_new_strv(ARRAY_AND_SIZE(signal_edges));
		break;
	case SR_CONF_EXTERNAL_CLOCK_SOURCE:
		*data = g_variant_new_strv(ARRAY_AND_SIZE(ext_clock_sources));
		break;
	default:
		return SR_ERR_NA;
	}

	return SR_OK;
}

static int dev_acquisition_start(const struct sr_dev_inst *sdi)
{
	struct sr_dev_driver *di = sdi->driver;
	struct drv_context *drvc = di->context;
	struct dev_context *devc = sdi->priv;
	struct sr_trigger *trigger = sr_session_trigger_get(sdi->session);
	struct h4032l_cmd_pkt *cmd_pkt = &devc->cmd_pkt;

	/* Initialize variables. */
	devc->acq_aborted = FALSE;
	devc->submitted_transfers = 0;
	devc->sent_samples = 0;

	/* Calculate packet ratio. */
	cmd_pkt->pre_trigger_size = (cmd_pkt->sample_size * devc->capture_ratio) / 100;
	devc->trigger_pos = cmd_pkt->pre_trigger_size;

	/* Set clock edge, when external clock is enabled. */
	if (devc->external_clock)
		cmd_pkt->sample_rate = ext_clock_edges[devc->external_clock_source][devc->clock_edge];
	else
		cmd_pkt->sample_rate = devc->sample_rate;

	/* Set pwm channel values. */
	devc->cmd_pkt.pwm_a = h4032l_voltage2pwm(devc->cur_threshold[0]);
	devc->cmd_pkt.pwm_b = h4032l_voltage2pwm(devc->cur_threshold[1]);

	cmd_pkt->trig_flags.enable_trigger1 = 0;
	cmd_pkt->trig_flags.enable_trigger2 = 0;
	cmd_pkt->trig_flags.trigger_and_logic = 0;

	if (trigger && trigger->stages) {
		GSList *stages = trigger->stages;
		struct sr_trigger_stage *stage1 = stages->data;
		if (stages->next) {
			sr_err("Only one trigger stage supported for now.");
			return SR_ERR;
		}
		cmd_pkt->trig_flags.enable_trigger1 = 1;
		cmd_pkt->trigger[0].flags.edge_type = H4032L_TRIGGER_EDGE_TYPE_DISABLED;
		cmd_pkt->trigger[0].flags.data_range_enabled = 0;
		cmd_pkt->trigger[0].flags.time_range_enabled = 0;
		cmd_pkt->trigger[0].flags.combined_enabled = 0;
		cmd_pkt->trigger[0].flags.data_range_type = H4032L_TRIGGER_DATA_RANGE_TYPE_MAX;
		cmd_pkt->trigger[0].data_range_mask = 0;
		cmd_pkt->trigger[0].data_range_max = 0;

		/* Initialize range mask values. */
		uint32_t range_mask = 0;
		uint32_t range_value = 0;

		GSList *channel = stage1->matches;
		while (channel) {
			struct sr_trigger_match *match = channel->data;

			switch (match->match) {
			case SR_TRIGGER_ZERO:
				range_mask |= (1 << match->channel->index);
				break;
			case SR_TRIGGER_ONE:
				range_mask |= (1 << match->channel->index);
				range_value |= (1 << match->channel->index);
				break;
			case SR_TRIGGER_RISING:
				if (cmd_pkt->trigger[0].flags.edge_type != H4032L_TRIGGER_EDGE_TYPE_DISABLED) {
					sr_err("Only one trigger signal with fall/rising/edge allowed.");
					return SR_ERR;
				}
				cmd_pkt->trigger[0].flags.edge_type = H4032L_TRIGGER_EDGE_TYPE_RISE;
				cmd_pkt->trigger[0].flags.edge_signal = match->channel->index;
				break;
			case SR_TRIGGER_FALLING:
				if (cmd_pkt->trigger[0].flags.edge_type != H4032L_TRIGGER_EDGE_TYPE_DISABLED) {
					sr_err("Only one trigger signal with fall/rising/edge allowed.");
					return SR_ERR;
				}
				cmd_pkt->trigger[0].flags.edge_type = H4032L_TRIGGER_EDGE_TYPE_FALL;
				cmd_pkt->trigger[0].flags.edge_signal = match->channel->index;
				break;
			case SR_TRIGGER_EDGE:
				if (cmd_pkt->trigger[0].flags.edge_type != H4032L_TRIGGER_EDGE_TYPE_DISABLED) {
					sr_err("Only one trigger signal with fall/rising/edge allowed.");
					return SR_ERR;
				}
				cmd_pkt->trigger[0].flags.edge_type = H4032L_TRIGGER_EDGE_TYPE_TOGGLE;
				cmd_pkt->trigger[0].flags.edge_signal = match->channel->index;
				break;
			default:
				sr_err("Unknown trigger value.");
				return SR_ERR;
			}

			channel = channel->next;
		}

		/* Compress range mask value and apply range settings. */
		if (range_mask) {
			cmd_pkt->trigger[0].flags.data_range_enabled = 1;
			cmd_pkt->trigger[0].data_range_mask |= (range_mask);

			uint32_t new_range_value = 0;
			uint32_t bit_mask = 1;
			while (range_mask) {
				if ((range_mask & 1) != 0) {
					new_range_value <<= 1;
					if ((range_value & 1) != 0)
						new_range_value |= bit_mask;
					bit_mask <<= 1;
				}
				range_mask >>= 1;
				range_value >>= 1;
			}
			cmd_pkt->trigger[0].data_range_max |= range_value;
		}
	}

	usb_source_add(sdi->session, drvc->sr_ctx, 1000,
		h4032l_receive_data, sdi->driver->context);

	/* Start capturing. */
	return h4032l_start(sdi);
}

static int dev_acquisition_stop(struct sr_dev_inst *sdi)
{
	/* Stop capturing. */
	return h4032l_stop(sdi);
}

SR_PRIV struct sr_dev_driver hantek_4032l_driver_info = {
	.name = "hantek-4032l",
	.longname = "Hantek 4032L",
	.api_version = 1,
	.init = std_init,
	.cleanup = std_cleanup,
	.scan = scan,
	.dev_list = std_dev_list,
	.dev_clear = std_dev_clear,
	.config_get = config_get,
	.config_set = config_set,
	.config_list = config_list,
	.dev_open = dev_open,
	.dev_close = dev_close,
	.dev_acquisition_start = dev_acquisition_start,
	.dev_acquisition_stop = dev_acquisition_stop,
	.context = NULL,
};
SR_REGISTER_DEV_DRIVER(hantek_4032l_driver_info);
Commit	Line	Data
6a25fa42 AZ	1	/*
	2	* This file is part of the libsigrok project.
	3	*
5089a143 AZ	4	* Copyright (C) 2016 Andreas Zschunke <andreas.zschunke@gmx.net>
	5	* Copyright (C) 2017 Andrej Valek <andy@skyrain.eu>
	6	* Copyright (C) 2017 Uwe Hermann <uwe@hermann-uwe.de>
6a25fa42 AZ	7	*
	8	* This program is free software: you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License as published by
	10	* the Free Software Foundation, either version 3 of the License, or
	11	* (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program. If not, see <http://www.gnu.org/licenses/>.
	20	*/
	21
	22	#include <config.h>
	23	#include "protocol.h"
	24
5089a143 AZ	25	#define USB_INTERFACE 0
5089a143 AZ	26	#define NUM_CHANNELS 32
6a25fa42	27
5089a143 AZ	28	static const uint32_t scanopts[] = {
	29	SR_CONF_CONN,
	30	};
	31
	32	static const uint32_t drvopts[] = {
	33	SR_CONF_LOGIC_ANALYZER,
	34	};
	35
	36	static const uint32_t devopts[] = {
	37	SR_CONF_SAMPLERATE \| SR_CONF_GET \| SR_CONF_SET \| SR_CONF_LIST,
3dc976fe	38	SR_CONF_CAPTURE_RATIO \| SR_CONF_GET \| SR_CONF_SET \| SR_CONF_LIST,
4b75f84c	39	SR_CONF_LIMIT_SAMPLES \| SR_CONF_GET \| SR_CONF_SET \| SR_CONF_LIST,
5089a143 AZ	40	SR_CONF_TRIGGER_MATCH \| SR_CONF_LIST,
5089a143 AZ	41	SR_CONF_CONN \| SR_CONF_GET,
f49065c6 AV	42	SR_CONF_EXTERNAL_CLOCK \| SR_CONF_GET \| SR_CONF_SET,
	43	SR_CONF_EXTERNAL_CLOCK_SOURCE \| SR_CONF_GET \| SR_CONF_SET \| SR_CONF_LIST,
	44	SR_CONF_CLOCK_EDGE \| SR_CONF_GET \| SR_CONF_SET \| SR_CONF_LIST,
	45	};
	46
	47	static const uint32_t devopts_fpga_zero[] = {
	48	SR_CONF_SAMPLERATE \| SR_CONF_GET \| SR_CONF_SET \| SR_CONF_LIST,
	49	SR_CONF_CAPTURE_RATIO \| SR_CONF_GET \| SR_CONF_SET \| SR_CONF_LIST,
	50	SR_CONF_LIMIT_SAMPLES \| SR_CONF_GET \| SR_CONF_SET \| SR_CONF_LIST,
	51	SR_CONF_TRIGGER_MATCH \| SR_CONF_LIST,
	52	SR_CONF_CONN \| SR_CONF_GET,
2a801861 AV	53	};
	54
	55	static const uint32_t devopts_cg[] = {
caad0024	56	SR_CONF_VOLTAGE_THRESHOLD \| SR_CONF_GET \| SR_CONF_SET \| SR_CONF_LIST,
5089a143 AZ	57	};
5089a143 AZ	58
f49065c6 AV	59	static const char *signal_edges[] = {
	60	[H4032L_CLOCK_EDGE_TYPE_RISE] = "rising",
	61	[H4032L_CLOCK_EDGE_TYPE_FALL] = "falling",
	62	[H4032L_CLOCK_EDGE_TYPE_BOTH] = "both",
	63	};
	64
	65	static const char *ext_clock_sources[] = {
	66	[H4032L_EXT_CLOCK_SOURCE_CHANNEL_A] = "ACLK",
	67	[H4032L_EXT_CLOCK_SOURCE_CHANNEL_B] = "BCLK"
	68	};
	69
	70	static const uint8_t ext_clock_edges[2][3] = {
	71	{
	72	H4032L_CLOCK_EDGE_TYPE_RISE_A,
	73	H4032L_CLOCK_EDGE_TYPE_FALL_A,
	74	H4032L_CLOCK_EDGE_TYPE_BOTH_A
	75	},
	76	{
	77	H4032L_CLOCK_EDGE_TYPE_RISE_B,
	78	H4032L_CLOCK_EDGE_TYPE_FALL_B,
	79	H4032L_CLOCK_EDGE_TYPE_BOTH_B
	80	}
	81	};
	82
5089a143 AZ	83	static const int32_t trigger_matches[] = {
	84	SR_TRIGGER_ZERO,
	85	SR_TRIGGER_ONE,
	86	SR_TRIGGER_RISING,
	87	SR_TRIGGER_FALLING,
	88	SR_TRIGGER_EDGE,
	89	};
	90
	91	static const uint64_t samplerates[] = {
	92	SR_KHZ(1),
	93	SR_KHZ(2),
	94	SR_KHZ(4),
	95	SR_KHZ(8),
	96	SR_KHZ(16),
	97	SR_HZ(31250),
	98	SR_HZ(62500),
	99	SR_KHZ(125),
	100	SR_KHZ(250),
	101	SR_KHZ(500),
	102	SR_KHZ(625),
	103	SR_HZ(781250),
	104	SR_MHZ(1),
	105	SR_KHZ(1250),
	106	SR_HZ(1562500),
	107	SR_MHZ(2),
	108	SR_KHZ(2500),
	109	SR_KHZ(3125),
	110	SR_MHZ(4),
	111	SR_MHZ(5),
	112	SR_KHZ(6250),
	113	SR_MHZ(10),
	114	SR_KHZ(12500),
	115	SR_MHZ(20),
	116	SR_MHZ(25),
	117	SR_MHZ(40),
	118	SR_MHZ(50),
	119	SR_MHZ(80),
	120	SR_MHZ(100),
	121	SR_MHZ(160),
	122	SR_MHZ(200),
	123	SR_MHZ(320),
	124	SR_MHZ(400),
	125	};
	126
	127	static const uint64_t samplerates_hw[] = {
	128	SR_MHZ(100),
	129	SR_MHZ(50),
	130	SR_MHZ(25),
	131	SR_KHZ(12500),
	132	SR_KHZ(6250),
	133	SR_KHZ(3125),
	134	SR_HZ(1562500),
	135	SR_HZ(781250),
	136	SR_MHZ(80),
	137	SR_MHZ(40),
	138	SR_MHZ(20),
	139	SR_MHZ(10),
	140	SR_MHZ(5),
	141	SR_KHZ(2500),
	142	SR_KHZ(1250),
	143	SR_KHZ(625),
	144	SR_MHZ(4),
	145	SR_MHZ(2),
	146	SR_MHZ(1),
147	SR_KHZ(500),
148	SR_KHZ(250),
149	SR_KHZ(125),
150	SR_HZ(62500),
151	SR_HZ(31250),
152	SR_KHZ(16),
153	SR_KHZ(8),
154	SR_KHZ(4),
155	SR_KHZ(2),
156	SR_KHZ(1),
157	0,
158	0,
159	0,
160	SR_MHZ(200),
161	SR_MHZ(160),
162	SR_MHZ(400),
163	SR_MHZ(320),
164	};
165
166	SR_PRIV struct sr_dev_driver hantek_4032l_driver_info;
6a25fa42 AZ	167
	168	static GSList scan(struct sr_dev_driver di, GSList *options)
	169	{
5089a143 AZ	170	struct drv_context *drvc = di->context;
	171	GSList l, devices, *conn_devices;
	172	libusb_device **devlist;
	173	struct libusb_device_descriptor des;
	174	const char *conn;
	175	int i;
	176	char connection_id[64];
	177	struct sr_channel_group *cg;
	178	struct sr_dev_inst *sdi;
	179	struct sr_channel *ch;
6a25fa42 AZ	180
6a25fa42 AZ	181	devices = NULL;
5089a143	182	conn_devices = NULL;
6a25fa42	183	drvc->instances = NULL;
5089a143 AZ	184	conn = NULL;
	185
	186	for (l = options; l; l = l->next) {
	187	struct sr_config *src = l->data;
	188	if (src->key == SR_CONF_CONN) {
	189	conn = g_variant_get_string(src->data, NULL);
	190	break;
	191	}
	192	}
6a25fa42	193
5089a143 AZ	194	if (conn)
	195	conn_devices = sr_usb_find(drvc->sr_ctx->libusb_ctx, conn);
	196	else
	197	conn_devices = NULL;
	198
	199	libusb_get_device_list(drvc->sr_ctx->libusb_ctx, &devlist);
	200	for (i = 0; devlist[i]; i++) {
	201	if (conn) {
	202	struct sr_usb_dev_inst *usb = NULL;
	203	for (l = conn_devices; l; l = l->next) {
	204	usb = l->data;
28f2d07f AV	205	if (usb->bus == libusb_get_bus_number(devlist[i]) &&
28f2d07f AV	206	usb->address == libusb_get_device_address(devlist[i]))
5089a143 AZ	207	break;
	208	}
	209	if (!l)
	210	/* This device matched none of the ones that
	211	* matched the conn specification. */
	212	continue;
	213	}
	214
	215	libusb_get_device_descriptor(devlist[i], &des);
	216
	217	if (des.idVendor != H4032L_USB_VENDOR \|\|
	218	des.idProduct != H4032L_USB_PRODUCT)
	219	continue;
	220
6c1a76d1 RT	221	if (usb_get_port_path(devlist[i], connection_id, sizeof(connection_id)) < 0)
6c1a76d1 RT	222	continue;
5089a143 AZ	223
	224	sdi = g_malloc0(sizeof(struct sr_dev_inst));
	225	sdi->driver = &hantek_4032l_driver_info;
	226	sdi->vendor = g_strdup("Hantek");
	227	sdi->model = g_strdup("4032L");
	228	sdi->connection_id = g_strdup(connection_id);
	229
	230	struct sr_channel_group *channel_groups[2];
	231	for (int j = 0; j < 2; j++) {
	232	cg = g_malloc0(sizeof(struct sr_channel_group));
	233	cg->name = g_strdup_printf("%c", 'A' + j);
	234	channel_groups[j] = cg;
	235	sdi->channel_groups = g_slist_append(sdi->channel_groups, cg);
	236	}
	237
	238	/* Assemble channel list and add channel to channel groups. */
	239	for (int j = 0; j < NUM_CHANNELS; j++) {
	240	char channel_name[4];
	241	sprintf(channel_name, "%c%d", 'A' + (j & 1), j / 2);
	242	ch = sr_channel_new(sdi, j, SR_CHANNEL_LOGIC, TRUE, channel_name);
	243	cg = channel_groups[j & 1];
	244	cg->channels = g_slist_append(cg->channels, ch);
	245	}
	246
	247	struct dev_context *devc = g_malloc0(sizeof(struct dev_context));
	248
	249	/* Initialize command packet. */
	250	devc->cmd_pkt.magic = H4032L_CMD_PKT_MAGIC;
5089a143	251	devc->cmd_pkt.sample_size = 16384;
f49065c6	252	devc->sample_rate = 0;
5089a143 AZ	253
	254	devc->status = H4032L_STATUS_IDLE;
	255
	256	devc->capture_ratio = 5;
f49065c6 AV	257	devc->external_clock = FALSE;
	258	devc->clock_edge = H4032L_CLOCK_EDGE_TYPE_RISE;
	259
2a801861 AV	260	devc->cur_threshold[0] = 2.5;
2a801861 AV	261	devc->cur_threshold[1] = 2.5;
5089a143	262
5089a143 AZ	263	sdi->priv = devc;
	264	devices = g_slist_append(devices, sdi);
	265
	266	sdi->status = SR_ST_INACTIVE;
	267	sdi->inst_type = SR_INST_USB;
	268	sdi->conn = sr_usb_dev_inst_new(
	269	libusb_get_bus_number(devlist[i]),
	270	libusb_get_device_address(devlist[i]), NULL);
	271	}
6a25fa42	272
5089a143 AZ	273	g_slist_free_full(conn_devices, (GDestroyNotify)sr_usb_dev_inst_free);
5089a143 AZ	274	libusb_free_device_list(devlist, 1);
6a25fa42	275
5089a143	276	return std_scan_complete(di, devices);
6a25fa42 AZ	277	}
	278
	279	static int dev_open(struct sr_dev_inst *sdi)
	280	{
5089a143 AZ	281	struct sr_usb_dev_inst *usb = sdi->conn;
5089a143 AZ	282	int ret;
6a25fa42	283
5089a143 AZ	284	ret = h4032l_dev_open(sdi);
	285	if (ret != SR_OK) {
	286	sr_err("Unable to open device.");
	287	return SR_ERR;
	288	}
6a25fa42	289
5089a143 AZ	290	ret = libusb_claim_interface(usb->devhdl, USB_INTERFACE);
	291	if (ret != 0) {
	292	switch (ret) {
	293	case LIBUSB_ERROR_BUSY:
	294	sr_err("Unable to claim USB interface. Another "
	295	"program or driver has already claimed it.");
	296	break;
	297	case LIBUSB_ERROR_NO_DEVICE:
	298	sr_err("Device has been disconnected.");
	299	break;
	300	default:
	301	sr_err("Unable to claim interface: %s.",
	302	libusb_error_name(ret));
	303	break;
	304	}
	305
	306	return SR_ERR;
	307	}
6a25fa42	308
7a7afc00 AV	309	/* Get FPGA version. */
	310	if ((ret = h4032l_get_fpga_version(sdi)) != SR_OK)
	311	return ret;
	312
6a25fa42 AZ	313	return SR_OK;
	314	}
	315
	316	static int dev_close(struct sr_dev_inst *sdi)
	317	{
5089a143	318	struct sr_usb_dev_inst *usb;
6a25fa42	319
5089a143	320	usb = sdi->conn;
6a25fa42	321
5089a143 AZ	322	if (!usb->devhdl)
5089a143 AZ	323	return SR_ERR_BUG;
6a25fa42	324
5089a143 AZ	325	sr_info("Closing device on %d.%d (logical) / %s (physical) interface %d.",
	326	usb->bus, usb->address, sdi->connection_id, USB_INTERFACE);
	327	libusb_release_interface(usb->devhdl, USB_INTERFACE);
	328	libusb_close(usb->devhdl);
	329	usb->devhdl = NULL;
6a25fa42 AZ	330
	331	return SR_OK;
	332	}
	333
	334	static int config_get(uint32_t key, GVariant **data,
	335	const struct sr_dev_inst sdi, const struct sr_channel_group cg)
	336	{
5089a143 AZ	337	struct dev_context *devc = sdi->priv;
5089a143 AZ	338	struct sr_usb_dev_inst *usb;
f49065c6	339	unsigned int idx;
6a25fa42	340
6a25fa42	341	switch (key) {
caad0024	342	case SR_CONF_VOLTAGE_THRESHOLD:
2a801861 AV	343	if (cg) {
	344	if (!strcmp(cg->name, "A"))
	345	*data = std_gvar_tuple_double(
	346	devc->cur_threshold[0], devc->cur_threshold[0]);
	347	else if (!strcmp(cg->name, "B"))
	348	*data = std_gvar_tuple_double(
	349	devc->cur_threshold[1], devc->cur_threshold[1]);
	350	else
	351	return SR_ERR_CHANNEL_GROUP;
	352	}
caad0024	353	break;
5089a143	354	case SR_CONF_SAMPLERATE:
f49065c6	355	*data = g_variant_new_uint64(samplerates_hw[devc->sample_rate]);
5089a143 AZ	356	break;
	357	case SR_CONF_CAPTURE_RATIO:
	358	*data = g_variant_new_uint64(devc->capture_ratio);
	359	break;
	360	case SR_CONF_LIMIT_SAMPLES:
	361	*data = g_variant_new_uint64(devc->cmd_pkt.sample_size);
	362	break;
f49065c6 AV	363	case SR_CONF_EXTERNAL_CLOCK:
	364	*data = g_variant_new_boolean(devc->external_clock);
	365	break;
	366	case SR_CONF_EXTERNAL_CLOCK_SOURCE:
	367	idx = devc->external_clock_source;
	368	if (idx >= ARRAY_SIZE(ext_clock_sources))
	369	return SR_ERR_BUG;
	370	*data = g_variant_new_string(ext_clock_sources[idx]);
	371	break;
5089a143 AZ	372	case SR_CONF_CONN:
	373	if (!sdi \|\| !(usb = sdi->conn))
	374	return SR_ERR_ARG;
	375	*data = g_variant_new_printf("%d.%d", usb->bus, usb->address);
	376	break;
f49065c6 AV	377	case SR_CONF_CLOCK_EDGE:
	378	idx = devc->clock_edge;
	379	if (idx >= ARRAY_SIZE(signal_edges))
	380	return SR_ERR_BUG;
	381	*data = g_variant_new_string(signal_edges[idx]);
	382	break;
6a25fa42 AZ	383	default:
	384	return SR_ERR_NA;
	385	}
	386
5089a143	387	return SR_OK;
6a25fa42 AZ	388	}
	389
	390	static int config_set(uint32_t key, GVariant *data,
	391	const struct sr_dev_inst sdi, const struct sr_channel_group cg)
	392	{
5089a143 AZ	393	struct dev_context *devc = sdi->priv;
5089a143 AZ	394	struct h4032l_cmd_pkt *cmd_pkt = &devc->cmd_pkt;
f49065c6	395	int idx;
6a25fa42	396
6a25fa42	397	switch (key) {
5089a143 AZ	398	case SR_CONF_SAMPLERATE: {
	399	uint64_t sample_rate = g_variant_get_uint64(data);
	400	uint8_t i = 0;
	401	while (i < ARRAY_SIZE(samplerates_hw) && samplerates_hw[i] != sample_rate)
	402	i++;
	403
	404	if (i == ARRAY_SIZE(samplerates_hw) \|\| sample_rate == 0) {
4868f15a	405	sr_err("Invalid sample rate.");
5089a143 AZ	406	return SR_ERR_SAMPLERATE;
5089a143 AZ	407	}
f49065c6	408	devc->sample_rate = i;
28f2d07f	409	break;
5089a143	410	}
3dc976fe AV	411	case SR_CONF_CAPTURE_RATIO: {
	412	uint64_t capture_ratio = g_variant_get_uint64(data);
	413	if (capture_ratio > 99) {
	414	sr_err("Invalid capture ratio.");
	415	return SR_ERR;
	416	}
	417	devc->capture_ratio = capture_ratio;
	418	break;
	419	}
5089a143 AZ	420	case SR_CONF_LIMIT_SAMPLES: {
	421	uint64_t number_samples = g_variant_get_uint64(data);
	422	number_samples += 511;
	423	number_samples &= 0xfffffe00;
4b75f84c AV	424	if (number_samples < H4043L_NUM_SAMPLES_MIN \|\|
4b75f84c AV	425	number_samples > H4032L_NUM_SAMPLES_MAX) {
4868f15a UH	426	sr_err("Invalid sample range 2k...64M: %"
4868f15a UH	427	PRIu64 ".", number_samples);
5089a143 AZ	428	return SR_ERR;
	429	}
	430	cmd_pkt->sample_size = number_samples;
28f2d07f	431	break;
5089a143 AZ	432	}
5089a143 AZ	433	case SR_CONF_VOLTAGE_THRESHOLD: {
caad0024 AV	434	double low, high;
caad0024 AV	435	g_variant_get(data, "(dd)", &low, &high);
2a801861 AV	436	double threshold = (low + high) / 2.0;
	437	if (cg) {
	438	if (!strcmp(cg->name, "A"))
	439	devc->cur_threshold[0] = threshold;
	440	else if (!strcmp(cg->name, "B"))
	441	devc->cur_threshold[1] = threshold;
	442	else
	443	return SR_ERR_CHANNEL_GROUP;
	444	}
28f2d07f	445	break;
5089a143	446	}
f49065c6 AV	447	case SR_CONF_EXTERNAL_CLOCK:
	448	devc->external_clock = g_variant_get_boolean(data);
	449	break;
	450	case SR_CONF_EXTERNAL_CLOCK_SOURCE:
	451	if ((idx = std_str_idx(data, ARRAY_AND_SIZE(ext_clock_sources))) < 0)
	452	return SR_ERR_ARG;
	453	devc->external_clock_source = idx;
	454	break;
	455	case SR_CONF_CLOCK_EDGE:
	456	if ((idx = std_str_idx(data, ARRAY_AND_SIZE(signal_edges))) < 0)
	457	return SR_ERR_ARG;
	458	devc->clock_edge = idx;
	459	break;
28f2d07f AV	460	default:
28f2d07f AV	461	return SR_ERR_NA;
6a25fa42 AZ	462	}
6a25fa42 AZ	463
28f2d07f	464	return SR_OK;
6a25fa42 AZ	465	}
	466
	467	static int config_list(uint32_t key, GVariant **data,
	468	const struct sr_dev_inst sdi, const struct sr_channel_group cg)
	469	{
f49065c6 AV	470
	471	struct dev_context *devc = (sdi) ? sdi->priv : NULL;
	472
6a25fa42	473	switch (key) {
5089a143 AZ	474	case SR_CONF_SCAN_OPTIONS:
5089a143 AZ	475	case SR_CONF_DEVICE_OPTIONS:
2a801861 AV	476	if (cg) {
	477	*data = std_gvar_array_u32(ARRAY_AND_SIZE(devopts_cg));
	478	break;
	479	}
f49065c6 AV	480	/* Disable external clock and edges for FPGA version 0. */
	481	if (devc && (!devc->fpga_version))
	482	return STD_CONFIG_LIST(key, data, sdi, cg, scanopts, drvopts, devopts_fpga_zero);
5089a143 AZ	483	return STD_CONFIG_LIST(key, data, sdi, cg, scanopts, drvopts, devopts);
	484	case SR_CONF_SAMPLERATE:
	485	*data = std_gvar_samplerates(ARRAY_AND_SIZE(samplerates));
	486	break;
	487	case SR_CONF_TRIGGER_MATCH:
	488	*data = std_gvar_array_i32(ARRAY_AND_SIZE(trigger_matches));
	489	break;
	490	case SR_CONF_VOLTAGE_THRESHOLD:
caad0024	491	*data = std_gvar_min_max_step_thresholds(-6.0, 6.0, 0.1);
5089a143	492	break;
4b75f84c AV	493	case SR_CONF_LIMIT_SAMPLES:
	494	*data = std_gvar_tuple_u64(H4043L_NUM_SAMPLES_MIN, H4032L_NUM_SAMPLES_MAX);
	495	break;
f49065c6 AV	496	case SR_CONF_CLOCK_EDGE:
	497	*data = g_variant_new_strv(ARRAY_AND_SIZE(signal_edges));
	498	break;
	499	case SR_CONF_EXTERNAL_CLOCK_SOURCE:
	500	*data = g_variant_new_strv(ARRAY_AND_SIZE(ext_clock_sources));
	501	break;
6a25fa42 AZ	502	default:
	503	return SR_ERR_NA;
	504	}
	505
5089a143	506	return SR_OK;
6a25fa42 AZ	507	}
6a25fa42 AZ	508
5089a143	509	static int dev_acquisition_start(const struct sr_dev_inst *sdi)
6a25fa42	510	{
5089a143 AZ	511	struct sr_dev_driver *di = sdi->driver;
	512	struct drv_context *drvc = di->context;
	513	struct dev_context *devc = sdi->priv;
	514	struct sr_trigger *trigger = sr_session_trigger_get(sdi->session);
	515	struct h4032l_cmd_pkt *cmd_pkt = &devc->cmd_pkt;
	516
28f2d07f	517	/* Initialize variables. */
a5b9880e	518	devc->acq_aborted = FALSE;
2958315d	519	devc->submitted_transfers = 0;
3dc976fe	520	devc->sent_samples = 0;
a5b9880e	521
5089a143 AZ	522	/* Calculate packet ratio. */
5089a143 AZ	523	cmd_pkt->pre_trigger_size = (cmd_pkt->sample_size * devc->capture_ratio) / 100;
3dc976fe	524	devc->trigger_pos = cmd_pkt->pre_trigger_size;
5089a143	525
f49065c6 AV	526	/* Set clock edge, when external clock is enabled. */
	527	if (devc->external_clock)
	528	cmd_pkt->sample_rate = ext_clock_edges[devc->external_clock_source][devc->clock_edge];
	529	else
	530	cmd_pkt->sample_rate = devc->sample_rate;
	531
caad0024	532	/* Set pwm channel values. */
2a801861 AV	533	devc->cmd_pkt.pwm_a = h4032l_voltage2pwm(devc->cur_threshold[0]);
2a801861 AV	534	devc->cmd_pkt.pwm_b = h4032l_voltage2pwm(devc->cur_threshold[1]);
caad0024	535
5089a143 AZ	536	cmd_pkt->trig_flags.enable_trigger1 = 0;
	537	cmd_pkt->trig_flags.enable_trigger2 = 0;
	538	cmd_pkt->trig_flags.trigger_and_logic = 0;
	539
	540	if (trigger && trigger->stages) {
	541	GSList *stages = trigger->stages;
	542	struct sr_trigger_stage *stage1 = stages->data;
	543	if (stages->next) {
4868f15a	544	sr_err("Only one trigger stage supported for now.");
5089a143 AZ	545	return SR_ERR;
	546	}
	547	cmd_pkt->trig_flags.enable_trigger1 = 1;
	548	cmd_pkt->trigger[0].flags.edge_type = H4032L_TRIGGER_EDGE_TYPE_DISABLED;
	549	cmd_pkt->trigger[0].flags.data_range_enabled = 0;
	550	cmd_pkt->trigger[0].flags.time_range_enabled = 0;
	551	cmd_pkt->trigger[0].flags.combined_enabled = 0;
	552	cmd_pkt->trigger[0].flags.data_range_type = H4032L_TRIGGER_DATA_RANGE_TYPE_MAX;
	553	cmd_pkt->trigger[0].data_range_mask = 0;
	554	cmd_pkt->trigger[0].data_range_max = 0;
	555
	556	/* Initialize range mask values. */
	557	uint32_t range_mask = 0;
	558	uint32_t range_value = 0;
	559
	560	GSList *channel = stage1->matches;
	561	while (channel) {
	562	struct sr_trigger_match *match = channel->data;
	563
	564	switch (match->match) {
	565	case SR_TRIGGER_ZERO:
	566	range_mask \|= (1 << match->channel->index);
	567	break;
	568	case SR_TRIGGER_ONE:
	569	range_mask \|= (1 << match->channel->index);
	570	range_value \|= (1 << match->channel->index);
	571	break;
	572	case SR_TRIGGER_RISING:
	573	if (cmd_pkt->trigger[0].flags.edge_type != H4032L_TRIGGER_EDGE_TYPE_DISABLED) {
4868f15a	574	sr_err("Only one trigger signal with fall/rising/edge allowed.");
5089a143 AZ	575	return SR_ERR;
	576	}
	577	cmd_pkt->trigger[0].flags.edge_type = H4032L_TRIGGER_EDGE_TYPE_RISE;
	578	cmd_pkt->trigger[0].flags.edge_signal = match->channel->index;
	579	break;
	580	case SR_TRIGGER_FALLING:
	581	if (cmd_pkt->trigger[0].flags.edge_type != H4032L_TRIGGER_EDGE_TYPE_DISABLED) {
4868f15a	582	sr_err("Only one trigger signal with fall/rising/edge allowed.");
5089a143 AZ	583	return SR_ERR;
	584	}
	585	cmd_pkt->trigger[0].flags.edge_type = H4032L_TRIGGER_EDGE_TYPE_FALL;
	586	cmd_pkt->trigger[0].flags.edge_signal = match->channel->index;
	587	break;
	588	case SR_TRIGGER_EDGE:
	589	if (cmd_pkt->trigger[0].flags.edge_type != H4032L_TRIGGER_EDGE_TYPE_DISABLED) {
4868f15a	590	sr_err("Only one trigger signal with fall/rising/edge allowed.");
5089a143 AZ	591	return SR_ERR;
	592	}
	593	cmd_pkt->trigger[0].flags.edge_type = H4032L_TRIGGER_EDGE_TYPE_TOGGLE;
	594	cmd_pkt->trigger[0].flags.edge_signal = match->channel->index;
	595	break;
	596	default:
4868f15a	597	sr_err("Unknown trigger value.");
5089a143 AZ	598	return SR_ERR;
	599	}
	600
	601	channel = channel->next;
	602	}
	603
	604	/* Compress range mask value and apply range settings. */
	605	if (range_mask) {
	606	cmd_pkt->trigger[0].flags.data_range_enabled = 1;
	607	cmd_pkt->trigger[0].data_range_mask \|= (range_mask);
	608
	609	uint32_t new_range_value = 0;
	610	uint32_t bit_mask = 1;
	611	while (range_mask) {
	612	if ((range_mask & 1) != 0) {
	613	new_range_value <<= 1;
	614	if ((range_value & 1) != 0)
	615	new_range_value \|= bit_mask;
	616	bit_mask <<= 1;
	617	}
	618	range_mask >>= 1;
	619	range_value >>= 1;
	620	}
	621	cmd_pkt->trigger[0].data_range_max \|= range_value;
	622	}
	623	}
6a25fa42	624
74c4c174	625	usb_source_add(sdi->session, drvc->sr_ctx, 1000,
5089a143	626	h4032l_receive_data, sdi->driver->context);
6a25fa42	627
5089a143 AZ	628	/* Start capturing. */
5089a143 AZ	629	return h4032l_start(sdi);
6a25fa42 AZ	630	}
6a25fa42 AZ	631
5089a143	632	static int dev_acquisition_stop(struct sr_dev_inst *sdi)
6a25fa42	633	{
2958315d AV	634	/* Stop capturing. */
2958315d AV	635	return h4032l_stop(sdi);
6a25fa42 AZ	636	}
	637
	638	SR_PRIV struct sr_dev_driver hantek_4032l_driver_info = {
	639	.name = "hantek-4032l",
5089a143	640	.longname = "Hantek 4032L",
6a25fa42	641	.api_version = 1,
5089a143 AZ	642	.init = std_init,
5089a143 AZ	643	.cleanup = std_cleanup,
6a25fa42	644	.scan = scan,
5089a143 AZ	645	.dev_list = std_dev_list,
5089a143 AZ	646	.dev_clear = std_dev_clear,
6a25fa42 AZ	647	.config_get = config_get,
	648	.config_set = config_set,
	649	.config_list = config_list,
	650	.dev_open = dev_open,
	651	.dev_close = dev_close,
	652	.dev_acquisition_start = dev_acquisition_start,
	653	.dev_acquisition_stop = dev_acquisition_stop,
	654	.context = NULL,
	655	};
5089a143	656	SR_REGISTER_DEV_DRIVER(hantek_4032l_driver_info);