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6a25fa42 AZ |
1 | /* |
2 | * This file is part of the libsigrok project. | |
3 | * | |
5089a143 AZ |
4 | * Copyright (C) 2016 Andreas Zschunke <andreas.zschunke@gmx.net> |
5 | * Copyright (C) 2017 Andrej Valek <andy@skyrain.eu> | |
6 | * Copyright (C) 2017 Uwe Hermann <uwe@hermann-uwe.de> | |
6a25fa42 AZ |
7 | * |
8 | * This program is free software: you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation, either version 3 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
20 | */ | |
21 | ||
22 | #include <config.h> | |
23 | #include "protocol.h" | |
24 | ||
5089a143 AZ |
25 | #define USB_INTERFACE 0 |
26 | #define NUM_CHANNELS 32 | |
6a25fa42 | 27 | |
5089a143 AZ |
28 | static const uint32_t scanopts[] = { |
29 | SR_CONF_CONN, | |
30 | }; | |
31 | ||
32 | static const uint32_t drvopts[] = { | |
33 | SR_CONF_LOGIC_ANALYZER, | |
34 | }; | |
35 | ||
36 | static const uint32_t devopts[] = { | |
37 | SR_CONF_SAMPLERATE | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST, | |
3dc976fe | 38 | SR_CONF_CAPTURE_RATIO | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST, |
4b75f84c | 39 | SR_CONF_LIMIT_SAMPLES | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST, |
5089a143 AZ |
40 | SR_CONF_TRIGGER_MATCH | SR_CONF_LIST, |
41 | SR_CONF_CONN | SR_CONF_GET, | |
f49065c6 AV |
42 | SR_CONF_EXTERNAL_CLOCK | SR_CONF_GET | SR_CONF_SET, |
43 | SR_CONF_EXTERNAL_CLOCK_SOURCE | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST, | |
44 | SR_CONF_CLOCK_EDGE | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST, | |
45 | }; | |
46 | ||
47 | static const uint32_t devopts_fpga_zero[] = { | |
48 | SR_CONF_SAMPLERATE | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST, | |
49 | SR_CONF_CAPTURE_RATIO | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST, | |
50 | SR_CONF_LIMIT_SAMPLES | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST, | |
51 | SR_CONF_TRIGGER_MATCH | SR_CONF_LIST, | |
52 | SR_CONF_CONN | SR_CONF_GET, | |
2a801861 AV |
53 | }; |
54 | ||
55 | static const uint32_t devopts_cg[] = { | |
caad0024 | 56 | SR_CONF_VOLTAGE_THRESHOLD | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST, |
5089a143 AZ |
57 | }; |
58 | ||
f49065c6 AV |
59 | static const char *signal_edges[] = { |
60 | [H4032L_CLOCK_EDGE_TYPE_RISE] = "rising", | |
61 | [H4032L_CLOCK_EDGE_TYPE_FALL] = "falling", | |
62 | [H4032L_CLOCK_EDGE_TYPE_BOTH] = "both", | |
63 | }; | |
64 | ||
65 | static const char *ext_clock_sources[] = { | |
66 | [H4032L_EXT_CLOCK_SOURCE_CHANNEL_A] = "ACLK", | |
67 | [H4032L_EXT_CLOCK_SOURCE_CHANNEL_B] = "BCLK" | |
68 | }; | |
69 | ||
70 | static const uint8_t ext_clock_edges[2][3] = { | |
71 | { | |
72 | H4032L_CLOCK_EDGE_TYPE_RISE_A, | |
73 | H4032L_CLOCK_EDGE_TYPE_FALL_A, | |
74 | H4032L_CLOCK_EDGE_TYPE_BOTH_A | |
75 | }, | |
76 | { | |
77 | H4032L_CLOCK_EDGE_TYPE_RISE_B, | |
78 | H4032L_CLOCK_EDGE_TYPE_FALL_B, | |
79 | H4032L_CLOCK_EDGE_TYPE_BOTH_B | |
80 | } | |
81 | }; | |
82 | ||
5089a143 AZ |
83 | static const int32_t trigger_matches[] = { |
84 | SR_TRIGGER_ZERO, | |
85 | SR_TRIGGER_ONE, | |
86 | SR_TRIGGER_RISING, | |
87 | SR_TRIGGER_FALLING, | |
88 | SR_TRIGGER_EDGE, | |
89 | }; | |
90 | ||
91 | static const uint64_t samplerates[] = { | |
92 | SR_KHZ(1), | |
93 | SR_KHZ(2), | |
94 | SR_KHZ(4), | |
95 | SR_KHZ(8), | |
96 | SR_KHZ(16), | |
97 | SR_HZ(31250), | |
98 | SR_HZ(62500), | |
99 | SR_KHZ(125), | |
100 | SR_KHZ(250), | |
101 | SR_KHZ(500), | |
102 | SR_KHZ(625), | |
103 | SR_HZ(781250), | |
104 | SR_MHZ(1), | |
105 | SR_KHZ(1250), | |
106 | SR_HZ(1562500), | |
107 | SR_MHZ(2), | |
108 | SR_KHZ(2500), | |
109 | SR_KHZ(3125), | |
110 | SR_MHZ(4), | |
111 | SR_MHZ(5), | |
112 | SR_KHZ(6250), | |
113 | SR_MHZ(10), | |
114 | SR_KHZ(12500), | |
115 | SR_MHZ(20), | |
116 | SR_MHZ(25), | |
117 | SR_MHZ(40), | |
118 | SR_MHZ(50), | |
119 | SR_MHZ(80), | |
120 | SR_MHZ(100), | |
121 | SR_MHZ(160), | |
122 | SR_MHZ(200), | |
123 | SR_MHZ(320), | |
124 | SR_MHZ(400), | |
125 | }; | |
126 | ||
127 | static const uint64_t samplerates_hw[] = { | |
128 | SR_MHZ(100), | |
129 | SR_MHZ(50), | |
130 | SR_MHZ(25), | |
131 | SR_KHZ(12500), | |
132 | SR_KHZ(6250), | |
133 | SR_KHZ(3125), | |
134 | SR_HZ(1562500), | |
135 | SR_HZ(781250), | |
136 | SR_MHZ(80), | |
137 | SR_MHZ(40), | |
138 | SR_MHZ(20), | |
139 | SR_MHZ(10), | |
140 | SR_MHZ(5), | |
141 | SR_KHZ(2500), | |
142 | SR_KHZ(1250), | |
143 | SR_KHZ(625), | |
144 | SR_MHZ(4), | |
145 | SR_MHZ(2), | |
146 | SR_MHZ(1), | |
147 | SR_KHZ(500), | |
148 | SR_KHZ(250), | |
149 | SR_KHZ(125), | |
150 | SR_HZ(62500), | |
151 | SR_HZ(31250), | |
152 | SR_KHZ(16), | |
153 | SR_KHZ(8), | |
154 | SR_KHZ(4), | |
155 | SR_KHZ(2), | |
156 | SR_KHZ(1), | |
157 | 0, | |
158 | 0, | |
159 | 0, | |
160 | SR_MHZ(200), | |
161 | SR_MHZ(160), | |
162 | SR_MHZ(400), | |
163 | SR_MHZ(320), | |
164 | }; | |
165 | ||
166 | SR_PRIV struct sr_dev_driver hantek_4032l_driver_info; | |
6a25fa42 AZ |
167 | |
168 | static GSList *scan(struct sr_dev_driver *di, GSList *options) | |
169 | { | |
5089a143 AZ |
170 | struct drv_context *drvc = di->context; |
171 | GSList *l, *devices, *conn_devices; | |
172 | libusb_device **devlist; | |
173 | struct libusb_device_descriptor des; | |
174 | const char *conn; | |
175 | int i; | |
176 | char connection_id[64]; | |
177 | struct sr_channel_group *cg; | |
178 | struct sr_dev_inst *sdi; | |
179 | struct sr_channel *ch; | |
6a25fa42 AZ |
180 | |
181 | devices = NULL; | |
5089a143 | 182 | conn_devices = NULL; |
6a25fa42 | 183 | drvc->instances = NULL; |
5089a143 AZ |
184 | conn = NULL; |
185 | ||
186 | for (l = options; l; l = l->next) { | |
187 | struct sr_config *src = l->data; | |
188 | if (src->key == SR_CONF_CONN) { | |
189 | conn = g_variant_get_string(src->data, NULL); | |
190 | break; | |
191 | } | |
192 | } | |
6a25fa42 | 193 | |
5089a143 AZ |
194 | if (conn) |
195 | conn_devices = sr_usb_find(drvc->sr_ctx->libusb_ctx, conn); | |
196 | else | |
197 | conn_devices = NULL; | |
198 | ||
199 | libusb_get_device_list(drvc->sr_ctx->libusb_ctx, &devlist); | |
200 | for (i = 0; devlist[i]; i++) { | |
201 | if (conn) { | |
202 | struct sr_usb_dev_inst *usb = NULL; | |
203 | for (l = conn_devices; l; l = l->next) { | |
204 | usb = l->data; | |
28f2d07f AV |
205 | if (usb->bus == libusb_get_bus_number(devlist[i]) && |
206 | usb->address == libusb_get_device_address(devlist[i])) | |
5089a143 AZ |
207 | break; |
208 | } | |
209 | if (!l) | |
210 | /* This device matched none of the ones that | |
211 | * matched the conn specification. */ | |
212 | continue; | |
213 | } | |
214 | ||
215 | libusb_get_device_descriptor(devlist[i], &des); | |
216 | ||
217 | if (des.idVendor != H4032L_USB_VENDOR || | |
218 | des.idProduct != H4032L_USB_PRODUCT) | |
219 | continue; | |
220 | ||
6c1a76d1 RT |
221 | if (usb_get_port_path(devlist[i], connection_id, sizeof(connection_id)) < 0) |
222 | continue; | |
5089a143 AZ |
223 | |
224 | sdi = g_malloc0(sizeof(struct sr_dev_inst)); | |
225 | sdi->driver = &hantek_4032l_driver_info; | |
226 | sdi->vendor = g_strdup("Hantek"); | |
227 | sdi->model = g_strdup("4032L"); | |
228 | sdi->connection_id = g_strdup(connection_id); | |
229 | ||
230 | struct sr_channel_group *channel_groups[2]; | |
231 | for (int j = 0; j < 2; j++) { | |
232 | cg = g_malloc0(sizeof(struct sr_channel_group)); | |
233 | cg->name = g_strdup_printf("%c", 'A' + j); | |
234 | channel_groups[j] = cg; | |
235 | sdi->channel_groups = g_slist_append(sdi->channel_groups, cg); | |
236 | } | |
237 | ||
238 | /* Assemble channel list and add channel to channel groups. */ | |
239 | for (int j = 0; j < NUM_CHANNELS; j++) { | |
240 | char channel_name[4]; | |
241 | sprintf(channel_name, "%c%d", 'A' + (j & 1), j / 2); | |
242 | ch = sr_channel_new(sdi, j, SR_CHANNEL_LOGIC, TRUE, channel_name); | |
243 | cg = channel_groups[j & 1]; | |
244 | cg->channels = g_slist_append(cg->channels, ch); | |
245 | } | |
246 | ||
247 | struct dev_context *devc = g_malloc0(sizeof(struct dev_context)); | |
248 | ||
249 | /* Initialize command packet. */ | |
250 | devc->cmd_pkt.magic = H4032L_CMD_PKT_MAGIC; | |
5089a143 | 251 | devc->cmd_pkt.sample_size = 16384; |
f49065c6 | 252 | devc->sample_rate = 0; |
5089a143 AZ |
253 | |
254 | devc->status = H4032L_STATUS_IDLE; | |
255 | ||
256 | devc->capture_ratio = 5; | |
f49065c6 AV |
257 | devc->external_clock = FALSE; |
258 | devc->clock_edge = H4032L_CLOCK_EDGE_TYPE_RISE; | |
259 | ||
2a801861 AV |
260 | devc->cur_threshold[0] = 2.5; |
261 | devc->cur_threshold[1] = 2.5; | |
5089a143 | 262 | |
5089a143 AZ |
263 | sdi->priv = devc; |
264 | devices = g_slist_append(devices, sdi); | |
265 | ||
266 | sdi->status = SR_ST_INACTIVE; | |
267 | sdi->inst_type = SR_INST_USB; | |
268 | sdi->conn = sr_usb_dev_inst_new( | |
269 | libusb_get_bus_number(devlist[i]), | |
270 | libusb_get_device_address(devlist[i]), NULL); | |
271 | } | |
6a25fa42 | 272 | |
5089a143 AZ |
273 | g_slist_free_full(conn_devices, (GDestroyNotify)sr_usb_dev_inst_free); |
274 | libusb_free_device_list(devlist, 1); | |
6a25fa42 | 275 | |
5089a143 | 276 | return std_scan_complete(di, devices); |
6a25fa42 AZ |
277 | } |
278 | ||
279 | static int dev_open(struct sr_dev_inst *sdi) | |
280 | { | |
5089a143 AZ |
281 | struct sr_usb_dev_inst *usb = sdi->conn; |
282 | int ret; | |
6a25fa42 | 283 | |
5089a143 AZ |
284 | ret = h4032l_dev_open(sdi); |
285 | if (ret != SR_OK) { | |
286 | sr_err("Unable to open device."); | |
287 | return SR_ERR; | |
288 | } | |
6a25fa42 | 289 | |
5089a143 AZ |
290 | ret = libusb_claim_interface(usb->devhdl, USB_INTERFACE); |
291 | if (ret != 0) { | |
292 | switch (ret) { | |
293 | case LIBUSB_ERROR_BUSY: | |
294 | sr_err("Unable to claim USB interface. Another " | |
295 | "program or driver has already claimed it."); | |
296 | break; | |
297 | case LIBUSB_ERROR_NO_DEVICE: | |
298 | sr_err("Device has been disconnected."); | |
299 | break; | |
300 | default: | |
301 | sr_err("Unable to claim interface: %s.", | |
302 | libusb_error_name(ret)); | |
303 | break; | |
304 | } | |
305 | ||
306 | return SR_ERR; | |
307 | } | |
6a25fa42 | 308 | |
7a7afc00 AV |
309 | /* Get FPGA version. */ |
310 | if ((ret = h4032l_get_fpga_version(sdi)) != SR_OK) | |
311 | return ret; | |
312 | ||
6a25fa42 AZ |
313 | return SR_OK; |
314 | } | |
315 | ||
316 | static int dev_close(struct sr_dev_inst *sdi) | |
317 | { | |
5089a143 | 318 | struct sr_usb_dev_inst *usb; |
6a25fa42 | 319 | |
5089a143 | 320 | usb = sdi->conn; |
6a25fa42 | 321 | |
5089a143 AZ |
322 | if (!usb->devhdl) |
323 | return SR_ERR_BUG; | |
6a25fa42 | 324 | |
5089a143 AZ |
325 | sr_info("Closing device on %d.%d (logical) / %s (physical) interface %d.", |
326 | usb->bus, usb->address, sdi->connection_id, USB_INTERFACE); | |
327 | libusb_release_interface(usb->devhdl, USB_INTERFACE); | |
328 | libusb_close(usb->devhdl); | |
329 | usb->devhdl = NULL; | |
6a25fa42 AZ |
330 | |
331 | return SR_OK; | |
332 | } | |
333 | ||
334 | static int config_get(uint32_t key, GVariant **data, | |
335 | const struct sr_dev_inst *sdi, const struct sr_channel_group *cg) | |
336 | { | |
5089a143 AZ |
337 | struct dev_context *devc = sdi->priv; |
338 | struct sr_usb_dev_inst *usb; | |
f49065c6 | 339 | unsigned int idx; |
6a25fa42 | 340 | |
6a25fa42 | 341 | switch (key) { |
caad0024 | 342 | case SR_CONF_VOLTAGE_THRESHOLD: |
61803a29 UH |
343 | if (!cg) |
344 | return SR_ERR_CHANNEL_GROUP; | |
345 | if (!strcmp(cg->name, "A")) | |
346 | *data = std_gvar_tuple_double( | |
347 | devc->cur_threshold[0], devc->cur_threshold[0]); | |
348 | else if (!strcmp(cg->name, "B")) | |
349 | *data = std_gvar_tuple_double( | |
350 | devc->cur_threshold[1], devc->cur_threshold[1]); | |
351 | else | |
352 | return SR_ERR_CHANNEL_GROUP; | |
caad0024 | 353 | break; |
5089a143 | 354 | case SR_CONF_SAMPLERATE: |
f49065c6 | 355 | *data = g_variant_new_uint64(samplerates_hw[devc->sample_rate]); |
5089a143 AZ |
356 | break; |
357 | case SR_CONF_CAPTURE_RATIO: | |
358 | *data = g_variant_new_uint64(devc->capture_ratio); | |
359 | break; | |
360 | case SR_CONF_LIMIT_SAMPLES: | |
361 | *data = g_variant_new_uint64(devc->cmd_pkt.sample_size); | |
362 | break; | |
f49065c6 AV |
363 | case SR_CONF_EXTERNAL_CLOCK: |
364 | *data = g_variant_new_boolean(devc->external_clock); | |
365 | break; | |
366 | case SR_CONF_EXTERNAL_CLOCK_SOURCE: | |
367 | idx = devc->external_clock_source; | |
368 | if (idx >= ARRAY_SIZE(ext_clock_sources)) | |
369 | return SR_ERR_BUG; | |
370 | *data = g_variant_new_string(ext_clock_sources[idx]); | |
371 | break; | |
5089a143 AZ |
372 | case SR_CONF_CONN: |
373 | if (!sdi || !(usb = sdi->conn)) | |
374 | return SR_ERR_ARG; | |
375 | *data = g_variant_new_printf("%d.%d", usb->bus, usb->address); | |
376 | break; | |
f49065c6 AV |
377 | case SR_CONF_CLOCK_EDGE: |
378 | idx = devc->clock_edge; | |
379 | if (idx >= ARRAY_SIZE(signal_edges)) | |
380 | return SR_ERR_BUG; | |
381 | *data = g_variant_new_string(signal_edges[idx]); | |
382 | break; | |
6a25fa42 AZ |
383 | default: |
384 | return SR_ERR_NA; | |
385 | } | |
386 | ||
5089a143 | 387 | return SR_OK; |
6a25fa42 AZ |
388 | } |
389 | ||
390 | static int config_set(uint32_t key, GVariant *data, | |
391 | const struct sr_dev_inst *sdi, const struct sr_channel_group *cg) | |
392 | { | |
61803a29 | 393 | int idx; |
5089a143 AZ |
394 | struct dev_context *devc = sdi->priv; |
395 | struct h4032l_cmd_pkt *cmd_pkt = &devc->cmd_pkt; | |
583fc126 | 396 | uint64_t sample_rate, number_samples; |
61803a29 | 397 | double low, high, threshold; |
6a25fa42 | 398 | |
6a25fa42 | 399 | switch (key) { |
61803a29 UH |
400 | case SR_CONF_SAMPLERATE: |
401 | idx = 0; | |
402 | sample_rate = g_variant_get_uint64(data); | |
403 | while (idx < ARRAY_SIZE(samplerates_hw) && samplerates_hw[idx] != sample_rate) | |
404 | idx++; | |
405 | if (idx == ARRAY_SIZE(samplerates_hw) || sample_rate == 0) { | |
406 | sr_err("Invalid sample rate."); | |
407 | return SR_ERR_SAMPLERATE; | |
3dc976fe | 408 | } |
61803a29 UH |
409 | devc->sample_rate = idx; |
410 | break; | |
411 | case SR_CONF_CAPTURE_RATIO: | |
583fc126 | 412 | devc->capture_ratio = g_variant_get_uint64(data); |
61803a29 UH |
413 | break; |
414 | case SR_CONF_LIMIT_SAMPLES: | |
415 | number_samples = g_variant_get_uint64(data); | |
416 | number_samples += 511; | |
417 | number_samples &= 0xfffffe00; | |
418 | if (number_samples < H4043L_NUM_SAMPLES_MIN || | |
419 | number_samples > H4032L_NUM_SAMPLES_MAX) { | |
420 | sr_err("Invalid sample range 2k...64M: %" | |
421 | PRIu64 ".", number_samples); | |
422 | return SR_ERR; | |
5089a143 | 423 | } |
61803a29 UH |
424 | cmd_pkt->sample_size = number_samples; |
425 | break; | |
426 | case SR_CONF_VOLTAGE_THRESHOLD: | |
427 | if (!cg) | |
428 | return SR_ERR_CHANNEL_GROUP; | |
429 | g_variant_get(data, "(dd)", &low, &high); | |
430 | threshold = (low + high) / 2.0; | |
431 | if (!strcmp(cg->name, "A")) | |
432 | devc->cur_threshold[0] = threshold; | |
433 | else if (!strcmp(cg->name, "B")) | |
434 | devc->cur_threshold[1] = threshold; | |
435 | else | |
436 | return SR_ERR_CHANNEL_GROUP; | |
437 | break; | |
f49065c6 AV |
438 | case SR_CONF_EXTERNAL_CLOCK: |
439 | devc->external_clock = g_variant_get_boolean(data); | |
440 | break; | |
441 | case SR_CONF_EXTERNAL_CLOCK_SOURCE: | |
442 | if ((idx = std_str_idx(data, ARRAY_AND_SIZE(ext_clock_sources))) < 0) | |
443 | return SR_ERR_ARG; | |
444 | devc->external_clock_source = idx; | |
445 | break; | |
446 | case SR_CONF_CLOCK_EDGE: | |
447 | if ((idx = std_str_idx(data, ARRAY_AND_SIZE(signal_edges))) < 0) | |
448 | return SR_ERR_ARG; | |
449 | devc->clock_edge = idx; | |
450 | break; | |
28f2d07f AV |
451 | default: |
452 | return SR_ERR_NA; | |
6a25fa42 AZ |
453 | } |
454 | ||
28f2d07f | 455 | return SR_OK; |
6a25fa42 AZ |
456 | } |
457 | ||
458 | static int config_list(uint32_t key, GVariant **data, | |
459 | const struct sr_dev_inst *sdi, const struct sr_channel_group *cg) | |
460 | { | |
f49065c6 AV |
461 | struct dev_context *devc = (sdi) ? sdi->priv : NULL; |
462 | ||
6a25fa42 | 463 | switch (key) { |
5089a143 AZ |
464 | case SR_CONF_SCAN_OPTIONS: |
465 | case SR_CONF_DEVICE_OPTIONS: | |
2a801861 AV |
466 | if (cg) { |
467 | *data = std_gvar_array_u32(ARRAY_AND_SIZE(devopts_cg)); | |
468 | break; | |
469 | } | |
f49065c6 AV |
470 | /* Disable external clock and edges for FPGA version 0. */ |
471 | if (devc && (!devc->fpga_version)) | |
472 | return STD_CONFIG_LIST(key, data, sdi, cg, scanopts, drvopts, devopts_fpga_zero); | |
5089a143 AZ |
473 | return STD_CONFIG_LIST(key, data, sdi, cg, scanopts, drvopts, devopts); |
474 | case SR_CONF_SAMPLERATE: | |
475 | *data = std_gvar_samplerates(ARRAY_AND_SIZE(samplerates)); | |
476 | break; | |
477 | case SR_CONF_TRIGGER_MATCH: | |
478 | *data = std_gvar_array_i32(ARRAY_AND_SIZE(trigger_matches)); | |
479 | break; | |
480 | case SR_CONF_VOLTAGE_THRESHOLD: | |
caad0024 | 481 | *data = std_gvar_min_max_step_thresholds(-6.0, 6.0, 0.1); |
5089a143 | 482 | break; |
4b75f84c AV |
483 | case SR_CONF_LIMIT_SAMPLES: |
484 | *data = std_gvar_tuple_u64(H4043L_NUM_SAMPLES_MIN, H4032L_NUM_SAMPLES_MAX); | |
485 | break; | |
f49065c6 AV |
486 | case SR_CONF_CLOCK_EDGE: |
487 | *data = g_variant_new_strv(ARRAY_AND_SIZE(signal_edges)); | |
488 | break; | |
489 | case SR_CONF_EXTERNAL_CLOCK_SOURCE: | |
490 | *data = g_variant_new_strv(ARRAY_AND_SIZE(ext_clock_sources)); | |
491 | break; | |
6a25fa42 AZ |
492 | default: |
493 | return SR_ERR_NA; | |
494 | } | |
495 | ||
5089a143 | 496 | return SR_OK; |
6a25fa42 AZ |
497 | } |
498 | ||
5089a143 | 499 | static int dev_acquisition_start(const struct sr_dev_inst *sdi) |
6a25fa42 | 500 | { |
5089a143 AZ |
501 | struct sr_dev_driver *di = sdi->driver; |
502 | struct drv_context *drvc = di->context; | |
503 | struct dev_context *devc = sdi->priv; | |
504 | struct sr_trigger *trigger = sr_session_trigger_get(sdi->session); | |
505 | struct h4032l_cmd_pkt *cmd_pkt = &devc->cmd_pkt; | |
506 | ||
28f2d07f | 507 | /* Initialize variables. */ |
a5b9880e | 508 | devc->acq_aborted = FALSE; |
2958315d | 509 | devc->submitted_transfers = 0; |
3dc976fe | 510 | devc->sent_samples = 0; |
a5b9880e | 511 | |
5089a143 AZ |
512 | /* Calculate packet ratio. */ |
513 | cmd_pkt->pre_trigger_size = (cmd_pkt->sample_size * devc->capture_ratio) / 100; | |
3dc976fe | 514 | devc->trigger_pos = cmd_pkt->pre_trigger_size; |
5089a143 | 515 | |
f49065c6 AV |
516 | /* Set clock edge, when external clock is enabled. */ |
517 | if (devc->external_clock) | |
518 | cmd_pkt->sample_rate = ext_clock_edges[devc->external_clock_source][devc->clock_edge]; | |
519 | else | |
520 | cmd_pkt->sample_rate = devc->sample_rate; | |
521 | ||
caad0024 | 522 | /* Set pwm channel values. */ |
2a801861 AV |
523 | devc->cmd_pkt.pwm_a = h4032l_voltage2pwm(devc->cur_threshold[0]); |
524 | devc->cmd_pkt.pwm_b = h4032l_voltage2pwm(devc->cur_threshold[1]); | |
caad0024 | 525 | |
5089a143 AZ |
526 | cmd_pkt->trig_flags.enable_trigger1 = 0; |
527 | cmd_pkt->trig_flags.enable_trigger2 = 0; | |
528 | cmd_pkt->trig_flags.trigger_and_logic = 0; | |
529 | ||
530 | if (trigger && trigger->stages) { | |
531 | GSList *stages = trigger->stages; | |
532 | struct sr_trigger_stage *stage1 = stages->data; | |
533 | if (stages->next) { | |
4868f15a | 534 | sr_err("Only one trigger stage supported for now."); |
5089a143 AZ |
535 | return SR_ERR; |
536 | } | |
537 | cmd_pkt->trig_flags.enable_trigger1 = 1; | |
538 | cmd_pkt->trigger[0].flags.edge_type = H4032L_TRIGGER_EDGE_TYPE_DISABLED; | |
539 | cmd_pkt->trigger[0].flags.data_range_enabled = 0; | |
540 | cmd_pkt->trigger[0].flags.time_range_enabled = 0; | |
541 | cmd_pkt->trigger[0].flags.combined_enabled = 0; | |
542 | cmd_pkt->trigger[0].flags.data_range_type = H4032L_TRIGGER_DATA_RANGE_TYPE_MAX; | |
543 | cmd_pkt->trigger[0].data_range_mask = 0; | |
544 | cmd_pkt->trigger[0].data_range_max = 0; | |
545 | ||
546 | /* Initialize range mask values. */ | |
547 | uint32_t range_mask = 0; | |
548 | uint32_t range_value = 0; | |
549 | ||
550 | GSList *channel = stage1->matches; | |
551 | while (channel) { | |
552 | struct sr_trigger_match *match = channel->data; | |
553 | ||
554 | switch (match->match) { | |
555 | case SR_TRIGGER_ZERO: | |
556 | range_mask |= (1 << match->channel->index); | |
557 | break; | |
558 | case SR_TRIGGER_ONE: | |
559 | range_mask |= (1 << match->channel->index); | |
560 | range_value |= (1 << match->channel->index); | |
561 | break; | |
562 | case SR_TRIGGER_RISING: | |
563 | if (cmd_pkt->trigger[0].flags.edge_type != H4032L_TRIGGER_EDGE_TYPE_DISABLED) { | |
4868f15a | 564 | sr_err("Only one trigger signal with fall/rising/edge allowed."); |
5089a143 AZ |
565 | return SR_ERR; |
566 | } | |
567 | cmd_pkt->trigger[0].flags.edge_type = H4032L_TRIGGER_EDGE_TYPE_RISE; | |
568 | cmd_pkt->trigger[0].flags.edge_signal = match->channel->index; | |
569 | break; | |
570 | case SR_TRIGGER_FALLING: | |
571 | if (cmd_pkt->trigger[0].flags.edge_type != H4032L_TRIGGER_EDGE_TYPE_DISABLED) { | |
4868f15a | 572 | sr_err("Only one trigger signal with fall/rising/edge allowed."); |
5089a143 AZ |
573 | return SR_ERR; |
574 | } | |
575 | cmd_pkt->trigger[0].flags.edge_type = H4032L_TRIGGER_EDGE_TYPE_FALL; | |
576 | cmd_pkt->trigger[0].flags.edge_signal = match->channel->index; | |
577 | break; | |
578 | case SR_TRIGGER_EDGE: | |
579 | if (cmd_pkt->trigger[0].flags.edge_type != H4032L_TRIGGER_EDGE_TYPE_DISABLED) { | |
4868f15a | 580 | sr_err("Only one trigger signal with fall/rising/edge allowed."); |
5089a143 AZ |
581 | return SR_ERR; |
582 | } | |
583 | cmd_pkt->trigger[0].flags.edge_type = H4032L_TRIGGER_EDGE_TYPE_TOGGLE; | |
584 | cmd_pkt->trigger[0].flags.edge_signal = match->channel->index; | |
585 | break; | |
586 | default: | |
4868f15a | 587 | sr_err("Unknown trigger value."); |
5089a143 AZ |
588 | return SR_ERR; |
589 | } | |
590 | ||
591 | channel = channel->next; | |
592 | } | |
593 | ||
594 | /* Compress range mask value and apply range settings. */ | |
595 | if (range_mask) { | |
596 | cmd_pkt->trigger[0].flags.data_range_enabled = 1; | |
597 | cmd_pkt->trigger[0].data_range_mask |= (range_mask); | |
598 | ||
599 | uint32_t new_range_value = 0; | |
600 | uint32_t bit_mask = 1; | |
601 | while (range_mask) { | |
602 | if ((range_mask & 1) != 0) { | |
603 | new_range_value <<= 1; | |
604 | if ((range_value & 1) != 0) | |
605 | new_range_value |= bit_mask; | |
606 | bit_mask <<= 1; | |
607 | } | |
608 | range_mask >>= 1; | |
609 | range_value >>= 1; | |
610 | } | |
611 | cmd_pkt->trigger[0].data_range_max |= range_value; | |
612 | } | |
613 | } | |
6a25fa42 | 614 | |
74c4c174 | 615 | usb_source_add(sdi->session, drvc->sr_ctx, 1000, |
5089a143 | 616 | h4032l_receive_data, sdi->driver->context); |
6a25fa42 | 617 | |
5089a143 AZ |
618 | /* Start capturing. */ |
619 | return h4032l_start(sdi); | |
6a25fa42 AZ |
620 | } |
621 | ||
5089a143 | 622 | static int dev_acquisition_stop(struct sr_dev_inst *sdi) |
6a25fa42 | 623 | { |
2958315d AV |
624 | /* Stop capturing. */ |
625 | return h4032l_stop(sdi); | |
6a25fa42 AZ |
626 | } |
627 | ||
628 | SR_PRIV struct sr_dev_driver hantek_4032l_driver_info = { | |
629 | .name = "hantek-4032l", | |
5089a143 | 630 | .longname = "Hantek 4032L", |
6a25fa42 | 631 | .api_version = 1, |
5089a143 AZ |
632 | .init = std_init, |
633 | .cleanup = std_cleanup, | |
6a25fa42 | 634 | .scan = scan, |
5089a143 AZ |
635 | .dev_list = std_dev_list, |
636 | .dev_clear = std_dev_clear, | |
6a25fa42 AZ |
637 | .config_get = config_get, |
638 | .config_set = config_set, | |
639 | .config_list = config_list, | |
640 | .dev_open = dev_open, | |
641 | .dev_close = dev_close, | |
642 | .dev_acquisition_start = dev_acquisition_start, | |
643 | .dev_acquisition_stop = dev_acquisition_stop, | |
644 | .context = NULL, | |
645 | }; | |
5089a143 | 646 | SR_REGISTER_DEV_DRIVER(hantek_4032l_driver_info); |