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Commit | Line | Data |
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28a35d8a HE |
1 | /* |
2 | * This file is part of the sigrok project. | |
3 | * | |
911f1834 UH |
4 | * Copyright (C) 2010 Håvard Espeland <gus@ping.uio.no>, |
5 | * Copyright (C) 2010 Martin Stensgård <mastensg@ping.uio.no> | |
6 | * Copyright (C) 2010 Carl Henrik Lunde <chlunde@ping.uio.no> | |
28a35d8a HE |
7 | * |
8 | * This program is free software: you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation, either version 3 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
20 | */ | |
21 | ||
911f1834 | 22 | /* |
da0918aa | 23 | * ASIX SIGMA Logic Analyzer Driver |
911f1834 UH |
24 | */ |
25 | ||
3bbd9849 UH |
26 | #include <glib.h> |
27 | #include <glib/gstdio.h> | |
28a35d8a HE |
28 | #include <ftdi.h> |
29 | #include <string.h> | |
30 | #include <zlib.h> | |
b7f09cf8 UH |
31 | #include "sigrok.h" |
32 | #include "sigrok-internal.h" | |
28a35d8a HE |
33 | #include "asix-sigma.h" |
34 | ||
35 | #define USB_VENDOR 0xa600 | |
36 | #define USB_PRODUCT 0xa000 | |
37 | #define USB_DESCRIPTION "ASIX SIGMA" | |
38 | #define USB_VENDOR_NAME "ASIX" | |
39 | #define USB_MODEL_NAME "SIGMA" | |
40 | #define USB_MODEL_VERSION "" | |
ee492173 | 41 | #define TRIGGER_TYPES "rf10" |
464d12c7 | 42 | #define NUM_PROBES 16 |
28a35d8a | 43 | |
d68e2d1a | 44 | static GSList *dev_insts = NULL; |
28a35d8a | 45 | |
28a35d8a | 46 | static uint64_t supported_samplerates[] = { |
59df0c77 UH |
47 | SR_KHZ(200), |
48 | SR_KHZ(250), | |
49 | SR_KHZ(500), | |
50 | SR_MHZ(1), | |
51 | SR_MHZ(5), | |
52 | SR_MHZ(10), | |
53 | SR_MHZ(25), | |
54 | SR_MHZ(50), | |
55 | SR_MHZ(100), | |
56 | SR_MHZ(200), | |
28a35d8a HE |
57 | 0, |
58 | }; | |
59 | ||
c37d2b1b | 60 | static const char *probe_names[NUM_PROBES + 1] = { |
464d12c7 KS |
61 | "0", |
62 | "1", | |
63 | "2", | |
64 | "3", | |
65 | "4", | |
66 | "5", | |
67 | "6", | |
68 | "7", | |
69 | "8", | |
70 | "9", | |
71 | "10", | |
72 | "11", | |
73 | "12", | |
74 | "13", | |
75 | "14", | |
76 | "15", | |
77 | NULL, | |
78 | }; | |
79 | ||
60679b18 | 80 | static struct sr_samplerates samplerates = { |
59df0c77 UH |
81 | SR_KHZ(200), |
82 | SR_MHZ(200), | |
c9140419 | 83 | SR_HZ(0), |
28a35d8a HE |
84 | supported_samplerates, |
85 | }; | |
86 | ||
87 | static int capabilities[] = { | |
5a2326a7 UH |
88 | SR_HWCAP_LOGIC_ANALYZER, |
89 | SR_HWCAP_SAMPLERATE, | |
90 | SR_HWCAP_CAPTURE_RATIO, | |
91 | SR_HWCAP_PROBECONFIG, | |
28a35d8a | 92 | |
5a2326a7 | 93 | SR_HWCAP_LIMIT_MSEC, |
28a35d8a HE |
94 | 0, |
95 | }; | |
96 | ||
fefa1800 UH |
97 | /* Force the FPGA to reboot. */ |
98 | static uint8_t suicide[] = { | |
99 | 0x84, 0x84, 0x88, 0x84, 0x88, 0x84, 0x88, 0x84, | |
100 | }; | |
101 | ||
102 | /* Prepare to upload firmware (FPGA specific). */ | |
103 | static uint8_t init[] = { | |
104 | 0x03, 0x03, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, | |
105 | }; | |
106 | ||
107 | /* Initialize the logic analyzer mode. */ | |
108 | static uint8_t logic_mode_start[] = { | |
109 | 0x00, 0x40, 0x0f, 0x25, 0x35, 0x40, | |
110 | 0x2a, 0x3a, 0x40, 0x03, 0x20, 0x38, | |
111 | }; | |
112 | ||
eec5275e | 113 | static const char *firmware_files[] = { |
a8116d76 HE |
114 | "asix-sigma-50.fw", /* 50 MHz, supports 8 bit fractions */ |
115 | "asix-sigma-100.fw", /* 100 MHz */ | |
116 | "asix-sigma-200.fw", /* 200 MHz */ | |
ed09fd07 | 117 | "asix-sigma-50sync.fw", /* Synchronous clock from pin */ |
a8116d76 | 118 | "asix-sigma-phasor.fw", /* Frequency counter */ |
f6564c8d HE |
119 | }; |
120 | ||
bb7ef793 | 121 | static int hw_stop_acquisition(int dev_index, gpointer session_data); |
6aac7737 | 122 | |
99965709 | 123 | static int sigma_read(void *buf, size_t size, struct sigma *sigma) |
28a35d8a HE |
124 | { |
125 | int ret; | |
fefa1800 | 126 | |
99965709 | 127 | ret = ftdi_read_data(&sigma->ftdic, (unsigned char *)buf, size); |
28a35d8a | 128 | if (ret < 0) { |
7b48d6e1 | 129 | sr_err("sigma: ftdi_read_data failed: %s", |
133a37bf | 130 | ftdi_get_error_string(&sigma->ftdic)); |
28a35d8a HE |
131 | } |
132 | ||
133 | return ret; | |
134 | } | |
135 | ||
99965709 | 136 | static int sigma_write(void *buf, size_t size, struct sigma *sigma) |
28a35d8a HE |
137 | { |
138 | int ret; | |
fefa1800 | 139 | |
99965709 | 140 | ret = ftdi_write_data(&sigma->ftdic, (unsigned char *)buf, size); |
28a35d8a | 141 | if (ret < 0) { |
7b48d6e1 | 142 | sr_err("sigma: ftdi_write_data failed: %s", |
133a37bf | 143 | ftdi_get_error_string(&sigma->ftdic)); |
fefa1800 | 144 | } else if ((size_t) ret != size) { |
7b48d6e1 | 145 | sr_err("sigma: ftdi_write_data did not complete write\n"); |
28a35d8a HE |
146 | } |
147 | ||
148 | return ret; | |
149 | } | |
150 | ||
99965709 HE |
151 | static int sigma_write_register(uint8_t reg, uint8_t *data, size_t len, |
152 | struct sigma *sigma) | |
28a35d8a HE |
153 | { |
154 | size_t i; | |
155 | uint8_t buf[len + 2]; | |
156 | int idx = 0; | |
157 | ||
158 | buf[idx++] = REG_ADDR_LOW | (reg & 0xf); | |
159 | buf[idx++] = REG_ADDR_HIGH | (reg >> 4); | |
160 | ||
fefa1800 | 161 | for (i = 0; i < len; ++i) { |
28a35d8a HE |
162 | buf[idx++] = REG_DATA_LOW | (data[i] & 0xf); |
163 | buf[idx++] = REG_DATA_HIGH_WRITE | (data[i] >> 4); | |
164 | } | |
165 | ||
99965709 | 166 | return sigma_write(buf, idx, sigma); |
28a35d8a HE |
167 | } |
168 | ||
99965709 | 169 | static int sigma_set_register(uint8_t reg, uint8_t value, struct sigma *sigma) |
28a35d8a | 170 | { |
99965709 | 171 | return sigma_write_register(reg, &value, 1, sigma); |
28a35d8a HE |
172 | } |
173 | ||
99965709 HE |
174 | static int sigma_read_register(uint8_t reg, uint8_t *data, size_t len, |
175 | struct sigma *sigma) | |
28a35d8a HE |
176 | { |
177 | uint8_t buf[3]; | |
fefa1800 | 178 | |
28a35d8a HE |
179 | buf[0] = REG_ADDR_LOW | (reg & 0xf); |
180 | buf[1] = REG_ADDR_HIGH | (reg >> 4); | |
28a35d8a HE |
181 | buf[2] = REG_READ_ADDR; |
182 | ||
99965709 | 183 | sigma_write(buf, sizeof(buf), sigma); |
28a35d8a | 184 | |
99965709 | 185 | return sigma_read(data, len, sigma); |
28a35d8a HE |
186 | } |
187 | ||
99965709 | 188 | static uint8_t sigma_get_register(uint8_t reg, struct sigma *sigma) |
28a35d8a HE |
189 | { |
190 | uint8_t value; | |
fefa1800 | 191 | |
99965709 | 192 | if (1 != sigma_read_register(reg, &value, 1, sigma)) { |
7b48d6e1 | 193 | sr_err("sigma: sigma_get_register: 1 byte expected"); |
28a35d8a HE |
194 | return 0; |
195 | } | |
196 | ||
197 | return value; | |
198 | } | |
199 | ||
99965709 HE |
200 | static int sigma_read_pos(uint32_t *stoppos, uint32_t *triggerpos, |
201 | struct sigma *sigma) | |
28a35d8a HE |
202 | { |
203 | uint8_t buf[] = { | |
204 | REG_ADDR_LOW | READ_TRIGGER_POS_LOW, | |
205 | ||
206 | REG_READ_ADDR | NEXT_REG, | |
207 | REG_READ_ADDR | NEXT_REG, | |
208 | REG_READ_ADDR | NEXT_REG, | |
209 | REG_READ_ADDR | NEXT_REG, | |
210 | REG_READ_ADDR | NEXT_REG, | |
211 | REG_READ_ADDR | NEXT_REG, | |
212 | }; | |
28a35d8a HE |
213 | uint8_t result[6]; |
214 | ||
99965709 | 215 | sigma_write(buf, sizeof(buf), sigma); |
28a35d8a | 216 | |
99965709 | 217 | sigma_read(result, sizeof(result), sigma); |
28a35d8a HE |
218 | |
219 | *triggerpos = result[0] | (result[1] << 8) | (result[2] << 16); | |
220 | *stoppos = result[3] | (result[4] << 8) | (result[5] << 16); | |
221 | ||
57bbf56b HE |
222 | /* Not really sure why this must be done, but according to spec. */ |
223 | if ((--*stoppos & 0x1ff) == 0x1ff) | |
224 | stoppos -= 64; | |
225 | ||
226 | if ((*--triggerpos & 0x1ff) == 0x1ff) | |
227 | triggerpos -= 64; | |
228 | ||
28a35d8a HE |
229 | return 1; |
230 | } | |
231 | ||
99965709 HE |
232 | static int sigma_read_dram(uint16_t startchunk, size_t numchunks, |
233 | uint8_t *data, struct sigma *sigma) | |
28a35d8a HE |
234 | { |
235 | size_t i; | |
236 | uint8_t buf[4096]; | |
237 | int idx = 0; | |
238 | ||
fefa1800 | 239 | /* Send the startchunk. Index start with 1. */ |
28a35d8a HE |
240 | buf[0] = startchunk >> 8; |
241 | buf[1] = startchunk & 0xff; | |
99965709 | 242 | sigma_write_register(WRITE_MEMROW, buf, 2, sigma); |
28a35d8a | 243 | |
fefa1800 | 244 | /* Read the DRAM. */ |
28a35d8a HE |
245 | buf[idx++] = REG_DRAM_BLOCK; |
246 | buf[idx++] = REG_DRAM_WAIT_ACK; | |
247 | ||
248 | for (i = 0; i < numchunks; ++i) { | |
fefa1800 UH |
249 | /* Alternate bit to copy from DRAM to cache. */ |
250 | if (i != (numchunks - 1)) | |
251 | buf[idx++] = REG_DRAM_BLOCK | (((i + 1) % 2) << 4); | |
28a35d8a HE |
252 | |
253 | buf[idx++] = REG_DRAM_BLOCK_DATA | ((i % 2) << 4); | |
254 | ||
fefa1800 | 255 | if (i != (numchunks - 1)) |
28a35d8a HE |
256 | buf[idx++] = REG_DRAM_WAIT_ACK; |
257 | } | |
258 | ||
99965709 | 259 | sigma_write(buf, idx, sigma); |
28a35d8a | 260 | |
99965709 | 261 | return sigma_read(data, numchunks * CHUNK_SIZE, sigma); |
28a35d8a HE |
262 | } |
263 | ||
4ae1f451 | 264 | /* Upload trigger look-up tables to Sigma. */ |
99965709 | 265 | static int sigma_write_trigger_lut(struct triggerlut *lut, struct sigma *sigma) |
ee492173 HE |
266 | { |
267 | int i; | |
268 | uint8_t tmp[2]; | |
269 | uint16_t bit; | |
270 | ||
271 | /* Transpose the table and send to Sigma. */ | |
272 | for (i = 0; i < 16; ++i) { | |
273 | bit = 1 << i; | |
274 | ||
275 | tmp[0] = tmp[1] = 0; | |
276 | ||
277 | if (lut->m2d[0] & bit) | |
278 | tmp[0] |= 0x01; | |
279 | if (lut->m2d[1] & bit) | |
280 | tmp[0] |= 0x02; | |
281 | if (lut->m2d[2] & bit) | |
282 | tmp[0] |= 0x04; | |
283 | if (lut->m2d[3] & bit) | |
284 | tmp[0] |= 0x08; | |
285 | ||
286 | if (lut->m3 & bit) | |
287 | tmp[0] |= 0x10; | |
288 | if (lut->m3s & bit) | |
289 | tmp[0] |= 0x20; | |
290 | if (lut->m4 & bit) | |
291 | tmp[0] |= 0x40; | |
292 | ||
293 | if (lut->m0d[0] & bit) | |
294 | tmp[1] |= 0x01; | |
295 | if (lut->m0d[1] & bit) | |
296 | tmp[1] |= 0x02; | |
297 | if (lut->m0d[2] & bit) | |
298 | tmp[1] |= 0x04; | |
299 | if (lut->m0d[3] & bit) | |
300 | tmp[1] |= 0x08; | |
301 | ||
302 | if (lut->m1d[0] & bit) | |
303 | tmp[1] |= 0x10; | |
304 | if (lut->m1d[1] & bit) | |
305 | tmp[1] |= 0x20; | |
306 | if (lut->m1d[2] & bit) | |
307 | tmp[1] |= 0x40; | |
308 | if (lut->m1d[3] & bit) | |
309 | tmp[1] |= 0x80; | |
310 | ||
99965709 HE |
311 | sigma_write_register(WRITE_TRIGGER_SELECT0, tmp, sizeof(tmp), |
312 | sigma); | |
313 | sigma_set_register(WRITE_TRIGGER_SELECT1, 0x30 | i, sigma); | |
ee492173 HE |
314 | } |
315 | ||
316 | /* Send the parameters */ | |
317 | sigma_write_register(WRITE_TRIGGER_SELECT0, (uint8_t *) &lut->params, | |
99965709 | 318 | sizeof(lut->params), sigma); |
ee492173 | 319 | |
e46b8fb1 | 320 | return SR_OK; |
ee492173 HE |
321 | } |
322 | ||
fefa1800 | 323 | /* Generate the bitbang stream for programming the FPGA. */ |
28a35d8a | 324 | static int bin2bitbang(const char *filename, |
fefa1800 | 325 | unsigned char **buf, size_t *buf_size) |
28a35d8a | 326 | { |
fefa1800 | 327 | FILE *f; |
28a35d8a HE |
328 | long file_size; |
329 | unsigned long offset = 0; | |
330 | unsigned char *p; | |
331 | uint8_t *compressed_buf, *firmware; | |
332 | uLongf csize, fwsize; | |
333 | const int buffer_size = 65536; | |
334 | size_t i; | |
fefa1800 UH |
335 | int c, ret, bit, v; |
336 | uint32_t imm = 0x3f6df2ab; | |
28a35d8a | 337 | |
868d8cef | 338 | f = g_fopen(filename, "rb"); |
28a35d8a | 339 | if (!f) { |
7b48d6e1 | 340 | sr_err("sigma: g_fopen(\"%s\", \"rb\")", filename); |
b53738ba | 341 | return SR_ERR; |
28a35d8a HE |
342 | } |
343 | ||
344 | if (-1 == fseek(f, 0, SEEK_END)) { | |
7b48d6e1 | 345 | sr_err("sigma: fseek on %s failed", filename); |
28a35d8a | 346 | fclose(f); |
b53738ba | 347 | return SR_ERR; |
28a35d8a HE |
348 | } |
349 | ||
350 | file_size = ftell(f); | |
351 | ||
352 | fseek(f, 0, SEEK_SET); | |
353 | ||
b53738ba | 354 | if (!(compressed_buf = g_try_malloc(file_size))) { |
340cfac0 | 355 | sr_err("sigma: %s: compressed_buf malloc failed", __func__); |
12ad53f5 | 356 | fclose(f); |
b53738ba UH |
357 | return SR_ERR_MALLOC; |
358 | } | |
28a35d8a | 359 | |
b53738ba | 360 | if (!(firmware = g_try_malloc(buffer_size))) { |
340cfac0 | 361 | sr_err("sigma: %s: firmware malloc failed", __func__); |
12ad53f5 UH |
362 | fclose(f); |
363 | g_free(compressed_buf); | |
b53738ba | 364 | return SR_ERR_MALLOC; |
28a35d8a HE |
365 | } |
366 | ||
28a35d8a HE |
367 | csize = 0; |
368 | while ((c = getc(f)) != EOF) { | |
369 | imm = (imm + 0xa853753) % 177 + (imm * 0x8034052); | |
370 | compressed_buf[csize++] = c ^ imm; | |
371 | } | |
372 | fclose(f); | |
373 | ||
374 | fwsize = buffer_size; | |
375 | ret = uncompress(firmware, &fwsize, compressed_buf, csize); | |
376 | if (ret < 0) { | |
377 | g_free(compressed_buf); | |
378 | g_free(firmware); | |
7b48d6e1 UH |
379 | sr_err("sigma: Could not unpack Sigma firmware. " |
380 | "(Error %d)\n", ret); | |
b53738ba | 381 | return SR_ERR; |
28a35d8a HE |
382 | } |
383 | ||
384 | g_free(compressed_buf); | |
385 | ||
386 | *buf_size = fwsize * 2 * 8; | |
387 | ||
b53738ba | 388 | *buf = p = (unsigned char *)g_try_malloc(*buf_size); |
28a35d8a | 389 | if (!p) { |
340cfac0 | 390 | sr_err("sigma: %s: buf/p malloc failed", __func__); |
12ad53f5 UH |
391 | g_free(compressed_buf); |
392 | g_free(firmware); | |
b53738ba | 393 | return SR_ERR_MALLOC; |
28a35d8a HE |
394 | } |
395 | ||
396 | for (i = 0; i < fwsize; ++i) { | |
28a35d8a | 397 | for (bit = 7; bit >= 0; --bit) { |
fefa1800 | 398 | v = firmware[i] & 1 << bit ? 0x40 : 0x00; |
28a35d8a HE |
399 | p[offset++] = v | 0x01; |
400 | p[offset++] = v; | |
401 | } | |
402 | } | |
403 | ||
404 | g_free(firmware); | |
405 | ||
406 | if (offset != *buf_size) { | |
407 | g_free(*buf); | |
7b48d6e1 | 408 | sr_err("sigma: Error reading firmware %s " |
133a37bf UH |
409 | "offset=%ld, file_size=%ld, buf_size=%zd\n", |
410 | filename, offset, file_size, *buf_size); | |
28a35d8a | 411 | |
b53738ba | 412 | return SR_ERR; |
28a35d8a HE |
413 | } |
414 | ||
b53738ba | 415 | return SR_OK; |
28a35d8a HE |
416 | } |
417 | ||
bb7ef793 | 418 | static int hw_init(const char *devinfo) |
28a35d8a | 419 | { |
d68e2d1a | 420 | struct sr_dev_inst *sdi; |
b53738ba | 421 | struct sigma *sigma; |
28a35d8a | 422 | |
b53738ba | 423 | /* Avoid compiler warnings. */ |
bb7ef793 | 424 | (void)devinfo; |
28a35d8a | 425 | |
b53738ba | 426 | if (!(sigma = g_try_malloc(sizeof(struct sigma)))) { |
340cfac0 | 427 | sr_err("sigma: %s: sigma malloc failed", __func__); |
b53738ba UH |
428 | return 0; /* FIXME: Should be SR_ERR_MALLOC. */ |
429 | } | |
99965709 HE |
430 | |
431 | ftdi_init(&sigma->ftdic); | |
28a35d8a | 432 | |
fefa1800 | 433 | /* Look for SIGMAs. */ |
99965709 | 434 | if (ftdi_usb_open_desc(&sigma->ftdic, USB_VENDOR, USB_PRODUCT, |
fefa1800 | 435 | USB_DESCRIPTION, NULL) < 0) |
99965709 HE |
436 | goto free; |
437 | ||
438 | sigma->cur_samplerate = 0; | |
9c939c51 | 439 | sigma->period_ps = 0; |
99965709 HE |
440 | sigma->limit_msec = 0; |
441 | sigma->cur_firmware = -1; | |
442 | sigma->num_probes = 0; | |
443 | sigma->samples_per_event = 0; | |
444 | sigma->capture_ratio = 50; | |
5b5ea7c6 | 445 | sigma->use_triggers = 0; |
28a35d8a | 446 | |
fefa1800 | 447 | /* Register SIGMA device. */ |
d68e2d1a UH |
448 | if (!(sdi = sr_dev_inst_new(0, SR_ST_INITIALIZING, USB_VENDOR_NAME, |
449 | USB_MODEL_NAME, USB_MODEL_VERSION))) { | |
450 | sr_err("sigma: %s: sdi was NULL", __func__); | |
99965709 | 451 | goto free; |
d68e2d1a | 452 | } |
99965709 HE |
453 | |
454 | sdi->priv = sigma; | |
28a35d8a | 455 | |
d68e2d1a | 456 | dev_insts = g_slist_append(dev_insts, sdi); |
28a35d8a | 457 | |
fefa1800 | 458 | /* We will open the device again when we need it. */ |
99965709 | 459 | ftdi_usb_close(&sigma->ftdic); |
28a35d8a HE |
460 | |
461 | return 1; | |
99965709 | 462 | free: |
12ad53f5 | 463 | g_free(sigma); |
99965709 | 464 | return 0; |
28a35d8a HE |
465 | } |
466 | ||
99965709 | 467 | static int upload_firmware(int firmware_idx, struct sigma *sigma) |
28a35d8a HE |
468 | { |
469 | int ret; | |
470 | unsigned char *buf; | |
471 | unsigned char pins; | |
472 | size_t buf_size; | |
28a35d8a | 473 | unsigned char result[32]; |
e8397563 | 474 | char firmware_path[128]; |
28a35d8a | 475 | |
fefa1800 | 476 | /* Make sure it's an ASIX SIGMA. */ |
99965709 | 477 | if ((ret = ftdi_usb_open_desc(&sigma->ftdic, |
28a35d8a | 478 | USB_VENDOR, USB_PRODUCT, USB_DESCRIPTION, NULL)) < 0) { |
7b48d6e1 | 479 | sr_err("sigma: ftdi_usb_open failed: %s", |
133a37bf | 480 | ftdi_get_error_string(&sigma->ftdic)); |
28a35d8a HE |
481 | return 0; |
482 | } | |
483 | ||
99965709 | 484 | if ((ret = ftdi_set_bitmode(&sigma->ftdic, 0xdf, BITMODE_BITBANG)) < 0) { |
7b48d6e1 | 485 | sr_err("sigma: ftdi_set_bitmode failed: %s", |
133a37bf | 486 | ftdi_get_error_string(&sigma->ftdic)); |
28a35d8a HE |
487 | return 0; |
488 | } | |
489 | ||
fefa1800 | 490 | /* Four times the speed of sigmalogan - Works well. */ |
99965709 | 491 | if ((ret = ftdi_set_baudrate(&sigma->ftdic, 750000)) < 0) { |
7b48d6e1 | 492 | sr_err("sigma: ftdi_set_baudrate failed: %s", |
133a37bf | 493 | ftdi_get_error_string(&sigma->ftdic)); |
28a35d8a HE |
494 | return 0; |
495 | } | |
496 | ||
fefa1800 | 497 | /* Force the FPGA to reboot. */ |
99965709 HE |
498 | sigma_write(suicide, sizeof(suicide), sigma); |
499 | sigma_write(suicide, sizeof(suicide), sigma); | |
500 | sigma_write(suicide, sizeof(suicide), sigma); | |
501 | sigma_write(suicide, sizeof(suicide), sigma); | |
28a35d8a | 502 | |
fefa1800 | 503 | /* Prepare to upload firmware (FPGA specific). */ |
99965709 | 504 | sigma_write(init, sizeof(init), sigma); |
28a35d8a | 505 | |
99965709 | 506 | ftdi_usb_purge_buffers(&sigma->ftdic); |
28a35d8a | 507 | |
fefa1800 | 508 | /* Wait until the FPGA asserts INIT_B. */ |
28a35d8a | 509 | while (1) { |
99965709 | 510 | ret = sigma_read(result, 1, sigma); |
28a35d8a HE |
511 | if (result[0] & 0x20) |
512 | break; | |
513 | } | |
514 | ||
9ddb2a12 | 515 | /* Prepare firmware. */ |
e8397563 | 516 | snprintf(firmware_path, sizeof(firmware_path), "%s/%s", FIRMWARE_DIR, |
f6564c8d HE |
517 | firmware_files[firmware_idx]); |
518 | ||
b53738ba | 519 | if ((ret = bin2bitbang(firmware_path, &buf, &buf_size)) != SR_OK) { |
7b48d6e1 | 520 | sr_err("sigma: An error occured while reading the firmware: %s", |
133a37bf | 521 | firmware_path); |
b53738ba | 522 | return ret; |
28a35d8a HE |
523 | } |
524 | ||
fefa1800 | 525 | /* Upload firmare. */ |
99965709 | 526 | sigma_write(buf, buf_size, sigma); |
28a35d8a HE |
527 | |
528 | g_free(buf); | |
529 | ||
99965709 | 530 | if ((ret = ftdi_set_bitmode(&sigma->ftdic, 0x00, BITMODE_RESET)) < 0) { |
7b48d6e1 | 531 | sr_err("sigma: ftdi_set_bitmode failed: %s", |
133a37bf | 532 | ftdi_get_error_string(&sigma->ftdic)); |
e46b8fb1 | 533 | return SR_ERR; |
28a35d8a HE |
534 | } |
535 | ||
99965709 | 536 | ftdi_usb_purge_buffers(&sigma->ftdic); |
28a35d8a | 537 | |
fefa1800 | 538 | /* Discard garbage. */ |
99965709 | 539 | while (1 == sigma_read(&pins, 1, sigma)) |
28a35d8a HE |
540 | ; |
541 | ||
fefa1800 | 542 | /* Initialize the logic analyzer mode. */ |
99965709 | 543 | sigma_write(logic_mode_start, sizeof(logic_mode_start), sigma); |
28a35d8a | 544 | |
fefa1800 | 545 | /* Expect a 3 byte reply. */ |
99965709 | 546 | ret = sigma_read(result, 3, sigma); |
28a35d8a HE |
547 | if (ret != 3 || |
548 | result[0] != 0xa6 || result[1] != 0x55 || result[2] != 0xaa) { | |
7b48d6e1 | 549 | sr_err("sigma: Configuration failed. Invalid reply received."); |
e46b8fb1 | 550 | return SR_ERR; |
28a35d8a HE |
551 | } |
552 | ||
99965709 | 553 | sigma->cur_firmware = firmware_idx; |
f6564c8d | 554 | |
e46b8fb1 | 555 | return SR_OK; |
f6564c8d HE |
556 | } |
557 | ||
bb7ef793 | 558 | static int hw_opendev(int dev_index) |
f6564c8d | 559 | { |
d68e2d1a | 560 | struct sr_dev_inst *sdi; |
99965709 | 561 | struct sigma *sigma; |
f6564c8d HE |
562 | int ret; |
563 | ||
bb7ef793 | 564 | if (!(sdi = sr_dev_inst_get(dev_insts, dev_index))) |
e46b8fb1 | 565 | return SR_ERR; |
99965709 HE |
566 | |
567 | sigma = sdi->priv; | |
568 | ||
9ddb2a12 | 569 | /* Make sure it's an ASIX SIGMA. */ |
99965709 | 570 | if ((ret = ftdi_usb_open_desc(&sigma->ftdic, |
f6564c8d HE |
571 | USB_VENDOR, USB_PRODUCT, USB_DESCRIPTION, NULL)) < 0) { |
572 | ||
7b48d6e1 | 573 | sr_err("sigma: ftdi_usb_open failed: %s", |
133a37bf | 574 | ftdi_get_error_string(&sigma->ftdic)); |
f6564c8d HE |
575 | |
576 | return 0; | |
577 | } | |
28a35d8a | 578 | |
5a2326a7 | 579 | sdi->status = SR_ST_ACTIVE; |
28a35d8a | 580 | |
e46b8fb1 | 581 | return SR_OK; |
f6564c8d HE |
582 | } |
583 | ||
d68e2d1a | 584 | static int set_samplerate(struct sr_dev_inst *sdi, uint64_t samplerate) |
f6564c8d | 585 | { |
e8397563 | 586 | int i, ret; |
99965709 | 587 | struct sigma *sigma = sdi->priv; |
f6564c8d HE |
588 | |
589 | for (i = 0; supported_samplerates[i]; i++) { | |
590 | if (supported_samplerates[i] == samplerate) | |
591 | break; | |
592 | } | |
593 | if (supported_samplerates[i] == 0) | |
e46b8fb1 | 594 | return SR_ERR_SAMPLERATE; |
f6564c8d | 595 | |
59df0c77 | 596 | if (samplerate <= SR_MHZ(50)) { |
99965709 HE |
597 | ret = upload_firmware(0, sigma); |
598 | sigma->num_probes = 16; | |
e8397563 | 599 | } |
59df0c77 | 600 | if (samplerate == SR_MHZ(100)) { |
99965709 HE |
601 | ret = upload_firmware(1, sigma); |
602 | sigma->num_probes = 8; | |
f78898e9 | 603 | } |
59df0c77 | 604 | else if (samplerate == SR_MHZ(200)) { |
99965709 HE |
605 | ret = upload_firmware(2, sigma); |
606 | sigma->num_probes = 4; | |
f78898e9 | 607 | } |
f6564c8d | 608 | |
99965709 | 609 | sigma->cur_samplerate = samplerate; |
9c939c51 | 610 | sigma->period_ps = 1000000000000 / samplerate; |
99965709 HE |
611 | sigma->samples_per_event = 16 / sigma->num_probes; |
612 | sigma->state.state = SIGMA_IDLE; | |
f6564c8d | 613 | |
7b48d6e1 | 614 | sr_info("sigma: Firmware uploaded"); |
28a35d8a | 615 | |
e8397563 | 616 | return ret; |
28a35d8a HE |
617 | } |
618 | ||
c53d793f HE |
619 | /* |
620 | * In 100 and 200 MHz mode, only a single pin rising/falling can be | |
621 | * set as trigger. In other modes, two rising/falling triggers can be set, | |
622 | * in addition to value/mask trigger for any number of probes. | |
623 | * | |
624 | * The Sigma supports complex triggers using boolean expressions, but this | |
625 | * has not been implemented yet. | |
626 | */ | |
d68e2d1a | 627 | static int configure_probes(struct sr_dev_inst *sdi, GSList *probes) |
57bbf56b | 628 | { |
99965709 | 629 | struct sigma *sigma = sdi->priv; |
1afe8989 | 630 | struct sr_probe *probe; |
57bbf56b HE |
631 | GSList *l; |
632 | int trigger_set = 0; | |
a42aec7f | 633 | int probebit; |
57bbf56b | 634 | |
99965709 | 635 | memset(&sigma->trigger, 0, sizeof(struct sigma_trigger)); |
eec5275e | 636 | |
57bbf56b | 637 | for (l = probes; l; l = l->next) { |
1afe8989 | 638 | probe = (struct sr_probe *)l->data; |
a42aec7f | 639 | probebit = 1 << (probe->index - 1); |
57bbf56b HE |
640 | |
641 | if (!probe->enabled || !probe->trigger) | |
642 | continue; | |
643 | ||
59df0c77 | 644 | if (sigma->cur_samplerate >= SR_MHZ(100)) { |
c53d793f | 645 | /* Fast trigger support. */ |
ee492173 | 646 | if (trigger_set) { |
7b48d6e1 | 647 | sr_err("sigma: ASIX SIGMA only supports a single " |
133a37bf | 648 | "pin trigger in 100 and 200MHz mode."); |
e46b8fb1 | 649 | return SR_ERR; |
ee492173 HE |
650 | } |
651 | if (probe->trigger[0] == 'f') | |
99965709 | 652 | sigma->trigger.fallingmask |= probebit; |
ee492173 | 653 | else if (probe->trigger[0] == 'r') |
99965709 | 654 | sigma->trigger.risingmask |= probebit; |
ee492173 | 655 | else { |
7b48d6e1 | 656 | sr_err("sigma: ASIX SIGMA only supports " |
133a37bf UH |
657 | "rising/falling trigger in 100 " |
658 | "and 200MHz mode."); | |
e46b8fb1 | 659 | return SR_ERR; |
ee492173 | 660 | } |
57bbf56b | 661 | |
c53d793f | 662 | ++trigger_set; |
ee492173 | 663 | } else { |
c53d793f HE |
664 | /* Simple trigger support (event). */ |
665 | if (probe->trigger[0] == '1') { | |
99965709 HE |
666 | sigma->trigger.simplevalue |= probebit; |
667 | sigma->trigger.simplemask |= probebit; | |
c53d793f HE |
668 | } |
669 | else if (probe->trigger[0] == '0') { | |
99965709 HE |
670 | sigma->trigger.simplevalue &= ~probebit; |
671 | sigma->trigger.simplemask |= probebit; | |
c53d793f HE |
672 | } |
673 | else if (probe->trigger[0] == 'f') { | |
99965709 | 674 | sigma->trigger.fallingmask |= probebit; |
c53d793f HE |
675 | ++trigger_set; |
676 | } | |
677 | else if (probe->trigger[0] == 'r') { | |
99965709 | 678 | sigma->trigger.risingmask |= probebit; |
c53d793f HE |
679 | ++trigger_set; |
680 | } | |
ee492173 | 681 | |
98b8cbc1 HE |
682 | /* |
683 | * Actually, Sigma supports 2 rising/falling triggers, | |
684 | * but they are ORed and the current trigger syntax | |
685 | * does not permit ORed triggers. | |
686 | */ | |
687 | if (trigger_set > 1) { | |
7b48d6e1 UH |
688 | sr_err("sigma: ASIX SIGMA only supports 1 " |
689 | "rising/falling triggers."); | |
e46b8fb1 | 690 | return SR_ERR; |
ee492173 | 691 | } |
ee492173 | 692 | } |
5b5ea7c6 HE |
693 | |
694 | if (trigger_set) | |
695 | sigma->use_triggers = 1; | |
57bbf56b HE |
696 | } |
697 | ||
e46b8fb1 | 698 | return SR_OK; |
57bbf56b HE |
699 | } |
700 | ||
bb7ef793 | 701 | static int hw_closedev(int dev_index) |
28a35d8a | 702 | { |
d68e2d1a | 703 | struct sr_dev_inst *sdi; |
99965709 | 704 | struct sigma *sigma; |
28a35d8a | 705 | |
bb7ef793 | 706 | if (!(sdi = sr_dev_inst_get(dev_insts, dev_index))) { |
340cfac0 | 707 | sr_err("sigma: %s: sdi was NULL", __func__); |
697785d1 UH |
708 | return SR_ERR; /* TODO: SR_ERR_ARG? */ |
709 | } | |
9be9893e | 710 | |
697785d1 | 711 | if (!(sigma = sdi->priv)) { |
340cfac0 | 712 | sr_err("sigma: %s: sdi->priv was NULL", __func__); |
697785d1 | 713 | return SR_ERR; /* TODO: SR_ERR_ARG? */ |
9be9893e | 714 | } |
697785d1 UH |
715 | |
716 | /* TODO */ | |
717 | if (sdi->status == SR_ST_ACTIVE) | |
718 | ftdi_usb_close(&sigma->ftdic); | |
719 | ||
720 | sdi->status = SR_ST_INACTIVE; | |
721 | ||
722 | return SR_OK; | |
28a35d8a HE |
723 | } |
724 | ||
57ab7d9f | 725 | static int hw_cleanup(void) |
28a35d8a | 726 | { |
99965709 | 727 | GSList *l; |
d68e2d1a | 728 | struct sr_dev_inst *sdi; |
57ab7d9f | 729 | int ret = SR_OK; |
99965709 HE |
730 | |
731 | /* Properly close all devices. */ | |
d68e2d1a | 732 | for (l = dev_insts; l; l = l->next) { |
57ab7d9f UH |
733 | if (!(sdi = l->data)) { |
734 | /* Log error, but continue cleaning up the rest. */ | |
7b48d6e1 | 735 | sr_err("sigma: %s: sdi was NULL, continuing", __func__); |
57ab7d9f UH |
736 | ret = SR_ERR_BUG; |
737 | continue; | |
738 | } | |
d3683c42 | 739 | sr_dev_inst_free(sdi); |
99965709 | 740 | } |
d68e2d1a UH |
741 | g_slist_free(dev_insts); |
742 | dev_insts = NULL; | |
57ab7d9f UH |
743 | |
744 | return ret; | |
28a35d8a HE |
745 | } |
746 | ||
bb7ef793 | 747 | static void *hw_get_dev_info(int dev_index, int dev_info_id) |
28a35d8a | 748 | { |
d68e2d1a | 749 | struct sr_dev_inst *sdi; |
99965709 | 750 | struct sigma *sigma; |
28a35d8a HE |
751 | void *info = NULL; |
752 | ||
bb7ef793 | 753 | if (!(sdi = sr_dev_inst_get(dev_insts, dev_index))) { |
7b48d6e1 | 754 | sr_err("sigma: %s: sdi was NULL", __func__); |
28a35d8a HE |
755 | return NULL; |
756 | } | |
757 | ||
99965709 HE |
758 | sigma = sdi->priv; |
759 | ||
bb7ef793 | 760 | switch (dev_info_id) { |
5a2326a7 | 761 | case SR_DI_INSTANCE: |
28a35d8a HE |
762 | info = sdi; |
763 | break; | |
5a2326a7 | 764 | case SR_DI_NUM_PROBES: |
464d12c7 KS |
765 | info = GINT_TO_POINTER(NUM_PROBES); |
766 | break; | |
767 | case SR_DI_PROBE_NAMES: | |
768 | info = probe_names; | |
28a35d8a | 769 | break; |
5a2326a7 | 770 | case SR_DI_SAMPLERATES: |
28a35d8a HE |
771 | info = &samplerates; |
772 | break; | |
5a2326a7 | 773 | case SR_DI_TRIGGER_TYPES: |
57bbf56b | 774 | info = (char *)TRIGGER_TYPES; |
28a35d8a | 775 | break; |
5a2326a7 | 776 | case SR_DI_CUR_SAMPLERATE: |
99965709 | 777 | info = &sigma->cur_samplerate; |
28a35d8a HE |
778 | break; |
779 | } | |
780 | ||
781 | return info; | |
782 | } | |
783 | ||
bb7ef793 | 784 | static int hw_get_status(int dev_index) |
28a35d8a | 785 | { |
d68e2d1a | 786 | struct sr_dev_inst *sdi; |
28a35d8a | 787 | |
bb7ef793 | 788 | sdi = sr_dev_inst_get(dev_insts, dev_index); |
28a35d8a HE |
789 | if (sdi) |
790 | return sdi->status; | |
791 | else | |
5a2326a7 | 792 | return SR_ST_NOT_FOUND; |
28a35d8a HE |
793 | } |
794 | ||
28a35d8a HE |
795 | static int *hw_get_capabilities(void) |
796 | { | |
797 | return capabilities; | |
798 | } | |
799 | ||
bb7ef793 | 800 | static int hw_set_configuration(int dev_index, int capability, void *value) |
28a35d8a | 801 | { |
d68e2d1a | 802 | struct sr_dev_inst *sdi; |
99965709 | 803 | struct sigma *sigma; |
28a35d8a | 804 | int ret; |
f6564c8d | 805 | |
bb7ef793 | 806 | if (!(sdi = sr_dev_inst_get(dev_insts, dev_index))) |
e46b8fb1 | 807 | return SR_ERR; |
28a35d8a | 808 | |
99965709 HE |
809 | sigma = sdi->priv; |
810 | ||
5a2326a7 | 811 | if (capability == SR_HWCAP_SAMPLERATE) { |
f6564c8d | 812 | ret = set_samplerate(sdi, *(uint64_t*) value); |
5a2326a7 | 813 | } else if (capability == SR_HWCAP_PROBECONFIG) { |
99965709 | 814 | ret = configure_probes(sdi, value); |
5a2326a7 | 815 | } else if (capability == SR_HWCAP_LIMIT_MSEC) { |
94ba4bd6 HE |
816 | sigma->limit_msec = *(uint64_t*) value; |
817 | if (sigma->limit_msec > 0) | |
e46b8fb1 | 818 | ret = SR_OK; |
94ba4bd6 | 819 | else |
e46b8fb1 | 820 | ret = SR_ERR; |
5a2326a7 | 821 | } else if (capability == SR_HWCAP_CAPTURE_RATIO) { |
94ba4bd6 HE |
822 | sigma->capture_ratio = *(uint64_t*) value; |
823 | if (sigma->capture_ratio < 0 || sigma->capture_ratio > 100) | |
e46b8fb1 | 824 | ret = SR_ERR; |
94ba4bd6 | 825 | else |
e46b8fb1 | 826 | ret = SR_OK; |
28a35d8a | 827 | } else { |
e46b8fb1 | 828 | ret = SR_ERR; |
28a35d8a HE |
829 | } |
830 | ||
831 | return ret; | |
832 | } | |
833 | ||
36b1c8e6 HE |
834 | /* Software trigger to determine exact trigger position. */ |
835 | static int get_trigger_offset(uint16_t *samples, uint16_t last_sample, | |
836 | struct sigma_trigger *t) | |
837 | { | |
838 | int i; | |
839 | ||
840 | for (i = 0; i < 8; ++i) { | |
841 | if (i > 0) | |
842 | last_sample = samples[i-1]; | |
843 | ||
844 | /* Simple triggers. */ | |
845 | if ((samples[i] & t->simplemask) != t->simplevalue) | |
846 | continue; | |
847 | ||
848 | /* Rising edge. */ | |
849 | if ((last_sample & t->risingmask) != 0 || (samples[i] & | |
850 | t->risingmask) != t->risingmask) | |
851 | continue; | |
852 | ||
853 | /* Falling edge. */ | |
bdfc7a89 HE |
854 | if ((last_sample & t->fallingmask) != t->fallingmask || |
855 | (samples[i] & t->fallingmask) != 0) | |
36b1c8e6 HE |
856 | continue; |
857 | ||
858 | break; | |
859 | } | |
860 | ||
861 | /* If we did not match, return original trigger pos. */ | |
862 | return i & 0x7; | |
863 | } | |
864 | ||
28a35d8a | 865 | /* |
fefa1800 UH |
866 | * Decode chunk of 1024 bytes, 64 clusters, 7 events per cluster. |
867 | * Each event is 20ns apart, and can contain multiple samples. | |
f78898e9 HE |
868 | * |
869 | * For 200 MHz, events contain 4 samples for each channel, spread 5 ns apart. | |
870 | * For 100 MHz, events contain 2 samples for each channel, spread 10 ns apart. | |
871 | * For 50 MHz and below, events contain one sample for each channel, | |
872 | * spread 20 ns apart. | |
28a35d8a HE |
873 | */ |
874 | static int decode_chunk_ts(uint8_t *buf, uint16_t *lastts, | |
88c51afe | 875 | uint16_t *lastsample, int triggerpos, |
9c939c51 | 876 | uint16_t limit_chunk, void *session_data) |
28a35d8a | 877 | { |
d68e2d1a | 878 | struct sr_dev_inst *sdi = session_data; |
99965709 | 879 | struct sigma *sigma = sdi->priv; |
fefa1800 | 880 | uint16_t tsdiff, ts; |
99965709 | 881 | uint16_t samples[65536 * sigma->samples_per_event]; |
b9c735a2 | 882 | struct sr_datafeed_packet packet; |
9c939c51 | 883 | struct sr_datafeed_logic logic; |
f78898e9 | 884 | int i, j, k, l, numpad, tosend; |
fefa1800 | 885 | size_t n = 0, sent = 0; |
99965709 | 886 | int clustersize = EVENTS_PER_CLUSTER * sigma->samples_per_event; |
fefa1800 | 887 | uint16_t *event; |
f78898e9 | 888 | uint16_t cur_sample; |
57bbf56b | 889 | int triggerts = -1; |
ee492173 | 890 | |
4ae1f451 | 891 | /* Check if trigger is in this chunk. */ |
ee492173 | 892 | if (triggerpos != -1) { |
59df0c77 | 893 | if (sigma->cur_samplerate <= SR_MHZ(50)) |
36b1c8e6 | 894 | triggerpos -= EVENTS_PER_CLUSTER - 1; |
ee492173 HE |
895 | |
896 | if (triggerpos < 0) | |
897 | triggerpos = 0; | |
57bbf56b | 898 | |
ee492173 HE |
899 | /* Find in which cluster the trigger occured. */ |
900 | triggerts = triggerpos / 7; | |
901 | } | |
28a35d8a | 902 | |
eec5275e | 903 | /* For each ts. */ |
28a35d8a | 904 | for (i = 0; i < 64; ++i) { |
fefa1800 | 905 | ts = *(uint16_t *) &buf[i * 16]; |
28a35d8a HE |
906 | tsdiff = ts - *lastts; |
907 | *lastts = ts; | |
908 | ||
88c51afe HE |
909 | /* Decode partial chunk. */ |
910 | if (limit_chunk && ts > limit_chunk) | |
e46b8fb1 | 911 | return SR_OK; |
88c51afe | 912 | |
fefa1800 | 913 | /* Pad last sample up to current point. */ |
99965709 | 914 | numpad = tsdiff * sigma->samples_per_event - clustersize; |
28a35d8a | 915 | if (numpad > 0) { |
f78898e9 HE |
916 | for (j = 0; j < numpad; ++j) |
917 | samples[j] = *lastsample; | |
918 | ||
919 | n = numpad; | |
28a35d8a HE |
920 | } |
921 | ||
57bbf56b HE |
922 | /* Send samples between previous and this timestamp to sigrok. */ |
923 | sent = 0; | |
924 | while (sent < n) { | |
925 | tosend = MIN(2048, n - sent); | |
926 | ||
5a2326a7 | 927 | packet.type = SR_DF_LOGIC; |
9c939c51 BV |
928 | packet.payload = &logic; |
929 | logic.length = tosend * sizeof(uint16_t); | |
930 | logic.unitsize = 2; | |
931 | logic.data = samples + sent; | |
8a2efef2 | 932 | sr_session_bus(sigma->session_id, &packet); |
28a35d8a | 933 | |
57bbf56b HE |
934 | sent += tosend; |
935 | } | |
936 | n = 0; | |
937 | ||
938 | event = (uint16_t *) &buf[i * 16 + 2]; | |
f78898e9 HE |
939 | cur_sample = 0; |
940 | ||
941 | /* For each event in cluster. */ | |
28a35d8a | 942 | for (j = 0; j < 7; ++j) { |
f78898e9 HE |
943 | |
944 | /* For each sample in event. */ | |
99965709 | 945 | for (k = 0; k < sigma->samples_per_event; ++k) { |
f78898e9 HE |
946 | cur_sample = 0; |
947 | ||
948 | /* For each probe. */ | |
99965709 | 949 | for (l = 0; l < sigma->num_probes; ++l) |
edca2c5c | 950 | cur_sample |= (!!(event[j] & (1 << (l * |
99965709 HE |
951 | sigma->samples_per_event |
952 | + k)))) | |
edca2c5c | 953 | << l; |
f78898e9 HE |
954 | |
955 | samples[n++] = cur_sample; | |
28a35d8a HE |
956 | } |
957 | } | |
958 | ||
eec5275e | 959 | /* Send data up to trigger point (if triggered). */ |
fefa1800 | 960 | sent = 0; |
57bbf56b HE |
961 | if (i == triggerts) { |
962 | /* | |
36b1c8e6 HE |
963 | * Trigger is not always accurate to sample because of |
964 | * pipeline delay. However, it always triggers before | |
965 | * the actual event. We therefore look at the next | |
966 | * samples to pinpoint the exact position of the trigger. | |
57bbf56b | 967 | */ |
bdfc7a89 | 968 | tosend = get_trigger_offset(samples, *lastsample, |
99965709 | 969 | &sigma->trigger); |
57bbf56b HE |
970 | |
971 | if (tosend > 0) { | |
5a2326a7 | 972 | packet.type = SR_DF_LOGIC; |
9c939c51 BV |
973 | packet.payload = &logic; |
974 | logic.length = tosend * sizeof(uint16_t); | |
975 | logic.unitsize = 2; | |
976 | logic.data = samples; | |
8a2efef2 | 977 | sr_session_bus(sigma->session_id, &packet); |
57bbf56b HE |
978 | |
979 | sent += tosend; | |
980 | } | |
28a35d8a | 981 | |
5b5ea7c6 HE |
982 | /* Only send trigger if explicitly enabled. */ |
983 | if (sigma->use_triggers) { | |
5a2326a7 | 984 | packet.type = SR_DF_TRIGGER; |
8a2efef2 | 985 | sr_session_bus(sigma->session_id, &packet); |
5b5ea7c6 | 986 | } |
28a35d8a | 987 | } |
57bbf56b | 988 | |
eec5275e | 989 | /* Send rest of the chunk to sigrok. */ |
57bbf56b HE |
990 | tosend = n - sent; |
991 | ||
abda62ce | 992 | if (tosend > 0) { |
5a2326a7 | 993 | packet.type = SR_DF_LOGIC; |
9c939c51 BV |
994 | packet.payload = &logic; |
995 | logic.length = tosend * sizeof(uint16_t); | |
996 | logic.unitsize = 2; | |
997 | logic.data = samples + sent; | |
8a2efef2 | 998 | sr_session_bus(sigma->session_id, &packet); |
abda62ce | 999 | } |
ee492173 HE |
1000 | |
1001 | *lastsample = samples[n - 1]; | |
28a35d8a HE |
1002 | } |
1003 | ||
e46b8fb1 | 1004 | return SR_OK; |
28a35d8a HE |
1005 | } |
1006 | ||
9c939c51 | 1007 | static int receive_data(int fd, int revents, void *session_data) |
28a35d8a | 1008 | { |
d68e2d1a | 1009 | struct sr_dev_inst *sdi = session_data; |
99965709 | 1010 | struct sigma *sigma = sdi->priv; |
b9c735a2 | 1011 | struct sr_datafeed_packet packet; |
28a35d8a HE |
1012 | const int chunks_per_read = 32; |
1013 | unsigned char buf[chunks_per_read * CHUNK_SIZE]; | |
6aac7737 | 1014 | int bufsz, numchunks, i, newchunks; |
94ba4bd6 | 1015 | uint64_t running_msec; |
28a35d8a | 1016 | struct timeval tv; |
28a35d8a | 1017 | |
cb93f8a9 UH |
1018 | /* Avoid compiler warnings. */ |
1019 | (void)fd; | |
1020 | (void)revents; | |
28a35d8a | 1021 | |
31facdd3 | 1022 | numchunks = (sigma->state.stoppos + 511) / 512; |
28a35d8a | 1023 | |
99965709 | 1024 | if (sigma->state.state == SIGMA_IDLE) |
28a35d8a HE |
1025 | return FALSE; |
1026 | ||
99965709 | 1027 | if (sigma->state.state == SIGMA_CAPTURE) { |
28a35d8a | 1028 | |
6aac7737 HE |
1029 | /* Check if the timer has expired, or memory is full. */ |
1030 | gettimeofday(&tv, 0); | |
99965709 HE |
1031 | running_msec = (tv.tv_sec - sigma->start_tv.tv_sec) * 1000 + |
1032 | (tv.tv_usec - sigma->start_tv.tv_usec) / 1000; | |
28a35d8a | 1033 | |
99965709 | 1034 | if (running_msec < sigma->limit_msec && numchunks < 32767) |
6aac7737 | 1035 | return FALSE; |
28a35d8a | 1036 | |
9c939c51 | 1037 | hw_stop_acquisition(sdi->index, session_data); |
6aac7737 HE |
1038 | |
1039 | return FALSE; | |
1040 | ||
99965709 HE |
1041 | } else if (sigma->state.state == SIGMA_DOWNLOAD) { |
1042 | if (sigma->state.chunks_downloaded >= numchunks) { | |
6aac7737 | 1043 | /* End of samples. */ |
5a2326a7 | 1044 | packet.type = SR_DF_END; |
8a2efef2 | 1045 | sr_session_bus(sigma->session_id, &packet); |
6aac7737 | 1046 | |
99965709 | 1047 | sigma->state.state = SIGMA_IDLE; |
f78898e9 | 1048 | |
6aac7737 HE |
1049 | return TRUE; |
1050 | } | |
1051 | ||
1052 | newchunks = MIN(chunks_per_read, | |
99965709 | 1053 | numchunks - sigma->state.chunks_downloaded); |
28a35d8a | 1054 | |
7b48d6e1 | 1055 | sr_info("sigma: Downloading sample data: %.0f %%", |
b08024a8 | 1056 | 100.0 * sigma->state.chunks_downloaded / numchunks); |
28a35d8a | 1057 | |
99965709 HE |
1058 | bufsz = sigma_read_dram(sigma->state.chunks_downloaded, |
1059 | newchunks, buf, sigma); | |
719c5a93 UH |
1060 | /* TODO: Check bufsz. For now, just avoid compiler warnings. */ |
1061 | (void)bufsz; | |
28a35d8a | 1062 | |
fefa1800 | 1063 | /* Find first ts. */ |
99965709 HE |
1064 | if (sigma->state.chunks_downloaded == 0) { |
1065 | sigma->state.lastts = *(uint16_t *) buf - 1; | |
1066 | sigma->state.lastsample = 0; | |
6aac7737 | 1067 | } |
28a35d8a | 1068 | |
fefa1800 | 1069 | /* Decode chunks and send them to sigrok. */ |
28a35d8a | 1070 | for (i = 0; i < newchunks; ++i) { |
88c51afe HE |
1071 | int limit_chunk = 0; |
1072 | ||
1073 | /* The last chunk may potentially be only in part. */ | |
1074 | if (sigma->state.chunks_downloaded == numchunks - 1) | |
1075 | { | |
1076 | /* Find the last valid timestamp */ | |
1077 | limit_chunk = sigma->state.stoppos % 512 + sigma->state.lastts; | |
1078 | } | |
1079 | ||
99965709 | 1080 | if (sigma->state.chunks_downloaded + i == sigma->state.triggerchunk) |
57bbf56b | 1081 | decode_chunk_ts(buf + (i * CHUNK_SIZE), |
99965709 HE |
1082 | &sigma->state.lastts, |
1083 | &sigma->state.lastsample, | |
1084 | sigma->state.triggerpos & 0x1ff, | |
9c939c51 | 1085 | limit_chunk, session_data); |
57bbf56b HE |
1086 | else |
1087 | decode_chunk_ts(buf + (i * CHUNK_SIZE), | |
99965709 HE |
1088 | &sigma->state.lastts, |
1089 | &sigma->state.lastsample, | |
9c939c51 | 1090 | -1, limit_chunk, session_data); |
28a35d8a | 1091 | |
88c51afe HE |
1092 | ++sigma->state.chunks_downloaded; |
1093 | } | |
28a35d8a HE |
1094 | } |
1095 | ||
28a35d8a HE |
1096 | return TRUE; |
1097 | } | |
1098 | ||
c53d793f HE |
1099 | /* Build a LUT entry used by the trigger functions. */ |
1100 | static void build_lut_entry(uint16_t value, uint16_t mask, uint16_t *entry) | |
ee492173 HE |
1101 | { |
1102 | int i, j, k, bit; | |
1103 | ||
f758d074 | 1104 | /* For each quad probe. */ |
ee492173 | 1105 | for (i = 0; i < 4; ++i) { |
c53d793f | 1106 | entry[i] = 0xffff; |
ee492173 | 1107 | |
f758d074 | 1108 | /* For each bit in LUT. */ |
ee492173 HE |
1109 | for (j = 0; j < 16; ++j) |
1110 | ||
f758d074 | 1111 | /* For each probe in quad. */ |
ee492173 HE |
1112 | for (k = 0; k < 4; ++k) { |
1113 | bit = 1 << (i * 4 + k); | |
1114 | ||
c53d793f HE |
1115 | /* Set bit in entry */ |
1116 | if ((mask & bit) && | |
1117 | ((!(value & bit)) != | |
4ae1f451 | 1118 | (!(j & (1 << k))))) |
c53d793f | 1119 | entry[i] &= ~(1 << j); |
ee492173 HE |
1120 | } |
1121 | } | |
c53d793f | 1122 | } |
ee492173 | 1123 | |
c53d793f HE |
1124 | /* Add a logical function to LUT mask. */ |
1125 | static void add_trigger_function(enum triggerop oper, enum triggerfunc func, | |
1126 | int index, int neg, uint16_t *mask) | |
1127 | { | |
1128 | int i, j; | |
1129 | int x[2][2], tmp, a, b, aset, bset, rset; | |
1130 | ||
1131 | memset(x, 0, 4 * sizeof(int)); | |
1132 | ||
1133 | /* Trigger detect condition. */ | |
1134 | switch (oper) { | |
1135 | case OP_LEVEL: | |
1136 | x[0][1] = 1; | |
1137 | x[1][1] = 1; | |
1138 | break; | |
1139 | case OP_NOT: | |
1140 | x[0][0] = 1; | |
1141 | x[1][0] = 1; | |
1142 | break; | |
1143 | case OP_RISE: | |
1144 | x[0][1] = 1; | |
1145 | break; | |
1146 | case OP_FALL: | |
1147 | x[1][0] = 1; | |
1148 | break; | |
1149 | case OP_RISEFALL: | |
1150 | x[0][1] = 1; | |
1151 | x[1][0] = 1; | |
1152 | break; | |
1153 | case OP_NOTRISE: | |
1154 | x[1][1] = 1; | |
1155 | x[0][0] = 1; | |
1156 | x[1][0] = 1; | |
1157 | break; | |
1158 | case OP_NOTFALL: | |
1159 | x[1][1] = 1; | |
1160 | x[0][0] = 1; | |
1161 | x[0][1] = 1; | |
1162 | break; | |
1163 | case OP_NOTRISEFALL: | |
1164 | x[1][1] = 1; | |
1165 | x[0][0] = 1; | |
1166 | break; | |
1167 | } | |
1168 | ||
1169 | /* Transpose if neg is set. */ | |
1170 | if (neg) { | |
1171 | for (i = 0; i < 2; ++i) | |
1172 | for (j = 0; j < 2; ++j) { | |
1173 | tmp = x[i][j]; | |
1174 | x[i][j] = x[1-i][1-j]; | |
1175 | x[1-i][1-j] = tmp; | |
1176 | } | |
1177 | } | |
1178 | ||
1179 | /* Update mask with function. */ | |
1180 | for (i = 0; i < 16; ++i) { | |
1181 | a = (i >> (2 * index + 0)) & 1; | |
1182 | b = (i >> (2 * index + 1)) & 1; | |
1183 | ||
1184 | aset = (*mask >> i) & 1; | |
1185 | bset = x[b][a]; | |
1186 | ||
1187 | if (func == FUNC_AND || func == FUNC_NAND) | |
1188 | rset = aset & bset; | |
1189 | else if (func == FUNC_OR || func == FUNC_NOR) | |
1190 | rset = aset | bset; | |
1191 | else if (func == FUNC_XOR || func == FUNC_NXOR) | |
1192 | rset = aset ^ bset; | |
1193 | ||
1194 | if (func == FUNC_NAND || func == FUNC_NOR || func == FUNC_NXOR) | |
1195 | rset = !rset; | |
1196 | ||
1197 | *mask &= ~(1 << i); | |
1198 | ||
1199 | if (rset) | |
1200 | *mask |= 1 << i; | |
1201 | } | |
1202 | } | |
1203 | ||
1204 | /* | |
1205 | * Build trigger LUTs used by 50 MHz and lower sample rates for supporting | |
1206 | * simple pin change and state triggers. Only two transitions (rise/fall) can be | |
1207 | * set at any time, but a full mask and value can be set (0/1). | |
1208 | */ | |
99965709 | 1209 | static int build_basic_trigger(struct triggerlut *lut, struct sigma *sigma) |
c53d793f HE |
1210 | { |
1211 | int i,j; | |
4ae1f451 | 1212 | uint16_t masks[2] = { 0, 0 }; |
c53d793f HE |
1213 | |
1214 | memset(lut, 0, sizeof(struct triggerlut)); | |
1215 | ||
1216 | /* Contant for simple triggers. */ | |
1217 | lut->m4 = 0xa000; | |
1218 | ||
1219 | /* Value/mask trigger support. */ | |
99965709 HE |
1220 | build_lut_entry(sigma->trigger.simplevalue, sigma->trigger.simplemask, |
1221 | lut->m2d); | |
c53d793f HE |
1222 | |
1223 | /* Rise/fall trigger support. */ | |
1224 | for (i = 0, j = 0; i < 16; ++i) { | |
99965709 HE |
1225 | if (sigma->trigger.risingmask & (1 << i) || |
1226 | sigma->trigger.fallingmask & (1 << i)) | |
c53d793f HE |
1227 | masks[j++] = 1 << i; |
1228 | } | |
1229 | ||
1230 | build_lut_entry(masks[0], masks[0], lut->m0d); | |
1231 | build_lut_entry(masks[1], masks[1], lut->m1d); | |
1232 | ||
1233 | /* Add glue logic */ | |
1234 | if (masks[0] || masks[1]) { | |
1235 | /* Transition trigger. */ | |
99965709 | 1236 | if (masks[0] & sigma->trigger.risingmask) |
c53d793f | 1237 | add_trigger_function(OP_RISE, FUNC_OR, 0, 0, &lut->m3); |
99965709 | 1238 | if (masks[0] & sigma->trigger.fallingmask) |
c53d793f | 1239 | add_trigger_function(OP_FALL, FUNC_OR, 0, 0, &lut->m3); |
99965709 | 1240 | if (masks[1] & sigma->trigger.risingmask) |
c53d793f | 1241 | add_trigger_function(OP_RISE, FUNC_OR, 1, 0, &lut->m3); |
99965709 | 1242 | if (masks[1] & sigma->trigger.fallingmask) |
c53d793f HE |
1243 | add_trigger_function(OP_FALL, FUNC_OR, 1, 0, &lut->m3); |
1244 | } else { | |
1245 | /* Only value/mask trigger. */ | |
1246 | lut->m3 = 0xffff; | |
1247 | } | |
ee492173 | 1248 | |
c53d793f | 1249 | /* Triggertype: event. */ |
ee492173 HE |
1250 | lut->params.selres = 3; |
1251 | ||
e46b8fb1 | 1252 | return SR_OK; |
ee492173 HE |
1253 | } |
1254 | ||
bb7ef793 | 1255 | static int hw_start_acquisition(int dev_index, gpointer session_data) |
28a35d8a | 1256 | { |
d68e2d1a | 1257 | struct sr_dev_inst *sdi; |
99965709 | 1258 | struct sigma *sigma; |
b9c735a2 UH |
1259 | struct sr_datafeed_packet packet; |
1260 | struct sr_datafeed_header header; | |
9ddb2a12 | 1261 | struct clockselect_50 clockselect; |
82957b65 | 1262 | int frac, triggerpin, ret; |
57bbf56b HE |
1263 | uint8_t triggerselect; |
1264 | struct triggerinout triggerinout_conf; | |
ee492173 | 1265 | struct triggerlut lut; |
28a35d8a | 1266 | |
cb93f8a9 UH |
1267 | /* Avoid compiler warnings. */ |
1268 | (void)session_data; | |
28a35d8a | 1269 | |
bb7ef793 | 1270 | if (!(sdi = sr_dev_inst_get(dev_insts, dev_index))) |
e46b8fb1 | 1271 | return SR_ERR; |
28a35d8a | 1272 | |
99965709 | 1273 | sigma = sdi->priv; |
28a35d8a | 1274 | |
7c70c538 | 1275 | /* If the samplerate has not been set, default to 200 KHz. */ |
82957b65 UH |
1276 | if (sigma->cur_firmware == -1) { |
1277 | if ((ret = set_samplerate(sdi, SR_KHZ(200))) != SR_OK) | |
1278 | return ret; | |
1279 | } | |
e8397563 | 1280 | |
eec5275e | 1281 | /* Enter trigger programming mode. */ |
99965709 | 1282 | sigma_set_register(WRITE_TRIGGER_SELECT1, 0x20, sigma); |
28a35d8a | 1283 | |
eec5275e | 1284 | /* 100 and 200 MHz mode. */ |
59df0c77 | 1285 | if (sigma->cur_samplerate >= SR_MHZ(100)) { |
99965709 | 1286 | sigma_set_register(WRITE_TRIGGER_SELECT1, 0x81, sigma); |
57bbf56b | 1287 | |
a42aec7f HE |
1288 | /* Find which pin to trigger on from mask. */ |
1289 | for (triggerpin = 0; triggerpin < 8; ++triggerpin) | |
99965709 | 1290 | if ((sigma->trigger.risingmask | sigma->trigger.fallingmask) & |
a42aec7f HE |
1291 | (1 << triggerpin)) |
1292 | break; | |
1293 | ||
1294 | /* Set trigger pin and light LED on trigger. */ | |
1295 | triggerselect = (1 << LEDSEL1) | (triggerpin & 0x7); | |
1296 | ||
1297 | /* Default rising edge. */ | |
99965709 | 1298 | if (sigma->trigger.fallingmask) |
a42aec7f | 1299 | triggerselect |= 1 << 3; |
57bbf56b | 1300 | |
eec5275e | 1301 | /* All other modes. */ |
59df0c77 | 1302 | } else if (sigma->cur_samplerate <= SR_MHZ(50)) { |
99965709 | 1303 | build_basic_trigger(&lut, sigma); |
ee492173 | 1304 | |
99965709 | 1305 | sigma_write_trigger_lut(&lut, sigma); |
57bbf56b HE |
1306 | |
1307 | triggerselect = (1 << LEDSEL1) | (1 << LEDSEL0); | |
1308 | } | |
1309 | ||
eec5275e | 1310 | /* Setup trigger in and out pins to default values. */ |
57bbf56b HE |
1311 | memset(&triggerinout_conf, 0, sizeof(struct triggerinout)); |
1312 | triggerinout_conf.trgout_bytrigger = 1; | |
1313 | triggerinout_conf.trgout_enable = 1; | |
1314 | ||
28a35d8a | 1315 | sigma_write_register(WRITE_TRIGGER_OPTION, |
57bbf56b | 1316 | (uint8_t *) &triggerinout_conf, |
99965709 | 1317 | sizeof(struct triggerinout), sigma); |
28a35d8a | 1318 | |
eec5275e | 1319 | /* Go back to normal mode. */ |
99965709 | 1320 | sigma_set_register(WRITE_TRIGGER_SELECT1, triggerselect, sigma); |
28a35d8a | 1321 | |
edca2c5c | 1322 | /* Set clock select register. */ |
59df0c77 | 1323 | if (sigma->cur_samplerate == SR_MHZ(200)) |
edca2c5c | 1324 | /* Enable 4 probes. */ |
99965709 | 1325 | sigma_set_register(WRITE_CLOCK_SELECT, 0xf0, sigma); |
59df0c77 | 1326 | else if (sigma->cur_samplerate == SR_MHZ(100)) |
edca2c5c | 1327 | /* Enable 8 probes. */ |
99965709 | 1328 | sigma_set_register(WRITE_CLOCK_SELECT, 0x00, sigma); |
edca2c5c HE |
1329 | else { |
1330 | /* | |
9ddb2a12 | 1331 | * 50 MHz mode (or fraction thereof). Any fraction down to |
eec5275e | 1332 | * 50 MHz / 256 can be used, but is not supported by sigrok API. |
edca2c5c | 1333 | */ |
59df0c77 | 1334 | frac = SR_MHZ(50) / sigma->cur_samplerate - 1; |
edca2c5c | 1335 | |
9ddb2a12 UH |
1336 | clockselect.async = 0; |
1337 | clockselect.fraction = frac; | |
1338 | clockselect.disabled_probes = 0; | |
edca2c5c HE |
1339 | |
1340 | sigma_write_register(WRITE_CLOCK_SELECT, | |
9ddb2a12 | 1341 | (uint8_t *) &clockselect, |
99965709 | 1342 | sizeof(clockselect), sigma); |
edca2c5c HE |
1343 | } |
1344 | ||
fefa1800 | 1345 | /* Setup maximum post trigger time. */ |
99965709 HE |
1346 | sigma_set_register(WRITE_POST_TRIGGER, |
1347 | (sigma->capture_ratio * 255) / 100, sigma); | |
28a35d8a | 1348 | |
eec5275e | 1349 | /* Start acqusition. */ |
99965709 HE |
1350 | gettimeofday(&sigma->start_tv, 0); |
1351 | sigma_set_register(WRITE_MODE, 0x0d, sigma); | |
1352 | ||
9c939c51 | 1353 | sigma->session_id = session_data; |
28a35d8a | 1354 | |
28a35d8a | 1355 | /* Send header packet to the session bus. */ |
5a2326a7 | 1356 | packet.type = SR_DF_HEADER; |
28a35d8a HE |
1357 | packet.payload = &header; |
1358 | header.feed_version = 1; | |
1359 | gettimeofday(&header.starttime, NULL); | |
99965709 | 1360 | header.samplerate = sigma->cur_samplerate; |
99965709 | 1361 | header.num_logic_probes = sigma->num_probes; |
9c939c51 | 1362 | sr_session_bus(session_data, &packet); |
28a35d8a | 1363 | |
57bbf56b | 1364 | /* Add capture source. */ |
6f1be0a2 | 1365 | sr_source_add(0, G_IO_IN, 10, receive_data, sdi); |
57bbf56b | 1366 | |
99965709 | 1367 | sigma->state.state = SIGMA_CAPTURE; |
6aac7737 | 1368 | |
e46b8fb1 | 1369 | return SR_OK; |
28a35d8a HE |
1370 | } |
1371 | ||
bb7ef793 | 1372 | static int hw_stop_acquisition(int dev_index, gpointer session_data) |
28a35d8a | 1373 | { |
d68e2d1a | 1374 | struct sr_dev_inst *sdi; |
99965709 | 1375 | struct sigma *sigma; |
6aac7737 HE |
1376 | uint8_t modestatus; |
1377 | ||
cb93f8a9 UH |
1378 | /* Avoid compiler warnings. */ |
1379 | (void)session_data; | |
28a35d8a | 1380 | |
bb7ef793 | 1381 | if (!(sdi = sr_dev_inst_get(dev_insts, dev_index))) { |
7b48d6e1 | 1382 | sr_err("sigma: %s: sdi was NULL", __func__); |
3010f21c UH |
1383 | return SR_ERR_BUG; |
1384 | } | |
1385 | ||
1386 | if (!(sigma = sdi->priv)) { | |
7b48d6e1 | 1387 | sr_err("sigma: %s: sdi->priv was NULL", __func__); |
3010f21c UH |
1388 | return SR_ERR_BUG; |
1389 | } | |
1390 | ||
fefa1800 | 1391 | /* Stop acquisition. */ |
99965709 | 1392 | sigma_set_register(WRITE_MODE, 0x11, sigma); |
28a35d8a | 1393 | |
6aac7737 | 1394 | /* Set SDRAM Read Enable. */ |
99965709 | 1395 | sigma_set_register(WRITE_MODE, 0x02, sigma); |
6aac7737 HE |
1396 | |
1397 | /* Get the current position. */ | |
99965709 | 1398 | sigma_read_pos(&sigma->state.stoppos, &sigma->state.triggerpos, sigma); |
6aac7737 HE |
1399 | |
1400 | /* Check if trigger has fired. */ | |
99965709 | 1401 | modestatus = sigma_get_register(READ_MODE, sigma); |
3010f21c | 1402 | if (modestatus & 0x20) |
99965709 | 1403 | sigma->state.triggerchunk = sigma->state.triggerpos / 512; |
3010f21c | 1404 | else |
99965709 | 1405 | sigma->state.triggerchunk = -1; |
6aac7737 | 1406 | |
99965709 | 1407 | sigma->state.chunks_downloaded = 0; |
6aac7737 | 1408 | |
99965709 | 1409 | sigma->state.state = SIGMA_DOWNLOAD; |
3010f21c UH |
1410 | |
1411 | return SR_OK; | |
28a35d8a HE |
1412 | } |
1413 | ||
bb7ef793 | 1414 | SR_PRIV struct sr_dev_plugin asix_sigma_plugin_info = { |
e519ba86 UH |
1415 | .name = "asix-sigma", |
1416 | .longname = "ASIX SIGMA", | |
1417 | .api_version = 1, | |
1418 | .init = hw_init, | |
1419 | .cleanup = hw_cleanup, | |
86f5e3d8 UH |
1420 | .opendev = hw_opendev, |
1421 | .closedev = hw_closedev, | |
bb7ef793 | 1422 | .get_dev_info = hw_get_dev_info, |
e519ba86 UH |
1423 | .get_status = hw_get_status, |
1424 | .get_capabilities = hw_get_capabilities, | |
1425 | .set_configuration = hw_set_configuration, | |
1426 | .start_acquisition = hw_start_acquisition, | |
1427 | .stop_acquisition = hw_stop_acquisition, | |
28a35d8a | 1428 | }; |