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Commit | Line | Data |
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28a35d8a HE |
1 | /* |
2 | * This file is part of the sigrok project. | |
3 | * | |
911f1834 UH |
4 | * Copyright (C) 2010 Håvard Espeland <gus@ping.uio.no>, |
5 | * Copyright (C) 2010 Martin Stensgård <mastensg@ping.uio.no> | |
6 | * Copyright (C) 2010 Carl Henrik Lunde <chlunde@ping.uio.no> | |
28a35d8a HE |
7 | * |
8 | * This program is free software: you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation, either version 3 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
20 | */ | |
21 | ||
911f1834 UH |
22 | /* |
23 | * ASIX Sigma Logic Analyzer Driver | |
24 | */ | |
25 | ||
28a35d8a HE |
26 | #include <ftdi.h> |
27 | #include <string.h> | |
28 | #include <zlib.h> | |
fefa1800 | 29 | #include <sigrok.h> |
5819184b | 30 | #include <config.h> |
28a35d8a HE |
31 | #include "asix-sigma.h" |
32 | ||
33 | #define USB_VENDOR 0xa600 | |
34 | #define USB_PRODUCT 0xa000 | |
35 | #define USB_DESCRIPTION "ASIX SIGMA" | |
36 | #define USB_VENDOR_NAME "ASIX" | |
37 | #define USB_MODEL_NAME "SIGMA" | |
38 | #define USB_MODEL_VERSION "" | |
ee492173 | 39 | #define TRIGGER_TYPES "rf10" |
28a35d8a HE |
40 | |
41 | static GSList *device_instances = NULL; | |
42 | ||
28a35d8a | 43 | static uint64_t supported_samplerates[] = { |
ed09fd07 | 44 | KHZ(200), |
edca2c5c | 45 | KHZ(250), |
ed09fd07 | 46 | KHZ(500), |
edca2c5c | 47 | MHZ(1), |
ed09fd07 | 48 | MHZ(5), |
edca2c5c HE |
49 | MHZ(10), |
50 | MHZ(25), | |
e8397563 HE |
51 | MHZ(50), |
52 | MHZ(100), | |
28a35d8a HE |
53 | MHZ(200), |
54 | 0, | |
55 | }; | |
56 | ||
57 | static struct samplerates samplerates = { | |
ed09fd07 | 58 | KHZ(200), |
28a35d8a HE |
59 | MHZ(200), |
60 | 0, | |
61 | supported_samplerates, | |
62 | }; | |
63 | ||
64 | static int capabilities[] = { | |
5a2326a7 UH |
65 | SR_HWCAP_LOGIC_ANALYZER, |
66 | SR_HWCAP_SAMPLERATE, | |
67 | SR_HWCAP_CAPTURE_RATIO, | |
68 | SR_HWCAP_PROBECONFIG, | |
28a35d8a | 69 | |
5a2326a7 | 70 | SR_HWCAP_LIMIT_MSEC, |
28a35d8a HE |
71 | 0, |
72 | }; | |
73 | ||
fefa1800 UH |
74 | /* Force the FPGA to reboot. */ |
75 | static uint8_t suicide[] = { | |
76 | 0x84, 0x84, 0x88, 0x84, 0x88, 0x84, 0x88, 0x84, | |
77 | }; | |
78 | ||
79 | /* Prepare to upload firmware (FPGA specific). */ | |
80 | static uint8_t init[] = { | |
81 | 0x03, 0x03, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, | |
82 | }; | |
83 | ||
84 | /* Initialize the logic analyzer mode. */ | |
85 | static uint8_t logic_mode_start[] = { | |
86 | 0x00, 0x40, 0x0f, 0x25, 0x35, 0x40, | |
87 | 0x2a, 0x3a, 0x40, 0x03, 0x20, 0x38, | |
88 | }; | |
89 | ||
eec5275e | 90 | static const char *firmware_files[] = { |
a8116d76 HE |
91 | "asix-sigma-50.fw", /* 50 MHz, supports 8 bit fractions */ |
92 | "asix-sigma-100.fw", /* 100 MHz */ | |
93 | "asix-sigma-200.fw", /* 200 MHz */ | |
ed09fd07 | 94 | "asix-sigma-50sync.fw", /* Synchronous clock from pin */ |
a8116d76 | 95 | "asix-sigma-phasor.fw", /* Frequency counter */ |
f6564c8d HE |
96 | }; |
97 | ||
6aac7737 HE |
98 | static void hw_stop_acquisition(int device_index, gpointer session_device_id); |
99 | ||
99965709 | 100 | static int sigma_read(void *buf, size_t size, struct sigma *sigma) |
28a35d8a HE |
101 | { |
102 | int ret; | |
fefa1800 | 103 | |
99965709 | 104 | ret = ftdi_read_data(&sigma->ftdic, (unsigned char *)buf, size); |
28a35d8a HE |
105 | if (ret < 0) { |
106 | g_warning("ftdi_read_data failed: %s", | |
99965709 | 107 | ftdi_get_error_string(&sigma->ftdic)); |
28a35d8a HE |
108 | } |
109 | ||
110 | return ret; | |
111 | } | |
112 | ||
99965709 | 113 | static int sigma_write(void *buf, size_t size, struct sigma *sigma) |
28a35d8a HE |
114 | { |
115 | int ret; | |
fefa1800 | 116 | |
99965709 | 117 | ret = ftdi_write_data(&sigma->ftdic, (unsigned char *)buf, size); |
28a35d8a HE |
118 | if (ret < 0) { |
119 | g_warning("ftdi_write_data failed: %s", | |
99965709 | 120 | ftdi_get_error_string(&sigma->ftdic)); |
fefa1800 | 121 | } else if ((size_t) ret != size) { |
28a35d8a HE |
122 | g_warning("ftdi_write_data did not complete write\n"); |
123 | } | |
124 | ||
125 | return ret; | |
126 | } | |
127 | ||
99965709 HE |
128 | static int sigma_write_register(uint8_t reg, uint8_t *data, size_t len, |
129 | struct sigma *sigma) | |
28a35d8a HE |
130 | { |
131 | size_t i; | |
132 | uint8_t buf[len + 2]; | |
133 | int idx = 0; | |
134 | ||
135 | buf[idx++] = REG_ADDR_LOW | (reg & 0xf); | |
136 | buf[idx++] = REG_ADDR_HIGH | (reg >> 4); | |
137 | ||
fefa1800 | 138 | for (i = 0; i < len; ++i) { |
28a35d8a HE |
139 | buf[idx++] = REG_DATA_LOW | (data[i] & 0xf); |
140 | buf[idx++] = REG_DATA_HIGH_WRITE | (data[i] >> 4); | |
141 | } | |
142 | ||
99965709 | 143 | return sigma_write(buf, idx, sigma); |
28a35d8a HE |
144 | } |
145 | ||
99965709 | 146 | static int sigma_set_register(uint8_t reg, uint8_t value, struct sigma *sigma) |
28a35d8a | 147 | { |
99965709 | 148 | return sigma_write_register(reg, &value, 1, sigma); |
28a35d8a HE |
149 | } |
150 | ||
99965709 HE |
151 | static int sigma_read_register(uint8_t reg, uint8_t *data, size_t len, |
152 | struct sigma *sigma) | |
28a35d8a HE |
153 | { |
154 | uint8_t buf[3]; | |
fefa1800 | 155 | |
28a35d8a HE |
156 | buf[0] = REG_ADDR_LOW | (reg & 0xf); |
157 | buf[1] = REG_ADDR_HIGH | (reg >> 4); | |
28a35d8a HE |
158 | buf[2] = REG_READ_ADDR; |
159 | ||
99965709 | 160 | sigma_write(buf, sizeof(buf), sigma); |
28a35d8a | 161 | |
99965709 | 162 | return sigma_read(data, len, sigma); |
28a35d8a HE |
163 | } |
164 | ||
99965709 | 165 | static uint8_t sigma_get_register(uint8_t reg, struct sigma *sigma) |
28a35d8a HE |
166 | { |
167 | uint8_t value; | |
fefa1800 | 168 | |
99965709 | 169 | if (1 != sigma_read_register(reg, &value, 1, sigma)) { |
28a35d8a HE |
170 | g_warning("Sigma_get_register: 1 byte expected"); |
171 | return 0; | |
172 | } | |
173 | ||
174 | return value; | |
175 | } | |
176 | ||
99965709 HE |
177 | static int sigma_read_pos(uint32_t *stoppos, uint32_t *triggerpos, |
178 | struct sigma *sigma) | |
28a35d8a HE |
179 | { |
180 | uint8_t buf[] = { | |
181 | REG_ADDR_LOW | READ_TRIGGER_POS_LOW, | |
182 | ||
183 | REG_READ_ADDR | NEXT_REG, | |
184 | REG_READ_ADDR | NEXT_REG, | |
185 | REG_READ_ADDR | NEXT_REG, | |
186 | REG_READ_ADDR | NEXT_REG, | |
187 | REG_READ_ADDR | NEXT_REG, | |
188 | REG_READ_ADDR | NEXT_REG, | |
189 | }; | |
28a35d8a HE |
190 | uint8_t result[6]; |
191 | ||
99965709 | 192 | sigma_write(buf, sizeof(buf), sigma); |
28a35d8a | 193 | |
99965709 | 194 | sigma_read(result, sizeof(result), sigma); |
28a35d8a HE |
195 | |
196 | *triggerpos = result[0] | (result[1] << 8) | (result[2] << 16); | |
197 | *stoppos = result[3] | (result[4] << 8) | (result[5] << 16); | |
198 | ||
57bbf56b HE |
199 | /* Not really sure why this must be done, but according to spec. */ |
200 | if ((--*stoppos & 0x1ff) == 0x1ff) | |
201 | stoppos -= 64; | |
202 | ||
203 | if ((*--triggerpos & 0x1ff) == 0x1ff) | |
204 | triggerpos -= 64; | |
205 | ||
28a35d8a HE |
206 | return 1; |
207 | } | |
208 | ||
99965709 HE |
209 | static int sigma_read_dram(uint16_t startchunk, size_t numchunks, |
210 | uint8_t *data, struct sigma *sigma) | |
28a35d8a HE |
211 | { |
212 | size_t i; | |
213 | uint8_t buf[4096]; | |
214 | int idx = 0; | |
215 | ||
fefa1800 | 216 | /* Send the startchunk. Index start with 1. */ |
28a35d8a HE |
217 | buf[0] = startchunk >> 8; |
218 | buf[1] = startchunk & 0xff; | |
99965709 | 219 | sigma_write_register(WRITE_MEMROW, buf, 2, sigma); |
28a35d8a | 220 | |
fefa1800 | 221 | /* Read the DRAM. */ |
28a35d8a HE |
222 | buf[idx++] = REG_DRAM_BLOCK; |
223 | buf[idx++] = REG_DRAM_WAIT_ACK; | |
224 | ||
225 | for (i = 0; i < numchunks; ++i) { | |
fefa1800 UH |
226 | /* Alternate bit to copy from DRAM to cache. */ |
227 | if (i != (numchunks - 1)) | |
228 | buf[idx++] = REG_DRAM_BLOCK | (((i + 1) % 2) << 4); | |
28a35d8a HE |
229 | |
230 | buf[idx++] = REG_DRAM_BLOCK_DATA | ((i % 2) << 4); | |
231 | ||
fefa1800 | 232 | if (i != (numchunks - 1)) |
28a35d8a HE |
233 | buf[idx++] = REG_DRAM_WAIT_ACK; |
234 | } | |
235 | ||
99965709 | 236 | sigma_write(buf, idx, sigma); |
28a35d8a | 237 | |
99965709 | 238 | return sigma_read(data, numchunks * CHUNK_SIZE, sigma); |
28a35d8a HE |
239 | } |
240 | ||
4ae1f451 | 241 | /* Upload trigger look-up tables to Sigma. */ |
99965709 | 242 | static int sigma_write_trigger_lut(struct triggerlut *lut, struct sigma *sigma) |
ee492173 HE |
243 | { |
244 | int i; | |
245 | uint8_t tmp[2]; | |
246 | uint16_t bit; | |
247 | ||
248 | /* Transpose the table and send to Sigma. */ | |
249 | for (i = 0; i < 16; ++i) { | |
250 | bit = 1 << i; | |
251 | ||
252 | tmp[0] = tmp[1] = 0; | |
253 | ||
254 | if (lut->m2d[0] & bit) | |
255 | tmp[0] |= 0x01; | |
256 | if (lut->m2d[1] & bit) | |
257 | tmp[0] |= 0x02; | |
258 | if (lut->m2d[2] & bit) | |
259 | tmp[0] |= 0x04; | |
260 | if (lut->m2d[3] & bit) | |
261 | tmp[0] |= 0x08; | |
262 | ||
263 | if (lut->m3 & bit) | |
264 | tmp[0] |= 0x10; | |
265 | if (lut->m3s & bit) | |
266 | tmp[0] |= 0x20; | |
267 | if (lut->m4 & bit) | |
268 | tmp[0] |= 0x40; | |
269 | ||
270 | if (lut->m0d[0] & bit) | |
271 | tmp[1] |= 0x01; | |
272 | if (lut->m0d[1] & bit) | |
273 | tmp[1] |= 0x02; | |
274 | if (lut->m0d[2] & bit) | |
275 | tmp[1] |= 0x04; | |
276 | if (lut->m0d[3] & bit) | |
277 | tmp[1] |= 0x08; | |
278 | ||
279 | if (lut->m1d[0] & bit) | |
280 | tmp[1] |= 0x10; | |
281 | if (lut->m1d[1] & bit) | |
282 | tmp[1] |= 0x20; | |
283 | if (lut->m1d[2] & bit) | |
284 | tmp[1] |= 0x40; | |
285 | if (lut->m1d[3] & bit) | |
286 | tmp[1] |= 0x80; | |
287 | ||
99965709 HE |
288 | sigma_write_register(WRITE_TRIGGER_SELECT0, tmp, sizeof(tmp), |
289 | sigma); | |
290 | sigma_set_register(WRITE_TRIGGER_SELECT1, 0x30 | i, sigma); | |
ee492173 HE |
291 | } |
292 | ||
293 | /* Send the parameters */ | |
294 | sigma_write_register(WRITE_TRIGGER_SELECT0, (uint8_t *) &lut->params, | |
99965709 | 295 | sizeof(lut->params), sigma); |
ee492173 | 296 | |
e46b8fb1 | 297 | return SR_OK; |
ee492173 HE |
298 | } |
299 | ||
fefa1800 | 300 | /* Generate the bitbang stream for programming the FPGA. */ |
28a35d8a | 301 | static int bin2bitbang(const char *filename, |
fefa1800 | 302 | unsigned char **buf, size_t *buf_size) |
28a35d8a | 303 | { |
fefa1800 | 304 | FILE *f; |
28a35d8a HE |
305 | long file_size; |
306 | unsigned long offset = 0; | |
307 | unsigned char *p; | |
308 | uint8_t *compressed_buf, *firmware; | |
309 | uLongf csize, fwsize; | |
310 | const int buffer_size = 65536; | |
311 | size_t i; | |
fefa1800 UH |
312 | int c, ret, bit, v; |
313 | uint32_t imm = 0x3f6df2ab; | |
28a35d8a | 314 | |
fefa1800 | 315 | f = fopen(filename, "r"); |
28a35d8a HE |
316 | if (!f) { |
317 | g_warning("fopen(\"%s\", \"r\")", filename); | |
318 | return -1; | |
319 | } | |
320 | ||
321 | if (-1 == fseek(f, 0, SEEK_END)) { | |
322 | g_warning("fseek on %s failed", filename); | |
323 | fclose(f); | |
324 | return -1; | |
325 | } | |
326 | ||
327 | file_size = ftell(f); | |
328 | ||
329 | fseek(f, 0, SEEK_SET); | |
330 | ||
28a35d8a HE |
331 | compressed_buf = g_malloc(file_size); |
332 | firmware = g_malloc(buffer_size); | |
333 | ||
334 | if (!compressed_buf || !firmware) { | |
335 | g_warning("Error allocating buffers"); | |
336 | return -1; | |
337 | } | |
338 | ||
28a35d8a HE |
339 | csize = 0; |
340 | while ((c = getc(f)) != EOF) { | |
341 | imm = (imm + 0xa853753) % 177 + (imm * 0x8034052); | |
342 | compressed_buf[csize++] = c ^ imm; | |
343 | } | |
344 | fclose(f); | |
345 | ||
346 | fwsize = buffer_size; | |
347 | ret = uncompress(firmware, &fwsize, compressed_buf, csize); | |
348 | if (ret < 0) { | |
349 | g_free(compressed_buf); | |
350 | g_free(firmware); | |
351 | g_warning("Could not unpack Sigma firmware. (Error %d)\n", ret); | |
352 | return -1; | |
353 | } | |
354 | ||
355 | g_free(compressed_buf); | |
356 | ||
357 | *buf_size = fwsize * 2 * 8; | |
358 | ||
fefa1800 | 359 | *buf = p = (unsigned char *)g_malloc(*buf_size); |
28a35d8a HE |
360 | |
361 | if (!p) { | |
362 | g_warning("Error allocating buffers"); | |
363 | return -1; | |
364 | } | |
365 | ||
366 | for (i = 0; i < fwsize; ++i) { | |
28a35d8a | 367 | for (bit = 7; bit >= 0; --bit) { |
fefa1800 | 368 | v = firmware[i] & 1 << bit ? 0x40 : 0x00; |
28a35d8a HE |
369 | p[offset++] = v | 0x01; |
370 | p[offset++] = v; | |
371 | } | |
372 | } | |
373 | ||
374 | g_free(firmware); | |
375 | ||
376 | if (offset != *buf_size) { | |
377 | g_free(*buf); | |
378 | g_warning("Error reading firmware %s " | |
fefa1800 UH |
379 | "offset=%ld, file_size=%ld, buf_size=%zd\n", |
380 | filename, offset, file_size, *buf_size); | |
28a35d8a HE |
381 | |
382 | return -1; | |
383 | } | |
384 | ||
385 | return 0; | |
386 | } | |
387 | ||
388 | static int hw_init(char *deviceinfo) | |
389 | { | |
a00ba012 | 390 | struct sr_device_instance *sdi; |
99965709 | 391 | struct sigma *sigma = g_malloc(sizeof(struct sigma)); |
28a35d8a HE |
392 | |
393 | deviceinfo = deviceinfo; | |
394 | ||
99965709 HE |
395 | if (!sigma) |
396 | return 0; | |
397 | ||
398 | ftdi_init(&sigma->ftdic); | |
28a35d8a | 399 | |
fefa1800 | 400 | /* Look for SIGMAs. */ |
99965709 | 401 | if (ftdi_usb_open_desc(&sigma->ftdic, USB_VENDOR, USB_PRODUCT, |
fefa1800 | 402 | USB_DESCRIPTION, NULL) < 0) |
99965709 HE |
403 | goto free; |
404 | ||
405 | sigma->cur_samplerate = 0; | |
406 | sigma->limit_msec = 0; | |
407 | sigma->cur_firmware = -1; | |
408 | sigma->num_probes = 0; | |
409 | sigma->samples_per_event = 0; | |
410 | sigma->capture_ratio = 50; | |
5b5ea7c6 | 411 | sigma->use_triggers = 0; |
28a35d8a | 412 | |
fefa1800 | 413 | /* Register SIGMA device. */ |
5a2326a7 | 414 | sdi = sr_device_instance_new(0, SR_ST_INITIALIZING, |
28a35d8a HE |
415 | USB_VENDOR_NAME, USB_MODEL_NAME, USB_MODEL_VERSION); |
416 | if (!sdi) | |
99965709 HE |
417 | goto free; |
418 | ||
419 | sdi->priv = sigma; | |
28a35d8a HE |
420 | |
421 | device_instances = g_slist_append(device_instances, sdi); | |
422 | ||
fefa1800 | 423 | /* We will open the device again when we need it. */ |
99965709 | 424 | ftdi_usb_close(&sigma->ftdic); |
28a35d8a HE |
425 | |
426 | return 1; | |
99965709 HE |
427 | free: |
428 | free(sigma); | |
429 | return 0; | |
28a35d8a HE |
430 | } |
431 | ||
99965709 | 432 | static int upload_firmware(int firmware_idx, struct sigma *sigma) |
28a35d8a HE |
433 | { |
434 | int ret; | |
435 | unsigned char *buf; | |
436 | unsigned char pins; | |
437 | size_t buf_size; | |
28a35d8a | 438 | unsigned char result[32]; |
e8397563 | 439 | char firmware_path[128]; |
28a35d8a | 440 | |
fefa1800 | 441 | /* Make sure it's an ASIX SIGMA. */ |
99965709 | 442 | if ((ret = ftdi_usb_open_desc(&sigma->ftdic, |
28a35d8a | 443 | USB_VENDOR, USB_PRODUCT, USB_DESCRIPTION, NULL)) < 0) { |
28a35d8a | 444 | g_warning("ftdi_usb_open failed: %s", |
99965709 | 445 | ftdi_get_error_string(&sigma->ftdic)); |
28a35d8a HE |
446 | return 0; |
447 | } | |
448 | ||
99965709 | 449 | if ((ret = ftdi_set_bitmode(&sigma->ftdic, 0xdf, BITMODE_BITBANG)) < 0) { |
28a35d8a | 450 | g_warning("ftdi_set_bitmode failed: %s", |
99965709 | 451 | ftdi_get_error_string(&sigma->ftdic)); |
28a35d8a HE |
452 | return 0; |
453 | } | |
454 | ||
fefa1800 | 455 | /* Four times the speed of sigmalogan - Works well. */ |
99965709 | 456 | if ((ret = ftdi_set_baudrate(&sigma->ftdic, 750000)) < 0) { |
28a35d8a | 457 | g_warning("ftdi_set_baudrate failed: %s", |
99965709 | 458 | ftdi_get_error_string(&sigma->ftdic)); |
28a35d8a HE |
459 | return 0; |
460 | } | |
461 | ||
fefa1800 | 462 | /* Force the FPGA to reboot. */ |
99965709 HE |
463 | sigma_write(suicide, sizeof(suicide), sigma); |
464 | sigma_write(suicide, sizeof(suicide), sigma); | |
465 | sigma_write(suicide, sizeof(suicide), sigma); | |
466 | sigma_write(suicide, sizeof(suicide), sigma); | |
28a35d8a | 467 | |
fefa1800 | 468 | /* Prepare to upload firmware (FPGA specific). */ |
99965709 | 469 | sigma_write(init, sizeof(init), sigma); |
28a35d8a | 470 | |
99965709 | 471 | ftdi_usb_purge_buffers(&sigma->ftdic); |
28a35d8a | 472 | |
fefa1800 | 473 | /* Wait until the FPGA asserts INIT_B. */ |
28a35d8a | 474 | while (1) { |
99965709 | 475 | ret = sigma_read(result, 1, sigma); |
28a35d8a HE |
476 | if (result[0] & 0x20) |
477 | break; | |
478 | } | |
479 | ||
9ddb2a12 | 480 | /* Prepare firmware. */ |
e8397563 | 481 | snprintf(firmware_path, sizeof(firmware_path), "%s/%s", FIRMWARE_DIR, |
f6564c8d HE |
482 | firmware_files[firmware_idx]); |
483 | ||
e8397563 | 484 | if (-1 == bin2bitbang(firmware_path, &buf, &buf_size)) { |
28a35d8a | 485 | g_warning("An error occured while reading the firmware: %s", |
e8397563 | 486 | firmware_path); |
e46b8fb1 | 487 | return SR_ERR; |
28a35d8a HE |
488 | } |
489 | ||
fefa1800 | 490 | /* Upload firmare. */ |
99965709 | 491 | sigma_write(buf, buf_size, sigma); |
28a35d8a HE |
492 | |
493 | g_free(buf); | |
494 | ||
99965709 | 495 | if ((ret = ftdi_set_bitmode(&sigma->ftdic, 0x00, BITMODE_RESET)) < 0) { |
9ddb2a12 | 496 | g_warning("ftdi_set_bitmode failed: %s", |
99965709 | 497 | ftdi_get_error_string(&sigma->ftdic)); |
e46b8fb1 | 498 | return SR_ERR; |
28a35d8a HE |
499 | } |
500 | ||
99965709 | 501 | ftdi_usb_purge_buffers(&sigma->ftdic); |
28a35d8a | 502 | |
fefa1800 | 503 | /* Discard garbage. */ |
99965709 | 504 | while (1 == sigma_read(&pins, 1, sigma)) |
28a35d8a HE |
505 | ; |
506 | ||
fefa1800 | 507 | /* Initialize the logic analyzer mode. */ |
99965709 | 508 | sigma_write(logic_mode_start, sizeof(logic_mode_start), sigma); |
28a35d8a | 509 | |
fefa1800 | 510 | /* Expect a 3 byte reply. */ |
99965709 | 511 | ret = sigma_read(result, 3, sigma); |
28a35d8a HE |
512 | if (ret != 3 || |
513 | result[0] != 0xa6 || result[1] != 0x55 || result[2] != 0xaa) { | |
fefa1800 | 514 | g_warning("Configuration failed. Invalid reply received."); |
e46b8fb1 | 515 | return SR_ERR; |
28a35d8a HE |
516 | } |
517 | ||
99965709 | 518 | sigma->cur_firmware = firmware_idx; |
f6564c8d | 519 | |
e46b8fb1 | 520 | return SR_OK; |
f6564c8d HE |
521 | } |
522 | ||
523 | static int hw_opendev(int device_index) | |
524 | { | |
a00ba012 | 525 | struct sr_device_instance *sdi; |
99965709 | 526 | struct sigma *sigma; |
f6564c8d HE |
527 | int ret; |
528 | ||
d32d961d | 529 | if (!(sdi = sr_get_device_instance(device_instances, device_index))) |
e46b8fb1 | 530 | return SR_ERR; |
99965709 HE |
531 | |
532 | sigma = sdi->priv; | |
533 | ||
9ddb2a12 | 534 | /* Make sure it's an ASIX SIGMA. */ |
99965709 | 535 | if ((ret = ftdi_usb_open_desc(&sigma->ftdic, |
f6564c8d HE |
536 | USB_VENDOR, USB_PRODUCT, USB_DESCRIPTION, NULL)) < 0) { |
537 | ||
538 | g_warning("ftdi_usb_open failed: %s", | |
99965709 | 539 | ftdi_get_error_string(&sigma->ftdic)); |
f6564c8d HE |
540 | |
541 | return 0; | |
542 | } | |
28a35d8a | 543 | |
5a2326a7 | 544 | sdi->status = SR_ST_ACTIVE; |
28a35d8a | 545 | |
e46b8fb1 | 546 | return SR_OK; |
f6564c8d HE |
547 | } |
548 | ||
a00ba012 | 549 | static int set_samplerate(struct sr_device_instance *sdi, |
6aac7737 | 550 | uint64_t samplerate) |
f6564c8d | 551 | { |
e8397563 | 552 | int i, ret; |
99965709 | 553 | struct sigma *sigma = sdi->priv; |
f6564c8d HE |
554 | |
555 | for (i = 0; supported_samplerates[i]; i++) { | |
556 | if (supported_samplerates[i] == samplerate) | |
557 | break; | |
558 | } | |
559 | if (supported_samplerates[i] == 0) | |
e46b8fb1 | 560 | return SR_ERR_SAMPLERATE; |
f6564c8d | 561 | |
e8397563 | 562 | if (samplerate <= MHZ(50)) { |
99965709 HE |
563 | ret = upload_firmware(0, sigma); |
564 | sigma->num_probes = 16; | |
e8397563 | 565 | } |
f78898e9 | 566 | if (samplerate == MHZ(100)) { |
99965709 HE |
567 | ret = upload_firmware(1, sigma); |
568 | sigma->num_probes = 8; | |
f78898e9 HE |
569 | } |
570 | else if (samplerate == MHZ(200)) { | |
99965709 HE |
571 | ret = upload_firmware(2, sigma); |
572 | sigma->num_probes = 4; | |
f78898e9 | 573 | } |
f6564c8d | 574 | |
99965709 HE |
575 | sigma->cur_samplerate = samplerate; |
576 | sigma->samples_per_event = 16 / sigma->num_probes; | |
577 | sigma->state.state = SIGMA_IDLE; | |
f6564c8d | 578 | |
28a35d8a HE |
579 | g_message("Firmware uploaded"); |
580 | ||
e8397563 | 581 | return ret; |
28a35d8a HE |
582 | } |
583 | ||
c53d793f HE |
584 | /* |
585 | * In 100 and 200 MHz mode, only a single pin rising/falling can be | |
586 | * set as trigger. In other modes, two rising/falling triggers can be set, | |
587 | * in addition to value/mask trigger for any number of probes. | |
588 | * | |
589 | * The Sigma supports complex triggers using boolean expressions, but this | |
590 | * has not been implemented yet. | |
591 | */ | |
a00ba012 | 592 | static int configure_probes(struct sr_device_instance *sdi, GSList *probes) |
57bbf56b | 593 | { |
99965709 | 594 | struct sigma *sigma = sdi->priv; |
57bbf56b HE |
595 | struct probe *probe; |
596 | GSList *l; | |
597 | int trigger_set = 0; | |
a42aec7f | 598 | int probebit; |
57bbf56b | 599 | |
99965709 | 600 | memset(&sigma->trigger, 0, sizeof(struct sigma_trigger)); |
eec5275e | 601 | |
57bbf56b HE |
602 | for (l = probes; l; l = l->next) { |
603 | probe = (struct probe *)l->data; | |
a42aec7f | 604 | probebit = 1 << (probe->index - 1); |
57bbf56b HE |
605 | |
606 | if (!probe->enabled || !probe->trigger) | |
607 | continue; | |
608 | ||
99965709 | 609 | if (sigma->cur_samplerate >= MHZ(100)) { |
c53d793f | 610 | /* Fast trigger support. */ |
ee492173 | 611 | if (trigger_set) { |
6aac7737 HE |
612 | g_warning("Asix Sigma only supports a single " |
613 | "pin trigger in 100 and 200 " | |
614 | "MHz mode."); | |
e46b8fb1 | 615 | return SR_ERR; |
ee492173 HE |
616 | } |
617 | if (probe->trigger[0] == 'f') | |
99965709 | 618 | sigma->trigger.fallingmask |= probebit; |
ee492173 | 619 | else if (probe->trigger[0] == 'r') |
99965709 | 620 | sigma->trigger.risingmask |= probebit; |
ee492173 HE |
621 | else { |
622 | g_warning("Asix Sigma only supports " | |
623 | "rising/falling trigger in 100 " | |
624 | "and 200 MHz mode."); | |
e46b8fb1 | 625 | return SR_ERR; |
ee492173 | 626 | } |
57bbf56b | 627 | |
c53d793f | 628 | ++trigger_set; |
ee492173 | 629 | } else { |
c53d793f HE |
630 | /* Simple trigger support (event). */ |
631 | if (probe->trigger[0] == '1') { | |
99965709 HE |
632 | sigma->trigger.simplevalue |= probebit; |
633 | sigma->trigger.simplemask |= probebit; | |
c53d793f HE |
634 | } |
635 | else if (probe->trigger[0] == '0') { | |
99965709 HE |
636 | sigma->trigger.simplevalue &= ~probebit; |
637 | sigma->trigger.simplemask |= probebit; | |
c53d793f HE |
638 | } |
639 | else if (probe->trigger[0] == 'f') { | |
99965709 | 640 | sigma->trigger.fallingmask |= probebit; |
c53d793f HE |
641 | ++trigger_set; |
642 | } | |
643 | else if (probe->trigger[0] == 'r') { | |
99965709 | 644 | sigma->trigger.risingmask |= probebit; |
c53d793f HE |
645 | ++trigger_set; |
646 | } | |
ee492173 | 647 | |
98b8cbc1 HE |
648 | /* |
649 | * Actually, Sigma supports 2 rising/falling triggers, | |
650 | * but they are ORed and the current trigger syntax | |
651 | * does not permit ORed triggers. | |
652 | */ | |
653 | if (trigger_set > 1) { | |
654 | g_warning("Asix Sigma only supports 1 rising/" | |
c53d793f | 655 | "falling triggers."); |
e46b8fb1 | 656 | return SR_ERR; |
ee492173 | 657 | } |
ee492173 | 658 | } |
5b5ea7c6 HE |
659 | |
660 | if (trigger_set) | |
661 | sigma->use_triggers = 1; | |
57bbf56b HE |
662 | } |
663 | ||
e46b8fb1 | 664 | return SR_OK; |
57bbf56b HE |
665 | } |
666 | ||
28a35d8a HE |
667 | static void hw_closedev(int device_index) |
668 | { | |
a00ba012 | 669 | struct sr_device_instance *sdi; |
99965709 | 670 | struct sigma *sigma; |
28a35d8a | 671 | |
d32d961d | 672 | if ((sdi = sr_get_device_instance(device_instances, device_index))) |
9be9893e | 673 | { |
99965709 | 674 | sigma = sdi->priv; |
5a2326a7 | 675 | if (sdi->status == SR_ST_ACTIVE) |
99965709 | 676 | ftdi_usb_close(&sigma->ftdic); |
9be9893e | 677 | |
5a2326a7 | 678 | sdi->status = SR_ST_INACTIVE; |
9be9893e | 679 | } |
28a35d8a HE |
680 | } |
681 | ||
28a35d8a HE |
682 | static void hw_cleanup(void) |
683 | { | |
99965709 | 684 | GSList *l; |
a00ba012 | 685 | struct sr_device_instance *sdi; |
99965709 HE |
686 | |
687 | /* Properly close all devices. */ | |
688 | for (l = device_instances; l; l = l->next) { | |
689 | sdi = l->data; | |
690 | if (sdi->priv != NULL) | |
691 | free(sdi->priv); | |
a00ba012 | 692 | sr_device_instance_free(sdi); |
99965709 HE |
693 | } |
694 | g_slist_free(device_instances); | |
695 | device_instances = NULL; | |
28a35d8a HE |
696 | } |
697 | ||
28a35d8a HE |
698 | static void *hw_get_device_info(int device_index, int device_info_id) |
699 | { | |
a00ba012 | 700 | struct sr_device_instance *sdi; |
99965709 | 701 | struct sigma *sigma; |
28a35d8a HE |
702 | void *info = NULL; |
703 | ||
d32d961d | 704 | if (!(sdi = sr_get_device_instance(device_instances, device_index))) { |
28a35d8a HE |
705 | fprintf(stderr, "It's NULL.\n"); |
706 | return NULL; | |
707 | } | |
708 | ||
99965709 HE |
709 | sigma = sdi->priv; |
710 | ||
28a35d8a | 711 | switch (device_info_id) { |
5a2326a7 | 712 | case SR_DI_INSTANCE: |
28a35d8a HE |
713 | info = sdi; |
714 | break; | |
5a2326a7 | 715 | case SR_DI_NUM_PROBES: |
edca2c5c | 716 | info = GINT_TO_POINTER(16); |
28a35d8a | 717 | break; |
5a2326a7 | 718 | case SR_DI_SAMPLERATES: |
28a35d8a HE |
719 | info = &samplerates; |
720 | break; | |
5a2326a7 | 721 | case SR_DI_TRIGGER_TYPES: |
57bbf56b | 722 | info = (char *)TRIGGER_TYPES; |
28a35d8a | 723 | break; |
5a2326a7 | 724 | case SR_DI_CUR_SAMPLERATE: |
99965709 | 725 | info = &sigma->cur_samplerate; |
28a35d8a HE |
726 | break; |
727 | } | |
728 | ||
729 | return info; | |
730 | } | |
731 | ||
28a35d8a HE |
732 | static int hw_get_status(int device_index) |
733 | { | |
a00ba012 | 734 | struct sr_device_instance *sdi; |
28a35d8a | 735 | |
d32d961d | 736 | sdi = sr_get_device_instance(device_instances, device_index); |
28a35d8a HE |
737 | if (sdi) |
738 | return sdi->status; | |
739 | else | |
5a2326a7 | 740 | return SR_ST_NOT_FOUND; |
28a35d8a HE |
741 | } |
742 | ||
28a35d8a HE |
743 | static int *hw_get_capabilities(void) |
744 | { | |
745 | return capabilities; | |
746 | } | |
747 | ||
748 | static int hw_set_configuration(int device_index, int capability, void *value) | |
749 | { | |
a00ba012 | 750 | struct sr_device_instance *sdi; |
99965709 | 751 | struct sigma *sigma; |
28a35d8a | 752 | int ret; |
f6564c8d | 753 | |
d32d961d | 754 | if (!(sdi = sr_get_device_instance(device_instances, device_index))) |
e46b8fb1 | 755 | return SR_ERR; |
28a35d8a | 756 | |
99965709 HE |
757 | sigma = sdi->priv; |
758 | ||
5a2326a7 | 759 | if (capability == SR_HWCAP_SAMPLERATE) { |
f6564c8d | 760 | ret = set_samplerate(sdi, *(uint64_t*) value); |
5a2326a7 | 761 | } else if (capability == SR_HWCAP_PROBECONFIG) { |
99965709 | 762 | ret = configure_probes(sdi, value); |
5a2326a7 | 763 | } else if (capability == SR_HWCAP_LIMIT_MSEC) { |
94ba4bd6 HE |
764 | sigma->limit_msec = *(uint64_t*) value; |
765 | if (sigma->limit_msec > 0) | |
e46b8fb1 | 766 | ret = SR_OK; |
94ba4bd6 | 767 | else |
e46b8fb1 | 768 | ret = SR_ERR; |
5a2326a7 | 769 | } else if (capability == SR_HWCAP_CAPTURE_RATIO) { |
94ba4bd6 HE |
770 | sigma->capture_ratio = *(uint64_t*) value; |
771 | if (sigma->capture_ratio < 0 || sigma->capture_ratio > 100) | |
e46b8fb1 | 772 | ret = SR_ERR; |
94ba4bd6 | 773 | else |
e46b8fb1 | 774 | ret = SR_OK; |
28a35d8a | 775 | } else { |
e46b8fb1 | 776 | ret = SR_ERR; |
28a35d8a HE |
777 | } |
778 | ||
779 | return ret; | |
780 | } | |
781 | ||
36b1c8e6 HE |
782 | /* Software trigger to determine exact trigger position. */ |
783 | static int get_trigger_offset(uint16_t *samples, uint16_t last_sample, | |
784 | struct sigma_trigger *t) | |
785 | { | |
786 | int i; | |
787 | ||
788 | for (i = 0; i < 8; ++i) { | |
789 | if (i > 0) | |
790 | last_sample = samples[i-1]; | |
791 | ||
792 | /* Simple triggers. */ | |
793 | if ((samples[i] & t->simplemask) != t->simplevalue) | |
794 | continue; | |
795 | ||
796 | /* Rising edge. */ | |
797 | if ((last_sample & t->risingmask) != 0 || (samples[i] & | |
798 | t->risingmask) != t->risingmask) | |
799 | continue; | |
800 | ||
801 | /* Falling edge. */ | |
bdfc7a89 HE |
802 | if ((last_sample & t->fallingmask) != t->fallingmask || |
803 | (samples[i] & t->fallingmask) != 0) | |
36b1c8e6 HE |
804 | continue; |
805 | ||
806 | break; | |
807 | } | |
808 | ||
809 | /* If we did not match, return original trigger pos. */ | |
810 | return i & 0x7; | |
811 | } | |
812 | ||
28a35d8a | 813 | /* |
fefa1800 UH |
814 | * Decode chunk of 1024 bytes, 64 clusters, 7 events per cluster. |
815 | * Each event is 20ns apart, and can contain multiple samples. | |
f78898e9 HE |
816 | * |
817 | * For 200 MHz, events contain 4 samples for each channel, spread 5 ns apart. | |
818 | * For 100 MHz, events contain 2 samples for each channel, spread 10 ns apart. | |
819 | * For 50 MHz and below, events contain one sample for each channel, | |
820 | * spread 20 ns apart. | |
28a35d8a HE |
821 | */ |
822 | static int decode_chunk_ts(uint8_t *buf, uint16_t *lastts, | |
88c51afe HE |
823 | uint16_t *lastsample, int triggerpos, |
824 | uint16_t limit_chunk, void *user_data) | |
28a35d8a | 825 | { |
a00ba012 | 826 | struct sr_device_instance *sdi = user_data; |
99965709 | 827 | struct sigma *sigma = sdi->priv; |
fefa1800 | 828 | uint16_t tsdiff, ts; |
99965709 | 829 | uint16_t samples[65536 * sigma->samples_per_event]; |
b9c735a2 | 830 | struct sr_datafeed_packet packet; |
f78898e9 | 831 | int i, j, k, l, numpad, tosend; |
fefa1800 | 832 | size_t n = 0, sent = 0; |
99965709 | 833 | int clustersize = EVENTS_PER_CLUSTER * sigma->samples_per_event; |
fefa1800 | 834 | uint16_t *event; |
f78898e9 | 835 | uint16_t cur_sample; |
57bbf56b | 836 | int triggerts = -1; |
ee492173 | 837 | |
4ae1f451 | 838 | /* Check if trigger is in this chunk. */ |
ee492173 | 839 | if (triggerpos != -1) { |
99965709 | 840 | if (sigma->cur_samplerate <= MHZ(50)) |
36b1c8e6 | 841 | triggerpos -= EVENTS_PER_CLUSTER - 1; |
ee492173 HE |
842 | |
843 | if (triggerpos < 0) | |
844 | triggerpos = 0; | |
57bbf56b | 845 | |
ee492173 HE |
846 | /* Find in which cluster the trigger occured. */ |
847 | triggerts = triggerpos / 7; | |
848 | } | |
28a35d8a | 849 | |
eec5275e | 850 | /* For each ts. */ |
28a35d8a | 851 | for (i = 0; i < 64; ++i) { |
fefa1800 | 852 | ts = *(uint16_t *) &buf[i * 16]; |
28a35d8a HE |
853 | tsdiff = ts - *lastts; |
854 | *lastts = ts; | |
855 | ||
88c51afe HE |
856 | /* Decode partial chunk. */ |
857 | if (limit_chunk && ts > limit_chunk) | |
e46b8fb1 | 858 | return SR_OK; |
88c51afe | 859 | |
fefa1800 | 860 | /* Pad last sample up to current point. */ |
99965709 | 861 | numpad = tsdiff * sigma->samples_per_event - clustersize; |
28a35d8a | 862 | if (numpad > 0) { |
f78898e9 HE |
863 | for (j = 0; j < numpad; ++j) |
864 | samples[j] = *lastsample; | |
865 | ||
866 | n = numpad; | |
28a35d8a HE |
867 | } |
868 | ||
57bbf56b HE |
869 | /* Send samples between previous and this timestamp to sigrok. */ |
870 | sent = 0; | |
871 | while (sent < n) { | |
872 | tosend = MIN(2048, n - sent); | |
873 | ||
5a2326a7 | 874 | packet.type = SR_DF_LOGIC; |
57bbf56b | 875 | packet.length = tosend * sizeof(uint16_t); |
4c046c6b | 876 | packet.unitsize = 2; |
57bbf56b | 877 | packet.payload = samples + sent; |
99965709 | 878 | session_bus(sigma->session_id, &packet); |
28a35d8a | 879 | |
57bbf56b HE |
880 | sent += tosend; |
881 | } | |
882 | n = 0; | |
883 | ||
884 | event = (uint16_t *) &buf[i * 16 + 2]; | |
f78898e9 HE |
885 | cur_sample = 0; |
886 | ||
887 | /* For each event in cluster. */ | |
28a35d8a | 888 | for (j = 0; j < 7; ++j) { |
f78898e9 HE |
889 | |
890 | /* For each sample in event. */ | |
99965709 | 891 | for (k = 0; k < sigma->samples_per_event; ++k) { |
f78898e9 HE |
892 | cur_sample = 0; |
893 | ||
894 | /* For each probe. */ | |
99965709 | 895 | for (l = 0; l < sigma->num_probes; ++l) |
edca2c5c | 896 | cur_sample |= (!!(event[j] & (1 << (l * |
99965709 HE |
897 | sigma->samples_per_event |
898 | + k)))) | |
edca2c5c | 899 | << l; |
f78898e9 HE |
900 | |
901 | samples[n++] = cur_sample; | |
28a35d8a HE |
902 | } |
903 | } | |
904 | ||
eec5275e | 905 | /* Send data up to trigger point (if triggered). */ |
fefa1800 | 906 | sent = 0; |
57bbf56b HE |
907 | if (i == triggerts) { |
908 | /* | |
36b1c8e6 HE |
909 | * Trigger is not always accurate to sample because of |
910 | * pipeline delay. However, it always triggers before | |
911 | * the actual event. We therefore look at the next | |
912 | * samples to pinpoint the exact position of the trigger. | |
57bbf56b | 913 | */ |
bdfc7a89 | 914 | tosend = get_trigger_offset(samples, *lastsample, |
99965709 | 915 | &sigma->trigger); |
57bbf56b HE |
916 | |
917 | if (tosend > 0) { | |
5a2326a7 | 918 | packet.type = SR_DF_LOGIC; |
57bbf56b | 919 | packet.length = tosend * sizeof(uint16_t); |
4c046c6b | 920 | packet.unitsize = 2; |
57bbf56b | 921 | packet.payload = samples; |
99965709 | 922 | session_bus(sigma->session_id, &packet); |
57bbf56b HE |
923 | |
924 | sent += tosend; | |
925 | } | |
28a35d8a | 926 | |
5b5ea7c6 HE |
927 | /* Only send trigger if explicitly enabled. */ |
928 | if (sigma->use_triggers) { | |
5a2326a7 | 929 | packet.type = SR_DF_TRIGGER; |
5b5ea7c6 HE |
930 | packet.length = 0; |
931 | packet.payload = 0; | |
932 | session_bus(sigma->session_id, &packet); | |
933 | } | |
28a35d8a | 934 | } |
57bbf56b | 935 | |
eec5275e | 936 | /* Send rest of the chunk to sigrok. */ |
57bbf56b HE |
937 | tosend = n - sent; |
938 | ||
abda62ce | 939 | if (tosend > 0) { |
5a2326a7 | 940 | packet.type = SR_DF_LOGIC; |
abda62ce HE |
941 | packet.length = tosend * sizeof(uint16_t); |
942 | packet.unitsize = 2; | |
943 | packet.payload = samples + sent; | |
944 | session_bus(sigma->session_id, &packet); | |
945 | } | |
ee492173 HE |
946 | |
947 | *lastsample = samples[n - 1]; | |
28a35d8a HE |
948 | } |
949 | ||
e46b8fb1 | 950 | return SR_OK; |
28a35d8a HE |
951 | } |
952 | ||
953 | static int receive_data(int fd, int revents, void *user_data) | |
954 | { | |
a00ba012 | 955 | struct sr_device_instance *sdi = user_data; |
99965709 | 956 | struct sigma *sigma = sdi->priv; |
b9c735a2 | 957 | struct sr_datafeed_packet packet; |
28a35d8a HE |
958 | const int chunks_per_read = 32; |
959 | unsigned char buf[chunks_per_read * CHUNK_SIZE]; | |
6aac7737 | 960 | int bufsz, numchunks, i, newchunks; |
94ba4bd6 | 961 | uint64_t running_msec; |
28a35d8a | 962 | struct timeval tv; |
28a35d8a HE |
963 | |
964 | fd = fd; | |
965 | revents = revents; | |
966 | ||
31facdd3 | 967 | numchunks = (sigma->state.stoppos + 511) / 512; |
28a35d8a | 968 | |
99965709 | 969 | if (sigma->state.state == SIGMA_IDLE) |
28a35d8a HE |
970 | return FALSE; |
971 | ||
99965709 | 972 | if (sigma->state.state == SIGMA_CAPTURE) { |
28a35d8a | 973 | |
6aac7737 HE |
974 | /* Check if the timer has expired, or memory is full. */ |
975 | gettimeofday(&tv, 0); | |
99965709 HE |
976 | running_msec = (tv.tv_sec - sigma->start_tv.tv_sec) * 1000 + |
977 | (tv.tv_usec - sigma->start_tv.tv_usec) / 1000; | |
28a35d8a | 978 | |
99965709 | 979 | if (running_msec < sigma->limit_msec && numchunks < 32767) |
6aac7737 | 980 | return FALSE; |
28a35d8a | 981 | |
99965709 | 982 | hw_stop_acquisition(sdi->index, user_data); |
6aac7737 HE |
983 | |
984 | return FALSE; | |
985 | ||
99965709 HE |
986 | } else if (sigma->state.state == SIGMA_DOWNLOAD) { |
987 | if (sigma->state.chunks_downloaded >= numchunks) { | |
6aac7737 | 988 | /* End of samples. */ |
5a2326a7 | 989 | packet.type = SR_DF_END; |
6aac7737 | 990 | packet.length = 0; |
99965709 | 991 | session_bus(sigma->session_id, &packet); |
6aac7737 | 992 | |
99965709 | 993 | sigma->state.state = SIGMA_IDLE; |
f78898e9 | 994 | |
6aac7737 HE |
995 | return TRUE; |
996 | } | |
997 | ||
998 | newchunks = MIN(chunks_per_read, | |
99965709 | 999 | numchunks - sigma->state.chunks_downloaded); |
28a35d8a HE |
1000 | |
1001 | g_message("Downloading sample data: %.0f %%", | |
99965709 | 1002 | 100.0 * sigma->state.chunks_downloaded / numchunks); |
28a35d8a | 1003 | |
99965709 HE |
1004 | bufsz = sigma_read_dram(sigma->state.chunks_downloaded, |
1005 | newchunks, buf, sigma); | |
28a35d8a | 1006 | |
fefa1800 | 1007 | /* Find first ts. */ |
99965709 HE |
1008 | if (sigma->state.chunks_downloaded == 0) { |
1009 | sigma->state.lastts = *(uint16_t *) buf - 1; | |
1010 | sigma->state.lastsample = 0; | |
6aac7737 | 1011 | } |
28a35d8a | 1012 | |
fefa1800 | 1013 | /* Decode chunks and send them to sigrok. */ |
28a35d8a | 1014 | for (i = 0; i < newchunks; ++i) { |
88c51afe HE |
1015 | int limit_chunk = 0; |
1016 | ||
1017 | /* The last chunk may potentially be only in part. */ | |
1018 | if (sigma->state.chunks_downloaded == numchunks - 1) | |
1019 | { | |
1020 | /* Find the last valid timestamp */ | |
1021 | limit_chunk = sigma->state.stoppos % 512 + sigma->state.lastts; | |
1022 | } | |
1023 | ||
99965709 | 1024 | if (sigma->state.chunks_downloaded + i == sigma->state.triggerchunk) |
57bbf56b | 1025 | decode_chunk_ts(buf + (i * CHUNK_SIZE), |
99965709 HE |
1026 | &sigma->state.lastts, |
1027 | &sigma->state.lastsample, | |
1028 | sigma->state.triggerpos & 0x1ff, | |
88c51afe | 1029 | limit_chunk, user_data); |
57bbf56b HE |
1030 | else |
1031 | decode_chunk_ts(buf + (i * CHUNK_SIZE), | |
99965709 HE |
1032 | &sigma->state.lastts, |
1033 | &sigma->state.lastsample, | |
88c51afe | 1034 | -1, limit_chunk, user_data); |
28a35d8a | 1035 | |
88c51afe HE |
1036 | ++sigma->state.chunks_downloaded; |
1037 | } | |
28a35d8a HE |
1038 | } |
1039 | ||
28a35d8a HE |
1040 | return TRUE; |
1041 | } | |
1042 | ||
c53d793f HE |
1043 | /* Build a LUT entry used by the trigger functions. */ |
1044 | static void build_lut_entry(uint16_t value, uint16_t mask, uint16_t *entry) | |
ee492173 HE |
1045 | { |
1046 | int i, j, k, bit; | |
1047 | ||
f758d074 | 1048 | /* For each quad probe. */ |
ee492173 | 1049 | for (i = 0; i < 4; ++i) { |
c53d793f | 1050 | entry[i] = 0xffff; |
ee492173 | 1051 | |
f758d074 | 1052 | /* For each bit in LUT. */ |
ee492173 HE |
1053 | for (j = 0; j < 16; ++j) |
1054 | ||
f758d074 | 1055 | /* For each probe in quad. */ |
ee492173 HE |
1056 | for (k = 0; k < 4; ++k) { |
1057 | bit = 1 << (i * 4 + k); | |
1058 | ||
c53d793f HE |
1059 | /* Set bit in entry */ |
1060 | if ((mask & bit) && | |
1061 | ((!(value & bit)) != | |
4ae1f451 | 1062 | (!(j & (1 << k))))) |
c53d793f | 1063 | entry[i] &= ~(1 << j); |
ee492173 HE |
1064 | } |
1065 | } | |
c53d793f | 1066 | } |
ee492173 | 1067 | |
c53d793f HE |
1068 | /* Add a logical function to LUT mask. */ |
1069 | static void add_trigger_function(enum triggerop oper, enum triggerfunc func, | |
1070 | int index, int neg, uint16_t *mask) | |
1071 | { | |
1072 | int i, j; | |
1073 | int x[2][2], tmp, a, b, aset, bset, rset; | |
1074 | ||
1075 | memset(x, 0, 4 * sizeof(int)); | |
1076 | ||
1077 | /* Trigger detect condition. */ | |
1078 | switch (oper) { | |
1079 | case OP_LEVEL: | |
1080 | x[0][1] = 1; | |
1081 | x[1][1] = 1; | |
1082 | break; | |
1083 | case OP_NOT: | |
1084 | x[0][0] = 1; | |
1085 | x[1][0] = 1; | |
1086 | break; | |
1087 | case OP_RISE: | |
1088 | x[0][1] = 1; | |
1089 | break; | |
1090 | case OP_FALL: | |
1091 | x[1][0] = 1; | |
1092 | break; | |
1093 | case OP_RISEFALL: | |
1094 | x[0][1] = 1; | |
1095 | x[1][0] = 1; | |
1096 | break; | |
1097 | case OP_NOTRISE: | |
1098 | x[1][1] = 1; | |
1099 | x[0][0] = 1; | |
1100 | x[1][0] = 1; | |
1101 | break; | |
1102 | case OP_NOTFALL: | |
1103 | x[1][1] = 1; | |
1104 | x[0][0] = 1; | |
1105 | x[0][1] = 1; | |
1106 | break; | |
1107 | case OP_NOTRISEFALL: | |
1108 | x[1][1] = 1; | |
1109 | x[0][0] = 1; | |
1110 | break; | |
1111 | } | |
1112 | ||
1113 | /* Transpose if neg is set. */ | |
1114 | if (neg) { | |
1115 | for (i = 0; i < 2; ++i) | |
1116 | for (j = 0; j < 2; ++j) { | |
1117 | tmp = x[i][j]; | |
1118 | x[i][j] = x[1-i][1-j]; | |
1119 | x[1-i][1-j] = tmp; | |
1120 | } | |
1121 | } | |
1122 | ||
1123 | /* Update mask with function. */ | |
1124 | for (i = 0; i < 16; ++i) { | |
1125 | a = (i >> (2 * index + 0)) & 1; | |
1126 | b = (i >> (2 * index + 1)) & 1; | |
1127 | ||
1128 | aset = (*mask >> i) & 1; | |
1129 | bset = x[b][a]; | |
1130 | ||
1131 | if (func == FUNC_AND || func == FUNC_NAND) | |
1132 | rset = aset & bset; | |
1133 | else if (func == FUNC_OR || func == FUNC_NOR) | |
1134 | rset = aset | bset; | |
1135 | else if (func == FUNC_XOR || func == FUNC_NXOR) | |
1136 | rset = aset ^ bset; | |
1137 | ||
1138 | if (func == FUNC_NAND || func == FUNC_NOR || func == FUNC_NXOR) | |
1139 | rset = !rset; | |
1140 | ||
1141 | *mask &= ~(1 << i); | |
1142 | ||
1143 | if (rset) | |
1144 | *mask |= 1 << i; | |
1145 | } | |
1146 | } | |
1147 | ||
1148 | /* | |
1149 | * Build trigger LUTs used by 50 MHz and lower sample rates for supporting | |
1150 | * simple pin change and state triggers. Only two transitions (rise/fall) can be | |
1151 | * set at any time, but a full mask and value can be set (0/1). | |
1152 | */ | |
99965709 | 1153 | static int build_basic_trigger(struct triggerlut *lut, struct sigma *sigma) |
c53d793f HE |
1154 | { |
1155 | int i,j; | |
4ae1f451 | 1156 | uint16_t masks[2] = { 0, 0 }; |
c53d793f HE |
1157 | |
1158 | memset(lut, 0, sizeof(struct triggerlut)); | |
1159 | ||
1160 | /* Contant for simple triggers. */ | |
1161 | lut->m4 = 0xa000; | |
1162 | ||
1163 | /* Value/mask trigger support. */ | |
99965709 HE |
1164 | build_lut_entry(sigma->trigger.simplevalue, sigma->trigger.simplemask, |
1165 | lut->m2d); | |
c53d793f HE |
1166 | |
1167 | /* Rise/fall trigger support. */ | |
1168 | for (i = 0, j = 0; i < 16; ++i) { | |
99965709 HE |
1169 | if (sigma->trigger.risingmask & (1 << i) || |
1170 | sigma->trigger.fallingmask & (1 << i)) | |
c53d793f HE |
1171 | masks[j++] = 1 << i; |
1172 | } | |
1173 | ||
1174 | build_lut_entry(masks[0], masks[0], lut->m0d); | |
1175 | build_lut_entry(masks[1], masks[1], lut->m1d); | |
1176 | ||
1177 | /* Add glue logic */ | |
1178 | if (masks[0] || masks[1]) { | |
1179 | /* Transition trigger. */ | |
99965709 | 1180 | if (masks[0] & sigma->trigger.risingmask) |
c53d793f | 1181 | add_trigger_function(OP_RISE, FUNC_OR, 0, 0, &lut->m3); |
99965709 | 1182 | if (masks[0] & sigma->trigger.fallingmask) |
c53d793f | 1183 | add_trigger_function(OP_FALL, FUNC_OR, 0, 0, &lut->m3); |
99965709 | 1184 | if (masks[1] & sigma->trigger.risingmask) |
c53d793f | 1185 | add_trigger_function(OP_RISE, FUNC_OR, 1, 0, &lut->m3); |
99965709 | 1186 | if (masks[1] & sigma->trigger.fallingmask) |
c53d793f HE |
1187 | add_trigger_function(OP_FALL, FUNC_OR, 1, 0, &lut->m3); |
1188 | } else { | |
1189 | /* Only value/mask trigger. */ | |
1190 | lut->m3 = 0xffff; | |
1191 | } | |
ee492173 | 1192 | |
c53d793f | 1193 | /* Triggertype: event. */ |
ee492173 HE |
1194 | lut->params.selres = 3; |
1195 | ||
e46b8fb1 | 1196 | return SR_OK; |
ee492173 HE |
1197 | } |
1198 | ||
28a35d8a HE |
1199 | static int hw_start_acquisition(int device_index, gpointer session_device_id) |
1200 | { | |
a00ba012 | 1201 | struct sr_device_instance *sdi; |
99965709 | 1202 | struct sigma *sigma; |
b9c735a2 UH |
1203 | struct sr_datafeed_packet packet; |
1204 | struct sr_datafeed_header header; | |
9ddb2a12 UH |
1205 | struct clockselect_50 clockselect; |
1206 | int frac; | |
57bbf56b HE |
1207 | uint8_t triggerselect; |
1208 | struct triggerinout triggerinout_conf; | |
ee492173 | 1209 | struct triggerlut lut; |
a42aec7f | 1210 | int triggerpin; |
28a35d8a HE |
1211 | |
1212 | session_device_id = session_device_id; | |
1213 | ||
d32d961d | 1214 | if (!(sdi = sr_get_device_instance(device_instances, device_index))) |
e46b8fb1 | 1215 | return SR_ERR; |
28a35d8a | 1216 | |
99965709 | 1217 | sigma = sdi->priv; |
28a35d8a | 1218 | |
7c70c538 | 1219 | /* If the samplerate has not been set, default to 200 KHz. */ |
99965709 | 1220 | if (sigma->cur_firmware == -1) |
7c70c538 | 1221 | set_samplerate(sdi, KHZ(200)); |
e8397563 | 1222 | |
eec5275e | 1223 | /* Enter trigger programming mode. */ |
99965709 | 1224 | sigma_set_register(WRITE_TRIGGER_SELECT1, 0x20, sigma); |
28a35d8a | 1225 | |
eec5275e | 1226 | /* 100 and 200 MHz mode. */ |
99965709 HE |
1227 | if (sigma->cur_samplerate >= MHZ(100)) { |
1228 | sigma_set_register(WRITE_TRIGGER_SELECT1, 0x81, sigma); | |
57bbf56b | 1229 | |
a42aec7f HE |
1230 | /* Find which pin to trigger on from mask. */ |
1231 | for (triggerpin = 0; triggerpin < 8; ++triggerpin) | |
99965709 | 1232 | if ((sigma->trigger.risingmask | sigma->trigger.fallingmask) & |
a42aec7f HE |
1233 | (1 << triggerpin)) |
1234 | break; | |
1235 | ||
1236 | /* Set trigger pin and light LED on trigger. */ | |
1237 | triggerselect = (1 << LEDSEL1) | (triggerpin & 0x7); | |
1238 | ||
1239 | /* Default rising edge. */ | |
99965709 | 1240 | if (sigma->trigger.fallingmask) |
a42aec7f | 1241 | triggerselect |= 1 << 3; |
57bbf56b | 1242 | |
eec5275e | 1243 | /* All other modes. */ |
99965709 HE |
1244 | } else if (sigma->cur_samplerate <= MHZ(50)) { |
1245 | build_basic_trigger(&lut, sigma); | |
ee492173 | 1246 | |
99965709 | 1247 | sigma_write_trigger_lut(&lut, sigma); |
57bbf56b HE |
1248 | |
1249 | triggerselect = (1 << LEDSEL1) | (1 << LEDSEL0); | |
1250 | } | |
1251 | ||
eec5275e | 1252 | /* Setup trigger in and out pins to default values. */ |
57bbf56b HE |
1253 | memset(&triggerinout_conf, 0, sizeof(struct triggerinout)); |
1254 | triggerinout_conf.trgout_bytrigger = 1; | |
1255 | triggerinout_conf.trgout_enable = 1; | |
1256 | ||
28a35d8a | 1257 | sigma_write_register(WRITE_TRIGGER_OPTION, |
57bbf56b | 1258 | (uint8_t *) &triggerinout_conf, |
99965709 | 1259 | sizeof(struct triggerinout), sigma); |
28a35d8a | 1260 | |
eec5275e | 1261 | /* Go back to normal mode. */ |
99965709 | 1262 | sigma_set_register(WRITE_TRIGGER_SELECT1, triggerselect, sigma); |
28a35d8a | 1263 | |
edca2c5c | 1264 | /* Set clock select register. */ |
99965709 | 1265 | if (sigma->cur_samplerate == MHZ(200)) |
edca2c5c | 1266 | /* Enable 4 probes. */ |
99965709 HE |
1267 | sigma_set_register(WRITE_CLOCK_SELECT, 0xf0, sigma); |
1268 | else if (sigma->cur_samplerate == MHZ(100)) | |
edca2c5c | 1269 | /* Enable 8 probes. */ |
99965709 | 1270 | sigma_set_register(WRITE_CLOCK_SELECT, 0x00, sigma); |
edca2c5c HE |
1271 | else { |
1272 | /* | |
9ddb2a12 | 1273 | * 50 MHz mode (or fraction thereof). Any fraction down to |
eec5275e | 1274 | * 50 MHz / 256 can be used, but is not supported by sigrok API. |
edca2c5c | 1275 | */ |
99965709 | 1276 | frac = MHZ(50) / sigma->cur_samplerate - 1; |
edca2c5c | 1277 | |
9ddb2a12 UH |
1278 | clockselect.async = 0; |
1279 | clockselect.fraction = frac; | |
1280 | clockselect.disabled_probes = 0; | |
edca2c5c HE |
1281 | |
1282 | sigma_write_register(WRITE_CLOCK_SELECT, | |
9ddb2a12 | 1283 | (uint8_t *) &clockselect, |
99965709 | 1284 | sizeof(clockselect), sigma); |
edca2c5c HE |
1285 | } |
1286 | ||
fefa1800 | 1287 | /* Setup maximum post trigger time. */ |
99965709 HE |
1288 | sigma_set_register(WRITE_POST_TRIGGER, |
1289 | (sigma->capture_ratio * 255) / 100, sigma); | |
28a35d8a | 1290 | |
eec5275e | 1291 | /* Start acqusition. */ |
99965709 HE |
1292 | gettimeofday(&sigma->start_tv, 0); |
1293 | sigma_set_register(WRITE_MODE, 0x0d, sigma); | |
1294 | ||
1295 | sigma->session_id = session_device_id; | |
28a35d8a | 1296 | |
28a35d8a | 1297 | /* Send header packet to the session bus. */ |
5a2326a7 | 1298 | packet.type = SR_DF_HEADER; |
b9c735a2 | 1299 | packet.length = sizeof(struct sr_datafeed_header); |
28a35d8a HE |
1300 | packet.payload = &header; |
1301 | header.feed_version = 1; | |
1302 | gettimeofday(&header.starttime, NULL); | |
99965709 | 1303 | header.samplerate = sigma->cur_samplerate; |
5a2326a7 | 1304 | header.protocol_id = SR_PROTO_RAW; |
99965709 | 1305 | header.num_logic_probes = sigma->num_probes; |
c2616fb9 | 1306 | header.num_analog_probes = 0; |
28a35d8a HE |
1307 | session_bus(session_device_id, &packet); |
1308 | ||
57bbf56b | 1309 | /* Add capture source. */ |
99965709 | 1310 | source_add(0, G_IO_IN, 10, receive_data, sdi); |
57bbf56b | 1311 | |
99965709 | 1312 | sigma->state.state = SIGMA_CAPTURE; |
6aac7737 | 1313 | |
e46b8fb1 | 1314 | return SR_OK; |
28a35d8a HE |
1315 | } |
1316 | ||
28a35d8a HE |
1317 | static void hw_stop_acquisition(int device_index, gpointer session_device_id) |
1318 | { | |
a00ba012 | 1319 | struct sr_device_instance *sdi; |
99965709 | 1320 | struct sigma *sigma; |
6aac7737 HE |
1321 | uint8_t modestatus; |
1322 | ||
d32d961d | 1323 | if (!(sdi = sr_get_device_instance(device_instances, device_index))) |
99965709 HE |
1324 | return; |
1325 | ||
1326 | sigma = sdi->priv; | |
1327 | ||
28a35d8a HE |
1328 | session_device_id = session_device_id; |
1329 | ||
fefa1800 | 1330 | /* Stop acquisition. */ |
99965709 | 1331 | sigma_set_register(WRITE_MODE, 0x11, sigma); |
28a35d8a | 1332 | |
6aac7737 | 1333 | /* Set SDRAM Read Enable. */ |
99965709 | 1334 | sigma_set_register(WRITE_MODE, 0x02, sigma); |
6aac7737 HE |
1335 | |
1336 | /* Get the current position. */ | |
99965709 | 1337 | sigma_read_pos(&sigma->state.stoppos, &sigma->state.triggerpos, sigma); |
6aac7737 HE |
1338 | |
1339 | /* Check if trigger has fired. */ | |
99965709 | 1340 | modestatus = sigma_get_register(READ_MODE, sigma); |
6aac7737 | 1341 | if (modestatus & 0x20) { |
99965709 | 1342 | sigma->state.triggerchunk = sigma->state.triggerpos / 512; |
6aac7737 HE |
1343 | |
1344 | } else | |
99965709 | 1345 | sigma->state.triggerchunk = -1; |
6aac7737 | 1346 | |
99965709 | 1347 | sigma->state.chunks_downloaded = 0; |
6aac7737 | 1348 | |
99965709 | 1349 | sigma->state.state = SIGMA_DOWNLOAD; |
28a35d8a HE |
1350 | } |
1351 | ||
5c2d46d1 | 1352 | struct sr_device_plugin asix_sigma_plugin_info = { |
28a35d8a | 1353 | "asix-sigma", |
9f8274a5 | 1354 | "ASIX SIGMA", |
28a35d8a HE |
1355 | 1, |
1356 | hw_init, | |
1357 | hw_cleanup, | |
28a35d8a HE |
1358 | hw_opendev, |
1359 | hw_closedev, | |
1360 | hw_get_device_info, | |
1361 | hw_get_status, | |
1362 | hw_get_capabilities, | |
1363 | hw_set_configuration, | |
1364 | hw_start_acquisition, | |
9ddb2a12 | 1365 | hw_stop_acquisition, |
28a35d8a | 1366 | }; |