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Commit | Line | Data |
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28a35d8a HE |
1 | /* |
2 | * This file is part of the sigrok project. | |
3 | * | |
911f1834 UH |
4 | * Copyright (C) 2010 Håvard Espeland <gus@ping.uio.no>, |
5 | * Copyright (C) 2010 Martin Stensgård <mastensg@ping.uio.no> | |
6 | * Copyright (C) 2010 Carl Henrik Lunde <chlunde@ping.uio.no> | |
28a35d8a HE |
7 | * |
8 | * This program is free software: you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation, either version 3 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
20 | */ | |
21 | ||
911f1834 UH |
22 | /* |
23 | * ASIX Sigma Logic Analyzer Driver | |
24 | */ | |
25 | ||
22b02383 | 26 | #include "config.h" |
3bbd9849 UH |
27 | #include <glib.h> |
28 | #include <glib/gstdio.h> | |
28a35d8a HE |
29 | #include <ftdi.h> |
30 | #include <string.h> | |
31 | #include <zlib.h> | |
fefa1800 | 32 | #include <sigrok.h> |
28a35d8a HE |
33 | #include "asix-sigma.h" |
34 | ||
35 | #define USB_VENDOR 0xa600 | |
36 | #define USB_PRODUCT 0xa000 | |
37 | #define USB_DESCRIPTION "ASIX SIGMA" | |
38 | #define USB_VENDOR_NAME "ASIX" | |
39 | #define USB_MODEL_NAME "SIGMA" | |
40 | #define USB_MODEL_VERSION "" | |
ee492173 | 41 | #define TRIGGER_TYPES "rf10" |
28a35d8a HE |
42 | |
43 | static GSList *device_instances = NULL; | |
44 | ||
28a35d8a | 45 | static uint64_t supported_samplerates[] = { |
59df0c77 UH |
46 | SR_KHZ(200), |
47 | SR_KHZ(250), | |
48 | SR_KHZ(500), | |
49 | SR_MHZ(1), | |
50 | SR_MHZ(5), | |
51 | SR_MHZ(10), | |
52 | SR_MHZ(25), | |
53 | SR_MHZ(50), | |
54 | SR_MHZ(100), | |
55 | SR_MHZ(200), | |
28a35d8a HE |
56 | 0, |
57 | }; | |
58 | ||
60679b18 | 59 | static struct sr_samplerates samplerates = { |
59df0c77 UH |
60 | SR_KHZ(200), |
61 | SR_MHZ(200), | |
c9140419 | 62 | SR_HZ(0), |
28a35d8a HE |
63 | supported_samplerates, |
64 | }; | |
65 | ||
66 | static int capabilities[] = { | |
5a2326a7 UH |
67 | SR_HWCAP_LOGIC_ANALYZER, |
68 | SR_HWCAP_SAMPLERATE, | |
69 | SR_HWCAP_CAPTURE_RATIO, | |
70 | SR_HWCAP_PROBECONFIG, | |
28a35d8a | 71 | |
5a2326a7 | 72 | SR_HWCAP_LIMIT_MSEC, |
28a35d8a HE |
73 | 0, |
74 | }; | |
75 | ||
fefa1800 UH |
76 | /* Force the FPGA to reboot. */ |
77 | static uint8_t suicide[] = { | |
78 | 0x84, 0x84, 0x88, 0x84, 0x88, 0x84, 0x88, 0x84, | |
79 | }; | |
80 | ||
81 | /* Prepare to upload firmware (FPGA specific). */ | |
82 | static uint8_t init[] = { | |
83 | 0x03, 0x03, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, | |
84 | }; | |
85 | ||
86 | /* Initialize the logic analyzer mode. */ | |
87 | static uint8_t logic_mode_start[] = { | |
88 | 0x00, 0x40, 0x0f, 0x25, 0x35, 0x40, | |
89 | 0x2a, 0x3a, 0x40, 0x03, 0x20, 0x38, | |
90 | }; | |
91 | ||
eec5275e | 92 | static const char *firmware_files[] = { |
a8116d76 HE |
93 | "asix-sigma-50.fw", /* 50 MHz, supports 8 bit fractions */ |
94 | "asix-sigma-100.fw", /* 100 MHz */ | |
95 | "asix-sigma-200.fw", /* 200 MHz */ | |
ed09fd07 | 96 | "asix-sigma-50sync.fw", /* Synchronous clock from pin */ |
a8116d76 | 97 | "asix-sigma-phasor.fw", /* Frequency counter */ |
f6564c8d HE |
98 | }; |
99 | ||
6aac7737 HE |
100 | static void hw_stop_acquisition(int device_index, gpointer session_device_id); |
101 | ||
99965709 | 102 | static int sigma_read(void *buf, size_t size, struct sigma *sigma) |
28a35d8a HE |
103 | { |
104 | int ret; | |
fefa1800 | 105 | |
99965709 | 106 | ret = ftdi_read_data(&sigma->ftdic, (unsigned char *)buf, size); |
28a35d8a HE |
107 | if (ret < 0) { |
108 | g_warning("ftdi_read_data failed: %s", | |
99965709 | 109 | ftdi_get_error_string(&sigma->ftdic)); |
28a35d8a HE |
110 | } |
111 | ||
112 | return ret; | |
113 | } | |
114 | ||
99965709 | 115 | static int sigma_write(void *buf, size_t size, struct sigma *sigma) |
28a35d8a HE |
116 | { |
117 | int ret; | |
fefa1800 | 118 | |
99965709 | 119 | ret = ftdi_write_data(&sigma->ftdic, (unsigned char *)buf, size); |
28a35d8a HE |
120 | if (ret < 0) { |
121 | g_warning("ftdi_write_data failed: %s", | |
99965709 | 122 | ftdi_get_error_string(&sigma->ftdic)); |
fefa1800 | 123 | } else if ((size_t) ret != size) { |
28a35d8a HE |
124 | g_warning("ftdi_write_data did not complete write\n"); |
125 | } | |
126 | ||
127 | return ret; | |
128 | } | |
129 | ||
99965709 HE |
130 | static int sigma_write_register(uint8_t reg, uint8_t *data, size_t len, |
131 | struct sigma *sigma) | |
28a35d8a HE |
132 | { |
133 | size_t i; | |
134 | uint8_t buf[len + 2]; | |
135 | int idx = 0; | |
136 | ||
137 | buf[idx++] = REG_ADDR_LOW | (reg & 0xf); | |
138 | buf[idx++] = REG_ADDR_HIGH | (reg >> 4); | |
139 | ||
fefa1800 | 140 | for (i = 0; i < len; ++i) { |
28a35d8a HE |
141 | buf[idx++] = REG_DATA_LOW | (data[i] & 0xf); |
142 | buf[idx++] = REG_DATA_HIGH_WRITE | (data[i] >> 4); | |
143 | } | |
144 | ||
99965709 | 145 | return sigma_write(buf, idx, sigma); |
28a35d8a HE |
146 | } |
147 | ||
99965709 | 148 | static int sigma_set_register(uint8_t reg, uint8_t value, struct sigma *sigma) |
28a35d8a | 149 | { |
99965709 | 150 | return sigma_write_register(reg, &value, 1, sigma); |
28a35d8a HE |
151 | } |
152 | ||
99965709 HE |
153 | static int sigma_read_register(uint8_t reg, uint8_t *data, size_t len, |
154 | struct sigma *sigma) | |
28a35d8a HE |
155 | { |
156 | uint8_t buf[3]; | |
fefa1800 | 157 | |
28a35d8a HE |
158 | buf[0] = REG_ADDR_LOW | (reg & 0xf); |
159 | buf[1] = REG_ADDR_HIGH | (reg >> 4); | |
28a35d8a HE |
160 | buf[2] = REG_READ_ADDR; |
161 | ||
99965709 | 162 | sigma_write(buf, sizeof(buf), sigma); |
28a35d8a | 163 | |
99965709 | 164 | return sigma_read(data, len, sigma); |
28a35d8a HE |
165 | } |
166 | ||
99965709 | 167 | static uint8_t sigma_get_register(uint8_t reg, struct sigma *sigma) |
28a35d8a HE |
168 | { |
169 | uint8_t value; | |
fefa1800 | 170 | |
99965709 | 171 | if (1 != sigma_read_register(reg, &value, 1, sigma)) { |
28a35d8a HE |
172 | g_warning("Sigma_get_register: 1 byte expected"); |
173 | return 0; | |
174 | } | |
175 | ||
176 | return value; | |
177 | } | |
178 | ||
99965709 HE |
179 | static int sigma_read_pos(uint32_t *stoppos, uint32_t *triggerpos, |
180 | struct sigma *sigma) | |
28a35d8a HE |
181 | { |
182 | uint8_t buf[] = { | |
183 | REG_ADDR_LOW | READ_TRIGGER_POS_LOW, | |
184 | ||
185 | REG_READ_ADDR | NEXT_REG, | |
186 | REG_READ_ADDR | NEXT_REG, | |
187 | REG_READ_ADDR | NEXT_REG, | |
188 | REG_READ_ADDR | NEXT_REG, | |
189 | REG_READ_ADDR | NEXT_REG, | |
190 | REG_READ_ADDR | NEXT_REG, | |
191 | }; | |
28a35d8a HE |
192 | uint8_t result[6]; |
193 | ||
99965709 | 194 | sigma_write(buf, sizeof(buf), sigma); |
28a35d8a | 195 | |
99965709 | 196 | sigma_read(result, sizeof(result), sigma); |
28a35d8a HE |
197 | |
198 | *triggerpos = result[0] | (result[1] << 8) | (result[2] << 16); | |
199 | *stoppos = result[3] | (result[4] << 8) | (result[5] << 16); | |
200 | ||
57bbf56b HE |
201 | /* Not really sure why this must be done, but according to spec. */ |
202 | if ((--*stoppos & 0x1ff) == 0x1ff) | |
203 | stoppos -= 64; | |
204 | ||
205 | if ((*--triggerpos & 0x1ff) == 0x1ff) | |
206 | triggerpos -= 64; | |
207 | ||
28a35d8a HE |
208 | return 1; |
209 | } | |
210 | ||
99965709 HE |
211 | static int sigma_read_dram(uint16_t startchunk, size_t numchunks, |
212 | uint8_t *data, struct sigma *sigma) | |
28a35d8a HE |
213 | { |
214 | size_t i; | |
215 | uint8_t buf[4096]; | |
216 | int idx = 0; | |
217 | ||
fefa1800 | 218 | /* Send the startchunk. Index start with 1. */ |
28a35d8a HE |
219 | buf[0] = startchunk >> 8; |
220 | buf[1] = startchunk & 0xff; | |
99965709 | 221 | sigma_write_register(WRITE_MEMROW, buf, 2, sigma); |
28a35d8a | 222 | |
fefa1800 | 223 | /* Read the DRAM. */ |
28a35d8a HE |
224 | buf[idx++] = REG_DRAM_BLOCK; |
225 | buf[idx++] = REG_DRAM_WAIT_ACK; | |
226 | ||
227 | for (i = 0; i < numchunks; ++i) { | |
fefa1800 UH |
228 | /* Alternate bit to copy from DRAM to cache. */ |
229 | if (i != (numchunks - 1)) | |
230 | buf[idx++] = REG_DRAM_BLOCK | (((i + 1) % 2) << 4); | |
28a35d8a HE |
231 | |
232 | buf[idx++] = REG_DRAM_BLOCK_DATA | ((i % 2) << 4); | |
233 | ||
fefa1800 | 234 | if (i != (numchunks - 1)) |
28a35d8a HE |
235 | buf[idx++] = REG_DRAM_WAIT_ACK; |
236 | } | |
237 | ||
99965709 | 238 | sigma_write(buf, idx, sigma); |
28a35d8a | 239 | |
99965709 | 240 | return sigma_read(data, numchunks * CHUNK_SIZE, sigma); |
28a35d8a HE |
241 | } |
242 | ||
4ae1f451 | 243 | /* Upload trigger look-up tables to Sigma. */ |
99965709 | 244 | static int sigma_write_trigger_lut(struct triggerlut *lut, struct sigma *sigma) |
ee492173 HE |
245 | { |
246 | int i; | |
247 | uint8_t tmp[2]; | |
248 | uint16_t bit; | |
249 | ||
250 | /* Transpose the table and send to Sigma. */ | |
251 | for (i = 0; i < 16; ++i) { | |
252 | bit = 1 << i; | |
253 | ||
254 | tmp[0] = tmp[1] = 0; | |
255 | ||
256 | if (lut->m2d[0] & bit) | |
257 | tmp[0] |= 0x01; | |
258 | if (lut->m2d[1] & bit) | |
259 | tmp[0] |= 0x02; | |
260 | if (lut->m2d[2] & bit) | |
261 | tmp[0] |= 0x04; | |
262 | if (lut->m2d[3] & bit) | |
263 | tmp[0] |= 0x08; | |
264 | ||
265 | if (lut->m3 & bit) | |
266 | tmp[0] |= 0x10; | |
267 | if (lut->m3s & bit) | |
268 | tmp[0] |= 0x20; | |
269 | if (lut->m4 & bit) | |
270 | tmp[0] |= 0x40; | |
271 | ||
272 | if (lut->m0d[0] & bit) | |
273 | tmp[1] |= 0x01; | |
274 | if (lut->m0d[1] & bit) | |
275 | tmp[1] |= 0x02; | |
276 | if (lut->m0d[2] & bit) | |
277 | tmp[1] |= 0x04; | |
278 | if (lut->m0d[3] & bit) | |
279 | tmp[1] |= 0x08; | |
280 | ||
281 | if (lut->m1d[0] & bit) | |
282 | tmp[1] |= 0x10; | |
283 | if (lut->m1d[1] & bit) | |
284 | tmp[1] |= 0x20; | |
285 | if (lut->m1d[2] & bit) | |
286 | tmp[1] |= 0x40; | |
287 | if (lut->m1d[3] & bit) | |
288 | tmp[1] |= 0x80; | |
289 | ||
99965709 HE |
290 | sigma_write_register(WRITE_TRIGGER_SELECT0, tmp, sizeof(tmp), |
291 | sigma); | |
292 | sigma_set_register(WRITE_TRIGGER_SELECT1, 0x30 | i, sigma); | |
ee492173 HE |
293 | } |
294 | ||
295 | /* Send the parameters */ | |
296 | sigma_write_register(WRITE_TRIGGER_SELECT0, (uint8_t *) &lut->params, | |
99965709 | 297 | sizeof(lut->params), sigma); |
ee492173 | 298 | |
e46b8fb1 | 299 | return SR_OK; |
ee492173 HE |
300 | } |
301 | ||
fefa1800 | 302 | /* Generate the bitbang stream for programming the FPGA. */ |
28a35d8a | 303 | static int bin2bitbang(const char *filename, |
fefa1800 | 304 | unsigned char **buf, size_t *buf_size) |
28a35d8a | 305 | { |
fefa1800 | 306 | FILE *f; |
28a35d8a HE |
307 | long file_size; |
308 | unsigned long offset = 0; | |
309 | unsigned char *p; | |
310 | uint8_t *compressed_buf, *firmware; | |
311 | uLongf csize, fwsize; | |
312 | const int buffer_size = 65536; | |
313 | size_t i; | |
fefa1800 UH |
314 | int c, ret, bit, v; |
315 | uint32_t imm = 0x3f6df2ab; | |
28a35d8a | 316 | |
868d8cef | 317 | f = g_fopen(filename, "rb"); |
28a35d8a | 318 | if (!f) { |
868d8cef | 319 | g_warning("g_fopen(\"%s\", \"rb\")", filename); |
28a35d8a HE |
320 | return -1; |
321 | } | |
322 | ||
323 | if (-1 == fseek(f, 0, SEEK_END)) { | |
324 | g_warning("fseek on %s failed", filename); | |
325 | fclose(f); | |
326 | return -1; | |
327 | } | |
328 | ||
329 | file_size = ftell(f); | |
330 | ||
331 | fseek(f, 0, SEEK_SET); | |
332 | ||
28a35d8a HE |
333 | compressed_buf = g_malloc(file_size); |
334 | firmware = g_malloc(buffer_size); | |
335 | ||
336 | if (!compressed_buf || !firmware) { | |
337 | g_warning("Error allocating buffers"); | |
338 | return -1; | |
339 | } | |
340 | ||
28a35d8a HE |
341 | csize = 0; |
342 | while ((c = getc(f)) != EOF) { | |
343 | imm = (imm + 0xa853753) % 177 + (imm * 0x8034052); | |
344 | compressed_buf[csize++] = c ^ imm; | |
345 | } | |
346 | fclose(f); | |
347 | ||
348 | fwsize = buffer_size; | |
349 | ret = uncompress(firmware, &fwsize, compressed_buf, csize); | |
350 | if (ret < 0) { | |
351 | g_free(compressed_buf); | |
352 | g_free(firmware); | |
353 | g_warning("Could not unpack Sigma firmware. (Error %d)\n", ret); | |
354 | return -1; | |
355 | } | |
356 | ||
357 | g_free(compressed_buf); | |
358 | ||
359 | *buf_size = fwsize * 2 * 8; | |
360 | ||
fefa1800 | 361 | *buf = p = (unsigned char *)g_malloc(*buf_size); |
28a35d8a HE |
362 | |
363 | if (!p) { | |
364 | g_warning("Error allocating buffers"); | |
365 | return -1; | |
366 | } | |
367 | ||
368 | for (i = 0; i < fwsize; ++i) { | |
28a35d8a | 369 | for (bit = 7; bit >= 0; --bit) { |
fefa1800 | 370 | v = firmware[i] & 1 << bit ? 0x40 : 0x00; |
28a35d8a HE |
371 | p[offset++] = v | 0x01; |
372 | p[offset++] = v; | |
373 | } | |
374 | } | |
375 | ||
376 | g_free(firmware); | |
377 | ||
378 | if (offset != *buf_size) { | |
379 | g_free(*buf); | |
380 | g_warning("Error reading firmware %s " | |
fefa1800 UH |
381 | "offset=%ld, file_size=%ld, buf_size=%zd\n", |
382 | filename, offset, file_size, *buf_size); | |
28a35d8a HE |
383 | |
384 | return -1; | |
385 | } | |
386 | ||
387 | return 0; | |
388 | } | |
389 | ||
54ac5277 | 390 | static int hw_init(const char *deviceinfo) |
28a35d8a | 391 | { |
a00ba012 | 392 | struct sr_device_instance *sdi; |
99965709 | 393 | struct sigma *sigma = g_malloc(sizeof(struct sigma)); |
28a35d8a HE |
394 | |
395 | deviceinfo = deviceinfo; | |
396 | ||
99965709 HE |
397 | if (!sigma) |
398 | return 0; | |
399 | ||
400 | ftdi_init(&sigma->ftdic); | |
28a35d8a | 401 | |
fefa1800 | 402 | /* Look for SIGMAs. */ |
99965709 | 403 | if (ftdi_usb_open_desc(&sigma->ftdic, USB_VENDOR, USB_PRODUCT, |
fefa1800 | 404 | USB_DESCRIPTION, NULL) < 0) |
99965709 HE |
405 | goto free; |
406 | ||
407 | sigma->cur_samplerate = 0; | |
408 | sigma->limit_msec = 0; | |
409 | sigma->cur_firmware = -1; | |
410 | sigma->num_probes = 0; | |
411 | sigma->samples_per_event = 0; | |
412 | sigma->capture_ratio = 50; | |
5b5ea7c6 | 413 | sigma->use_triggers = 0; |
28a35d8a | 414 | |
fefa1800 | 415 | /* Register SIGMA device. */ |
5a2326a7 | 416 | sdi = sr_device_instance_new(0, SR_ST_INITIALIZING, |
28a35d8a HE |
417 | USB_VENDOR_NAME, USB_MODEL_NAME, USB_MODEL_VERSION); |
418 | if (!sdi) | |
99965709 HE |
419 | goto free; |
420 | ||
421 | sdi->priv = sigma; | |
28a35d8a HE |
422 | |
423 | device_instances = g_slist_append(device_instances, sdi); | |
424 | ||
fefa1800 | 425 | /* We will open the device again when we need it. */ |
99965709 | 426 | ftdi_usb_close(&sigma->ftdic); |
28a35d8a HE |
427 | |
428 | return 1; | |
99965709 HE |
429 | free: |
430 | free(sigma); | |
431 | return 0; | |
28a35d8a HE |
432 | } |
433 | ||
99965709 | 434 | static int upload_firmware(int firmware_idx, struct sigma *sigma) |
28a35d8a HE |
435 | { |
436 | int ret; | |
437 | unsigned char *buf; | |
438 | unsigned char pins; | |
439 | size_t buf_size; | |
28a35d8a | 440 | unsigned char result[32]; |
e8397563 | 441 | char firmware_path[128]; |
28a35d8a | 442 | |
fefa1800 | 443 | /* Make sure it's an ASIX SIGMA. */ |
99965709 | 444 | if ((ret = ftdi_usb_open_desc(&sigma->ftdic, |
28a35d8a | 445 | USB_VENDOR, USB_PRODUCT, USB_DESCRIPTION, NULL)) < 0) { |
28a35d8a | 446 | g_warning("ftdi_usb_open failed: %s", |
99965709 | 447 | ftdi_get_error_string(&sigma->ftdic)); |
28a35d8a HE |
448 | return 0; |
449 | } | |
450 | ||
99965709 | 451 | if ((ret = ftdi_set_bitmode(&sigma->ftdic, 0xdf, BITMODE_BITBANG)) < 0) { |
28a35d8a | 452 | g_warning("ftdi_set_bitmode failed: %s", |
99965709 | 453 | ftdi_get_error_string(&sigma->ftdic)); |
28a35d8a HE |
454 | return 0; |
455 | } | |
456 | ||
fefa1800 | 457 | /* Four times the speed of sigmalogan - Works well. */ |
99965709 | 458 | if ((ret = ftdi_set_baudrate(&sigma->ftdic, 750000)) < 0) { |
28a35d8a | 459 | g_warning("ftdi_set_baudrate failed: %s", |
99965709 | 460 | ftdi_get_error_string(&sigma->ftdic)); |
28a35d8a HE |
461 | return 0; |
462 | } | |
463 | ||
fefa1800 | 464 | /* Force the FPGA to reboot. */ |
99965709 HE |
465 | sigma_write(suicide, sizeof(suicide), sigma); |
466 | sigma_write(suicide, sizeof(suicide), sigma); | |
467 | sigma_write(suicide, sizeof(suicide), sigma); | |
468 | sigma_write(suicide, sizeof(suicide), sigma); | |
28a35d8a | 469 | |
fefa1800 | 470 | /* Prepare to upload firmware (FPGA specific). */ |
99965709 | 471 | sigma_write(init, sizeof(init), sigma); |
28a35d8a | 472 | |
99965709 | 473 | ftdi_usb_purge_buffers(&sigma->ftdic); |
28a35d8a | 474 | |
fefa1800 | 475 | /* Wait until the FPGA asserts INIT_B. */ |
28a35d8a | 476 | while (1) { |
99965709 | 477 | ret = sigma_read(result, 1, sigma); |
28a35d8a HE |
478 | if (result[0] & 0x20) |
479 | break; | |
480 | } | |
481 | ||
9ddb2a12 | 482 | /* Prepare firmware. */ |
e8397563 | 483 | snprintf(firmware_path, sizeof(firmware_path), "%s/%s", FIRMWARE_DIR, |
f6564c8d HE |
484 | firmware_files[firmware_idx]); |
485 | ||
e8397563 | 486 | if (-1 == bin2bitbang(firmware_path, &buf, &buf_size)) { |
28a35d8a | 487 | g_warning("An error occured while reading the firmware: %s", |
e8397563 | 488 | firmware_path); |
e46b8fb1 | 489 | return SR_ERR; |
28a35d8a HE |
490 | } |
491 | ||
fefa1800 | 492 | /* Upload firmare. */ |
99965709 | 493 | sigma_write(buf, buf_size, sigma); |
28a35d8a HE |
494 | |
495 | g_free(buf); | |
496 | ||
99965709 | 497 | if ((ret = ftdi_set_bitmode(&sigma->ftdic, 0x00, BITMODE_RESET)) < 0) { |
9ddb2a12 | 498 | g_warning("ftdi_set_bitmode failed: %s", |
99965709 | 499 | ftdi_get_error_string(&sigma->ftdic)); |
e46b8fb1 | 500 | return SR_ERR; |
28a35d8a HE |
501 | } |
502 | ||
99965709 | 503 | ftdi_usb_purge_buffers(&sigma->ftdic); |
28a35d8a | 504 | |
fefa1800 | 505 | /* Discard garbage. */ |
99965709 | 506 | while (1 == sigma_read(&pins, 1, sigma)) |
28a35d8a HE |
507 | ; |
508 | ||
fefa1800 | 509 | /* Initialize the logic analyzer mode. */ |
99965709 | 510 | sigma_write(logic_mode_start, sizeof(logic_mode_start), sigma); |
28a35d8a | 511 | |
fefa1800 | 512 | /* Expect a 3 byte reply. */ |
99965709 | 513 | ret = sigma_read(result, 3, sigma); |
28a35d8a HE |
514 | if (ret != 3 || |
515 | result[0] != 0xa6 || result[1] != 0x55 || result[2] != 0xaa) { | |
fefa1800 | 516 | g_warning("Configuration failed. Invalid reply received."); |
e46b8fb1 | 517 | return SR_ERR; |
28a35d8a HE |
518 | } |
519 | ||
99965709 | 520 | sigma->cur_firmware = firmware_idx; |
f6564c8d | 521 | |
e46b8fb1 | 522 | return SR_OK; |
f6564c8d HE |
523 | } |
524 | ||
525 | static int hw_opendev(int device_index) | |
526 | { | |
a00ba012 | 527 | struct sr_device_instance *sdi; |
99965709 | 528 | struct sigma *sigma; |
f6564c8d HE |
529 | int ret; |
530 | ||
d32d961d | 531 | if (!(sdi = sr_get_device_instance(device_instances, device_index))) |
e46b8fb1 | 532 | return SR_ERR; |
99965709 HE |
533 | |
534 | sigma = sdi->priv; | |
535 | ||
9ddb2a12 | 536 | /* Make sure it's an ASIX SIGMA. */ |
99965709 | 537 | if ((ret = ftdi_usb_open_desc(&sigma->ftdic, |
f6564c8d HE |
538 | USB_VENDOR, USB_PRODUCT, USB_DESCRIPTION, NULL)) < 0) { |
539 | ||
540 | g_warning("ftdi_usb_open failed: %s", | |
99965709 | 541 | ftdi_get_error_string(&sigma->ftdic)); |
f6564c8d HE |
542 | |
543 | return 0; | |
544 | } | |
28a35d8a | 545 | |
5a2326a7 | 546 | sdi->status = SR_ST_ACTIVE; |
28a35d8a | 547 | |
e46b8fb1 | 548 | return SR_OK; |
f6564c8d HE |
549 | } |
550 | ||
a00ba012 | 551 | static int set_samplerate(struct sr_device_instance *sdi, |
6aac7737 | 552 | uint64_t samplerate) |
f6564c8d | 553 | { |
e8397563 | 554 | int i, ret; |
99965709 | 555 | struct sigma *sigma = sdi->priv; |
f6564c8d HE |
556 | |
557 | for (i = 0; supported_samplerates[i]; i++) { | |
558 | if (supported_samplerates[i] == samplerate) | |
559 | break; | |
560 | } | |
561 | if (supported_samplerates[i] == 0) | |
e46b8fb1 | 562 | return SR_ERR_SAMPLERATE; |
f6564c8d | 563 | |
59df0c77 | 564 | if (samplerate <= SR_MHZ(50)) { |
99965709 HE |
565 | ret = upload_firmware(0, sigma); |
566 | sigma->num_probes = 16; | |
e8397563 | 567 | } |
59df0c77 | 568 | if (samplerate == SR_MHZ(100)) { |
99965709 HE |
569 | ret = upload_firmware(1, sigma); |
570 | sigma->num_probes = 8; | |
f78898e9 | 571 | } |
59df0c77 | 572 | else if (samplerate == SR_MHZ(200)) { |
99965709 HE |
573 | ret = upload_firmware(2, sigma); |
574 | sigma->num_probes = 4; | |
f78898e9 | 575 | } |
f6564c8d | 576 | |
99965709 HE |
577 | sigma->cur_samplerate = samplerate; |
578 | sigma->samples_per_event = 16 / sigma->num_probes; | |
579 | sigma->state.state = SIGMA_IDLE; | |
f6564c8d | 580 | |
28a35d8a HE |
581 | g_message("Firmware uploaded"); |
582 | ||
e8397563 | 583 | return ret; |
28a35d8a HE |
584 | } |
585 | ||
c53d793f HE |
586 | /* |
587 | * In 100 and 200 MHz mode, only a single pin rising/falling can be | |
588 | * set as trigger. In other modes, two rising/falling triggers can be set, | |
589 | * in addition to value/mask trigger for any number of probes. | |
590 | * | |
591 | * The Sigma supports complex triggers using boolean expressions, but this | |
592 | * has not been implemented yet. | |
593 | */ | |
a00ba012 | 594 | static int configure_probes(struct sr_device_instance *sdi, GSList *probes) |
57bbf56b | 595 | { |
99965709 | 596 | struct sigma *sigma = sdi->priv; |
1afe8989 | 597 | struct sr_probe *probe; |
57bbf56b HE |
598 | GSList *l; |
599 | int trigger_set = 0; | |
a42aec7f | 600 | int probebit; |
57bbf56b | 601 | |
99965709 | 602 | memset(&sigma->trigger, 0, sizeof(struct sigma_trigger)); |
eec5275e | 603 | |
57bbf56b | 604 | for (l = probes; l; l = l->next) { |
1afe8989 | 605 | probe = (struct sr_probe *)l->data; |
a42aec7f | 606 | probebit = 1 << (probe->index - 1); |
57bbf56b HE |
607 | |
608 | if (!probe->enabled || !probe->trigger) | |
609 | continue; | |
610 | ||
59df0c77 | 611 | if (sigma->cur_samplerate >= SR_MHZ(100)) { |
c53d793f | 612 | /* Fast trigger support. */ |
ee492173 | 613 | if (trigger_set) { |
6aac7737 HE |
614 | g_warning("Asix Sigma only supports a single " |
615 | "pin trigger in 100 and 200 " | |
616 | "MHz mode."); | |
e46b8fb1 | 617 | return SR_ERR; |
ee492173 HE |
618 | } |
619 | if (probe->trigger[0] == 'f') | |
99965709 | 620 | sigma->trigger.fallingmask |= probebit; |
ee492173 | 621 | else if (probe->trigger[0] == 'r') |
99965709 | 622 | sigma->trigger.risingmask |= probebit; |
ee492173 HE |
623 | else { |
624 | g_warning("Asix Sigma only supports " | |
625 | "rising/falling trigger in 100 " | |
626 | "and 200 MHz mode."); | |
e46b8fb1 | 627 | return SR_ERR; |
ee492173 | 628 | } |
57bbf56b | 629 | |
c53d793f | 630 | ++trigger_set; |
ee492173 | 631 | } else { |
c53d793f HE |
632 | /* Simple trigger support (event). */ |
633 | if (probe->trigger[0] == '1') { | |
99965709 HE |
634 | sigma->trigger.simplevalue |= probebit; |
635 | sigma->trigger.simplemask |= probebit; | |
c53d793f HE |
636 | } |
637 | else if (probe->trigger[0] == '0') { | |
99965709 HE |
638 | sigma->trigger.simplevalue &= ~probebit; |
639 | sigma->trigger.simplemask |= probebit; | |
c53d793f HE |
640 | } |
641 | else if (probe->trigger[0] == 'f') { | |
99965709 | 642 | sigma->trigger.fallingmask |= probebit; |
c53d793f HE |
643 | ++trigger_set; |
644 | } | |
645 | else if (probe->trigger[0] == 'r') { | |
99965709 | 646 | sigma->trigger.risingmask |= probebit; |
c53d793f HE |
647 | ++trigger_set; |
648 | } | |
ee492173 | 649 | |
98b8cbc1 HE |
650 | /* |
651 | * Actually, Sigma supports 2 rising/falling triggers, | |
652 | * but they are ORed and the current trigger syntax | |
653 | * does not permit ORed triggers. | |
654 | */ | |
655 | if (trigger_set > 1) { | |
656 | g_warning("Asix Sigma only supports 1 rising/" | |
c53d793f | 657 | "falling triggers."); |
e46b8fb1 | 658 | return SR_ERR; |
ee492173 | 659 | } |
ee492173 | 660 | } |
5b5ea7c6 HE |
661 | |
662 | if (trigger_set) | |
663 | sigma->use_triggers = 1; | |
57bbf56b HE |
664 | } |
665 | ||
e46b8fb1 | 666 | return SR_OK; |
57bbf56b HE |
667 | } |
668 | ||
28a35d8a HE |
669 | static void hw_closedev(int device_index) |
670 | { | |
a00ba012 | 671 | struct sr_device_instance *sdi; |
99965709 | 672 | struct sigma *sigma; |
28a35d8a | 673 | |
d32d961d | 674 | if ((sdi = sr_get_device_instance(device_instances, device_index))) |
9be9893e | 675 | { |
99965709 | 676 | sigma = sdi->priv; |
5a2326a7 | 677 | if (sdi->status == SR_ST_ACTIVE) |
99965709 | 678 | ftdi_usb_close(&sigma->ftdic); |
9be9893e | 679 | |
5a2326a7 | 680 | sdi->status = SR_ST_INACTIVE; |
9be9893e | 681 | } |
28a35d8a HE |
682 | } |
683 | ||
28a35d8a HE |
684 | static void hw_cleanup(void) |
685 | { | |
99965709 | 686 | GSList *l; |
a00ba012 | 687 | struct sr_device_instance *sdi; |
99965709 HE |
688 | |
689 | /* Properly close all devices. */ | |
690 | for (l = device_instances; l; l = l->next) { | |
691 | sdi = l->data; | |
692 | if (sdi->priv != NULL) | |
693 | free(sdi->priv); | |
a00ba012 | 694 | sr_device_instance_free(sdi); |
99965709 HE |
695 | } |
696 | g_slist_free(device_instances); | |
697 | device_instances = NULL; | |
28a35d8a HE |
698 | } |
699 | ||
28a35d8a HE |
700 | static void *hw_get_device_info(int device_index, int device_info_id) |
701 | { | |
a00ba012 | 702 | struct sr_device_instance *sdi; |
99965709 | 703 | struct sigma *sigma; |
28a35d8a HE |
704 | void *info = NULL; |
705 | ||
d32d961d | 706 | if (!(sdi = sr_get_device_instance(device_instances, device_index))) { |
28a35d8a HE |
707 | fprintf(stderr, "It's NULL.\n"); |
708 | return NULL; | |
709 | } | |
710 | ||
99965709 HE |
711 | sigma = sdi->priv; |
712 | ||
28a35d8a | 713 | switch (device_info_id) { |
5a2326a7 | 714 | case SR_DI_INSTANCE: |
28a35d8a HE |
715 | info = sdi; |
716 | break; | |
5a2326a7 | 717 | case SR_DI_NUM_PROBES: |
edca2c5c | 718 | info = GINT_TO_POINTER(16); |
28a35d8a | 719 | break; |
5a2326a7 | 720 | case SR_DI_SAMPLERATES: |
28a35d8a HE |
721 | info = &samplerates; |
722 | break; | |
5a2326a7 | 723 | case SR_DI_TRIGGER_TYPES: |
57bbf56b | 724 | info = (char *)TRIGGER_TYPES; |
28a35d8a | 725 | break; |
5a2326a7 | 726 | case SR_DI_CUR_SAMPLERATE: |
99965709 | 727 | info = &sigma->cur_samplerate; |
28a35d8a HE |
728 | break; |
729 | } | |
730 | ||
731 | return info; | |
732 | } | |
733 | ||
28a35d8a HE |
734 | static int hw_get_status(int device_index) |
735 | { | |
a00ba012 | 736 | struct sr_device_instance *sdi; |
28a35d8a | 737 | |
d32d961d | 738 | sdi = sr_get_device_instance(device_instances, device_index); |
28a35d8a HE |
739 | if (sdi) |
740 | return sdi->status; | |
741 | else | |
5a2326a7 | 742 | return SR_ST_NOT_FOUND; |
28a35d8a HE |
743 | } |
744 | ||
28a35d8a HE |
745 | static int *hw_get_capabilities(void) |
746 | { | |
747 | return capabilities; | |
748 | } | |
749 | ||
750 | static int hw_set_configuration(int device_index, int capability, void *value) | |
751 | { | |
a00ba012 | 752 | struct sr_device_instance *sdi; |
99965709 | 753 | struct sigma *sigma; |
28a35d8a | 754 | int ret; |
f6564c8d | 755 | |
d32d961d | 756 | if (!(sdi = sr_get_device_instance(device_instances, device_index))) |
e46b8fb1 | 757 | return SR_ERR; |
28a35d8a | 758 | |
99965709 HE |
759 | sigma = sdi->priv; |
760 | ||
5a2326a7 | 761 | if (capability == SR_HWCAP_SAMPLERATE) { |
f6564c8d | 762 | ret = set_samplerate(sdi, *(uint64_t*) value); |
5a2326a7 | 763 | } else if (capability == SR_HWCAP_PROBECONFIG) { |
99965709 | 764 | ret = configure_probes(sdi, value); |
5a2326a7 | 765 | } else if (capability == SR_HWCAP_LIMIT_MSEC) { |
94ba4bd6 HE |
766 | sigma->limit_msec = *(uint64_t*) value; |
767 | if (sigma->limit_msec > 0) | |
e46b8fb1 | 768 | ret = SR_OK; |
94ba4bd6 | 769 | else |
e46b8fb1 | 770 | ret = SR_ERR; |
5a2326a7 | 771 | } else if (capability == SR_HWCAP_CAPTURE_RATIO) { |
94ba4bd6 HE |
772 | sigma->capture_ratio = *(uint64_t*) value; |
773 | if (sigma->capture_ratio < 0 || sigma->capture_ratio > 100) | |
e46b8fb1 | 774 | ret = SR_ERR; |
94ba4bd6 | 775 | else |
e46b8fb1 | 776 | ret = SR_OK; |
28a35d8a | 777 | } else { |
e46b8fb1 | 778 | ret = SR_ERR; |
28a35d8a HE |
779 | } |
780 | ||
781 | return ret; | |
782 | } | |
783 | ||
36b1c8e6 HE |
784 | /* Software trigger to determine exact trigger position. */ |
785 | static int get_trigger_offset(uint16_t *samples, uint16_t last_sample, | |
786 | struct sigma_trigger *t) | |
787 | { | |
788 | int i; | |
789 | ||
790 | for (i = 0; i < 8; ++i) { | |
791 | if (i > 0) | |
792 | last_sample = samples[i-1]; | |
793 | ||
794 | /* Simple triggers. */ | |
795 | if ((samples[i] & t->simplemask) != t->simplevalue) | |
796 | continue; | |
797 | ||
798 | /* Rising edge. */ | |
799 | if ((last_sample & t->risingmask) != 0 || (samples[i] & | |
800 | t->risingmask) != t->risingmask) | |
801 | continue; | |
802 | ||
803 | /* Falling edge. */ | |
bdfc7a89 HE |
804 | if ((last_sample & t->fallingmask) != t->fallingmask || |
805 | (samples[i] & t->fallingmask) != 0) | |
36b1c8e6 HE |
806 | continue; |
807 | ||
808 | break; | |
809 | } | |
810 | ||
811 | /* If we did not match, return original trigger pos. */ | |
812 | return i & 0x7; | |
813 | } | |
814 | ||
28a35d8a | 815 | /* |
fefa1800 UH |
816 | * Decode chunk of 1024 bytes, 64 clusters, 7 events per cluster. |
817 | * Each event is 20ns apart, and can contain multiple samples. | |
f78898e9 HE |
818 | * |
819 | * For 200 MHz, events contain 4 samples for each channel, spread 5 ns apart. | |
820 | * For 100 MHz, events contain 2 samples for each channel, spread 10 ns apart. | |
821 | * For 50 MHz and below, events contain one sample for each channel, | |
822 | * spread 20 ns apart. | |
28a35d8a HE |
823 | */ |
824 | static int decode_chunk_ts(uint8_t *buf, uint16_t *lastts, | |
88c51afe HE |
825 | uint16_t *lastsample, int triggerpos, |
826 | uint16_t limit_chunk, void *user_data) | |
28a35d8a | 827 | { |
a00ba012 | 828 | struct sr_device_instance *sdi = user_data; |
99965709 | 829 | struct sigma *sigma = sdi->priv; |
fefa1800 | 830 | uint16_t tsdiff, ts; |
99965709 | 831 | uint16_t samples[65536 * sigma->samples_per_event]; |
b9c735a2 | 832 | struct sr_datafeed_packet packet; |
f78898e9 | 833 | int i, j, k, l, numpad, tosend; |
fefa1800 | 834 | size_t n = 0, sent = 0; |
99965709 | 835 | int clustersize = EVENTS_PER_CLUSTER * sigma->samples_per_event; |
fefa1800 | 836 | uint16_t *event; |
f78898e9 | 837 | uint16_t cur_sample; |
57bbf56b | 838 | int triggerts = -1; |
ee492173 | 839 | |
4ae1f451 | 840 | /* Check if trigger is in this chunk. */ |
ee492173 | 841 | if (triggerpos != -1) { |
59df0c77 | 842 | if (sigma->cur_samplerate <= SR_MHZ(50)) |
36b1c8e6 | 843 | triggerpos -= EVENTS_PER_CLUSTER - 1; |
ee492173 HE |
844 | |
845 | if (triggerpos < 0) | |
846 | triggerpos = 0; | |
57bbf56b | 847 | |
ee492173 HE |
848 | /* Find in which cluster the trigger occured. */ |
849 | triggerts = triggerpos / 7; | |
850 | } | |
28a35d8a | 851 | |
eec5275e | 852 | /* For each ts. */ |
28a35d8a | 853 | for (i = 0; i < 64; ++i) { |
fefa1800 | 854 | ts = *(uint16_t *) &buf[i * 16]; |
28a35d8a HE |
855 | tsdiff = ts - *lastts; |
856 | *lastts = ts; | |
857 | ||
88c51afe HE |
858 | /* Decode partial chunk. */ |
859 | if (limit_chunk && ts > limit_chunk) | |
e46b8fb1 | 860 | return SR_OK; |
88c51afe | 861 | |
fefa1800 | 862 | /* Pad last sample up to current point. */ |
99965709 | 863 | numpad = tsdiff * sigma->samples_per_event - clustersize; |
28a35d8a | 864 | if (numpad > 0) { |
f78898e9 HE |
865 | for (j = 0; j < numpad; ++j) |
866 | samples[j] = *lastsample; | |
867 | ||
868 | n = numpad; | |
28a35d8a HE |
869 | } |
870 | ||
57bbf56b HE |
871 | /* Send samples between previous and this timestamp to sigrok. */ |
872 | sent = 0; | |
873 | while (sent < n) { | |
874 | tosend = MIN(2048, n - sent); | |
875 | ||
5a2326a7 | 876 | packet.type = SR_DF_LOGIC; |
57bbf56b | 877 | packet.length = tosend * sizeof(uint16_t); |
4c046c6b | 878 | packet.unitsize = 2; |
57bbf56b | 879 | packet.payload = samples + sent; |
8a2efef2 | 880 | sr_session_bus(sigma->session_id, &packet); |
28a35d8a | 881 | |
57bbf56b HE |
882 | sent += tosend; |
883 | } | |
884 | n = 0; | |
885 | ||
886 | event = (uint16_t *) &buf[i * 16 + 2]; | |
f78898e9 HE |
887 | cur_sample = 0; |
888 | ||
889 | /* For each event in cluster. */ | |
28a35d8a | 890 | for (j = 0; j < 7; ++j) { |
f78898e9 HE |
891 | |
892 | /* For each sample in event. */ | |
99965709 | 893 | for (k = 0; k < sigma->samples_per_event; ++k) { |
f78898e9 HE |
894 | cur_sample = 0; |
895 | ||
896 | /* For each probe. */ | |
99965709 | 897 | for (l = 0; l < sigma->num_probes; ++l) |
edca2c5c | 898 | cur_sample |= (!!(event[j] & (1 << (l * |
99965709 HE |
899 | sigma->samples_per_event |
900 | + k)))) | |
edca2c5c | 901 | << l; |
f78898e9 HE |
902 | |
903 | samples[n++] = cur_sample; | |
28a35d8a HE |
904 | } |
905 | } | |
906 | ||
eec5275e | 907 | /* Send data up to trigger point (if triggered). */ |
fefa1800 | 908 | sent = 0; |
57bbf56b HE |
909 | if (i == triggerts) { |
910 | /* | |
36b1c8e6 HE |
911 | * Trigger is not always accurate to sample because of |
912 | * pipeline delay. However, it always triggers before | |
913 | * the actual event. We therefore look at the next | |
914 | * samples to pinpoint the exact position of the trigger. | |
57bbf56b | 915 | */ |
bdfc7a89 | 916 | tosend = get_trigger_offset(samples, *lastsample, |
99965709 | 917 | &sigma->trigger); |
57bbf56b HE |
918 | |
919 | if (tosend > 0) { | |
5a2326a7 | 920 | packet.type = SR_DF_LOGIC; |
57bbf56b | 921 | packet.length = tosend * sizeof(uint16_t); |
4c046c6b | 922 | packet.unitsize = 2; |
57bbf56b | 923 | packet.payload = samples; |
8a2efef2 | 924 | sr_session_bus(sigma->session_id, &packet); |
57bbf56b HE |
925 | |
926 | sent += tosend; | |
927 | } | |
28a35d8a | 928 | |
5b5ea7c6 HE |
929 | /* Only send trigger if explicitly enabled. */ |
930 | if (sigma->use_triggers) { | |
5a2326a7 | 931 | packet.type = SR_DF_TRIGGER; |
5b5ea7c6 HE |
932 | packet.length = 0; |
933 | packet.payload = 0; | |
8a2efef2 | 934 | sr_session_bus(sigma->session_id, &packet); |
5b5ea7c6 | 935 | } |
28a35d8a | 936 | } |
57bbf56b | 937 | |
eec5275e | 938 | /* Send rest of the chunk to sigrok. */ |
57bbf56b HE |
939 | tosend = n - sent; |
940 | ||
abda62ce | 941 | if (tosend > 0) { |
5a2326a7 | 942 | packet.type = SR_DF_LOGIC; |
abda62ce HE |
943 | packet.length = tosend * sizeof(uint16_t); |
944 | packet.unitsize = 2; | |
945 | packet.payload = samples + sent; | |
8a2efef2 | 946 | sr_session_bus(sigma->session_id, &packet); |
abda62ce | 947 | } |
ee492173 HE |
948 | |
949 | *lastsample = samples[n - 1]; | |
28a35d8a HE |
950 | } |
951 | ||
e46b8fb1 | 952 | return SR_OK; |
28a35d8a HE |
953 | } |
954 | ||
955 | static int receive_data(int fd, int revents, void *user_data) | |
956 | { | |
a00ba012 | 957 | struct sr_device_instance *sdi = user_data; |
99965709 | 958 | struct sigma *sigma = sdi->priv; |
b9c735a2 | 959 | struct sr_datafeed_packet packet; |
28a35d8a HE |
960 | const int chunks_per_read = 32; |
961 | unsigned char buf[chunks_per_read * CHUNK_SIZE]; | |
6aac7737 | 962 | int bufsz, numchunks, i, newchunks; |
94ba4bd6 | 963 | uint64_t running_msec; |
28a35d8a | 964 | struct timeval tv; |
28a35d8a HE |
965 | |
966 | fd = fd; | |
967 | revents = revents; | |
968 | ||
31facdd3 | 969 | numchunks = (sigma->state.stoppos + 511) / 512; |
28a35d8a | 970 | |
99965709 | 971 | if (sigma->state.state == SIGMA_IDLE) |
28a35d8a HE |
972 | return FALSE; |
973 | ||
99965709 | 974 | if (sigma->state.state == SIGMA_CAPTURE) { |
28a35d8a | 975 | |
6aac7737 HE |
976 | /* Check if the timer has expired, or memory is full. */ |
977 | gettimeofday(&tv, 0); | |
99965709 HE |
978 | running_msec = (tv.tv_sec - sigma->start_tv.tv_sec) * 1000 + |
979 | (tv.tv_usec - sigma->start_tv.tv_usec) / 1000; | |
28a35d8a | 980 | |
99965709 | 981 | if (running_msec < sigma->limit_msec && numchunks < 32767) |
6aac7737 | 982 | return FALSE; |
28a35d8a | 983 | |
99965709 | 984 | hw_stop_acquisition(sdi->index, user_data); |
6aac7737 HE |
985 | |
986 | return FALSE; | |
987 | ||
99965709 HE |
988 | } else if (sigma->state.state == SIGMA_DOWNLOAD) { |
989 | if (sigma->state.chunks_downloaded >= numchunks) { | |
6aac7737 | 990 | /* End of samples. */ |
5a2326a7 | 991 | packet.type = SR_DF_END; |
6aac7737 | 992 | packet.length = 0; |
8a2efef2 | 993 | sr_session_bus(sigma->session_id, &packet); |
6aac7737 | 994 | |
99965709 | 995 | sigma->state.state = SIGMA_IDLE; |
f78898e9 | 996 | |
6aac7737 HE |
997 | return TRUE; |
998 | } | |
999 | ||
1000 | newchunks = MIN(chunks_per_read, | |
99965709 | 1001 | numchunks - sigma->state.chunks_downloaded); |
28a35d8a HE |
1002 | |
1003 | g_message("Downloading sample data: %.0f %%", | |
99965709 | 1004 | 100.0 * sigma->state.chunks_downloaded / numchunks); |
28a35d8a | 1005 | |
99965709 HE |
1006 | bufsz = sigma_read_dram(sigma->state.chunks_downloaded, |
1007 | newchunks, buf, sigma); | |
28a35d8a | 1008 | |
fefa1800 | 1009 | /* Find first ts. */ |
99965709 HE |
1010 | if (sigma->state.chunks_downloaded == 0) { |
1011 | sigma->state.lastts = *(uint16_t *) buf - 1; | |
1012 | sigma->state.lastsample = 0; | |
6aac7737 | 1013 | } |
28a35d8a | 1014 | |
fefa1800 | 1015 | /* Decode chunks and send them to sigrok. */ |
28a35d8a | 1016 | for (i = 0; i < newchunks; ++i) { |
88c51afe HE |
1017 | int limit_chunk = 0; |
1018 | ||
1019 | /* The last chunk may potentially be only in part. */ | |
1020 | if (sigma->state.chunks_downloaded == numchunks - 1) | |
1021 | { | |
1022 | /* Find the last valid timestamp */ | |
1023 | limit_chunk = sigma->state.stoppos % 512 + sigma->state.lastts; | |
1024 | } | |
1025 | ||
99965709 | 1026 | if (sigma->state.chunks_downloaded + i == sigma->state.triggerchunk) |
57bbf56b | 1027 | decode_chunk_ts(buf + (i * CHUNK_SIZE), |
99965709 HE |
1028 | &sigma->state.lastts, |
1029 | &sigma->state.lastsample, | |
1030 | sigma->state.triggerpos & 0x1ff, | |
88c51afe | 1031 | limit_chunk, user_data); |
57bbf56b HE |
1032 | else |
1033 | decode_chunk_ts(buf + (i * CHUNK_SIZE), | |
99965709 HE |
1034 | &sigma->state.lastts, |
1035 | &sigma->state.lastsample, | |
88c51afe | 1036 | -1, limit_chunk, user_data); |
28a35d8a | 1037 | |
88c51afe HE |
1038 | ++sigma->state.chunks_downloaded; |
1039 | } | |
28a35d8a HE |
1040 | } |
1041 | ||
28a35d8a HE |
1042 | return TRUE; |
1043 | } | |
1044 | ||
c53d793f HE |
1045 | /* Build a LUT entry used by the trigger functions. */ |
1046 | static void build_lut_entry(uint16_t value, uint16_t mask, uint16_t *entry) | |
ee492173 HE |
1047 | { |
1048 | int i, j, k, bit; | |
1049 | ||
f758d074 | 1050 | /* For each quad probe. */ |
ee492173 | 1051 | for (i = 0; i < 4; ++i) { |
c53d793f | 1052 | entry[i] = 0xffff; |
ee492173 | 1053 | |
f758d074 | 1054 | /* For each bit in LUT. */ |
ee492173 HE |
1055 | for (j = 0; j < 16; ++j) |
1056 | ||
f758d074 | 1057 | /* For each probe in quad. */ |
ee492173 HE |
1058 | for (k = 0; k < 4; ++k) { |
1059 | bit = 1 << (i * 4 + k); | |
1060 | ||
c53d793f HE |
1061 | /* Set bit in entry */ |
1062 | if ((mask & bit) && | |
1063 | ((!(value & bit)) != | |
4ae1f451 | 1064 | (!(j & (1 << k))))) |
c53d793f | 1065 | entry[i] &= ~(1 << j); |
ee492173 HE |
1066 | } |
1067 | } | |
c53d793f | 1068 | } |
ee492173 | 1069 | |
c53d793f HE |
1070 | /* Add a logical function to LUT mask. */ |
1071 | static void add_trigger_function(enum triggerop oper, enum triggerfunc func, | |
1072 | int index, int neg, uint16_t *mask) | |
1073 | { | |
1074 | int i, j; | |
1075 | int x[2][2], tmp, a, b, aset, bset, rset; | |
1076 | ||
1077 | memset(x, 0, 4 * sizeof(int)); | |
1078 | ||
1079 | /* Trigger detect condition. */ | |
1080 | switch (oper) { | |
1081 | case OP_LEVEL: | |
1082 | x[0][1] = 1; | |
1083 | x[1][1] = 1; | |
1084 | break; | |
1085 | case OP_NOT: | |
1086 | x[0][0] = 1; | |
1087 | x[1][0] = 1; | |
1088 | break; | |
1089 | case OP_RISE: | |
1090 | x[0][1] = 1; | |
1091 | break; | |
1092 | case OP_FALL: | |
1093 | x[1][0] = 1; | |
1094 | break; | |
1095 | case OP_RISEFALL: | |
1096 | x[0][1] = 1; | |
1097 | x[1][0] = 1; | |
1098 | break; | |
1099 | case OP_NOTRISE: | |
1100 | x[1][1] = 1; | |
1101 | x[0][0] = 1; | |
1102 | x[1][0] = 1; | |
1103 | break; | |
1104 | case OP_NOTFALL: | |
1105 | x[1][1] = 1; | |
1106 | x[0][0] = 1; | |
1107 | x[0][1] = 1; | |
1108 | break; | |
1109 | case OP_NOTRISEFALL: | |
1110 | x[1][1] = 1; | |
1111 | x[0][0] = 1; | |
1112 | break; | |
1113 | } | |
1114 | ||
1115 | /* Transpose if neg is set. */ | |
1116 | if (neg) { | |
1117 | for (i = 0; i < 2; ++i) | |
1118 | for (j = 0; j < 2; ++j) { | |
1119 | tmp = x[i][j]; | |
1120 | x[i][j] = x[1-i][1-j]; | |
1121 | x[1-i][1-j] = tmp; | |
1122 | } | |
1123 | } | |
1124 | ||
1125 | /* Update mask with function. */ | |
1126 | for (i = 0; i < 16; ++i) { | |
1127 | a = (i >> (2 * index + 0)) & 1; | |
1128 | b = (i >> (2 * index + 1)) & 1; | |
1129 | ||
1130 | aset = (*mask >> i) & 1; | |
1131 | bset = x[b][a]; | |
1132 | ||
1133 | if (func == FUNC_AND || func == FUNC_NAND) | |
1134 | rset = aset & bset; | |
1135 | else if (func == FUNC_OR || func == FUNC_NOR) | |
1136 | rset = aset | bset; | |
1137 | else if (func == FUNC_XOR || func == FUNC_NXOR) | |
1138 | rset = aset ^ bset; | |
1139 | ||
1140 | if (func == FUNC_NAND || func == FUNC_NOR || func == FUNC_NXOR) | |
1141 | rset = !rset; | |
1142 | ||
1143 | *mask &= ~(1 << i); | |
1144 | ||
1145 | if (rset) | |
1146 | *mask |= 1 << i; | |
1147 | } | |
1148 | } | |
1149 | ||
1150 | /* | |
1151 | * Build trigger LUTs used by 50 MHz and lower sample rates for supporting | |
1152 | * simple pin change and state triggers. Only two transitions (rise/fall) can be | |
1153 | * set at any time, but a full mask and value can be set (0/1). | |
1154 | */ | |
99965709 | 1155 | static int build_basic_trigger(struct triggerlut *lut, struct sigma *sigma) |
c53d793f HE |
1156 | { |
1157 | int i,j; | |
4ae1f451 | 1158 | uint16_t masks[2] = { 0, 0 }; |
c53d793f HE |
1159 | |
1160 | memset(lut, 0, sizeof(struct triggerlut)); | |
1161 | ||
1162 | /* Contant for simple triggers. */ | |
1163 | lut->m4 = 0xa000; | |
1164 | ||
1165 | /* Value/mask trigger support. */ | |
99965709 HE |
1166 | build_lut_entry(sigma->trigger.simplevalue, sigma->trigger.simplemask, |
1167 | lut->m2d); | |
c53d793f HE |
1168 | |
1169 | /* Rise/fall trigger support. */ | |
1170 | for (i = 0, j = 0; i < 16; ++i) { | |
99965709 HE |
1171 | if (sigma->trigger.risingmask & (1 << i) || |
1172 | sigma->trigger.fallingmask & (1 << i)) | |
c53d793f HE |
1173 | masks[j++] = 1 << i; |
1174 | } | |
1175 | ||
1176 | build_lut_entry(masks[0], masks[0], lut->m0d); | |
1177 | build_lut_entry(masks[1], masks[1], lut->m1d); | |
1178 | ||
1179 | /* Add glue logic */ | |
1180 | if (masks[0] || masks[1]) { | |
1181 | /* Transition trigger. */ | |
99965709 | 1182 | if (masks[0] & sigma->trigger.risingmask) |
c53d793f | 1183 | add_trigger_function(OP_RISE, FUNC_OR, 0, 0, &lut->m3); |
99965709 | 1184 | if (masks[0] & sigma->trigger.fallingmask) |
c53d793f | 1185 | add_trigger_function(OP_FALL, FUNC_OR, 0, 0, &lut->m3); |
99965709 | 1186 | if (masks[1] & sigma->trigger.risingmask) |
c53d793f | 1187 | add_trigger_function(OP_RISE, FUNC_OR, 1, 0, &lut->m3); |
99965709 | 1188 | if (masks[1] & sigma->trigger.fallingmask) |
c53d793f HE |
1189 | add_trigger_function(OP_FALL, FUNC_OR, 1, 0, &lut->m3); |
1190 | } else { | |
1191 | /* Only value/mask trigger. */ | |
1192 | lut->m3 = 0xffff; | |
1193 | } | |
ee492173 | 1194 | |
c53d793f | 1195 | /* Triggertype: event. */ |
ee492173 HE |
1196 | lut->params.selres = 3; |
1197 | ||
e46b8fb1 | 1198 | return SR_OK; |
ee492173 HE |
1199 | } |
1200 | ||
28a35d8a HE |
1201 | static int hw_start_acquisition(int device_index, gpointer session_device_id) |
1202 | { | |
a00ba012 | 1203 | struct sr_device_instance *sdi; |
99965709 | 1204 | struct sigma *sigma; |
b9c735a2 UH |
1205 | struct sr_datafeed_packet packet; |
1206 | struct sr_datafeed_header header; | |
9ddb2a12 | 1207 | struct clockselect_50 clockselect; |
82957b65 | 1208 | int frac, triggerpin, ret; |
57bbf56b HE |
1209 | uint8_t triggerselect; |
1210 | struct triggerinout triggerinout_conf; | |
ee492173 | 1211 | struct triggerlut lut; |
28a35d8a HE |
1212 | |
1213 | session_device_id = session_device_id; | |
1214 | ||
d32d961d | 1215 | if (!(sdi = sr_get_device_instance(device_instances, device_index))) |
e46b8fb1 | 1216 | return SR_ERR; |
28a35d8a | 1217 | |
99965709 | 1218 | sigma = sdi->priv; |
28a35d8a | 1219 | |
7c70c538 | 1220 | /* If the samplerate has not been set, default to 200 KHz. */ |
82957b65 UH |
1221 | if (sigma->cur_firmware == -1) { |
1222 | if ((ret = set_samplerate(sdi, SR_KHZ(200))) != SR_OK) | |
1223 | return ret; | |
1224 | } | |
e8397563 | 1225 | |
eec5275e | 1226 | /* Enter trigger programming mode. */ |
99965709 | 1227 | sigma_set_register(WRITE_TRIGGER_SELECT1, 0x20, sigma); |
28a35d8a | 1228 | |
eec5275e | 1229 | /* 100 and 200 MHz mode. */ |
59df0c77 | 1230 | if (sigma->cur_samplerate >= SR_MHZ(100)) { |
99965709 | 1231 | sigma_set_register(WRITE_TRIGGER_SELECT1, 0x81, sigma); |
57bbf56b | 1232 | |
a42aec7f HE |
1233 | /* Find which pin to trigger on from mask. */ |
1234 | for (triggerpin = 0; triggerpin < 8; ++triggerpin) | |
99965709 | 1235 | if ((sigma->trigger.risingmask | sigma->trigger.fallingmask) & |
a42aec7f HE |
1236 | (1 << triggerpin)) |
1237 | break; | |
1238 | ||
1239 | /* Set trigger pin and light LED on trigger. */ | |
1240 | triggerselect = (1 << LEDSEL1) | (triggerpin & 0x7); | |
1241 | ||
1242 | /* Default rising edge. */ | |
99965709 | 1243 | if (sigma->trigger.fallingmask) |
a42aec7f | 1244 | triggerselect |= 1 << 3; |
57bbf56b | 1245 | |
eec5275e | 1246 | /* All other modes. */ |
59df0c77 | 1247 | } else if (sigma->cur_samplerate <= SR_MHZ(50)) { |
99965709 | 1248 | build_basic_trigger(&lut, sigma); |
ee492173 | 1249 | |
99965709 | 1250 | sigma_write_trigger_lut(&lut, sigma); |
57bbf56b HE |
1251 | |
1252 | triggerselect = (1 << LEDSEL1) | (1 << LEDSEL0); | |
1253 | } | |
1254 | ||
eec5275e | 1255 | /* Setup trigger in and out pins to default values. */ |
57bbf56b HE |
1256 | memset(&triggerinout_conf, 0, sizeof(struct triggerinout)); |
1257 | triggerinout_conf.trgout_bytrigger = 1; | |
1258 | triggerinout_conf.trgout_enable = 1; | |
1259 | ||
28a35d8a | 1260 | sigma_write_register(WRITE_TRIGGER_OPTION, |
57bbf56b | 1261 | (uint8_t *) &triggerinout_conf, |
99965709 | 1262 | sizeof(struct triggerinout), sigma); |
28a35d8a | 1263 | |
eec5275e | 1264 | /* Go back to normal mode. */ |
99965709 | 1265 | sigma_set_register(WRITE_TRIGGER_SELECT1, triggerselect, sigma); |
28a35d8a | 1266 | |
edca2c5c | 1267 | /* Set clock select register. */ |
59df0c77 | 1268 | if (sigma->cur_samplerate == SR_MHZ(200)) |
edca2c5c | 1269 | /* Enable 4 probes. */ |
99965709 | 1270 | sigma_set_register(WRITE_CLOCK_SELECT, 0xf0, sigma); |
59df0c77 | 1271 | else if (sigma->cur_samplerate == SR_MHZ(100)) |
edca2c5c | 1272 | /* Enable 8 probes. */ |
99965709 | 1273 | sigma_set_register(WRITE_CLOCK_SELECT, 0x00, sigma); |
edca2c5c HE |
1274 | else { |
1275 | /* | |
9ddb2a12 | 1276 | * 50 MHz mode (or fraction thereof). Any fraction down to |
eec5275e | 1277 | * 50 MHz / 256 can be used, but is not supported by sigrok API. |
edca2c5c | 1278 | */ |
59df0c77 | 1279 | frac = SR_MHZ(50) / sigma->cur_samplerate - 1; |
edca2c5c | 1280 | |
9ddb2a12 UH |
1281 | clockselect.async = 0; |
1282 | clockselect.fraction = frac; | |
1283 | clockselect.disabled_probes = 0; | |
edca2c5c HE |
1284 | |
1285 | sigma_write_register(WRITE_CLOCK_SELECT, | |
9ddb2a12 | 1286 | (uint8_t *) &clockselect, |
99965709 | 1287 | sizeof(clockselect), sigma); |
edca2c5c HE |
1288 | } |
1289 | ||
fefa1800 | 1290 | /* Setup maximum post trigger time. */ |
99965709 HE |
1291 | sigma_set_register(WRITE_POST_TRIGGER, |
1292 | (sigma->capture_ratio * 255) / 100, sigma); | |
28a35d8a | 1293 | |
eec5275e | 1294 | /* Start acqusition. */ |
99965709 HE |
1295 | gettimeofday(&sigma->start_tv, 0); |
1296 | sigma_set_register(WRITE_MODE, 0x0d, sigma); | |
1297 | ||
1298 | sigma->session_id = session_device_id; | |
28a35d8a | 1299 | |
28a35d8a | 1300 | /* Send header packet to the session bus. */ |
5a2326a7 | 1301 | packet.type = SR_DF_HEADER; |
b9c735a2 | 1302 | packet.length = sizeof(struct sr_datafeed_header); |
28a35d8a HE |
1303 | packet.payload = &header; |
1304 | header.feed_version = 1; | |
1305 | gettimeofday(&header.starttime, NULL); | |
99965709 | 1306 | header.samplerate = sigma->cur_samplerate; |
5a2326a7 | 1307 | header.protocol_id = SR_PROTO_RAW; |
99965709 | 1308 | header.num_logic_probes = sigma->num_probes; |
c2616fb9 | 1309 | header.num_analog_probes = 0; |
8a2efef2 | 1310 | sr_session_bus(session_device_id, &packet); |
28a35d8a | 1311 | |
57bbf56b | 1312 | /* Add capture source. */ |
6f1be0a2 | 1313 | sr_source_add(0, G_IO_IN, 10, receive_data, sdi); |
57bbf56b | 1314 | |
99965709 | 1315 | sigma->state.state = SIGMA_CAPTURE; |
6aac7737 | 1316 | |
e46b8fb1 | 1317 | return SR_OK; |
28a35d8a HE |
1318 | } |
1319 | ||
28a35d8a HE |
1320 | static void hw_stop_acquisition(int device_index, gpointer session_device_id) |
1321 | { | |
a00ba012 | 1322 | struct sr_device_instance *sdi; |
99965709 | 1323 | struct sigma *sigma; |
6aac7737 HE |
1324 | uint8_t modestatus; |
1325 | ||
d32d961d | 1326 | if (!(sdi = sr_get_device_instance(device_instances, device_index))) |
99965709 HE |
1327 | return; |
1328 | ||
1329 | sigma = sdi->priv; | |
1330 | ||
28a35d8a HE |
1331 | session_device_id = session_device_id; |
1332 | ||
fefa1800 | 1333 | /* Stop acquisition. */ |
99965709 | 1334 | sigma_set_register(WRITE_MODE, 0x11, sigma); |
28a35d8a | 1335 | |
6aac7737 | 1336 | /* Set SDRAM Read Enable. */ |
99965709 | 1337 | sigma_set_register(WRITE_MODE, 0x02, sigma); |
6aac7737 HE |
1338 | |
1339 | /* Get the current position. */ | |
99965709 | 1340 | sigma_read_pos(&sigma->state.stoppos, &sigma->state.triggerpos, sigma); |
6aac7737 HE |
1341 | |
1342 | /* Check if trigger has fired. */ | |
99965709 | 1343 | modestatus = sigma_get_register(READ_MODE, sigma); |
6aac7737 | 1344 | if (modestatus & 0x20) { |
99965709 | 1345 | sigma->state.triggerchunk = sigma->state.triggerpos / 512; |
6aac7737 HE |
1346 | |
1347 | } else | |
99965709 | 1348 | sigma->state.triggerchunk = -1; |
6aac7737 | 1349 | |
99965709 | 1350 | sigma->state.chunks_downloaded = 0; |
6aac7737 | 1351 | |
99965709 | 1352 | sigma->state.state = SIGMA_DOWNLOAD; |
28a35d8a HE |
1353 | } |
1354 | ||
5c2d46d1 | 1355 | struct sr_device_plugin asix_sigma_plugin_info = { |
28a35d8a | 1356 | "asix-sigma", |
9f8274a5 | 1357 | "ASIX SIGMA", |
28a35d8a HE |
1358 | 1, |
1359 | hw_init, | |
1360 | hw_cleanup, | |
28a35d8a HE |
1361 | hw_opendev, |
1362 | hw_closedev, | |
1363 | hw_get_device_info, | |
1364 | hw_get_status, | |
1365 | hw_get_capabilities, | |
1366 | hw_set_configuration, | |
1367 | hw_start_acquisition, | |
9ddb2a12 | 1368 | hw_stop_acquisition, |
28a35d8a | 1369 | }; |