[sigrok-firmware-fx2lafw.git] / hantek_6022bl.c

/*
 * This file is part of the sigrok-firmware-fx2lafw project.
 *
 * Copyright (C) 2009 Ubixum, Inc.
 * Copyright (C) 2015 Jochen Hoenicke
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2.1 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
 */

#include <fx2macros.h>
#include <fx2ints.h>
#include <autovector.h>
#include <delay.h>
#include <setupdat.h>

#define SET_ANALOG_MODE() PA7 = 1

#define SET_COUPLING(x)

#define SET_CALIBRATION_PULSE(x)

/* Toggle the 1kHz calibration pin, only accurate up to ca. 8MHz. */
#define TOGGLE_CALIBRATION_PIN() PC2 = !PC2

#define LED_CLEAR() PC0 = 1; PC1 = 1;
#define LED_GREEN() PC0 = 1; PC1 = 0;
#define LED_RED()   PC0 = 0; PC1 = 1;

#define TIMER2_VAL 500

/* CTLx pin index (IFCLK, ADC clock input). */
#define CTL_BIT 0

#define OUT0 ((1 << CTL_BIT) << 4) /* OEx = 1, CTLx = 0 */
#define OE_CTL (((1 << CTL_BIT) << 4) | (1 << CTL_BIT)) /* OEx = CTLx = 1 */

/* Change to support as many interfaces as you need. */
static BYTE altiface = 0;

static volatile WORD ledcounter = 0;

static volatile __bit dosud = FALSE;
static volatile __bit dosuspend = FALSE;

extern __code BYTE highspd_dscr;
extern __code BYTE fullspd_dscr;

void resume_isr(void) __interrupt RESUME_ISR
{
	CLEAR_RESUME();
}

void sudav_isr(void) __interrupt SUDAV_ISR
{
	dosud = TRUE;
	CLEAR_SUDAV();
}

void usbreset_isr(void) __interrupt USBRESET_ISR
{
	handle_hispeed(FALSE);
	CLEAR_USBRESET();
}

void hispeed_isr(void) __interrupt HISPEED_ISR
{
	handle_hispeed(TRUE);
	CLEAR_HISPEED();
}

void suspend_isr(void) __interrupt SUSPEND_ISR
{
	dosuspend = TRUE;
	CLEAR_SUSPEND();
}

void timer2_isr(void) __interrupt TF2_ISR
{
	TOGGLE_CALIBRATION_PIN();

	if (ledcounter && (--ledcounter == 0))
		LED_CLEAR();

	TF2 = 0;
}

/*
 * This sets three bits for each channel, one channel at a time.
 * For channel 0 we want to set bits 1, 2 & 3
 * For channel 1 we want to set bits 4, 5 & 6
 *
 * We convert the input values that are strange due to original
 * firmware code into the value of the three bits as follows:
 *
 * val -> bits
 * 1  -> 010b
 * 2  -> 001b
 * 5  -> 000b
 * 10 -> 011b
 *
 * The third bit is always zero since there are only four outputs connected
 * in the serial selector chip.
 *
 * The multiplication of the converted value by 0x24 sets the relevant bits in
 * both channels and then we mask it out to only affect the channel currently
 * requested.
 */
static BOOL set_voltage(BYTE channel, BYTE val)
{
	BYTE bits, mask;

	switch (val) {
	case 1:
		bits = 0x02;
		break;
	case 2:
		bits = 0x01;
		break;
	case 5:
		bits = 0x00;
		break;
	case 10:
		bits = 0x03;
		break;
	default:
		return FALSE;
	}

	bits = bits << (channel ? 1 : 4);
	mask = (channel) ? 0x70 : 0x0e;
	IOA = (IOA & ~mask) | (bits & mask);

	return TRUE;
}

/**
 * Each LSB in the nibble of the byte controls the coupling per channel.
 *
 * Setting PE3 disables AC coupling capacitor on CH0.
 * Setting PE0 disables AC coupling capacitor on CH1.
 */
static void set_coupling(BYTE coupling_cfg)
{
	if (coupling_cfg & 0x01)
		IOE |= 0x08;
	else
		IOE &= ~0x08;

	if (coupling_cfg & 0x10)
		IOE |= 0x01;
	else
		IOE &= ~0x01;
}

static BOOL set_numchannels(BYTE numchannels)
{
	if (numchannels == 1 || numchannels == 2) {
		BYTE fifocfg = 7 + numchannels;
		EP2FIFOCFG = fifocfg;
		EP6FIFOCFG = fifocfg;
		return TRUE;
	}

	return FALSE;
}

static void clear_fifo(void)
{
	GPIFABORT = 0xff;
	SYNCDELAY3;
	FIFORESET = 0x80;
	SYNCDELAY3;
	FIFORESET = 0x82;
	SYNCDELAY3;
	FIFORESET = 0x86;
	SYNCDELAY3;
	FIFORESET = 0;
}

static void stop_sampling(void)
{
	GPIFABORT = 0xff;
	SYNCDELAY3;
	INPKTEND = (altiface == 0) ? 6 : 2;
}

static void start_sampling(void)
{
	int i;

	SET_ANALOG_MODE();

	clear_fifo();

	for (i = 0; i < 1000; i++);

	while (!(GPIFTRIG & 0x80))
		;

	SYNCDELAY3;
	GPIFTCB1 = 0x28;
	SYNCDELAY3;
	GPIFTCB0 = 0;
	GPIFTRIG = (altiface == 0) ? 6 : 4;

	/* Set green LED, don't clear LED afterwards (ledcounter = 0). */
	LED_GREEN();
	ledcounter = 0;
}

static void select_interface(BYTE alt)
{
	const BYTE *pPacketSize = \
		((USBCS & bmHSM) ? &highspd_dscr : &fullspd_dscr)
		+ (9 + (16 * alt) + 9 + 4);

	altiface = alt;

	if (alt == 0) {
		/* Bulk on EP6. */
		EP2CFG = 0x00;
		EP6CFG = 0xe0;
		EP6GPIFFLGSEL = 1;
		EP6AUTOINLENL = pPacketSize[0];
		EP6AUTOINLENH = pPacketSize[1];
	} else {
		/* Iso on EP2. */
		EP2CFG = 0xd8;
		EP6CFG = 0x00;
		EP2GPIFFLGSEL = 1;
		EP2AUTOINLENL = pPacketSize[0];
		EP2AUTOINLENH = pPacketSize[1] & 0x7;
		EP2ISOINPKTS = (pPacketSize[1] >> 3) + 1;
	}
}

static const struct samplerate_info {
	BYTE rate;
	BYTE wait0;
	BYTE wait1;
	BYTE opc0;
	BYTE opc1;
	BYTE out0;
	BYTE ifcfg;
} samplerates[] = {
	{ 48, 0x80,   0, 3, 0, 0x00, 0xea },
	{ 30, 0x80,   0, 3, 0, 0x00, 0xaa },
	{ 24,    1,   0, 2, 1, OUT0, 0xca },
	{ 16,    1,   1, 2, 0, OUT0, 0xca },
	{ 12,    2,   1, 2, 0, OUT0, 0xca },
	{  8,    3,   2, 2, 0, OUT0, 0xca },
	{  4,    6,   5, 2, 0, OUT0, 0xca },
	{  2,   12,  11, 2, 0, OUT0, 0xca },
	{  1,   24,  23, 2, 0, OUT0, 0xca },
	{ 50,   48,  47, 2, 0, OUT0, 0xca },
	{ 20,  120, 119, 2, 0, OUT0, 0xca },
	{ 10,  240, 239, 2, 0, OUT0, 0xca },
};

static BOOL set_samplerate(BYTE rate)
{
	BYTE i = 0;

	while (samplerates[i].rate != rate) {
		i++;
		if (i == sizeof(samplerates) / sizeof(samplerates[0]))
			return FALSE;
	}

	IFCONFIG = samplerates[i].ifcfg;

	AUTOPTRSETUP = 7;
	AUTOPTRH2 = 0xE4; /* 0xE400: GPIF waveform descriptor 0. */
	AUTOPTRL2 = 0x00;

	/*
	 * The program for low-speed, e.g. 1 MHz, is:
	 * wait 24, CTLx=0, FIFO
	 * wait 23, CTLx=1
	 * jump 0, CTLx=1
	 *
	 * The program for 24 MHz is:
	 * wait 1, CTLx=0, FIFO
	 * jump 0, CTLx=1
	 *
	 * The program for 30/48 MHz is:
	 * jump 0, CTLx=Z, FIFO, LOOP
	 *
	 * (CTLx is device-dependent, could be e.g. CTL0 or CTL2.)
	 */

	/* LENGTH / BRANCH 0-7 */
	EXTAUTODAT2 = samplerates[i].wait0;
	EXTAUTODAT2 = samplerates[i].wait1;
	EXTAUTODAT2 = 1;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;

	/* OPCODE 0-7 */
	EXTAUTODAT2 = samplerates[i].opc0;
	EXTAUTODAT2 = samplerates[i].opc1;
	EXTAUTODAT2 = 1; /* DATA=0 DP=1 */
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;

	/* OUTPUT 0-7 */
	EXTAUTODAT2 = samplerates[i].out0;
	EXTAUTODAT2 = OE_CTL;
	EXTAUTODAT2 = OE_CTL;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;

	/* LOGIC FUNCTION 0-7 */
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;

	for (i = 0; i < 96; i++)
		EXTAUTODAT2 = 0;

	return TRUE;
}

static BOOL set_calibration_pulse(BYTE fs)
{
	switch (fs) {
	case 0:		// 100Hz
		RCAP2L = -10000 & 0xff;
		RCAP2H = (-10000 & 0xff00) >> 8;
		return TRUE;
	case 1:		// 1kHz
		RCAP2L = -1000 & 0xff;
		RCAP2H = (-1000 & 0xff00) >> 8;
		return TRUE;
	case 10:	// 1kHz
		RCAP2L = (BYTE)(-100 & 0xff);
		RCAP2H = 0xff;
		return TRUE;
	case 50:	// 50kHz
		RCAP2L = (BYTE)(-20 & 0xff);
		RCAP2H = 0xff;
		return TRUE;
	default:
		return FALSE;
	}
}

/* Set *alt_ifc to the current alt interface for ifc. */
BOOL handle_get_interface(BYTE ifc, BYTE *alt_ifc)
{
	(void)ifc;

	*alt_ifc = altiface;

	return TRUE;
}

/*
 * Return TRUE if you set the interface requested.
 *
 * Note: This function should reconfigure and reset the endpoints
 * according to the interface descriptors you provided.
 */
BOOL handle_set_interface(BYTE ifc,BYTE alt_ifc)
{
	if (ifc == 0)
		select_interface(alt_ifc);

	return TRUE;
}

BYTE handle_get_configuration(void)
{
	/* We only support configuration 0. */
	return 0;
}

BOOL handle_set_configuration(BYTE cfg)
{
	/* We only support configuration 0. */
	(void)cfg;

	return TRUE;
}

BOOL handle_vendorcommand(BYTE cmd)
{
	stop_sampling();

	/* Set red LED, clear after timeout. */
	LED_RED();
	ledcounter = 1000;

	/* Clear EP0BCH/L for each valid command. */
	if (cmd >= 0xe0 && cmd <= 0xe6) {
		EP0BCH = 0;
		EP0BCL = 0;
		while (EP0CS & bmEPBUSY);
	}

	switch (cmd) {
	case 0xe0:
	case 0xe1:
		set_voltage(cmd - 0xe0, EP0BUF[0]);
		return TRUE;
	case 0xe2:
		set_samplerate(EP0BUF[0]);
		return TRUE;
	case 0xe3:
		if (EP0BUF[0] == 1)
			start_sampling();
		return TRUE;
	case 0xe4:
		set_numchannels(EP0BUF[0]);
		return TRUE;
	case 0xe5:
		SET_COUPLING(EP0BUF[0]);
		return TRUE;
	case 0xe6:
		SET_CALIBRATION_PULSE(EP0BUF[0]);
		return TRUE;
	}

	return FALSE; /* Not handled by handlers. */
}

static void init(void)
{
	EP4CFG = 0;
	EP8CFG = 0;

	SET_ANALOG_MODE();

	/* In idle mode tristate all outputs. */
	GPIFIDLECTL = 0x00; /* Don't enable CTL0-5 outputs. */
	GPIFCTLCFG = 0x80; /* TRICTL=1. CTL0-2: CMOS outputs, tri-statable. */
	GPIFWFSELECT = 0x00;
	GPIFREADYSTAT = 0x00;

	stop_sampling();

	set_voltage(0, 1);
	set_voltage(1, 1);
	set_samplerate(1);
	set_numchannels(2);
	select_interface(0);
}

static void main(void)
{
	/* Save energy. */
	SETCPUFREQ(CLK_12M);

	init();

	/* Set up interrupts. */
	USE_USB_INTS();

	ENABLE_SUDAV();
	ENABLE_USBRESET();
	ENABLE_HISPEED(); 
	ENABLE_SUSPEND();
	ENABLE_RESUME();

	/* Global (8051) interrupt enable. */
	EA = 1;

	/* Init timer2. */
	RCAP2L = -TIMER2_VAL & 0xff;
	RCAP2H = (-TIMER2_VAL & 0xff00) >> 8;
	T2CON = 0;
	ET2 = 1;
	TR2 = 1;

	RENUMERATE_UNCOND();

	PORTECFG = 0;
	PORTCCFG = 0;
	PORTACFG = 0;
	OEE = 0xff;
	OEC = 0xff;
	OEA = 0xff;

	while (TRUE) {
		if (dosud) {
			dosud = FALSE;
			handle_setupdata();
		}

		if (dosuspend) {
			dosuspend = FALSE;
			do {
				/* Make sure ext wakeups are cleared. */
				WAKEUPCS |= bmWU | bmWU2;
				SUSPEND = 1;
				PCON |= 1;
				__asm
				nop
				nop
				nop
				nop
				nop
				nop
				nop
				__endasm;
			} while (!remote_wakeup_allowed && REMOTE_WAKEUP());

			/* Resume (TRM 6.4). */
			if (REMOTE_WAKEUP()) {
				delay(5);
				USBCS |= bmSIGRESUME;
				delay(15);
				USBCS &= ~bmSIGRESUME;
			}
		}
	}
}
Commit	Line	Data
1d203181 STA	1	/*
	2	* This file is part of the sigrok-firmware-fx2lafw project.
	3	*
	4	* Copyright (C) 2009 Ubixum, Inc.
	5	* Copyright (C) 2015 Jochen Hoenicke
	6	*
	7	* This library is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU Lesser General Public
	9	* License as published by the Free Software Foundation; either
	10	* version 2.1 of the License, or (at your option) any later version.
	11	*
	12	* This library is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	15	* Lesser General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU Lesser General Public
	18	* License along with this library; if not, see <http://www.gnu.org/licenses/>.
	19	*/
	20
	21	#include <fx2macros.h>
	22	#include <fx2ints.h>
	23	#include <autovector.h>
	24	#include <delay.h>
	25	#include <setupdat.h>
	26
be6d306d UH	27	#define SET_ANALOG_MODE() PA7 = 1
be6d306d UH	28
297fb13a UH	29	#define SET_COUPLING(x)
	30
	31	#define SET_CALIBRATION_PULSE(x)
	32
e583c3fc UH	33	/* Toggle the 1kHz calibration pin, only accurate up to ca. 8MHz. */
	34	#define TOGGLE_CALIBRATION_PIN() PC2 = !PC2
	35
65b34f7e UH	36	#define LED_CLEAR() PC0 = 1; PC1 = 1;
	37	#define LED_GREEN() PC0 = 1; PC1 = 0;
	38	#define LED_RED() PC0 = 0; PC1 = 1;
	39
2c57c00b UH	40	#define TIMER2_VAL 500
2c57c00b UH	41
e1c5ba21 UH	42	/* CTLx pin index (IFCLK, ADC clock input). */
	43	#define CTL_BIT 0
	44
	45	#define OUT0 ((1 << CTL_BIT) << 4) /* OEx = 1, CTLx = 0 */
	46	#define OE_CTL (((1 << CTL_BIT) << 4) \| (1 << CTL_BIT)) /* OEx = CTLx = 1 */
	47
1d203181 STA	48	/* Change to support as many interfaces as you need. */
	49	static BYTE altiface = 0;
	50
	51	static volatile WORD ledcounter = 0;
	52
	53	static volatile __bit dosud = FALSE;
	54	static volatile __bit dosuspend = FALSE;
	55
	56	extern __code BYTE highspd_dscr;
	57	extern __code BYTE fullspd_dscr;
	58
	59	void resume_isr(void) __interrupt RESUME_ISR
	60	{
	61	CLEAR_RESUME();
	62	}
	63
	64	void sudav_isr(void) __interrupt SUDAV_ISR
	65	{
	66	dosud = TRUE;
	67	CLEAR_SUDAV();
	68	}
	69
	70	void usbreset_isr(void) __interrupt USBRESET_ISR
	71	{
	72	handle_hispeed(FALSE);
	73	CLEAR_USBRESET();
	74	}
	75
	76	void hispeed_isr(void) __interrupt HISPEED_ISR
	77	{
	78	handle_hispeed(TRUE);
	79	CLEAR_HISPEED();
	80	}
	81
	82	void suspend_isr(void) __interrupt SUSPEND_ISR
	83	{
	84	dosuspend = TRUE;
	85	CLEAR_SUSPEND();
	86	}
	87
	88	void timer2_isr(void) __interrupt TF2_ISR
	89	{
e583c3fc	90	TOGGLE_CALIBRATION_PIN();
cbd1bc65	91
65b34f7e UH	92	if (ledcounter && (--ledcounter == 0))
65b34f7e UH	93	LED_CLEAR();
3968bbfb	94
1d203181 STA	95	TF2 = 0;
	96	}
	97
	98	/*
	99	* This sets three bits for each channel, one channel at a time.
ae56b4f6 JL	100	* For channel 0 we want to set bits 1, 2 & 3
ae56b4f6 JL	101	* For channel 1 we want to set bits 4, 5 & 6
1d203181 STA	102	*
	103	* We convert the input values that are strange due to original
	104	* firmware code into the value of the three bits as follows:
	105	*
	106	* val -> bits
	107	* 1 -> 010b
	108	* 2 -> 001b
	109	* 5 -> 000b
	110	* 10 -> 011b
	111	*
	112	* The third bit is always zero since there are only four outputs connected
	113	* in the serial selector chip.
	114	*
	115	* The multiplication of the converted value by 0x24 sets the relevant bits in
	116	* both channels and then we mask it out to only affect the channel currently
	117	* requested.
	118	*/
	119	static BOOL set_voltage(BYTE channel, BYTE val)
	120	{
	121	BYTE bits, mask;
	122
	123	switch (val) {
	124	case 1:
ae56b4f6	125	bits = 0x02;
1d203181 STA	126	break;
1d203181 STA	127	case 2:
ae56b4f6	128	bits = 0x01;
1d203181 STA	129	break;
1d203181 STA	130	case 5:
ae56b4f6	131	bits = 0x00;
1d203181 STA	132	break;
1d203181 STA	133	case 10:
ae56b4f6	134	bits = 0x03;
1d203181 STA	135	break;
	136	default:
	137	return FALSE;
	138	}
	139
ae56b4f6 JL	140	bits = bits << (channel ? 1 : 4);
	141	mask = (channel) ? 0x70 : 0x0e;
	142	IOA = (IOA & ~mask) \| (bits & mask);
1d203181 STA	143
	144	return TRUE;
	145	}
	146
297fb13a UH	147	/**
	148	* Each LSB in the nibble of the byte controls the coupling per channel.
	149	*
	150	* Setting PE3 disables AC coupling capacitor on CH0.
	151	* Setting PE0 disables AC coupling capacitor on CH1.
	152	*/
	153	static void set_coupling(BYTE coupling_cfg)
	154	{
	155	if (coupling_cfg & 0x01)
	156	IOE \|= 0x08;
	157	else
	158	IOE &= ~0x08;
	159
	160	if (coupling_cfg & 0x10)
	161	IOE \|= 0x01;
	162	else
	163	IOE &= ~0x01;
	164	}
	165
1d203181 STA	166	static BOOL set_numchannels(BYTE numchannels)
	167	{
	168	if (numchannels == 1 \|\| numchannels == 2) {
	169	BYTE fifocfg = 7 + numchannels;
	170	EP2FIFOCFG = fifocfg;
	171	EP6FIFOCFG = fifocfg;
	172	return TRUE;
	173	}
	174
	175	return FALSE;
	176	}
	177
	178	static void clear_fifo(void)
	179	{
	180	GPIFABORT = 0xff;
	181	SYNCDELAY3;
	182	FIFORESET = 0x80;
	183	SYNCDELAY3;
	184	FIFORESET = 0x82;
	185	SYNCDELAY3;
	186	FIFORESET = 0x86;
	187	SYNCDELAY3;
	188	FIFORESET = 0;
	189	}
	190
	191	static void stop_sampling(void)
	192	{
	193	GPIFABORT = 0xff;
	194	SYNCDELAY3;
	195	INPKTEND = (altiface == 0) ? 6 : 2;
	196	}
	197
	198	static void start_sampling(void)
	199	{
	200	int i;
	201
be6d306d	202	SET_ANALOG_MODE();
59562384	203
1d203181 STA	204	clear_fifo();
	205
	206	for (i = 0; i < 1000; i++);
	207
	208	while (!(GPIFTRIG & 0x80))
	209	;
	210
	211	SYNCDELAY3;
	212	GPIFTCB1 = 0x28;
	213	SYNCDELAY3;
	214	GPIFTCB0 = 0;
	215	GPIFTRIG = (altiface == 0) ? 6 : 4;
	216
65b34f7e UH	217	/* Set green LED, don't clear LED afterwards (ledcounter = 0). */
65b34f7e UH	218	LED_GREEN();
1d203181	219	ledcounter = 0;
1d203181 STA	220	}
	221
	222	static void select_interface(BYTE alt)
	223	{
	224	const BYTE *pPacketSize = \
	225	((USBCS & bmHSM) ? &highspd_dscr : &fullspd_dscr)
	226	+ (9 + (16 * alt) + 9 + 4);
	227
	228	altiface = alt;
	229
	230	if (alt == 0) {
	231	/* Bulk on EP6. */
	232	EP2CFG = 0x00;
	233	EP6CFG = 0xe0;
	234	EP6GPIFFLGSEL = 1;
	235	EP6AUTOINLENL = pPacketSize[0];
	236	EP6AUTOINLENH = pPacketSize[1];
	237	} else {
	238	/* Iso on EP2. */
	239	EP2CFG = 0xd8;
	240	EP6CFG = 0x00;
	241	EP2GPIFFLGSEL = 1;
	242	EP2AUTOINLENL = pPacketSize[0];
	243	EP2AUTOINLENH = pPacketSize[1] & 0x7;
	244	EP2ISOINPKTS = (pPacketSize[1] >> 3) + 1;
	245	}
	246	}
	247
	248	static const struct samplerate_info {
	249	BYTE rate;
	250	BYTE wait0;
	251	BYTE wait1;
	252	BYTE opc0;
	253	BYTE opc1;
	254	BYTE out0;
	255	BYTE ifcfg;
	256	} samplerates[] = {
	257	{ 48, 0x80, 0, 3, 0, 0x00, 0xea },
	258	{ 30, 0x80, 0, 3, 0, 0x00, 0xaa },
e1c5ba21 UH	259	{ 24, 1, 0, 2, 1, OUT0, 0xca },
	260	{ 16, 1, 1, 2, 0, OUT0, 0xca },
	261	{ 12, 2, 1, 2, 0, OUT0, 0xca },
	262	{ 8, 3, 2, 2, 0, OUT0, 0xca },
	263	{ 4, 6, 5, 2, 0, OUT0, 0xca },
	264	{ 2, 12, 11, 2, 0, OUT0, 0xca },
	265	{ 1, 24, 23, 2, 0, OUT0, 0xca },
	266	{ 50, 48, 47, 2, 0, OUT0, 0xca },
	267	{ 20, 120, 119, 2, 0, OUT0, 0xca },
	268	{ 10, 240, 239, 2, 0, OUT0, 0xca },
1d203181 STA	269	};
	270
	271	static BOOL set_samplerate(BYTE rate)
	272	{
	273	BYTE i = 0;
	274
	275	while (samplerates[i].rate != rate) {
	276	i++;
	277	if (i == sizeof(samplerates) / sizeof(samplerates[0]))
	278	return FALSE;
	279	}
	280
	281	IFCONFIG = samplerates[i].ifcfg;
	282
	283	AUTOPTRSETUP = 7;
	284	AUTOPTRH2 = 0xE4; /* 0xE400: GPIF waveform descriptor 0. */
	285	AUTOPTRL2 = 0x00;
	286
	287	/*
	288	* The program for low-speed, e.g. 1 MHz, is:
3968bbfb UH	289	* wait 24, CTLx=0, FIFO
	290	* wait 23, CTLx=1
	291	* jump 0, CTLx=1
1d203181 STA	292	*
1d203181 STA	293	* The program for 24 MHz is:
3968bbfb UH	294	* wait 1, CTLx=0, FIFO
3968bbfb UH	295	* jump 0, CTLx=1
1d203181 STA	296	*
1d203181 STA	297	* The program for 30/48 MHz is:
3968bbfb UH	298	* jump 0, CTLx=Z, FIFO, LOOP
	299	*
	300	* (CTLx is device-dependent, could be e.g. CTL0 or CTL2.)
1d203181 STA	301	*/
	302
	303	/* LENGTH / BRANCH 0-7 */
	304	EXTAUTODAT2 = samplerates[i].wait0;
	305	EXTAUTODAT2 = samplerates[i].wait1;
	306	EXTAUTODAT2 = 1;
	307	EXTAUTODAT2 = 0;
	308	EXTAUTODAT2 = 0;
	309	EXTAUTODAT2 = 0;
	310	EXTAUTODAT2 = 0;
	311	EXTAUTODAT2 = 0;
	312
	313	/* OPCODE 0-7 */
	314	EXTAUTODAT2 = samplerates[i].opc0;
	315	EXTAUTODAT2 = samplerates[i].opc1;
	316	EXTAUTODAT2 = 1; /* DATA=0 DP=1 */
	317	EXTAUTODAT2 = 0;
	318	EXTAUTODAT2 = 0;
	319	EXTAUTODAT2 = 0;
	320	EXTAUTODAT2 = 0;
	321	EXTAUTODAT2 = 0;
	322
	323	/* OUTPUT 0-7 */
	324	EXTAUTODAT2 = samplerates[i].out0;
e1c5ba21 UH	325	EXTAUTODAT2 = OE_CTL;
e1c5ba21 UH	326	EXTAUTODAT2 = OE_CTL;
1d203181 STA	327	EXTAUTODAT2 = 0;
	328	EXTAUTODAT2 = 0;
	329	EXTAUTODAT2 = 0;
	330	EXTAUTODAT2 = 0;
	331	EXTAUTODAT2 = 0;
	332
	333	/* LOGIC FUNCTION 0-7 */
	334	EXTAUTODAT2 = 0;
	335	EXTAUTODAT2 = 0;
	336	EXTAUTODAT2 = 0;
	337	EXTAUTODAT2 = 0;
	338	EXTAUTODAT2 = 0;
	339	EXTAUTODAT2 = 0;
	340	EXTAUTODAT2 = 0;
	341	EXTAUTODAT2 = 0;
	342
	343	for (i = 0; i < 96; i++)
	344	EXTAUTODAT2 = 0;
	345
	346	return TRUE;
	347	}
	348
297fb13a UH	349	static BOOL set_calibration_pulse(BYTE fs)
	350	{
	351	switch (fs) {
	352	case 0: // 100Hz
	353	RCAP2L = -10000 & 0xff;
	354	RCAP2H = (-10000 & 0xff00) >> 8;
	355	return TRUE;
	356	case 1: // 1kHz
	357	RCAP2L = -1000 & 0xff;
	358	RCAP2H = (-1000 & 0xff00) >> 8;
	359	return TRUE;
	360	case 10: // 1kHz
	361	RCAP2L = (BYTE)(-100 & 0xff);
	362	RCAP2H = 0xff;
	363	return TRUE;
	364	case 50: // 50kHz
	365	RCAP2L = (BYTE)(-20 & 0xff);
	366	RCAP2H = 0xff;
	367	return TRUE;
	368	default:
	369	return FALSE;
	370	}
	371	}
	372
1d203181 STA	373	/* Set alt_ifc to the current alt interface for ifc. /
	374	BOOL handle_get_interface(BYTE ifc, BYTE *alt_ifc)
	375	{
	376	(void)ifc;
	377
	378	*alt_ifc = altiface;
	379
	380	return TRUE;
	381	}
	382
	383	/*
	384	* Return TRUE if you set the interface requested.
	385	*
	386	* Note: This function should reconfigure and reset the endpoints
	387	* according to the interface descriptors you provided.
	388	*/
	389	BOOL handle_set_interface(BYTE ifc,BYTE alt_ifc)
	390	{
	391	if (ifc == 0)
	392	select_interface(alt_ifc);
	393
	394	return TRUE;
	395	}
	396
	397	BYTE handle_get_configuration(void)
	398	{
	399	/* We only support configuration 0. */
	400	return 0;
	401	}
	402
	403	BOOL handle_set_configuration(BYTE cfg)
	404	{
	405	/* We only support configuration 0. */
	406	(void)cfg;
	407
	408	return TRUE;
	409	}
	410
	411	BOOL handle_vendorcommand(BYTE cmd)
	412	{
	413	stop_sampling();
	414
65b34f7e UH	415	/* Set red LED, clear after timeout. */
65b34f7e UH	416	LED_RED();
1d203181 STA	417	ledcounter = 1000;
	418
	419	/* Clear EP0BCH/L for each valid command. */
297fb13a	420	if (cmd >= 0xe0 && cmd <= 0xe6) {
1d203181 STA	421	EP0BCH = 0;
	422	EP0BCL = 0;
	423	while (EP0CS & bmEPBUSY);
	424	}
	425
	426	switch (cmd) {
	427	case 0xe0:
	428	case 0xe1:
	429	set_voltage(cmd - 0xe0, EP0BUF[0]);
	430	return TRUE;
	431	case 0xe2:
	432	set_samplerate(EP0BUF[0]);
	433	return TRUE;
	434	case 0xe3:
	435	if (EP0BUF[0] == 1)
	436	start_sampling();
	437	return TRUE;
	438	case 0xe4:
	439	set_numchannels(EP0BUF[0]);
	440	return TRUE;
297fb13a UH	441	case 0xe5:
	442	SET_COUPLING(EP0BUF[0]);
	443	return TRUE;
	444	case 0xe6:
	445	SET_CALIBRATION_PULSE(EP0BUF[0]);
	446	return TRUE;
1d203181 STA	447	}
	448
	449	return FALSE; /* Not handled by handlers. */
	450	}
	451
	452	static void init(void)
	453	{
	454	EP4CFG = 0;
	455	EP8CFG = 0;
	456
be6d306d	457	SET_ANALOG_MODE();
eb52aca4	458
1d203181 STA	459	/* In idle mode tristate all outputs. */
	460	GPIFIDLECTL = 0x00; /* Don't enable CTL0-5 outputs. */
	461	GPIFCTLCFG = 0x80; /* TRICTL=1. CTL0-2: CMOS outputs, tri-statable. */
	462	GPIFWFSELECT = 0x00;
	463	GPIFREADYSTAT = 0x00;
	464
	465	stop_sampling();
	466
	467	set_voltage(0, 1);
	468	set_voltage(1, 1);
	469	set_samplerate(1);
	470	set_numchannels(2);
	471	select_interface(0);
	472	}
	473
	474	static void main(void)
	475	{
	476	/* Save energy. */
	477	SETCPUFREQ(CLK_12M);
	478
	479	init();
	480
	481	/* Set up interrupts. */
	482	USE_USB_INTS();
	483
	484	ENABLE_SUDAV();
	485	ENABLE_USBRESET();
	486	ENABLE_HISPEED();
	487	ENABLE_SUSPEND();
	488	ENABLE_RESUME();
	489
	490	/* Global (8051) interrupt enable. */
	491	EA = 1;
	492
	493	/* Init timer2. */
2c57c00b UH	494	RCAP2L = -TIMER2_VAL & 0xff;
2c57c00b UH	495	RCAP2H = (-TIMER2_VAL & 0xff00) >> 8;
1d203181 STA	496	T2CON = 0;
	497	ET2 = 1;
	498	TR2 = 1;
	499
beaa03fc	500	RENUMERATE_UNCOND();
1d203181	501
4d971e01	502	PORTECFG = 0;
1d203181 STA	503	PORTCCFG = 0;
1d203181 STA	504	PORTACFG = 0;
4d971e01	505	OEE = 0xff;
1d203181	506	OEC = 0xff;
f6eb6aec	507	OEA = 0xff;
1d203181 STA	508
	509	while (TRUE) {
	510	if (dosud) {
	511	dosud = FALSE;
	512	handle_setupdata();
	513	}
	514
	515	if (dosuspend) {
	516	dosuspend = FALSE;
	517	do {
	518	/* Make sure ext wakeups are cleared. */
3968bbfb	519	WAKEUPCS \|= bmWU \| bmWU2;
1d203181 STA	520	SUSPEND = 1;
	521	PCON \|= 1;
	522	__asm
	523	nop
	524	nop
	525	nop
	526	nop
	527	nop
	528	nop
	529	nop
	530	__endasm;
	531	} while (!remote_wakeup_allowed && REMOTE_WAKEUP());
	532
	533	/* Resume (TRM 6.4). */
	534	if (REMOTE_WAKEUP()) {
	535	delay(5);
	536	USBCS \|= bmSIGRESUME;
	537	delay(15);
	538	USBCS &= ~bmSIGRESUME;
	539	}
	540	}
	541	}
	542	}