[sigrok-firmware-fx2lafw.git] / hantek_6022bl.c

/*
 * This file is part of the sigrok-firmware-fx2lafw project.
 *
 * Copyright (C) 2009 Ubixum, Inc.
 * Copyright (C) 2015 Jochen Hoenicke
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2.1 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
 */

#include <fx2macros.h>
#include <fx2ints.h>
#include <autovector.h>
#include <delay.h>
#include <setupdat.h>

#define SET_ANALOG_MODE() PA7 = 1

#define SET_COUPLING(x)

#define SET_CALIBRATION_PULSE(x)

/* Toggle the 1kHz calibration pin, only accurate up to ca. 8MHz. */
#define TOGGLE_CALIBRATION_PIN() PC2 = !PC2

#define LED_CLEAR() PC0 = 1; PC1 = 1;
#define LED_GREEN() PC0 = 1; PC1 = 0;
#define LED_RED()   PC0 = 0; PC1 = 1;

/* CTLx pin index (IFCLK, ADC clock input). */
#define CTL_BIT 0

#define OUT0 ((1 << CTL_BIT) << 4) /* OEx = 1, CTLx = 0 */
#define OE_CTL (((1 << CTL_BIT) << 4) | (1 << CTL_BIT)) /* OEx = CTLx = 1 */

/* Change to support as many interfaces as you need. */
static BYTE altiface = 0;

static volatile WORD ledcounter = 0;

static volatile __bit dosud = FALSE;
static volatile __bit dosuspend = FALSE;

extern __code BYTE highspd_dscr;
extern __code BYTE fullspd_dscr;

void resume_isr(void) __interrupt RESUME_ISR
{
	CLEAR_RESUME();
}

void sudav_isr(void) __interrupt SUDAV_ISR
{
	dosud = TRUE;
	CLEAR_SUDAV();
}

void usbreset_isr(void) __interrupt USBRESET_ISR
{
	handle_hispeed(FALSE);
	CLEAR_USBRESET();
}

void hispeed_isr(void) __interrupt HISPEED_ISR
{
	handle_hispeed(TRUE);
	CLEAR_HISPEED();
}

void suspend_isr(void) __interrupt SUSPEND_ISR
{
	dosuspend = TRUE;
	CLEAR_SUSPEND();
}

void timer2_isr(void) __interrupt TF2_ISR
{
	TOGGLE_CALIBRATION_PIN();

	if (ledcounter && (--ledcounter == 0))
		LED_CLEAR();

	TF2 = 0;
}

/*
 * This sets three bits for each channel, one channel at a time.
 * For channel 0 we want to set bits 1, 2 & 3
 * For channel 1 we want to set bits 4, 5 & 6
 *
 * We convert the input values that are strange due to original
 * firmware code into the value of the three bits as follows:
 *
 * val -> bits
 * 1  -> 010b
 * 2  -> 001b
 * 5  -> 000b
 * 10 -> 011b
 *
 * The third bit is always zero since there are only four outputs connected
 * in the serial selector chip.
 *
 * The multiplication of the converted value by 0x24 sets the relevant bits in
 * both channels and then we mask it out to only affect the channel currently
 * requested.
 */
static BOOL set_voltage(BYTE channel, BYTE val)
{
	BYTE bits, mask;

	switch (val) {
	case 1:
		bits = 0x02;
		break;
	case 2:
		bits = 0x01;
		break;
	case 5:
		bits = 0x00;
		break;
	case 10:
		bits = 0x03;
		break;
	default:
		return FALSE;
	}

	bits = bits << (channel ? 1 : 4);
	mask = (channel) ? 0x70 : 0x0e;
	IOA = (IOA & ~mask) | (bits & mask);

	return TRUE;
}

/**
 * Each LSB in the nibble of the byte controls the coupling per channel.
 *
 * Setting PE3 disables AC coupling capacitor on CH0.
 * Setting PE0 disables AC coupling capacitor on CH1.
 */
static void set_coupling(BYTE coupling_cfg)
{
	if (coupling_cfg & 0x01)
		IOE |= 0x08;
	else
		IOE &= ~0x08;

	if (coupling_cfg & 0x10)
		IOE |= 0x01;
	else
		IOE &= ~0x01;
}

static BOOL set_numchannels(BYTE numchannels)
{
	if (numchannels == 1 || numchannels == 2) {
		BYTE fifocfg = 7 + numchannels;
		EP2FIFOCFG = fifocfg;
		EP6FIFOCFG = fifocfg;
		return TRUE;
	}

	return FALSE;
}

static void clear_fifo(void)
{
	GPIFABORT = 0xff;
	SYNCDELAY3;
	FIFORESET = 0x80;
	SYNCDELAY3;
	FIFORESET = 0x82;
	SYNCDELAY3;
	FIFORESET = 0x86;
	SYNCDELAY3;
	FIFORESET = 0;
}

static void stop_sampling(void)
{
	GPIFABORT = 0xff;
	SYNCDELAY3;
	INPKTEND = (altiface == 0) ? 6 : 2;
}

static void start_sampling(void)
{
	int i;

	SET_ANALOG_MODE();

	clear_fifo();

	for (i = 0; i < 1000; i++);

	while (!(GPIFTRIG & 0x80))
		;

	SYNCDELAY3;
	GPIFTCB1 = 0x28;
	SYNCDELAY3;
	GPIFTCB0 = 0;
	GPIFTRIG = (altiface == 0) ? 6 : 4;

	/* Set green LED, don't clear LED afterwards (ledcounter = 0). */
	LED_GREEN();
	ledcounter = 0;
}

static void select_interface(BYTE alt)
{
	const BYTE *pPacketSize = \
		((USBCS & bmHSM) ? &highspd_dscr : &fullspd_dscr)
		+ (9 + (16 * alt) + 9 + 4);

	altiface = alt;

	if (alt == 0) {
		/* Bulk on EP6. */
		EP2CFG = 0x00;
		EP6CFG = 0xe0;
		EP6GPIFFLGSEL = 1;
		EP6AUTOINLENL = pPacketSize[0];
		EP6AUTOINLENH = pPacketSize[1];
	} else {
		/* Iso on EP2. */
		EP2CFG = 0xd8;
		EP6CFG = 0x00;
		EP2GPIFFLGSEL = 1;
		EP2AUTOINLENL = pPacketSize[0];
		EP2AUTOINLENH = pPacketSize[1] & 0x7;
		EP2ISOINPKTS = (pPacketSize[1] >> 3) + 1;
	}
}

static const struct samplerate_info {
	BYTE rate;
	BYTE wait0;
	BYTE wait1;
	BYTE opc0;
	BYTE opc1;
	BYTE out0;
	BYTE ifcfg;
} samplerates[] = {
	{ 48, 0x80,   0, 3, 0, 0x00, 0xea },
	{ 30, 0x80,   0, 3, 0, 0x00, 0xaa },
	{ 24,    1,   0, 2, 1, OUT0, 0xca },
	{ 16,    1,   1, 2, 0, OUT0, 0xca },
	{ 12,    2,   1, 2, 0, OUT0, 0xca },
	{  8,    3,   2, 2, 0, OUT0, 0xca },
	{  4,    6,   5, 2, 0, OUT0, 0xca },
	{  2,   12,  11, 2, 0, OUT0, 0xca },
	{  1,   24,  23, 2, 0, OUT0, 0xca },
	{ 50,   48,  47, 2, 0, OUT0, 0xca },
	{ 20,  120, 119, 2, 0, OUT0, 0xca },
	{ 10,  240, 239, 2, 0, OUT0, 0xca },
};

static BOOL set_samplerate(BYTE rate)
{
	BYTE i = 0;

	while (samplerates[i].rate != rate) {
		i++;
		if (i == sizeof(samplerates) / sizeof(samplerates[0]))
			return FALSE;
	}

	IFCONFIG = samplerates[i].ifcfg;

	AUTOPTRSETUP = 7;
	AUTOPTRH2 = 0xE4; /* 0xE400: GPIF waveform descriptor 0. */
	AUTOPTRL2 = 0x00;

	/*
	 * The program for low-speed, e.g. 1 MHz, is:
	 * wait 24, CTLx=0, FIFO
	 * wait 23, CTLx=1
	 * jump 0, CTLx=1
	 *
	 * The program for 24 MHz is:
	 * wait 1, CTLx=0, FIFO
	 * jump 0, CTLx=1
	 *
	 * The program for 30/48 MHz is:
	 * jump 0, CTLx=Z, FIFO, LOOP
	 *
	 * (CTLx is device-dependent, could be e.g. CTL0 or CTL2.)
	 */

	/* LENGTH / BRANCH 0-7 */
	EXTAUTODAT2 = samplerates[i].wait0;
	EXTAUTODAT2 = samplerates[i].wait1;
	EXTAUTODAT2 = 1;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;

	/* OPCODE 0-7 */
	EXTAUTODAT2 = samplerates[i].opc0;
	EXTAUTODAT2 = samplerates[i].opc1;
	EXTAUTODAT2 = 1; /* DATA=0 DP=1 */
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;

	/* OUTPUT 0-7 */
	EXTAUTODAT2 = samplerates[i].out0;
	EXTAUTODAT2 = OE_CTL;
	EXTAUTODAT2 = OE_CTL;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;

	/* LOGIC FUNCTION 0-7 */
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;
	EXTAUTODAT2 = 0;

	for (i = 0; i < 96; i++)
		EXTAUTODAT2 = 0;

	return TRUE;
}

static BOOL set_calibration_pulse(BYTE fs)
{
	switch (fs) {
	case 0:		// 100Hz
		RCAP2L = -10000 & 0xff;
		RCAP2H = (-10000 & 0xff00) >> 8;
		return TRUE;
	case 1:		// 1kHz
		RCAP2L = -1000 & 0xff;
		RCAP2H = (-1000 & 0xff00) >> 8;
		return TRUE;
	case 10:	// 1kHz
		RCAP2L = (BYTE)(-100 & 0xff);
		RCAP2H = 0xff;
		return TRUE;
	case 50:	// 50kHz
		RCAP2L = (BYTE)(-20 & 0xff);
		RCAP2H = 0xff;
		return TRUE;
	default:
		return FALSE;
	}
}

/* Set *alt_ifc to the current alt interface for ifc. */
BOOL handle_get_interface(BYTE ifc, BYTE *alt_ifc)
{
	(void)ifc;

	*alt_ifc = altiface;

	return TRUE;
}

/*
 * Return TRUE if you set the interface requested.
 *
 * Note: This function should reconfigure and reset the endpoints
 * according to the interface descriptors you provided.
 */
BOOL handle_set_interface(BYTE ifc,BYTE alt_ifc)
{
	if (ifc == 0)
		select_interface(alt_ifc);

	return TRUE;
}

BYTE handle_get_configuration(void)
{
	/* We only support configuration 0. */
	return 0;
}

BOOL handle_set_configuration(BYTE cfg)
{
	/* We only support configuration 0. */
	(void)cfg;

	return TRUE;
}

BOOL handle_vendorcommand(BYTE cmd)
{
	stop_sampling();

	/* Set red LED, clear after timeout. */
	LED_RED();
	ledcounter = 1000;

	/* Clear EP0BCH/L for each valid command. */
	if (cmd >= 0xe0 && cmd <= 0xe6) {
		EP0BCH = 0;
		EP0BCL = 0;
		while (EP0CS & bmEPBUSY);
	}

	switch (cmd) {
	case 0xe0:
	case 0xe1:
		set_voltage(cmd - 0xe0, EP0BUF[0]);
		return TRUE;
	case 0xe2:
		set_samplerate(EP0BUF[0]);
		return TRUE;
	case 0xe3:
		if (EP0BUF[0] == 1)
			start_sampling();
		return TRUE;
	case 0xe4:
		set_numchannels(EP0BUF[0]);
		return TRUE;
	case 0xe5:
		SET_COUPLING(EP0BUF[0]);
		return TRUE;
	case 0xe6:
		SET_CALIBRATION_PULSE(EP0BUF[0]);
		return TRUE;
	}

	return FALSE; /* Not handled by handlers. */
}

static void init(void)
{
	EP4CFG = 0;
	EP8CFG = 0;

	SET_ANALOG_MODE();

	/* In idle mode tristate all outputs. */
	GPIFIDLECTL = 0x00; /* Don't enable CTL0-5 outputs. */
	GPIFCTLCFG = 0x80; /* TRICTL=1. CTL0-2: CMOS outputs, tri-statable. */
	GPIFWFSELECT = 0x00;
	GPIFREADYSTAT = 0x00;

	stop_sampling();

	set_voltage(0, 1);
	set_voltage(1, 1);
	set_samplerate(1);
	set_numchannels(2);
	select_interface(0);
}

static void main(void)
{
	/* Save energy. */
	SETCPUFREQ(CLK_12M);

	init();

	/* Set up interrupts. */
	USE_USB_INTS();

	ENABLE_SUDAV();
	ENABLE_USBRESET();
	ENABLE_HISPEED(); 
	ENABLE_SUSPEND();
	ENABLE_RESUME();

	/* Global (8051) interrupt enable. */
	EA = 1;

	/* Init timer2. */
	RCAP2L = -500 & 0xff;
	RCAP2H = (-500 & 0xff00) >> 8;
	T2CON = 0;
	ET2 = 1;
	TR2 = 1;

	RENUMERATE_UNCOND();

	PORTECFG = 0;
	PORTCCFG = 0;
	PORTACFG = 0;
	OEE = 0xff;
	OEC = 0xff;
	OEA = 0xff;

	while (TRUE) {
		if (dosud) {
			dosud = FALSE;
			handle_setupdata();
		}

		if (dosuspend) {
			dosuspend = FALSE;
			do {
				/* Make sure ext wakeups are cleared. */
				WAKEUPCS |= bmWU | bmWU2;
				SUSPEND = 1;
				PCON |= 1;
				__asm
				nop
				nop
				nop
				nop
				nop
				nop
				nop
				__endasm;
			} while (!remote_wakeup_allowed && REMOTE_WAKEUP());

			/* Resume (TRM 6.4). */
			if (REMOTE_WAKEUP()) {
				delay(5);
				USBCS |= bmSIGRESUME;
				delay(15);
				USBCS &= ~bmSIGRESUME;
			}
		}
	}
}
Commit	Line	Data
1d203181 STA	1	/*
	2	* This file is part of the sigrok-firmware-fx2lafw project.
	3	*
	4	* Copyright (C) 2009 Ubixum, Inc.
	5	* Copyright (C) 2015 Jochen Hoenicke
	6	*
	7	* This library is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU Lesser General Public
	9	* License as published by the Free Software Foundation; either
	10	* version 2.1 of the License, or (at your option) any later version.
	11	*
	12	* This library is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	15	* Lesser General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU Lesser General Public
	18	* License along with this library; if not, see <http://www.gnu.org/licenses/>.
	19	*/
	20
	21	#include <fx2macros.h>
	22	#include <fx2ints.h>
	23	#include <autovector.h>
	24	#include <delay.h>
	25	#include <setupdat.h>
	26
be6d306d UH	27	#define SET_ANALOG_MODE() PA7 = 1
be6d306d UH	28
297fb13a UH	29	#define SET_COUPLING(x)
	30
	31	#define SET_CALIBRATION_PULSE(x)
	32
e583c3fc UH	33	/* Toggle the 1kHz calibration pin, only accurate up to ca. 8MHz. */
	34	#define TOGGLE_CALIBRATION_PIN() PC2 = !PC2
	35
65b34f7e UH	36	#define LED_CLEAR() PC0 = 1; PC1 = 1;
	37	#define LED_GREEN() PC0 = 1; PC1 = 0;
	38	#define LED_RED() PC0 = 0; PC1 = 1;
	39
e1c5ba21 UH	40	/* CTLx pin index (IFCLK, ADC clock input). */
	41	#define CTL_BIT 0
	42
	43	#define OUT0 ((1 << CTL_BIT) << 4) /* OEx = 1, CTLx = 0 */
	44	#define OE_CTL (((1 << CTL_BIT) << 4) \| (1 << CTL_BIT)) /* OEx = CTLx = 1 */
	45
1d203181 STA	46	/* Change to support as many interfaces as you need. */
	47	static BYTE altiface = 0;
	48
	49	static volatile WORD ledcounter = 0;
	50
	51	static volatile __bit dosud = FALSE;
	52	static volatile __bit dosuspend = FALSE;
	53
	54	extern __code BYTE highspd_dscr;
	55	extern __code BYTE fullspd_dscr;
	56
	57	void resume_isr(void) __interrupt RESUME_ISR
	58	{
	59	CLEAR_RESUME();
	60	}
	61
	62	void sudav_isr(void) __interrupt SUDAV_ISR
	63	{
	64	dosud = TRUE;
	65	CLEAR_SUDAV();
	66	}
	67
	68	void usbreset_isr(void) __interrupt USBRESET_ISR
	69	{
	70	handle_hispeed(FALSE);
	71	CLEAR_USBRESET();
	72	}
	73
	74	void hispeed_isr(void) __interrupt HISPEED_ISR
	75	{
	76	handle_hispeed(TRUE);
	77	CLEAR_HISPEED();
	78	}
	79
	80	void suspend_isr(void) __interrupt SUSPEND_ISR
	81	{
	82	dosuspend = TRUE;
	83	CLEAR_SUSPEND();
	84	}
	85
	86	void timer2_isr(void) __interrupt TF2_ISR
	87	{
e583c3fc	88	TOGGLE_CALIBRATION_PIN();
cbd1bc65	89
65b34f7e UH	90	if (ledcounter && (--ledcounter == 0))
65b34f7e UH	91	LED_CLEAR();
3968bbfb	92
1d203181 STA	93	TF2 = 0;
	94	}
	95
	96	/*
	97	* This sets three bits for each channel, one channel at a time.
ae56b4f6 JL	98	* For channel 0 we want to set bits 1, 2 & 3
ae56b4f6 JL	99	* For channel 1 we want to set bits 4, 5 & 6
1d203181 STA	100	*
	101	* We convert the input values that are strange due to original
	102	* firmware code into the value of the three bits as follows:
	103	*
	104	* val -> bits
	105	* 1 -> 010b
	106	* 2 -> 001b
	107	* 5 -> 000b
	108	* 10 -> 011b
	109	*
	110	* The third bit is always zero since there are only four outputs connected
	111	* in the serial selector chip.
	112	*
	113	* The multiplication of the converted value by 0x24 sets the relevant bits in
	114	* both channels and then we mask it out to only affect the channel currently
	115	* requested.
	116	*/
	117	static BOOL set_voltage(BYTE channel, BYTE val)
	118	{
	119	BYTE bits, mask;
	120
	121	switch (val) {
	122	case 1:
ae56b4f6	123	bits = 0x02;
1d203181 STA	124	break;
1d203181 STA	125	case 2:
ae56b4f6	126	bits = 0x01;
1d203181 STA	127	break;
1d203181 STA	128	case 5:
ae56b4f6	129	bits = 0x00;
1d203181 STA	130	break;
1d203181 STA	131	case 10:
ae56b4f6	132	bits = 0x03;
1d203181 STA	133	break;
	134	default:
	135	return FALSE;
	136	}
	137
ae56b4f6 JL	138	bits = bits << (channel ? 1 : 4);
	139	mask = (channel) ? 0x70 : 0x0e;
	140	IOA = (IOA & ~mask) \| (bits & mask);
1d203181 STA	141
	142	return TRUE;
	143	}
	144
297fb13a UH	145	/**
	146	* Each LSB in the nibble of the byte controls the coupling per channel.
	147	*
	148	* Setting PE3 disables AC coupling capacitor on CH0.
	149	* Setting PE0 disables AC coupling capacitor on CH1.
	150	*/
	151	static void set_coupling(BYTE coupling_cfg)
	152	{
	153	if (coupling_cfg & 0x01)
	154	IOE \|= 0x08;
	155	else
	156	IOE &= ~0x08;
	157
	158	if (coupling_cfg & 0x10)
	159	IOE \|= 0x01;
	160	else
	161	IOE &= ~0x01;
	162	}
	163
1d203181 STA	164	static BOOL set_numchannels(BYTE numchannels)
	165	{
	166	if (numchannels == 1 \|\| numchannels == 2) {
	167	BYTE fifocfg = 7 + numchannels;
	168	EP2FIFOCFG = fifocfg;
	169	EP6FIFOCFG = fifocfg;
	170	return TRUE;
	171	}
	172
	173	return FALSE;
	174	}
	175
	176	static void clear_fifo(void)
	177	{
	178	GPIFABORT = 0xff;
	179	SYNCDELAY3;
	180	FIFORESET = 0x80;
	181	SYNCDELAY3;
	182	FIFORESET = 0x82;
	183	SYNCDELAY3;
	184	FIFORESET = 0x86;
	185	SYNCDELAY3;
	186	FIFORESET = 0;
	187	}
	188
	189	static void stop_sampling(void)
	190	{
	191	GPIFABORT = 0xff;
	192	SYNCDELAY3;
	193	INPKTEND = (altiface == 0) ? 6 : 2;
	194	}
	195
	196	static void start_sampling(void)
	197	{
	198	int i;
	199
be6d306d	200	SET_ANALOG_MODE();
59562384	201
1d203181 STA	202	clear_fifo();
	203
	204	for (i = 0; i < 1000; i++);
	205
	206	while (!(GPIFTRIG & 0x80))
	207	;
	208
	209	SYNCDELAY3;
	210	GPIFTCB1 = 0x28;
	211	SYNCDELAY3;
	212	GPIFTCB0 = 0;
	213	GPIFTRIG = (altiface == 0) ? 6 : 4;
	214
65b34f7e UH	215	/* Set green LED, don't clear LED afterwards (ledcounter = 0). */
65b34f7e UH	216	LED_GREEN();
1d203181	217	ledcounter = 0;
1d203181 STA	218	}
	219
	220	static void select_interface(BYTE alt)
	221	{
	222	const BYTE *pPacketSize = \
	223	((USBCS & bmHSM) ? &highspd_dscr : &fullspd_dscr)
	224	+ (9 + (16 * alt) + 9 + 4);
	225
	226	altiface = alt;
	227
	228	if (alt == 0) {
	229	/* Bulk on EP6. */
	230	EP2CFG = 0x00;
	231	EP6CFG = 0xe0;
	232	EP6GPIFFLGSEL = 1;
	233	EP6AUTOINLENL = pPacketSize[0];
	234	EP6AUTOINLENH = pPacketSize[1];
	235	} else {
	236	/* Iso on EP2. */
	237	EP2CFG = 0xd8;
	238	EP6CFG = 0x00;
	239	EP2GPIFFLGSEL = 1;
	240	EP2AUTOINLENL = pPacketSize[0];
	241	EP2AUTOINLENH = pPacketSize[1] & 0x7;
	242	EP2ISOINPKTS = (pPacketSize[1] >> 3) + 1;
	243	}
	244	}
	245
	246	static const struct samplerate_info {
	247	BYTE rate;
	248	BYTE wait0;
	249	BYTE wait1;
	250	BYTE opc0;
	251	BYTE opc1;
	252	BYTE out0;
	253	BYTE ifcfg;
	254	} samplerates[] = {
	255	{ 48, 0x80, 0, 3, 0, 0x00, 0xea },
	256	{ 30, 0x80, 0, 3, 0, 0x00, 0xaa },
e1c5ba21 UH	257	{ 24, 1, 0, 2, 1, OUT0, 0xca },
	258	{ 16, 1, 1, 2, 0, OUT0, 0xca },
	259	{ 12, 2, 1, 2, 0, OUT0, 0xca },
	260	{ 8, 3, 2, 2, 0, OUT0, 0xca },
	261	{ 4, 6, 5, 2, 0, OUT0, 0xca },
	262	{ 2, 12, 11, 2, 0, OUT0, 0xca },
	263	{ 1, 24, 23, 2, 0, OUT0, 0xca },
	264	{ 50, 48, 47, 2, 0, OUT0, 0xca },
	265	{ 20, 120, 119, 2, 0, OUT0, 0xca },
	266	{ 10, 240, 239, 2, 0, OUT0, 0xca },
1d203181 STA	267	};
	268
	269	static BOOL set_samplerate(BYTE rate)
	270	{
	271	BYTE i = 0;
	272
	273	while (samplerates[i].rate != rate) {
	274	i++;
	275	if (i == sizeof(samplerates) / sizeof(samplerates[0]))
	276	return FALSE;
	277	}
	278
	279	IFCONFIG = samplerates[i].ifcfg;
	280
	281	AUTOPTRSETUP = 7;
	282	AUTOPTRH2 = 0xE4; /* 0xE400: GPIF waveform descriptor 0. */
	283	AUTOPTRL2 = 0x00;
	284
	285	/*
	286	* The program for low-speed, e.g. 1 MHz, is:
3968bbfb UH	287	* wait 24, CTLx=0, FIFO
	288	* wait 23, CTLx=1
	289	* jump 0, CTLx=1
1d203181 STA	290	*
1d203181 STA	291	* The program for 24 MHz is:
3968bbfb UH	292	* wait 1, CTLx=0, FIFO
3968bbfb UH	293	* jump 0, CTLx=1
1d203181 STA	294	*
1d203181 STA	295	* The program for 30/48 MHz is:
3968bbfb UH	296	* jump 0, CTLx=Z, FIFO, LOOP
	297	*
	298	* (CTLx is device-dependent, could be e.g. CTL0 or CTL2.)
1d203181 STA	299	*/
	300
	301	/* LENGTH / BRANCH 0-7 */
	302	EXTAUTODAT2 = samplerates[i].wait0;
	303	EXTAUTODAT2 = samplerates[i].wait1;
	304	EXTAUTODAT2 = 1;
	305	EXTAUTODAT2 = 0;
	306	EXTAUTODAT2 = 0;
	307	EXTAUTODAT2 = 0;
	308	EXTAUTODAT2 = 0;
	309	EXTAUTODAT2 = 0;
	310
	311	/* OPCODE 0-7 */
	312	EXTAUTODAT2 = samplerates[i].opc0;
	313	EXTAUTODAT2 = samplerates[i].opc1;
	314	EXTAUTODAT2 = 1; /* DATA=0 DP=1 */
	315	EXTAUTODAT2 = 0;
	316	EXTAUTODAT2 = 0;
	317	EXTAUTODAT2 = 0;
	318	EXTAUTODAT2 = 0;
	319	EXTAUTODAT2 = 0;
	320
	321	/* OUTPUT 0-7 */
	322	EXTAUTODAT2 = samplerates[i].out0;
e1c5ba21 UH	323	EXTAUTODAT2 = OE_CTL;
e1c5ba21 UH	324	EXTAUTODAT2 = OE_CTL;
1d203181 STA	325	EXTAUTODAT2 = 0;
	326	EXTAUTODAT2 = 0;
	327	EXTAUTODAT2 = 0;
	328	EXTAUTODAT2 = 0;
	329	EXTAUTODAT2 = 0;
	330
	331	/* LOGIC FUNCTION 0-7 */
	332	EXTAUTODAT2 = 0;
	333	EXTAUTODAT2 = 0;
	334	EXTAUTODAT2 = 0;
	335	EXTAUTODAT2 = 0;
	336	EXTAUTODAT2 = 0;
	337	EXTAUTODAT2 = 0;
	338	EXTAUTODAT2 = 0;
	339	EXTAUTODAT2 = 0;
	340
	341	for (i = 0; i < 96; i++)
	342	EXTAUTODAT2 = 0;
	343
	344	return TRUE;
	345	}
	346
297fb13a UH	347	static BOOL set_calibration_pulse(BYTE fs)
	348	{
	349	switch (fs) {
	350	case 0: // 100Hz
	351	RCAP2L = -10000 & 0xff;
	352	RCAP2H = (-10000 & 0xff00) >> 8;
	353	return TRUE;
	354	case 1: // 1kHz
	355	RCAP2L = -1000 & 0xff;
	356	RCAP2H = (-1000 & 0xff00) >> 8;
	357	return TRUE;
	358	case 10: // 1kHz
	359	RCAP2L = (BYTE)(-100 & 0xff);
	360	RCAP2H = 0xff;
	361	return TRUE;
	362	case 50: // 50kHz
	363	RCAP2L = (BYTE)(-20 & 0xff);
	364	RCAP2H = 0xff;
	365	return TRUE;
	366	default:
	367	return FALSE;
	368	}
	369	}
	370
1d203181 STA	371	/* Set alt_ifc to the current alt interface for ifc. /
	372	BOOL handle_get_interface(BYTE ifc, BYTE *alt_ifc)
	373	{
	374	(void)ifc;
	375
	376	*alt_ifc = altiface;
	377
	378	return TRUE;
	379	}
	380
	381	/*
	382	* Return TRUE if you set the interface requested.
	383	*
	384	* Note: This function should reconfigure and reset the endpoints
	385	* according to the interface descriptors you provided.
	386	*/
	387	BOOL handle_set_interface(BYTE ifc,BYTE alt_ifc)
	388	{
	389	if (ifc == 0)
	390	select_interface(alt_ifc);
	391
	392	return TRUE;
	393	}
	394
	395	BYTE handle_get_configuration(void)
	396	{
	397	/* We only support configuration 0. */
	398	return 0;
	399	}
	400
	401	BOOL handle_set_configuration(BYTE cfg)
	402	{
	403	/* We only support configuration 0. */
	404	(void)cfg;
	405
	406	return TRUE;
	407	}
	408
	409	BOOL handle_vendorcommand(BYTE cmd)
	410	{
	411	stop_sampling();
	412
65b34f7e UH	413	/* Set red LED, clear after timeout. */
65b34f7e UH	414	LED_RED();
1d203181 STA	415	ledcounter = 1000;
	416
	417	/* Clear EP0BCH/L for each valid command. */
297fb13a	418	if (cmd >= 0xe0 && cmd <= 0xe6) {
1d203181 STA	419	EP0BCH = 0;
	420	EP0BCL = 0;
	421	while (EP0CS & bmEPBUSY);
	422	}
	423
	424	switch (cmd) {
	425	case 0xe0:
	426	case 0xe1:
	427	set_voltage(cmd - 0xe0, EP0BUF[0]);
	428	return TRUE;
	429	case 0xe2:
	430	set_samplerate(EP0BUF[0]);
	431	return TRUE;
	432	case 0xe3:
	433	if (EP0BUF[0] == 1)
	434	start_sampling();
	435	return TRUE;
	436	case 0xe4:
	437	set_numchannels(EP0BUF[0]);
	438	return TRUE;
297fb13a UH	439	case 0xe5:
	440	SET_COUPLING(EP0BUF[0]);
	441	return TRUE;
	442	case 0xe6:
	443	SET_CALIBRATION_PULSE(EP0BUF[0]);
	444	return TRUE;
1d203181 STA	445	}
	446
	447	return FALSE; /* Not handled by handlers. */
	448	}
	449
	450	static void init(void)
	451	{
	452	EP4CFG = 0;
	453	EP8CFG = 0;
	454
be6d306d	455	SET_ANALOG_MODE();
eb52aca4	456
1d203181 STA	457	/* In idle mode tristate all outputs. */
	458	GPIFIDLECTL = 0x00; /* Don't enable CTL0-5 outputs. */
	459	GPIFCTLCFG = 0x80; /* TRICTL=1. CTL0-2: CMOS outputs, tri-statable. */
	460	GPIFWFSELECT = 0x00;
	461	GPIFREADYSTAT = 0x00;
	462
	463	stop_sampling();
	464
	465	set_voltage(0, 1);
	466	set_voltage(1, 1);
	467	set_samplerate(1);
	468	set_numchannels(2);
	469	select_interface(0);
	470	}
	471
	472	static void main(void)
	473	{
	474	/* Save energy. */
	475	SETCPUFREQ(CLK_12M);
	476
	477	init();
	478
	479	/* Set up interrupts. */
	480	USE_USB_INTS();
	481
	482	ENABLE_SUDAV();
	483	ENABLE_USBRESET();
	484	ENABLE_HISPEED();
	485	ENABLE_SUSPEND();
	486	ENABLE_RESUME();
	487
	488	/* Global (8051) interrupt enable. */
	489	EA = 1;
	490
	491	/* Init timer2. */
	492	RCAP2L = -500 & 0xff;
	493	RCAP2H = (-500 & 0xff00) >> 8;
	494	T2CON = 0;
	495	ET2 = 1;
	496	TR2 = 1;
	497
beaa03fc	498	RENUMERATE_UNCOND();
1d203181	499
4d971e01	500	PORTECFG = 0;
1d203181 STA	501	PORTCCFG = 0;
1d203181 STA	502	PORTACFG = 0;
4d971e01	503	OEE = 0xff;
1d203181	504	OEC = 0xff;
f6eb6aec	505	OEA = 0xff;
1d203181 STA	506
	507	while (TRUE) {
	508	if (dosud) {
	509	dosud = FALSE;
	510	handle_setupdata();
	511	}
	512
	513	if (dosuspend) {
	514	dosuspend = FALSE;
	515	do {
	516	/* Make sure ext wakeups are cleared. */
3968bbfb	517	WAKEUPCS \|= bmWU \| bmWU2;
1d203181 STA	518	SUSPEND = 1;
	519	PCON \|= 1;
	520	__asm
	521	nop
	522	nop
	523	nop
	524	nop
	525	nop
	526	nop
	527	nop
	528	__endasm;
	529	} while (!remote_wakeup_allowed && REMOTE_WAKEUP());
	530
	531	/* Resume (TRM 6.4). */
	532	if (REMOTE_WAKEUP()) {
	533	delay(5);
	534	USBCS \|= bmSIGRESUME;
	535	delay(15);
	536	USBCS &= ~bmSIGRESUME;
	537	}
	538	}
	539	}
	540	}