[libsigrok.git] / src / hardware / link-mso19 / protocol.c

/*
 * This file is part of the libsigrok project.
 *
 * Copyright (C) 2011 Daniel Ribeiro <drwyrm@gmail.com>
 * Copyright (C) 2012 Renato Caldas <rmsc@fe.up.pt>
 * Copyright (C) 2013 Lior Elazary <lelazary@yahoo.com>
 *
 * This program is free software: you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation, either version 3 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#include <config.h>
#include "protocol.h"

/* serial protocol */
#define mso_trans(a, v) \
	(((v) & 0x3f) | (((v) & 0xc0) << 6) | (((a) & 0xf) << 8) | \
	((~(v) & 0x20) << 1) | ((~(v) & 0x80) << 7))

static const char mso_head[] = { 0x40, 0x4c, 0x44, 0x53, 0x7e };
static const char mso_foot[] = { 0x7e };

SR_PRIV int mso_send_control_message(struct sr_serial_dev_inst *serial,
				     uint16_t payload[], int n)
{
	int i, w, ret, s = n * 2 + sizeof(mso_head) + sizeof(mso_foot);
	char *p, *buf;

	ret = SR_ERR;

	if (serial->fd < 0)
		goto ret;

	buf = g_malloc(s);

	p = buf;
	memcpy(p, mso_head, sizeof(mso_head));
	p += sizeof(mso_head);

	for (i = 0; i < n; i++) {
		*(uint16_t *) p = g_htons(payload[i]);
		p += 2;
	}
	memcpy(p, mso_foot, sizeof(mso_foot));

	w = 0;
	while (w < s) {
		ret = serial_write(serial, buf + w, s - w);
		if (ret < 0) {
			ret = SR_ERR;
			goto free;
		}
		w += ret;
	}
	ret = SR_OK;
free:
	g_free(buf);
ret:
	return ret;
}

SR_PRIV int mso_configure_trigger(const struct sr_dev_inst *sdi)
{
	struct dev_context *devc = sdi->priv;
	uint16_t threshold_value = mso_calc_raw_from_mv(devc);

	threshold_value = 0x153C;
	uint8_t trigger_config = 0;

	if (devc->trigger_slope)
		trigger_config |= 0x04;	//Trigger on falling edge

	switch (devc->trigger_outsrc) {
	case 1:
		trigger_config |= 0x00;	//Trigger pulse output
		break;
	case 2:
		trigger_config |= 0x08;	//PWM DAC from the pattern generator buffer
		break;
	case 3:
		trigger_config |= 0x18;	//White noise
		break;
	}

	switch (devc->trigger_chan) {
	case 0:
		trigger_config |= 0x00;	//DSO level trigger //b00000000
		break;
	case 1:
		trigger_config |= 0x20;	//DSO level trigger & width < trigger_width
		break;
	case 2:
		trigger_config |= 0x40;	//DSO level trigger & width >= trigger_width 
		break;
	case 3:
		trigger_config |= 0x60;	//LA combination trigger
		break;
	}

	//Last bit of trigger config reg 4 needs to be 1 for trigger enable,
	//otherwise the trigger is not enabled
	if (devc->use_trigger)
		trigger_config |= 0x80;

	uint16_t ops[18];
	ops[0] = mso_trans(3, threshold_value & 0xff);
	//The trigger_config also holds the 2 MSB bits from the threshold value
	ops[1] = mso_trans(4, trigger_config | ((threshold_value >> 8) & 0x03));
	ops[2] = mso_trans(5, devc->la_trigger);
	ops[3] = mso_trans(6, devc->la_trigger_mask);
	ops[4] = mso_trans(7, devc->trigger_holdoff[0]);
	ops[5] = mso_trans(8, devc->trigger_holdoff[1]);

	ops[6] = mso_trans(11,
			   devc->dso_trigger_width /
			   SR_HZ_TO_NS(devc->cur_rate));

	/* Select the SPI/I2C trigger config bank */
	ops[7] = mso_trans(REG_CTL2, (devc->ctlbase2 | BITS_CTL2_BANK(2)));
	/* Configure the SPI/I2C protocol trigger */
	ops[8] = mso_trans(REG_PT_WORD(0), devc->protocol_trigger.word[0]);
	ops[9] = mso_trans(REG_PT_WORD(1), devc->protocol_trigger.word[1]);
	ops[10] = mso_trans(REG_PT_WORD(2), devc->protocol_trigger.word[2]);
	ops[11] = mso_trans(REG_PT_WORD(3), devc->protocol_trigger.word[3]);
	ops[12] = mso_trans(REG_PT_MASK(0), devc->protocol_trigger.mask[0]);
	ops[13] = mso_trans(REG_PT_MASK(1), devc->protocol_trigger.mask[1]);
	ops[14] = mso_trans(REG_PT_MASK(2), devc->protocol_trigger.mask[2]);
	ops[15] = mso_trans(REG_PT_MASK(3), devc->protocol_trigger.mask[3]);
	ops[16] = mso_trans(REG_PT_SPIMODE, devc->protocol_trigger.spimode);
	/* Select the default config bank */
	ops[17] = mso_trans(REG_CTL2, devc->ctlbase2);

	return mso_send_control_message(devc->serial, ARRAY_AND_SIZE(ops));
}

SR_PRIV int mso_configure_threshold_level(const struct sr_dev_inst *sdi)
{
	struct dev_context *devc = sdi->priv;

	return mso_dac_out(sdi, la_threshold_map[devc->la_threshold]);
}

SR_PRIV int mso_read_buffer(struct sr_dev_inst *sdi)
{
	uint16_t ops[] = { mso_trans(REG_BUFFER, 0) };
	struct dev_context *devc = sdi->priv;

	sr_dbg("Requesting buffer dump.");
	return mso_send_control_message(devc->serial, ARRAY_AND_SIZE(ops));
}

SR_PRIV int mso_arm(const struct sr_dev_inst *sdi)
{
	struct dev_context *devc = sdi->priv;
	uint16_t ops[] = {
		mso_trans(REG_CTL1, devc->ctlbase1 | BIT_CTL1_RESETFSM),
		mso_trans(REG_CTL1, devc->ctlbase1 | BIT_CTL1_ARM),
		mso_trans(REG_CTL1, devc->ctlbase1),
	};

	sr_dbg("Requesting trigger arm.");
	return mso_send_control_message(devc->serial, ARRAY_AND_SIZE(ops));
}

SR_PRIV int mso_force_capture(struct sr_dev_inst *sdi)
{
	struct dev_context *devc = sdi->priv;
	uint16_t ops[] = {
		mso_trans(REG_CTL1, devc->ctlbase1 | 8),
		mso_trans(REG_CTL1, devc->ctlbase1),
	};

	sr_dbg("Requesting forced capture.");
	return mso_send_control_message(devc->serial, ARRAY_AND_SIZE(ops));
}

SR_PRIV int mso_dac_out(const struct sr_dev_inst *sdi, uint16_t val)
{
	struct dev_context *devc = sdi->priv;
	uint16_t ops[] = {
		mso_trans(REG_DAC1, (val >> 8) & 0xff),
		mso_trans(REG_DAC2, val & 0xff),
		mso_trans(REG_CTL1, devc->ctlbase1 | BIT_CTL1_RESETADC),
	};

	sr_dbg("Setting dac word to 0x%x.", val);
	return mso_send_control_message(devc->serial, ARRAY_AND_SIZE(ops));
}

SR_PRIV uint16_t mso_calc_raw_from_mv(struct dev_context *devc)
{
	return (uint16_t) (0x200 -
			   ((devc->dso_trigger_voltage / devc->dso_probe_attn) /
			    devc->vbit));
}

SR_PRIV int mso_parse_serial(const char *iSerial, const char *iProduct,
			     struct dev_context *devc)
{
	unsigned int u1, u2, u3, u4, u5, u6;

	(void)iProduct;

	/* FIXME: This code is in the original app, but I think its
	 * used only for the GUI */
	/*    if (strstr(iProduct, "REV_02") || strstr(iProduct, "REV_03"))
	   devc->num_sample_rates = 0x16;
	   else
	   devc->num_sample_rates = 0x10; */

	/* parse iSerial */
	if (iSerial[0] != '4' || sscanf(iSerial, "%5u%3u%3u%1u%1u%6u",
					&u1, &u2, &u3, &u4, &u5, &u6) != 6)
		return SR_ERR;
	devc->hwmodel = u4;
	devc->hwrev = u5;
	devc->vbit = u1 / 10000;
	if (devc->vbit == 0)
		devc->vbit = 4.19195;
	devc->dac_offset = u2;
	if (devc->dac_offset == 0)
		devc->dac_offset = 0x1ff;
	devc->offset_range = u3;
	if (devc->offset_range == 0)
		devc->offset_range = 0x17d;

	/*
	 * FIXME: There is more code on the original software to handle
	 * bigger iSerial strings, but as I can't test on my device
	 * I will not implement it yet
	 */

	return SR_OK;
}

SR_PRIV int mso_reset_adc(struct sr_dev_inst *sdi)
{
	struct dev_context *devc = sdi->priv;
	uint16_t ops[2];

	ops[0] = mso_trans(REG_CTL1, (devc->ctlbase1 | BIT_CTL1_RESETADC));
	ops[1] = mso_trans(REG_CTL1, devc->ctlbase1);
	devc->ctlbase1 |= BIT_CTL1_ADC_UNKNOWN4;

	sr_dbg("Requesting ADC reset.");
	return mso_send_control_message(devc->serial, ARRAY_AND_SIZE(ops));
}

SR_PRIV int mso_reset_fsm(struct sr_dev_inst *sdi)
{
	struct dev_context *devc = sdi->priv;
	uint16_t ops[1];

	devc->ctlbase1 |= BIT_CTL1_RESETFSM;
	ops[0] = mso_trans(REG_CTL1, devc->ctlbase1);

	sr_dbg("Requesting ADC reset.");
	return mso_send_control_message(devc->serial, ARRAY_AND_SIZE(ops));
}

SR_PRIV int mso_toggle_led(struct sr_dev_inst *sdi, int state)
{
	struct dev_context *devc = sdi->priv;
	uint16_t ops[1];

	devc->ctlbase1 &= ~BIT_CTL1_LED;
	if (state)
		devc->ctlbase1 |= BIT_CTL1_LED;
	ops[0] = mso_trans(REG_CTL1, devc->ctlbase1);

	sr_dbg("Requesting LED toggle.");
	return mso_send_control_message(devc->serial, ARRAY_AND_SIZE(ops));
}

SR_PRIV void stop_acquisition(const struct sr_dev_inst *sdi)
{
	struct dev_context *devc;

	devc = sdi->priv;
	serial_source_remove(sdi->session, devc->serial);

	std_session_send_df_end(sdi);
}

SR_PRIV int mso_clkrate_out(struct sr_serial_dev_inst *serial, uint16_t val)
{
	uint16_t ops[] = {
		mso_trans(REG_CLKRATE1, (val >> 8) & 0xff),
		mso_trans(REG_CLKRATE2, val & 0xff),
	};

	sr_dbg("Setting clkrate word to 0x%x.", val);
	return mso_send_control_message(serial, ARRAY_AND_SIZE(ops));
}

SR_PRIV int mso_configure_rate(const struct sr_dev_inst *sdi, uint32_t rate)
{
	struct dev_context *devc = sdi->priv;
	unsigned int i;
	int ret = SR_ERR;

	for (i = 0; i < ARRAY_SIZE(rate_map); i++) {
		if (rate_map[i].rate == rate) {
			devc->ctlbase2 = rate_map[i].slowmode;
			ret = mso_clkrate_out(devc->serial, rate_map[i].val);
			if (ret == SR_OK)
				devc->cur_rate = rate;
			return ret;
		}
	}

	if (ret != SR_OK)
		sr_err("Unsupported rate.");

	return ret;
}

SR_PRIV int mso_check_trigger(struct sr_serial_dev_inst *serial, uint8_t *info)
{
	uint16_t ops[] = { mso_trans(REG_TRIGGER, 0) };
	int ret;

	sr_dbg("Requesting trigger state.");
	ret = mso_send_control_message(serial, ARRAY_AND_SIZE(ops));
	if (!info || ret != SR_OK)
		return ret;

	uint8_t buf = 0;
	if (serial_read(serial, &buf, 1) != 1)	/* FIXME: Need timeout */
		ret = SR_ERR;
	if (!info)
		*info = buf;

	sr_dbg("Trigger state is: 0x%x.", *info);
	return ret;
}

SR_PRIV int mso_receive_data(int fd, int revents, void *cb_data)
{
	struct sr_datafeed_packet packet;
	struct sr_datafeed_logic logic;
	struct sr_dev_inst *sdi = cb_data;
	struct dev_context *devc = sdi->priv;
	int i;

	(void)revents;

	uint8_t in[1024];
	size_t s = serial_read(devc->serial, in, sizeof(in));

	if (s <= 0)
		return FALSE;

	/* Check if we triggered, then send a command that we are ready
	 * to read the data */
	if (devc->trigger_state != MSO_TRIGGER_DATAREADY) {
		devc->trigger_state = in[0];
		if (devc->trigger_state == MSO_TRIGGER_DATAREADY) {
			mso_read_buffer(sdi);
			devc->buffer_n = 0;
		} else {
			mso_check_trigger(devc->serial, NULL);
		}
		return TRUE;
	}

	/* the hardware always dumps 1024 samples, 24bits each */
	if (devc->buffer_n < 3072) {
		memcpy(devc->buffer + devc->buffer_n, in, s);
		devc->buffer_n += s;
	}
	if (devc->buffer_n < 3072)
		return TRUE;

	/* do the conversion */
	uint8_t logic_out[1024];
	double analog_out[1024];
	for (i = 0; i < 1024; i++) {
		/* FIXME: Need to do conversion to mV */
		analog_out[i] = (devc->buffer[i * 3] & 0x3f) |
		    ((devc->buffer[i * 3 + 1] & 0xf) << 6);
		(void)analog_out;
		logic_out[i] = ((devc->buffer[i * 3 + 1] & 0x30) >> 4) |
		    ((devc->buffer[i * 3 + 2] & 0x3f) << 2);
	}

	packet.type = SR_DF_LOGIC;
	packet.payload = &logic;
	logic.length = 1024;
	logic.unitsize = 1;
	logic.data = logic_out;
	sr_session_send(sdi, &packet);

	devc->num_samples += 1024;

	if (devc->limit_samples && devc->num_samples >= devc->limit_samples) {
		sr_info("Requested number of samples reached.");
		sdi->driver->dev_acquisition_stop(sdi);
	}

	return TRUE;
}

SR_PRIV int mso_configure_channels(const struct sr_dev_inst *sdi)
{
	struct dev_context *devc;
	struct sr_channel *ch;
	GSList *l;
	char *tc;

	devc = sdi->priv;

	devc->la_trigger_mask = 0xFF;	//the mask for the LA_TRIGGER (bits set to 0 matter, those set to 1 are ignored).
	devc->la_trigger = 0x00;	//The value of the LA byte that generates a trigger event (in that mode).
	devc->dso_trigger_voltage = 3;
	devc->dso_probe_attn = 1;
	devc->trigger_outsrc = 0;
	devc->trigger_chan = 3;	//LA combination trigger
	devc->use_trigger = FALSE;

	for (l = sdi->channels; l; l = l->next) {
		ch = (struct sr_channel *)l->data;
		if (ch->enabled == FALSE)
			continue;

		int channel_bit = 1 << (ch->index);
		if (!(ch->trigger))
			continue;

		devc->use_trigger = TRUE;
		//Configure trigger mask and value.
		for (tc = ch->trigger; *tc; tc++) {
			devc->la_trigger_mask &= ~channel_bit;
			if (*tc == '1')
				devc->la_trigger |= channel_bit;
		}
	}

	return SR_OK;
}
Commit	Line	Data
df92e5cf	1	/*
50985c20	2	* This file is part of the libsigrok project.
df92e5cf	3	*
f48cef78 UH	4	* Copyright (C) 2011 Daniel Ribeiro <drwyrm@gmail.com>
	5	* Copyright (C) 2012 Renato Caldas <rmsc@fe.up.pt>
	6	* Copyright (C) 2013 Lior Elazary <lelazary@yahoo.com>
df92e5cf	7	*
	8	* This program is free software: you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License as published by
	10	* the Free Software Foundation, either version 3 of the License, or
	11	* (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program. If not, see <http://www.gnu.org/licenses/>.
	20	*/
	21
6ec6c43b	22	#include <config.h>
df92e5cf	23	#include "protocol.h"
df92e5cf	24
753d722f UH	25	/* serial protocol */
	26	#define mso_trans(a, v) \
	27	(((v) & 0x3f) \| (((v) & 0xc0) << 6) \| (((a) & 0xf) << 8) \| \
	28	((~(v) & 0x20) << 1) \| ((~(v) & 0x80) << 7))
	29
	30	static const char mso_head[] = { 0x40, 0x4c, 0x44, 0x53, 0x7e };
	31	static const char mso_foot[] = { 0x7e };
	32
4db2aaff	33	SR_PRIV int mso_send_control_message(struct sr_serial_dev_inst *serial,
00b44ccb	34	uint16_t payload[], int n)
4db2aaff	35	{
	36	int i, w, ret, s = n * 2 + sizeof(mso_head) + sizeof(mso_foot);
	37	char p, buf;
	38
	39	ret = SR_ERR;
	40
	41	if (serial->fd < 0)
	42	goto ret;
	43
a95f142e	44	buf = g_malloc(s);
4db2aaff	45
	46	p = buf;
	47	memcpy(p, mso_head, sizeof(mso_head));
	48	p += sizeof(mso_head);
	49
	50	for (i = 0; i < n; i++) {
a24e9d04	51	(uint16_t ) p = g_htons(payload[i]);
4db2aaff	52	p += 2;
	53	}
	54	memcpy(p, mso_foot, sizeof(mso_foot));
	55
	56	w = 0;
	57	while (w < s) {
	58	ret = serial_write(serial, buf + w, s - w);
	59	if (ret < 0) {
	60	ret = SR_ERR;
	61	goto free;
	62	}
	63	w += ret;
	64	}
	65	ret = SR_OK;
	66	free:
	67	g_free(buf);
	68	ret:
	69	return ret;
	70	}
	71
753d722f	72	SR_PRIV int mso_configure_trigger(const struct sr_dev_inst *sdi)
4b719338	73	{
4b719338	74	struct dev_context *devc = sdi->priv;
087a9161	75	uint16_t threshold_value = mso_calc_raw_from_mv(devc);
4b719338	76
00b44ccb UH	77	threshold_value = 0x153C;
00b44ccb UH	78	uint8_t trigger_config = 0;
4b719338	79
00b44ccb UH	80	if (devc->trigger_slope)
00b44ccb UH	81	trigger_config \|= 0x04; //Trigger on falling edge
4b719338	82
	83	switch (devc->trigger_outsrc) {
	84	case 1:
00b44ccb	85	trigger_config \|= 0x00; //Trigger pulse output
4b719338	86	break;
4b719338	87	case 2:
00b44ccb	88	trigger_config \|= 0x08; //PWM DAC from the pattern generator buffer
4b719338	89	break;
4b719338	90	case 3:
00b44ccb	91	trigger_config \|= 0x18; //White noise
4b719338	92	break;
4b719338	93	}
4b719338	94
087a9161	95	switch (devc->trigger_chan) {
00b44ccb UH	96	case 0:
	97	trigger_config \|= 0x00; //DSO level trigger //b00000000
	98	break;
	99	case 1:
	100	trigger_config \|= 0x20; //DSO level trigger & width < trigger_width
	101	break;
	102	case 2:
	103	trigger_config \|= 0x40; //DSO level trigger & width >= trigger_width
	104	break;
	105	case 3:
	106	trigger_config \|= 0x60; //LA combination trigger
	107	break;
	108	}
	109
	110	//Last bit of trigger config reg 4 needs to be 1 for trigger enable,
	111	//otherwise the trigger is not enabled
	112	if (devc->use_trigger)
	113	trigger_config \|= 0x80;
087a9161	114
	115	uint16_t ops[18];
	116	ops[0] = mso_trans(3, threshold_value & 0xff);
00b44ccb	117	//The trigger_config also holds the 2 MSB bits from the threshold value
5952553f	118	ops[1] = mso_trans(4, trigger_config \| ((threshold_value >> 8) & 0x03));
087a9161	119	ops[2] = mso_trans(5, devc->la_trigger);
	120	ops[3] = mso_trans(6, devc->la_trigger_mask);
	121	ops[4] = mso_trans(7, devc->trigger_holdoff[0]);
	122	ops[5] = mso_trans(8, devc->trigger_holdoff[1]);
	123
	124	ops[6] = mso_trans(11,
00b44ccb UH	125	devc->dso_trigger_width /
00b44ccb UH	126	SR_HZ_TO_NS(devc->cur_rate));
4b719338	127
4b719338	128	/* Select the SPI/I2C trigger config bank */
087a9161	129	ops[7] = mso_trans(REG_CTL2, (devc->ctlbase2 \| BITS_CTL2_BANK(2)));
4b719338	130	/* Configure the SPI/I2C protocol trigger */
087a9161	131	ops[8] = mso_trans(REG_PT_WORD(0), devc->protocol_trigger.word[0]);
	132	ops[9] = mso_trans(REG_PT_WORD(1), devc->protocol_trigger.word[1]);
	133	ops[10] = mso_trans(REG_PT_WORD(2), devc->protocol_trigger.word[2]);
	134	ops[11] = mso_trans(REG_PT_WORD(3), devc->protocol_trigger.word[3]);
	135	ops[12] = mso_trans(REG_PT_MASK(0), devc->protocol_trigger.mask[0]);
	136	ops[13] = mso_trans(REG_PT_MASK(1), devc->protocol_trigger.mask[1]);
	137	ops[14] = mso_trans(REG_PT_MASK(2), devc->protocol_trigger.mask[2]);
	138	ops[15] = mso_trans(REG_PT_MASK(3), devc->protocol_trigger.mask[3]);
	139	ops[16] = mso_trans(REG_PT_SPIMODE, devc->protocol_trigger.spimode);
4b719338	140	/* Select the default config bank */
087a9161	141	ops[17] = mso_trans(REG_CTL2, devc->ctlbase2);
4b719338	142
4db2aaff	143	return mso_send_control_message(devc->serial, ARRAY_AND_SIZE(ops));
4b719338	144	}
4b719338	145
753d722f	146	SR_PRIV int mso_configure_threshold_level(const struct sr_dev_inst *sdi)
4b719338	147	{
	148	struct dev_context *devc = sdi->priv;
	149
	150	return mso_dac_out(sdi, la_threshold_map[devc->la_threshold]);
	151	}
	152
	153	SR_PRIV int mso_read_buffer(struct sr_dev_inst *sdi)
	154	{
	155	uint16_t ops[] = { mso_trans(REG_BUFFER, 0) };
	156	struct dev_context *devc = sdi->priv;
	157
	158	sr_dbg("Requesting buffer dump.");
	159	return mso_send_control_message(devc->serial, ARRAY_AND_SIZE(ops));
	160	}
	161
753d722f	162	SR_PRIV int mso_arm(const struct sr_dev_inst *sdi)
4b719338	163	{
	164	struct dev_context *devc = sdi->priv;
	165	uint16_t ops[] = {
	166	mso_trans(REG_CTL1, devc->ctlbase1 \| BIT_CTL1_RESETFSM),
	167	mso_trans(REG_CTL1, devc->ctlbase1 \| BIT_CTL1_ARM),
	168	mso_trans(REG_CTL1, devc->ctlbase1),
	169	};
	170
	171	sr_dbg("Requesting trigger arm.");
	172	return mso_send_control_message(devc->serial, ARRAY_AND_SIZE(ops));
	173	}
	174
	175	SR_PRIV int mso_force_capture(struct sr_dev_inst *sdi)
	176	{
	177	struct dev_context *devc = sdi->priv;
	178	uint16_t ops[] = {
	179	mso_trans(REG_CTL1, devc->ctlbase1 \| 8),
	180	mso_trans(REG_CTL1, devc->ctlbase1),
	181	};
	182
	183	sr_dbg("Requesting forced capture.");
	184	return mso_send_control_message(devc->serial, ARRAY_AND_SIZE(ops));
	185	}
	186
753d722f	187	SR_PRIV int mso_dac_out(const struct sr_dev_inst *sdi, uint16_t val)
4b719338	188	{
	189	struct dev_context *devc = sdi->priv;
	190	uint16_t ops[] = {
	191	mso_trans(REG_DAC1, (val >> 8) & 0xff),
	192	mso_trans(REG_DAC2, val & 0xff),
	193	mso_trans(REG_CTL1, devc->ctlbase1 \| BIT_CTL1_RESETADC),
	194	};
	195
	196	sr_dbg("Setting dac word to 0x%x.", val);
	197	return mso_send_control_message(devc->serial, ARRAY_AND_SIZE(ops));
	198	}
	199
c442ffda	200	SR_PRIV uint16_t mso_calc_raw_from_mv(struct dev_context *devc)
4b719338	201	{
4b719338	202	return (uint16_t) (0x200 -
00b44ccb UH	203	((devc->dso_trigger_voltage / devc->dso_probe_attn) /
00b44ccb UH	204	devc->vbit));
4b719338	205	}
4b719338	206
df92e5cf	207	SR_PRIV int mso_parse_serial(const char iSerial, const char iProduct,
00b44ccb	208	struct dev_context *devc)
df92e5cf	209	{
	210	unsigned int u1, u2, u3, u4, u5, u6;
	211
31e53772 UH	212	(void)iProduct;
31e53772 UH	213
00b44ccb UH	214	/* FIXME: This code is in the original app, but I think its
	215	* used only for the GUI */
	216	/* if (strstr(iProduct, "REV_02") \|\| strstr(iProduct, "REV_03"))
	217	devc->num_sample_rates = 0x16;
	218	else
	219	devc->num_sample_rates = 0x10; */
df92e5cf	220
	221	/* parse iSerial */
	222	if (iSerial[0] != '4' \|\| sscanf(iSerial, "%5u%3u%3u%1u%1u%6u",
00b44ccb	223	&u1, &u2, &u3, &u4, &u5, &u6) != 6)
df92e5cf	224	return SR_ERR;
	225	devc->hwmodel = u4;
	226	devc->hwrev = u5;
df92e5cf	227	devc->vbit = u1 / 10000;
	228	if (devc->vbit == 0)
	229	devc->vbit = 4.19195;
	230	devc->dac_offset = u2;
	231	if (devc->dac_offset == 0)
	232	devc->dac_offset = 0x1ff;
	233	devc->offset_range = u3;
	234	if (devc->offset_range == 0)
	235	devc->offset_range = 0x17d;
	236
	237	/*
	238	* FIXME: There is more code on the original software to handle
	239	* bigger iSerial strings, but as I can't test on my device
	240	* I will not implement it yet
	241	*/
	242
	243	return SR_OK;
	244	}
	245
4db2aaff	246	SR_PRIV int mso_reset_adc(struct sr_dev_inst *sdi)
df92e5cf	247	{
4db2aaff	248	struct dev_context *devc = sdi->priv;
4db2aaff	249	uint16_t ops[2];
df92e5cf	250
4db2aaff	251	ops[0] = mso_trans(REG_CTL1, (devc->ctlbase1 \| BIT_CTL1_RESETADC));
	252	ops[1] = mso_trans(REG_CTL1, devc->ctlbase1);
	253	devc->ctlbase1 \|= BIT_CTL1_ADC_UNKNOWN4;
df92e5cf	254
4db2aaff	255	sr_dbg("Requesting ADC reset.");
	256	return mso_send_control_message(devc->serial, ARRAY_AND_SIZE(ops));
	257	}
df92e5cf	258
4db2aaff	259	SR_PRIV int mso_reset_fsm(struct sr_dev_inst *sdi)
	260	{
	261	struct dev_context *devc = sdi->priv;
	262	uint16_t ops[1];
df92e5cf	263
4db2aaff	264	devc->ctlbase1 \|= BIT_CTL1_RESETFSM;
4db2aaff	265	ops[0] = mso_trans(REG_CTL1, devc->ctlbase1);
df92e5cf	266
4db2aaff	267	sr_dbg("Requesting ADC reset.");
4db2aaff	268	return mso_send_control_message(devc->serial, ARRAY_AND_SIZE(ops));
df92e5cf	269	}
df92e5cf	270
4db2aaff	271	SR_PRIV int mso_toggle_led(struct sr_dev_inst *sdi, int state)
df92e5cf	272	{
df92e5cf	273	struct dev_context *devc = sdi->priv;
4db2aaff	274	uint16_t ops[1];
df92e5cf	275
4db2aaff	276	devc->ctlbase1 &= ~BIT_CTL1_LED;
	277	if (state)
	278	devc->ctlbase1 \|= BIT_CTL1_LED;
	279	ops[0] = mso_trans(REG_CTL1, devc->ctlbase1);
df92e5cf	280
4db2aaff	281	sr_dbg("Requesting LED toggle.");
df92e5cf	282	return mso_send_control_message(devc->serial, ARRAY_AND_SIZE(ops));
	283	}
	284
	285	SR_PRIV void stop_acquisition(const struct sr_dev_inst *sdi)
	286	{
df92e5cf	287	struct dev_context *devc;
	288
	289	devc = sdi->priv;
102f1239	290	serial_source_remove(sdi->session, devc->serial);
df92e5cf	291
bee2b016	292	std_session_send_df_end(sdi);
df92e5cf	293	}
	294
	295	SR_PRIV int mso_clkrate_out(struct sr_serial_dev_inst *serial, uint16_t val)
	296	{
	297	uint16_t ops[] = {
	298	mso_trans(REG_CLKRATE1, (val >> 8) & 0xff),
	299	mso_trans(REG_CLKRATE2, val & 0xff),
	300	};
	301
	302	sr_dbg("Setting clkrate word to 0x%x.", val);
	303	return mso_send_control_message(serial, ARRAY_AND_SIZE(ops));
	304	}
	305
753d722f	306	SR_PRIV int mso_configure_rate(const struct sr_dev_inst *sdi, uint32_t rate)
df92e5cf	307	{
	308	struct dev_context *devc = sdi->priv;
	309	unsigned int i;
	310	int ret = SR_ERR;
	311
	312	for (i = 0; i < ARRAY_SIZE(rate_map); i++) {
	313	if (rate_map[i].rate == rate) {
	314	devc->ctlbase2 = rate_map[i].slowmode;
4b719338	315	ret = mso_clkrate_out(devc->serial, rate_map[i].val);
df92e5cf	316	if (ret == SR_OK)
	317	devc->cur_rate = rate;
	318	return ret;
	319	}
	320	}
4db2aaff	321
00b44ccb	322	if (ret != SR_OK)
4db2aaff	323	sr_err("Unsupported rate.");
4db2aaff	324
df92e5cf	325	return ret;
	326	}
	327
365f04d6	328	SR_PRIV int mso_check_trigger(struct sr_serial_dev_inst serial, uint8_t info)
df92e5cf	329	{
	330	uint16_t ops[] = { mso_trans(REG_TRIGGER, 0) };
	331	int ret;
	332
	333	sr_dbg("Requesting trigger state.");
	334	ret = mso_send_control_message(serial, ARRAY_AND_SIZE(ops));
98fec29e	335	if (!info \|\| ret != SR_OK)
df92e5cf	336	return ret;
df92e5cf	337
00b44ccb UH	338	uint8_t buf = 0;
00b44ccb UH	339	if (serial_read(serial, &buf, 1) != 1) /* FIXME: Need timeout */
df92e5cf	340	ret = SR_ERR;
365f04d6	341	if (!info)
365f04d6	342	*info = buf;
df92e5cf	343
	344	sr_dbg("Trigger state is: 0x%x.", *info);
	345	return ret;
	346	}
	347
	348	SR_PRIV int mso_receive_data(int fd, int revents, void *cb_data)
	349	{
df92e5cf	350	struct sr_datafeed_packet packet;
df92e5cf	351	struct sr_datafeed_logic logic;
f53ff643 LPC	352	struct sr_dev_inst *sdi = cb_data;
f53ff643 LPC	353	struct dev_context *devc = sdi->priv;
4db2aaff	354	int i;
df92e5cf	355
df92e5cf	356	(void)revents;
	357
	358	uint8_t in[1024];
	359	size_t s = serial_read(devc->serial, in, sizeof(in));
5a24e89c	360
df92e5cf	361	if (s <= 0)
df92e5cf	362	return FALSE;
00b44ccb UH	363
	364	/* Check if we triggered, then send a command that we are ready
	365	* to read the data */
	366	if (devc->trigger_state != MSO_TRIGGER_DATAREADY) {
	367	devc->trigger_state = in[0];
	368	if (devc->trigger_state == MSO_TRIGGER_DATAREADY) {
	369	mso_read_buffer(sdi);
	370	devc->buffer_n = 0;
	371	} else {
	372	mso_check_trigger(devc->serial, NULL);
	373	}
	374	return TRUE;
	375	}
df92e5cf	376
	377	/* the hardware always dumps 1024 samples, 24bits each */
	378	if (devc->buffer_n < 3072) {
	379	memcpy(devc->buffer + devc->buffer_n, in, s);
	380	devc->buffer_n += s;
	381	}
	382	if (devc->buffer_n < 3072)
5a24e89c	383	return TRUE;
df92e5cf	384
	385	/* do the conversion */
	386	uint8_t logic_out[1024];
	387	double analog_out[1024];
	388	for (i = 0; i < 1024; i++) {
	389	/* FIXME: Need to do conversion to mV */
	390	analog_out[i] = (devc->buffer[i * 3] & 0x3f) \|
00b44ccb	391	((devc->buffer[i * 3 + 1] & 0xf) << 6);
ff08a52a	392	(void)analog_out;
df92e5cf	393	logic_out[i] = ((devc->buffer[i * 3 + 1] & 0x30) >> 4) \|
00b44ccb	394	((devc->buffer[i * 3 + 2] & 0x3f) << 2);
df92e5cf	395	}
	396
	397	packet.type = SR_DF_LOGIC;
	398	packet.payload = &logic;
	399	logic.length = 1024;
	400	logic.unitsize = 1;
	401	logic.data = logic_out;
695dc859	402	sr_session_send(sdi, &packet);
df92e5cf	403
00b44ccb	404	devc->num_samples += 1024;
eb913174	405
00b44ccb UH	406	if (devc->limit_samples && devc->num_samples >= devc->limit_samples) {
00b44ccb UH	407	sr_info("Requested number of samples reached.");
6525d819	408	sdi->driver->dev_acquisition_stop(sdi);
00b44ccb UH	409	}
	410
	411	return TRUE;
df92e5cf	412	}
5a24e89c	413
ba7dd8bb	414	SR_PRIV int mso_configure_channels(const struct sr_dev_inst *sdi)
5a24e89c	415	{
5a24e89c	416	struct dev_context *devc;
ba7dd8bb	417	struct sr_channel *ch;
5a24e89c	418	GSList *l;
5a24e89c	419	char *tc;
5a24e89c	420
5a24e89c	421	devc = sdi->priv;
5a24e89c	422
00b44ccb UH	423	devc->la_trigger_mask = 0xFF; //the mask for the LA_TRIGGER (bits set to 0 matter, those set to 1 are ignored).
	424	devc->la_trigger = 0x00; //The value of the LA byte that generates a trigger event (in that mode).
	425	devc->dso_trigger_voltage = 3;
	426	devc->dso_probe_attn = 1;
	427	devc->trigger_outsrc = 0;
	428	devc->trigger_chan = 3; //LA combination trigger
	429	devc->use_trigger = FALSE;
087a9161	430
ba7dd8bb UH	431	for (l = sdi->channels; l; l = l->next) {
	432	ch = (struct sr_channel *)l->data;
	433	if (ch->enabled == FALSE)
5a24e89c	434	continue;
5a24e89c	435
ba7dd8bb UH	436	int channel_bit = 1 << (ch->index);
ba7dd8bb UH	437	if (!(ch->trigger))
5a24e89c	438	continue;
5a24e89c	439
00b44ccb	440	devc->use_trigger = TRUE;
5a24e89c	441	//Configure trigger mask and value.
ba7dd8bb UH	442	for (tc = ch->trigger; *tc; tc++) {
ba7dd8bb UH	443	devc->la_trigger_mask &= ~channel_bit;
00b44ccb	444	if (*tc == '1')
ba7dd8bb	445	devc->la_trigger \|= channel_bit;
00b44ccb UH	446	}
00b44ccb UH	447	}
5a24e89c	448
5a24e89c	449	return SR_OK;
5a24e89c	450	}