[libsigrok.git] / hardware / link-mso19 / protocol.c

/*
 * This file is part of the sigrok project.
 *
 * Copyright (C) 2011 Daniel Ribeiro <drwyrm@gmail.com>
 * Copyright (C) 2012 Renato Caldas <rmsc@fe.up.pt>
 * Copyright (C) 2013 Lior Elazary <lelazary@yahoo.com>
 *
 * This program is free software: you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation, either version 3 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#include "protocol.h"
#include <arpa/inet.h>

/* serial protocol */
#define mso_trans(a, v) \
	(((v) & 0x3f) | (((v) & 0xc0) << 6) | (((a) & 0xf) << 8) | \
	((~(v) & 0x20) << 1) | ((~(v) & 0x80) << 7))

static const char mso_head[] = { 0x40, 0x4c, 0x44, 0x53, 0x7e };
static const char mso_foot[] = { 0x7e };

extern SR_PRIV struct sr_dev_driver link_mso19_driver_info;
static struct sr_dev_driver *di = &link_mso19_driver_info;

SR_PRIV int mso_send_control_message(struct sr_serial_dev_inst *serial,
				     uint16_t payload[], int n)
{
	int i, w, ret, s = n * 2 + sizeof(mso_head) + sizeof(mso_foot);
	char *p, *buf;

	ret = SR_ERR;

	if (serial->fd < 0)
		goto ret;

	if (!(buf = g_try_malloc(s))) {
		sr_err("Failed to malloc message buffer.");
		ret = SR_ERR_MALLOC;
		goto ret;
	}

	p = buf;
	memcpy(p, mso_head, sizeof(mso_head));
	p += sizeof(mso_head);

	for (i = 0; i < n; i++) {
		*(uint16_t *) p = htons(payload[i]);
		p += 2;
	}
	memcpy(p, mso_foot, sizeof(mso_foot));

	w = 0;
	while (w < s) {
		ret = serial_write(serial, buf + w, s - w);
		if (ret < 0) {
			ret = SR_ERR;
			goto free;
		}
		w += ret;
	}
	ret = SR_OK;
free:
	g_free(buf);
ret:
	return ret;
}

SR_PRIV int mso_configure_trigger(const struct sr_dev_inst *sdi)
{
	struct dev_context *devc = sdi->priv;
	uint16_t threshold_value = mso_calc_raw_from_mv(devc);

	threshold_value = 0x153C;
	uint8_t trigger_config = 0;

	if (devc->trigger_slope)
		trigger_config |= 0x04;	//Trigger on falling edge

	switch (devc->trigger_outsrc) {
	case 1:
		trigger_config |= 0x00;	//Trigger pulse output
		break;
	case 2:
		trigger_config |= 0x08;	//PWM DAC from the pattern generator buffer
		break;
	case 3:
		trigger_config |= 0x18;	//White noise
		break;
	}

	switch (devc->trigger_chan) {
	case 0:
		trigger_config |= 0x00;	//DSO level trigger //b00000000
		break;
	case 1:
		trigger_config |= 0x20;	//DSO level trigger & width < trigger_width
		break;
	case 2:
		trigger_config |= 0x40;	//DSO level trigger & width >= trigger_width 
		break;
	case 3:
		trigger_config |= 0x60;	//LA combination trigger
		break;
	}

	//Last bit of trigger config reg 4 needs to be 1 for trigger enable,
	//otherwise the trigger is not enabled
	if (devc->use_trigger)
		trigger_config |= 0x80;

	uint16_t ops[18];
	ops[0] = mso_trans(3, threshold_value & 0xff);
	//The trigger_config also holds the 2 MSB bits from the threshold value
	ops[1] = mso_trans(4, trigger_config | (threshold_value >> 8) & 0x03);
	ops[2] = mso_trans(5, devc->la_trigger);
	ops[3] = mso_trans(6, devc->la_trigger_mask);
	ops[4] = mso_trans(7, devc->trigger_holdoff[0]);
	ops[5] = mso_trans(8, devc->trigger_holdoff[1]);

	ops[6] = mso_trans(11,
			   devc->dso_trigger_width /
			   SR_HZ_TO_NS(devc->cur_rate));

	/* Select the SPI/I2C trigger config bank */
	ops[7] = mso_trans(REG_CTL2, (devc->ctlbase2 | BITS_CTL2_BANK(2)));
	/* Configure the SPI/I2C protocol trigger */
	ops[8] = mso_trans(REG_PT_WORD(0), devc->protocol_trigger.word[0]);
	ops[9] = mso_trans(REG_PT_WORD(1), devc->protocol_trigger.word[1]);
	ops[10] = mso_trans(REG_PT_WORD(2), devc->protocol_trigger.word[2]);
	ops[11] = mso_trans(REG_PT_WORD(3), devc->protocol_trigger.word[3]);
	ops[12] = mso_trans(REG_PT_MASK(0), devc->protocol_trigger.mask[0]);
	ops[13] = mso_trans(REG_PT_MASK(1), devc->protocol_trigger.mask[1]);
	ops[14] = mso_trans(REG_PT_MASK(2), devc->protocol_trigger.mask[2]);
	ops[15] = mso_trans(REG_PT_MASK(3), devc->protocol_trigger.mask[3]);
	ops[16] = mso_trans(REG_PT_SPIMODE, devc->protocol_trigger.spimode);
	/* Select the default config bank */
	ops[17] = mso_trans(REG_CTL2, devc->ctlbase2);

	return mso_send_control_message(devc->serial, ARRAY_AND_SIZE(ops));
}

SR_PRIV int mso_configure_threshold_level(const struct sr_dev_inst *sdi)
{
	struct dev_context *devc = sdi->priv;

	return mso_dac_out(sdi, la_threshold_map[devc->la_threshold]);
}

SR_PRIV int mso_read_buffer(struct sr_dev_inst *sdi)
{
	uint16_t ops[] = { mso_trans(REG_BUFFER, 0) };
	struct dev_context *devc = sdi->priv;

	sr_dbg("Requesting buffer dump.");
	return mso_send_control_message(devc->serial, ARRAY_AND_SIZE(ops));
}

SR_PRIV int mso_arm(const struct sr_dev_inst *sdi)
{
	struct dev_context *devc = sdi->priv;
	uint16_t ops[] = {
		mso_trans(REG_CTL1, devc->ctlbase1 | BIT_CTL1_RESETFSM),
		mso_trans(REG_CTL1, devc->ctlbase1 | BIT_CTL1_ARM),
		mso_trans(REG_CTL1, devc->ctlbase1),
	};

	sr_dbg("Requesting trigger arm.");
	return mso_send_control_message(devc->serial, ARRAY_AND_SIZE(ops));
}

SR_PRIV int mso_force_capture(struct sr_dev_inst *sdi)
{
	struct dev_context *devc = sdi->priv;
	uint16_t ops[] = {
		mso_trans(REG_CTL1, devc->ctlbase1 | 8),
		mso_trans(REG_CTL1, devc->ctlbase1),
	};

	sr_dbg("Requesting forced capture.");
	return mso_send_control_message(devc->serial, ARRAY_AND_SIZE(ops));
}

SR_PRIV int mso_dac_out(const struct sr_dev_inst *sdi, uint16_t val)
{
	struct dev_context *devc = sdi->priv;
	uint16_t ops[] = {
		mso_trans(REG_DAC1, (val >> 8) & 0xff),
		mso_trans(REG_DAC2, val & 0xff),
		mso_trans(REG_CTL1, devc->ctlbase1 | BIT_CTL1_RESETADC),
	};

	sr_dbg("Setting dac word to 0x%x.", val);
	return mso_send_control_message(devc->serial, ARRAY_AND_SIZE(ops));
}

SR_PRIV inline uint16_t mso_calc_raw_from_mv(struct dev_context * devc)
{
	return (uint16_t) (0x200 -
			   ((devc->dso_trigger_voltage / devc->dso_probe_attn) /
			    devc->vbit));
}

SR_PRIV int mso_parse_serial(const char *iSerial, const char *iProduct,
			     struct dev_context *devc)
{
	unsigned int u1, u2, u3, u4, u5, u6;

	iProduct = iProduct;
	/* FIXME: This code is in the original app, but I think its
	 * used only for the GUI */
	/*    if (strstr(iProduct, "REV_02") || strstr(iProduct, "REV_03"))
	   devc->num_sample_rates = 0x16;
	   else
	   devc->num_sample_rates = 0x10; */

	/* parse iSerial */
	if (iSerial[0] != '4' || sscanf(iSerial, "%5u%3u%3u%1u%1u%6u",
					&u1, &u2, &u3, &u4, &u5, &u6) != 6)
		return SR_ERR;
	devc->hwmodel = u4;
	devc->hwrev = u5;
	devc->vbit = u1 / 10000;
	if (devc->vbit == 0)
		devc->vbit = 4.19195;
	devc->dac_offset = u2;
	if (devc->dac_offset == 0)
		devc->dac_offset = 0x1ff;
	devc->offset_range = u3;
	if (devc->offset_range == 0)
		devc->offset_range = 0x17d;

	/*
	 * FIXME: There is more code on the original software to handle
	 * bigger iSerial strings, but as I can't test on my device
	 * I will not implement it yet
	 */

	return SR_OK;
}

SR_PRIV int mso_reset_adc(struct sr_dev_inst *sdi)
{
	struct dev_context *devc = sdi->priv;
	uint16_t ops[2];

	ops[0] = mso_trans(REG_CTL1, (devc->ctlbase1 | BIT_CTL1_RESETADC));
	ops[1] = mso_trans(REG_CTL1, devc->ctlbase1);
	devc->ctlbase1 |= BIT_CTL1_ADC_UNKNOWN4;

	sr_dbg("Requesting ADC reset.");
	return mso_send_control_message(devc->serial, ARRAY_AND_SIZE(ops));
}

SR_PRIV int mso_reset_fsm(struct sr_dev_inst *sdi)
{
	struct dev_context *devc = sdi->priv;
	uint16_t ops[1];

	devc->ctlbase1 |= BIT_CTL1_RESETFSM;
	ops[0] = mso_trans(REG_CTL1, devc->ctlbase1);

	sr_dbg("Requesting ADC reset.");
	return mso_send_control_message(devc->serial, ARRAY_AND_SIZE(ops));
}

SR_PRIV int mso_toggle_led(struct sr_dev_inst *sdi, int state)
{
	struct dev_context *devc = sdi->priv;
	uint16_t ops[1];

	devc->ctlbase1 &= ~BIT_CTL1_LED;
	if (state)
		devc->ctlbase1 |= BIT_CTL1_LED;
	ops[0] = mso_trans(REG_CTL1, devc->ctlbase1);

	sr_dbg("Requesting LED toggle.");
	return mso_send_control_message(devc->serial, ARRAY_AND_SIZE(ops));
}

SR_PRIV void stop_acquisition(const struct sr_dev_inst *sdi)
{
	struct sr_datafeed_packet packet;
	struct dev_context *devc;

	devc = sdi->priv;
	sr_source_remove(devc->serial->fd);

	/* Terminate session */
	packet.type = SR_DF_END;
	sr_session_send(sdi, &packet);
}

SR_PRIV int mso_clkrate_out(struct sr_serial_dev_inst *serial, uint16_t val)
{
	uint16_t ops[] = {
		mso_trans(REG_CLKRATE1, (val >> 8) & 0xff),
		mso_trans(REG_CLKRATE2, val & 0xff),
	};

	sr_dbg("Setting clkrate word to 0x%x.", val);
	return mso_send_control_message(serial, ARRAY_AND_SIZE(ops));
}

SR_PRIV int mso_configure_rate(const struct sr_dev_inst *sdi, uint32_t rate)
{
	struct dev_context *devc = sdi->priv;
	unsigned int i;
	int ret = SR_ERR;

	for (i = 0; i < ARRAY_SIZE(rate_map); i++) {
		if (rate_map[i].rate == rate) {
			devc->ctlbase2 = rate_map[i].slowmode;
			ret = mso_clkrate_out(devc->serial, rate_map[i].val);
			if (ret == SR_OK)
				devc->cur_rate = rate;
			return ret;
		}
	}

	if (ret != SR_OK)
		sr_err("Unsupported rate.");

	return ret;
}

SR_PRIV int mso_check_trigger(struct sr_serial_dev_inst *serial, uint8_t * info)
{
	uint16_t ops[] = { mso_trans(REG_TRIGGER, 0) };
	int ret;

	sr_dbg("Requesting trigger state.");
	ret = mso_send_control_message(serial, ARRAY_AND_SIZE(ops));
	if (info == NULL || ret != SR_OK)
		return ret;

	uint8_t buf = 0;
	if (serial_read(serial, &buf, 1) != 1)	/* FIXME: Need timeout */
		ret = SR_ERR;
	*info = buf;

	sr_dbg("Trigger state is: 0x%x.", *info);
	return ret;
}

SR_PRIV int mso_receive_data(int fd, int revents, void *cb_data)
{
	struct sr_datafeed_packet packet;
	struct sr_datafeed_logic logic;
	struct sr_dev_inst *sdi;
	GSList *l;
	int i;

	struct drv_context *drvc = di->priv;

	/* Find this device's devc struct by its fd. */
	struct dev_context *devc = NULL;
	for (l = drvc->instances; l; l = l->next) {
		sdi = l->data;
		devc = sdi->priv;
		if (devc->serial->fd == fd)
			break;
		devc = NULL;
	}
	if (!devc)
		/* Shouldn't happen. */
		return TRUE;

	(void)revents;

	uint8_t in[1024];
	size_t s = serial_read(devc->serial, in, sizeof(in));

	if (s <= 0)
		return FALSE;

	/* Check if we triggered, then send a command that we are ready
	 * to read the data */
	if (devc->trigger_state != MSO_TRIGGER_DATAREADY) {
		devc->trigger_state = in[0];
		if (devc->trigger_state == MSO_TRIGGER_DATAREADY) {
			mso_read_buffer(sdi);
			devc->buffer_n = 0;
		} else {
			mso_check_trigger(devc->serial, NULL);
		}
		return TRUE;
	}

	/* the hardware always dumps 1024 samples, 24bits each */
	if (devc->buffer_n < 3072) {
		memcpy(devc->buffer + devc->buffer_n, in, s);
		devc->buffer_n += s;
	}
	if (devc->buffer_n < 3072)
		return TRUE;

	/* do the conversion */
	uint8_t logic_out[1024];
	double analog_out[1024];
	for (i = 0; i < 1024; i++) {
		/* FIXME: Need to do conversion to mV */
		analog_out[i] = (devc->buffer[i * 3] & 0x3f) |
		    ((devc->buffer[i * 3 + 1] & 0xf) << 6);
		logic_out[i] = ((devc->buffer[i * 3 + 1] & 0x30) >> 4) |
		    ((devc->buffer[i * 3 + 2] & 0x3f) << 2);
	}

	packet.type = SR_DF_LOGIC;
	packet.payload = &logic;
	logic.length = 1024;
	logic.unitsize = 1;
	logic.data = logic_out;
	sr_session_send(cb_data, &packet);

	devc->num_samples += 1024;

	if (devc->limit_samples && devc->num_samples >= devc->limit_samples) {
		sr_info("Requested number of samples reached.");
		sdi->driver->dev_acquisition_stop(sdi, cb_data);
	}

	return TRUE;
}

SR_PRIV int mso_configure_probes(const struct sr_dev_inst *sdi)
{
	struct dev_context *devc;
	struct sr_probe *probe;
	GSList *l;
	char *tc;

	devc = sdi->priv;

	devc->la_trigger_mask = 0xFF;	//the mask for the LA_TRIGGER (bits set to 0 matter, those set to 1 are ignored).
	devc->la_trigger = 0x00;	//The value of the LA byte that generates a trigger event (in that mode).
	devc->dso_trigger_voltage = 3;
	devc->dso_probe_attn = 1;
	devc->trigger_outsrc = 0;
	devc->trigger_chan = 3;	//LA combination trigger
	devc->use_trigger = FALSE;

	for (l = sdi->probes; l; l = l->next) {
		probe = (struct sr_probe *)l->data;
		if (probe->enabled == FALSE)
			continue;

		int probe_bit = 1 << (probe->index);
		if (!(probe->trigger))
			continue;

		devc->use_trigger = TRUE;
		//Configure trigger mask and value.
		for (tc = probe->trigger; *tc; tc++) {
			devc->la_trigger_mask &= ~probe_bit;
			if (*tc == '1')
				devc->la_trigger |= probe_bit;
		}
	}

	return SR_OK;
}
Commit	Line	Data
df92e5cf	1	/*
	2	* This file is part of the sigrok project.
	3	*
f48cef78 UH	4	* Copyright (C) 2011 Daniel Ribeiro <drwyrm@gmail.com>
	5	* Copyright (C) 2012 Renato Caldas <rmsc@fe.up.pt>
	6	* Copyright (C) 2013 Lior Elazary <lelazary@yahoo.com>
df92e5cf	7	*
	8	* This program is free software: you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License as published by
	10	* the Free Software Foundation, either version 3 of the License, or
	11	* (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program. If not, see <http://www.gnu.org/licenses/>.
	20	*/
	21
	22	#include "protocol.h"
4db2aaff	23	#include <arpa/inet.h>
df92e5cf	24
753d722f UH	25	/* serial protocol */
	26	#define mso_trans(a, v) \
	27	(((v) & 0x3f) \| (((v) & 0xc0) << 6) \| (((a) & 0xf) << 8) \| \
	28	((~(v) & 0x20) << 1) \| ((~(v) & 0x80) << 7))
	29
	30	static const char mso_head[] = { 0x40, 0x4c, 0x44, 0x53, 0x7e };
	31	static const char mso_foot[] = { 0x7e };
	32
df92e5cf	33	extern SR_PRIV struct sr_dev_driver link_mso19_driver_info;
	34	static struct sr_dev_driver *di = &link_mso19_driver_info;
	35
4db2aaff	36	SR_PRIV int mso_send_control_message(struct sr_serial_dev_inst *serial,
00b44ccb	37	uint16_t payload[], int n)
4db2aaff	38	{
	39	int i, w, ret, s = n * 2 + sizeof(mso_head) + sizeof(mso_foot);
	40	char p, buf;
	41
	42	ret = SR_ERR;
	43
	44	if (serial->fd < 0)
	45	goto ret;
	46
	47	if (!(buf = g_try_malloc(s))) {
	48	sr_err("Failed to malloc message buffer.");
	49	ret = SR_ERR_MALLOC;
	50	goto ret;
	51	}
	52
	53	p = buf;
	54	memcpy(p, mso_head, sizeof(mso_head));
	55	p += sizeof(mso_head);
	56
	57	for (i = 0; i < n; i++) {
	58	(uint16_t ) p = htons(payload[i]);
	59	p += 2;
	60	}
	61	memcpy(p, mso_foot, sizeof(mso_foot));
	62
	63	w = 0;
	64	while (w < s) {
	65	ret = serial_write(serial, buf + w, s - w);
	66	if (ret < 0) {
	67	ret = SR_ERR;
	68	goto free;
	69	}
	70	w += ret;
	71	}
	72	ret = SR_OK;
	73	free:
	74	g_free(buf);
	75	ret:
	76	return ret;
	77	}
	78
753d722f	79	SR_PRIV int mso_configure_trigger(const struct sr_dev_inst *sdi)
4b719338	80	{
4b719338	81	struct dev_context *devc = sdi->priv;
087a9161	82	uint16_t threshold_value = mso_calc_raw_from_mv(devc);
4b719338	83
00b44ccb UH	84	threshold_value = 0x153C;
00b44ccb UH	85	uint8_t trigger_config = 0;
4b719338	86
00b44ccb UH	87	if (devc->trigger_slope)
00b44ccb UH	88	trigger_config \|= 0x04; //Trigger on falling edge
4b719338	89
	90	switch (devc->trigger_outsrc) {
	91	case 1:
00b44ccb	92	trigger_config \|= 0x00; //Trigger pulse output
4b719338	93	break;
4b719338	94	case 2:
00b44ccb	95	trigger_config \|= 0x08; //PWM DAC from the pattern generator buffer
4b719338	96	break;
4b719338	97	case 3:
00b44ccb	98	trigger_config \|= 0x18; //White noise
4b719338	99	break;
4b719338	100	}
4b719338	101
087a9161	102	switch (devc->trigger_chan) {
00b44ccb UH	103	case 0:
	104	trigger_config \|= 0x00; //DSO level trigger //b00000000
	105	break;
	106	case 1:
	107	trigger_config \|= 0x20; //DSO level trigger & width < trigger_width
	108	break;
	109	case 2:
	110	trigger_config \|= 0x40; //DSO level trigger & width >= trigger_width
	111	break;
	112	case 3:
	113	trigger_config \|= 0x60; //LA combination trigger
	114	break;
	115	}
	116
	117	//Last bit of trigger config reg 4 needs to be 1 for trigger enable,
	118	//otherwise the trigger is not enabled
	119	if (devc->use_trigger)
	120	trigger_config \|= 0x80;
087a9161	121
	122	uint16_t ops[18];
	123	ops[0] = mso_trans(3, threshold_value & 0xff);
00b44ccb	124	//The trigger_config also holds the 2 MSB bits from the threshold value
087a9161	125	ops[1] = mso_trans(4, trigger_config \| (threshold_value >> 8) & 0x03);
	126	ops[2] = mso_trans(5, devc->la_trigger);
	127	ops[3] = mso_trans(6, devc->la_trigger_mask);
	128	ops[4] = mso_trans(7, devc->trigger_holdoff[0]);
	129	ops[5] = mso_trans(8, devc->trigger_holdoff[1]);
	130
	131	ops[6] = mso_trans(11,
00b44ccb UH	132	devc->dso_trigger_width /
00b44ccb UH	133	SR_HZ_TO_NS(devc->cur_rate));
4b719338	134
4b719338	135	/* Select the SPI/I2C trigger config bank */
087a9161	136	ops[7] = mso_trans(REG_CTL2, (devc->ctlbase2 \| BITS_CTL2_BANK(2)));
4b719338	137	/* Configure the SPI/I2C protocol trigger */
087a9161	138	ops[8] = mso_trans(REG_PT_WORD(0), devc->protocol_trigger.word[0]);
	139	ops[9] = mso_trans(REG_PT_WORD(1), devc->protocol_trigger.word[1]);
	140	ops[10] = mso_trans(REG_PT_WORD(2), devc->protocol_trigger.word[2]);
	141	ops[11] = mso_trans(REG_PT_WORD(3), devc->protocol_trigger.word[3]);
	142	ops[12] = mso_trans(REG_PT_MASK(0), devc->protocol_trigger.mask[0]);
	143	ops[13] = mso_trans(REG_PT_MASK(1), devc->protocol_trigger.mask[1]);
	144	ops[14] = mso_trans(REG_PT_MASK(2), devc->protocol_trigger.mask[2]);
	145	ops[15] = mso_trans(REG_PT_MASK(3), devc->protocol_trigger.mask[3]);
	146	ops[16] = mso_trans(REG_PT_SPIMODE, devc->protocol_trigger.spimode);
4b719338	147	/* Select the default config bank */
087a9161	148	ops[17] = mso_trans(REG_CTL2, devc->ctlbase2);
4b719338	149
4db2aaff	150	return mso_send_control_message(devc->serial, ARRAY_AND_SIZE(ops));
4b719338	151	}
4b719338	152
753d722f	153	SR_PRIV int mso_configure_threshold_level(const struct sr_dev_inst *sdi)
4b719338	154	{
	155	struct dev_context *devc = sdi->priv;
	156
	157	return mso_dac_out(sdi, la_threshold_map[devc->la_threshold]);
	158	}
	159
	160	SR_PRIV int mso_read_buffer(struct sr_dev_inst *sdi)
	161	{
	162	uint16_t ops[] = { mso_trans(REG_BUFFER, 0) };
	163	struct dev_context *devc = sdi->priv;
	164
	165	sr_dbg("Requesting buffer dump.");
	166	return mso_send_control_message(devc->serial, ARRAY_AND_SIZE(ops));
	167	}
	168
753d722f	169	SR_PRIV int mso_arm(const struct sr_dev_inst *sdi)
4b719338	170	{
	171	struct dev_context *devc = sdi->priv;
	172	uint16_t ops[] = {
	173	mso_trans(REG_CTL1, devc->ctlbase1 \| BIT_CTL1_RESETFSM),
	174	mso_trans(REG_CTL1, devc->ctlbase1 \| BIT_CTL1_ARM),
	175	mso_trans(REG_CTL1, devc->ctlbase1),
	176	};
	177
	178	sr_dbg("Requesting trigger arm.");
	179	return mso_send_control_message(devc->serial, ARRAY_AND_SIZE(ops));
	180	}
	181
	182	SR_PRIV int mso_force_capture(struct sr_dev_inst *sdi)
	183	{
	184	struct dev_context *devc = sdi->priv;
	185	uint16_t ops[] = {
	186	mso_trans(REG_CTL1, devc->ctlbase1 \| 8),
	187	mso_trans(REG_CTL1, devc->ctlbase1),
	188	};
	189
	190	sr_dbg("Requesting forced capture.");
	191	return mso_send_control_message(devc->serial, ARRAY_AND_SIZE(ops));
	192	}
	193
753d722f	194	SR_PRIV int mso_dac_out(const struct sr_dev_inst *sdi, uint16_t val)
4b719338	195	{
	196	struct dev_context *devc = sdi->priv;
	197	uint16_t ops[] = {
	198	mso_trans(REG_DAC1, (val >> 8) & 0xff),
	199	mso_trans(REG_DAC2, val & 0xff),
	200	mso_trans(REG_CTL1, devc->ctlbase1 \| BIT_CTL1_RESETADC),
	201	};
	202
	203	sr_dbg("Setting dac word to 0x%x.", val);
	204	return mso_send_control_message(devc->serial, ARRAY_AND_SIZE(ops));
	205	}
	206
00b44ccb	207	SR_PRIV inline uint16_t mso_calc_raw_from_mv(struct dev_context * devc)
4b719338	208	{
4b719338	209	return (uint16_t) (0x200 -
00b44ccb UH	210	((devc->dso_trigger_voltage / devc->dso_probe_attn) /
00b44ccb UH	211	devc->vbit));
4b719338	212	}
4b719338	213
df92e5cf	214	SR_PRIV int mso_parse_serial(const char iSerial, const char iProduct,
00b44ccb	215	struct dev_context *devc)
df92e5cf	216	{
	217	unsigned int u1, u2, u3, u4, u5, u6;
	218
00b44ccb UH	219	iProduct = iProduct;
	220	/* FIXME: This code is in the original app, but I think its
	221	* used only for the GUI */
	222	/* if (strstr(iProduct, "REV_02") \|\| strstr(iProduct, "REV_03"))
	223	devc->num_sample_rates = 0x16;
	224	else
	225	devc->num_sample_rates = 0x10; */
df92e5cf	226
	227	/* parse iSerial */
	228	if (iSerial[0] != '4' \|\| sscanf(iSerial, "%5u%3u%3u%1u%1u%6u",
00b44ccb	229	&u1, &u2, &u3, &u4, &u5, &u6) != 6)
df92e5cf	230	return SR_ERR;
	231	devc->hwmodel = u4;
	232	devc->hwrev = u5;
df92e5cf	233	devc->vbit = u1 / 10000;
	234	if (devc->vbit == 0)
	235	devc->vbit = 4.19195;
	236	devc->dac_offset = u2;
	237	if (devc->dac_offset == 0)
	238	devc->dac_offset = 0x1ff;
	239	devc->offset_range = u3;
	240	if (devc->offset_range == 0)
	241	devc->offset_range = 0x17d;
	242
	243	/*
	244	* FIXME: There is more code on the original software to handle
	245	* bigger iSerial strings, but as I can't test on my device
	246	* I will not implement it yet
	247	*/
	248
	249	return SR_OK;
	250	}
	251
4db2aaff	252	SR_PRIV int mso_reset_adc(struct sr_dev_inst *sdi)
df92e5cf	253	{
4db2aaff	254	struct dev_context *devc = sdi->priv;
4db2aaff	255	uint16_t ops[2];
df92e5cf	256
4db2aaff	257	ops[0] = mso_trans(REG_CTL1, (devc->ctlbase1 \| BIT_CTL1_RESETADC));
	258	ops[1] = mso_trans(REG_CTL1, devc->ctlbase1);
	259	devc->ctlbase1 \|= BIT_CTL1_ADC_UNKNOWN4;
df92e5cf	260
4db2aaff	261	sr_dbg("Requesting ADC reset.");
	262	return mso_send_control_message(devc->serial, ARRAY_AND_SIZE(ops));
	263	}
df92e5cf	264
4db2aaff	265	SR_PRIV int mso_reset_fsm(struct sr_dev_inst *sdi)
	266	{
	267	struct dev_context *devc = sdi->priv;
	268	uint16_t ops[1];
df92e5cf	269
4db2aaff	270	devc->ctlbase1 \|= BIT_CTL1_RESETFSM;
4db2aaff	271	ops[0] = mso_trans(REG_CTL1, devc->ctlbase1);
df92e5cf	272
4db2aaff	273	sr_dbg("Requesting ADC reset.");
4db2aaff	274	return mso_send_control_message(devc->serial, ARRAY_AND_SIZE(ops));
df92e5cf	275	}
df92e5cf	276
4db2aaff	277	SR_PRIV int mso_toggle_led(struct sr_dev_inst *sdi, int state)
df92e5cf	278	{
df92e5cf	279	struct dev_context *devc = sdi->priv;
4db2aaff	280	uint16_t ops[1];
df92e5cf	281
4db2aaff	282	devc->ctlbase1 &= ~BIT_CTL1_LED;
	283	if (state)
	284	devc->ctlbase1 \|= BIT_CTL1_LED;
	285	ops[0] = mso_trans(REG_CTL1, devc->ctlbase1);
df92e5cf	286
4db2aaff	287	sr_dbg("Requesting LED toggle.");
df92e5cf	288	return mso_send_control_message(devc->serial, ARRAY_AND_SIZE(ops));
	289	}
	290
	291	SR_PRIV void stop_acquisition(const struct sr_dev_inst *sdi)
	292	{
	293	struct sr_datafeed_packet packet;
	294	struct dev_context *devc;
	295
	296	devc = sdi->priv;
	297	sr_source_remove(devc->serial->fd);
	298
	299	/* Terminate session */
	300	packet.type = SR_DF_END;
	301	sr_session_send(sdi, &packet);
	302	}
	303
	304	SR_PRIV int mso_clkrate_out(struct sr_serial_dev_inst *serial, uint16_t val)
	305	{
	306	uint16_t ops[] = {
	307	mso_trans(REG_CLKRATE1, (val >> 8) & 0xff),
	308	mso_trans(REG_CLKRATE2, val & 0xff),
	309	};
	310
	311	sr_dbg("Setting clkrate word to 0x%x.", val);
	312	return mso_send_control_message(serial, ARRAY_AND_SIZE(ops));
	313	}
	314
753d722f	315	SR_PRIV int mso_configure_rate(const struct sr_dev_inst *sdi, uint32_t rate)
df92e5cf	316	{
	317	struct dev_context *devc = sdi->priv;
	318	unsigned int i;
	319	int ret = SR_ERR;
	320
	321	for (i = 0; i < ARRAY_SIZE(rate_map); i++) {
	322	if (rate_map[i].rate == rate) {
	323	devc->ctlbase2 = rate_map[i].slowmode;
4b719338	324	ret = mso_clkrate_out(devc->serial, rate_map[i].val);
df92e5cf	325	if (ret == SR_OK)
	326	devc->cur_rate = rate;
	327	return ret;
	328	}
	329	}
4db2aaff	330
00b44ccb	331	if (ret != SR_OK)
4db2aaff	332	sr_err("Unsupported rate.");
4db2aaff	333
df92e5cf	334	return ret;
	335	}
	336
00b44ccb	337	SR_PRIV int mso_check_trigger(struct sr_serial_dev_inst serial, uint8_t info)
df92e5cf	338	{
	339	uint16_t ops[] = { mso_trans(REG_TRIGGER, 0) };
	340	int ret;
	341
	342	sr_dbg("Requesting trigger state.");
	343	ret = mso_send_control_message(serial, ARRAY_AND_SIZE(ops));
	344	if (info == NULL \|\| ret != SR_OK)
	345	return ret;
	346
00b44ccb UH	347	uint8_t buf = 0;
00b44ccb UH	348	if (serial_read(serial, &buf, 1) != 1) /* FIXME: Need timeout */
df92e5cf	349	ret = SR_ERR;
	350	*info = buf;
	351
	352	sr_dbg("Trigger state is: 0x%x.", *info);
	353	return ret;
	354	}
	355
	356	SR_PRIV int mso_receive_data(int fd, int revents, void *cb_data)
	357	{
df92e5cf	358	struct sr_datafeed_packet packet;
	359	struct sr_datafeed_logic logic;
	360	struct sr_dev_inst *sdi;
df92e5cf	361	GSList *l;
4db2aaff	362	int i;
df92e5cf	363
4db2aaff	364	struct drv_context *drvc = di->priv;
df92e5cf	365
df92e5cf	366	/* Find this device's devc struct by its fd. */
4db2aaff	367	struct dev_context *devc = NULL;
df92e5cf	368	for (l = drvc->instances; l; l = l->next) {
	369	sdi = l->data;
	370	devc = sdi->priv;
	371	if (devc->serial->fd == fd)
	372	break;
	373	devc = NULL;
	374	}
	375	if (!devc)
	376	/* Shouldn't happen. */
	377	return TRUE;
	378
	379	(void)revents;
	380
	381	uint8_t in[1024];
	382	size_t s = serial_read(devc->serial, in, sizeof(in));
5a24e89c	383
df92e5cf	384	if (s <= 0)
df92e5cf	385	return FALSE;
00b44ccb UH	386
	387	/* Check if we triggered, then send a command that we are ready
	388	* to read the data */
	389	if (devc->trigger_state != MSO_TRIGGER_DATAREADY) {
	390	devc->trigger_state = in[0];
	391	if (devc->trigger_state == MSO_TRIGGER_DATAREADY) {
	392	mso_read_buffer(sdi);
	393	devc->buffer_n = 0;
	394	} else {
	395	mso_check_trigger(devc->serial, NULL);
	396	}
	397	return TRUE;
	398	}
df92e5cf	399
	400	/* the hardware always dumps 1024 samples, 24bits each */
	401	if (devc->buffer_n < 3072) {
	402	memcpy(devc->buffer + devc->buffer_n, in, s);
	403	devc->buffer_n += s;
	404	}
	405	if (devc->buffer_n < 3072)
5a24e89c	406	return TRUE;
df92e5cf	407
	408	/* do the conversion */
	409	uint8_t logic_out[1024];
	410	double analog_out[1024];
	411	for (i = 0; i < 1024; i++) {
	412	/* FIXME: Need to do conversion to mV */
	413	analog_out[i] = (devc->buffer[i * 3] & 0x3f) \|
00b44ccb	414	((devc->buffer[i * 3 + 1] & 0xf) << 6);
df92e5cf	415	logic_out[i] = ((devc->buffer[i * 3 + 1] & 0x30) >> 4) \|
00b44ccb	416	((devc->buffer[i * 3 + 2] & 0x3f) << 2);
df92e5cf	417	}
	418
	419	packet.type = SR_DF_LOGIC;
	420	packet.payload = &logic;
	421	logic.length = 1024;
	422	logic.unitsize = 1;
	423	logic.data = logic_out;
	424	sr_session_send(cb_data, &packet);
	425
00b44ccb	426	devc->num_samples += 1024;
eb913174	427
00b44ccb UH	428	if (devc->limit_samples && devc->num_samples >= devc->limit_samples) {
	429	sr_info("Requested number of samples reached.");
	430	sdi->driver->dev_acquisition_stop(sdi, cb_data);
	431	}
	432
	433	return TRUE;
df92e5cf	434	}
5a24e89c	435
	436	SR_PRIV int mso_configure_probes(const struct sr_dev_inst *sdi)
	437	{
5a24e89c	438	struct dev_context *devc;
	439	struct sr_probe *probe;
	440	GSList *l;
5a24e89c	441	char *tc;
5a24e89c	442
5a24e89c	443	devc = sdi->priv;
5a24e89c	444
00b44ccb UH	445	devc->la_trigger_mask = 0xFF; //the mask for the LA_TRIGGER (bits set to 0 matter, those set to 1 are ignored).
	446	devc->la_trigger = 0x00; //The value of the LA byte that generates a trigger event (in that mode).
	447	devc->dso_trigger_voltage = 3;
	448	devc->dso_probe_attn = 1;
	449	devc->trigger_outsrc = 0;
	450	devc->trigger_chan = 3; //LA combination trigger
	451	devc->use_trigger = FALSE;
087a9161	452
5a24e89c	453	for (l = sdi->probes; l; l = l->next) {
	454	probe = (struct sr_probe *)l->data;
	455	if (probe->enabled == FALSE)
	456	continue;
	457
087a9161	458	int probe_bit = 1 << (probe->index);
5a24e89c	459	if (!(probe->trigger))
	460	continue;
	461
00b44ccb	462	devc->use_trigger = TRUE;
5a24e89c	463	//Configure trigger mask and value.
5a24e89c	464	for (tc = probe->trigger; *tc; tc++) {
087a9161	465	devc->la_trigger_mask &= ~probe_bit;
00b44ccb UH	466	if (*tc == '1')
	467	devc->la_trigger \|= probe_bit;
	468	}
	469	}
5a24e89c	470
5a24e89c	471	return SR_OK;
5a24e89c	472	}