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df92e5cf | 1 | /* |
2 | * This file is part of the sigrok project. | |
3 | * | |
f48cef78 UH |
4 | * Copyright (C) 2011 Daniel Ribeiro <drwyrm@gmail.com> |
5 | * Copyright (C) 2012 Renato Caldas <rmsc@fe.up.pt> | |
6 | * Copyright (C) 2013 Lior Elazary <lelazary@yahoo.com> | |
df92e5cf | 7 | * |
8 | * This program is free software: you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation, either version 3 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
20 | */ | |
21 | ||
22 | #include "protocol.h" | |
4db2aaff | 23 | #include <arpa/inet.h> |
df92e5cf | 24 | |
25 | extern SR_PRIV struct sr_dev_driver link_mso19_driver_info; | |
26 | static struct sr_dev_driver *di = &link_mso19_driver_info; | |
27 | ||
4db2aaff | 28 | SR_PRIV int mso_send_control_message(struct sr_serial_dev_inst *serial, |
00b44ccb | 29 | uint16_t payload[], int n) |
4db2aaff | 30 | { |
31 | int i, w, ret, s = n * 2 + sizeof(mso_head) + sizeof(mso_foot); | |
32 | char *p, *buf; | |
33 | ||
34 | ret = SR_ERR; | |
35 | ||
36 | if (serial->fd < 0) | |
37 | goto ret; | |
38 | ||
39 | if (!(buf = g_try_malloc(s))) { | |
40 | sr_err("Failed to malloc message buffer."); | |
41 | ret = SR_ERR_MALLOC; | |
42 | goto ret; | |
43 | } | |
44 | ||
45 | p = buf; | |
46 | memcpy(p, mso_head, sizeof(mso_head)); | |
47 | p += sizeof(mso_head); | |
48 | ||
49 | for (i = 0; i < n; i++) { | |
50 | *(uint16_t *) p = htons(payload[i]); | |
51 | p += 2; | |
52 | } | |
53 | memcpy(p, mso_foot, sizeof(mso_foot)); | |
54 | ||
55 | w = 0; | |
56 | while (w < s) { | |
57 | ret = serial_write(serial, buf + w, s - w); | |
58 | if (ret < 0) { | |
59 | ret = SR_ERR; | |
60 | goto free; | |
61 | } | |
62 | w += ret; | |
63 | } | |
64 | ret = SR_OK; | |
65 | free: | |
66 | g_free(buf); | |
67 | ret: | |
68 | return ret; | |
69 | } | |
70 | ||
4b719338 | 71 | SR_PRIV int mso_configure_trigger(struct sr_dev_inst *sdi) |
72 | { | |
73 | struct dev_context *devc = sdi->priv; | |
087a9161 | 74 | uint16_t threshold_value = mso_calc_raw_from_mv(devc); |
4b719338 | 75 | |
00b44ccb UH |
76 | threshold_value = 0x153C; |
77 | uint8_t trigger_config = 0; | |
4b719338 | 78 | |
00b44ccb UH |
79 | if (devc->trigger_slope) |
80 | trigger_config |= 0x04; //Trigger on falling edge | |
4b719338 | 81 | |
82 | switch (devc->trigger_outsrc) { | |
83 | case 1: | |
00b44ccb | 84 | trigger_config |= 0x00; //Trigger pulse output |
4b719338 | 85 | break; |
86 | case 2: | |
00b44ccb | 87 | trigger_config |= 0x08; //PWM DAC from the pattern generator buffer |
4b719338 | 88 | break; |
89 | case 3: | |
00b44ccb | 90 | trigger_config |= 0x18; //White noise |
4b719338 | 91 | break; |
4b719338 | 92 | } |
93 | ||
087a9161 | 94 | switch (devc->trigger_chan) { |
00b44ccb UH |
95 | case 0: |
96 | trigger_config |= 0x00; //DSO level trigger //b00000000 | |
97 | break; | |
98 | case 1: | |
99 | trigger_config |= 0x20; //DSO level trigger & width < trigger_width | |
100 | break; | |
101 | case 2: | |
102 | trigger_config |= 0x40; //DSO level trigger & width >= trigger_width | |
103 | break; | |
104 | case 3: | |
105 | trigger_config |= 0x60; //LA combination trigger | |
106 | break; | |
107 | } | |
108 | ||
109 | //Last bit of trigger config reg 4 needs to be 1 for trigger enable, | |
110 | //otherwise the trigger is not enabled | |
111 | if (devc->use_trigger) | |
112 | trigger_config |= 0x80; | |
087a9161 | 113 | |
114 | uint16_t ops[18]; | |
115 | ops[0] = mso_trans(3, threshold_value & 0xff); | |
00b44ccb | 116 | //The trigger_config also holds the 2 MSB bits from the threshold value |
087a9161 | 117 | ops[1] = mso_trans(4, trigger_config | (threshold_value >> 8) & 0x03); |
118 | ops[2] = mso_trans(5, devc->la_trigger); | |
119 | ops[3] = mso_trans(6, devc->la_trigger_mask); | |
120 | ops[4] = mso_trans(7, devc->trigger_holdoff[0]); | |
121 | ops[5] = mso_trans(8, devc->trigger_holdoff[1]); | |
122 | ||
123 | ops[6] = mso_trans(11, | |
00b44ccb UH |
124 | devc->dso_trigger_width / |
125 | SR_HZ_TO_NS(devc->cur_rate)); | |
4b719338 | 126 | |
127 | /* Select the SPI/I2C trigger config bank */ | |
087a9161 | 128 | ops[7] = mso_trans(REG_CTL2, (devc->ctlbase2 | BITS_CTL2_BANK(2))); |
4b719338 | 129 | /* Configure the SPI/I2C protocol trigger */ |
087a9161 | 130 | ops[8] = mso_trans(REG_PT_WORD(0), devc->protocol_trigger.word[0]); |
131 | ops[9] = mso_trans(REG_PT_WORD(1), devc->protocol_trigger.word[1]); | |
132 | ops[10] = mso_trans(REG_PT_WORD(2), devc->protocol_trigger.word[2]); | |
133 | ops[11] = mso_trans(REG_PT_WORD(3), devc->protocol_trigger.word[3]); | |
134 | ops[12] = mso_trans(REG_PT_MASK(0), devc->protocol_trigger.mask[0]); | |
135 | ops[13] = mso_trans(REG_PT_MASK(1), devc->protocol_trigger.mask[1]); | |
136 | ops[14] = mso_trans(REG_PT_MASK(2), devc->protocol_trigger.mask[2]); | |
137 | ops[15] = mso_trans(REG_PT_MASK(3), devc->protocol_trigger.mask[3]); | |
138 | ops[16] = mso_trans(REG_PT_SPIMODE, devc->protocol_trigger.spimode); | |
4b719338 | 139 | /* Select the default config bank */ |
087a9161 | 140 | ops[17] = mso_trans(REG_CTL2, devc->ctlbase2); |
4b719338 | 141 | |
4db2aaff | 142 | return mso_send_control_message(devc->serial, ARRAY_AND_SIZE(ops)); |
4b719338 | 143 | } |
144 | ||
145 | SR_PRIV int mso_configure_threshold_level(struct sr_dev_inst *sdi) | |
146 | { | |
147 | struct dev_context *devc = sdi->priv; | |
148 | ||
149 | return mso_dac_out(sdi, la_threshold_map[devc->la_threshold]); | |
150 | } | |
151 | ||
152 | SR_PRIV int mso_read_buffer(struct sr_dev_inst *sdi) | |
153 | { | |
154 | uint16_t ops[] = { mso_trans(REG_BUFFER, 0) }; | |
155 | struct dev_context *devc = sdi->priv; | |
156 | ||
157 | sr_dbg("Requesting buffer dump."); | |
158 | return mso_send_control_message(devc->serial, ARRAY_AND_SIZE(ops)); | |
159 | } | |
160 | ||
161 | SR_PRIV int mso_arm(struct sr_dev_inst *sdi) | |
162 | { | |
163 | struct dev_context *devc = sdi->priv; | |
164 | uint16_t ops[] = { | |
165 | mso_trans(REG_CTL1, devc->ctlbase1 | BIT_CTL1_RESETFSM), | |
166 | mso_trans(REG_CTL1, devc->ctlbase1 | BIT_CTL1_ARM), | |
167 | mso_trans(REG_CTL1, devc->ctlbase1), | |
168 | }; | |
169 | ||
170 | sr_dbg("Requesting trigger arm."); | |
171 | return mso_send_control_message(devc->serial, ARRAY_AND_SIZE(ops)); | |
172 | } | |
173 | ||
174 | SR_PRIV int mso_force_capture(struct sr_dev_inst *sdi) | |
175 | { | |
176 | struct dev_context *devc = sdi->priv; | |
177 | uint16_t ops[] = { | |
178 | mso_trans(REG_CTL1, devc->ctlbase1 | 8), | |
179 | mso_trans(REG_CTL1, devc->ctlbase1), | |
180 | }; | |
181 | ||
182 | sr_dbg("Requesting forced capture."); | |
183 | return mso_send_control_message(devc->serial, ARRAY_AND_SIZE(ops)); | |
184 | } | |
185 | ||
186 | SR_PRIV int mso_dac_out(struct sr_dev_inst *sdi, uint16_t val) | |
187 | { | |
188 | struct dev_context *devc = sdi->priv; | |
189 | uint16_t ops[] = { | |
190 | mso_trans(REG_DAC1, (val >> 8) & 0xff), | |
191 | mso_trans(REG_DAC2, val & 0xff), | |
192 | mso_trans(REG_CTL1, devc->ctlbase1 | BIT_CTL1_RESETADC), | |
193 | }; | |
194 | ||
195 | sr_dbg("Setting dac word to 0x%x.", val); | |
196 | return mso_send_control_message(devc->serial, ARRAY_AND_SIZE(ops)); | |
197 | } | |
198 | ||
00b44ccb | 199 | SR_PRIV inline uint16_t mso_calc_raw_from_mv(struct dev_context * devc) |
4b719338 | 200 | { |
201 | return (uint16_t) (0x200 - | |
00b44ccb UH |
202 | ((devc->dso_trigger_voltage / devc->dso_probe_attn) / |
203 | devc->vbit)); | |
4b719338 | 204 | } |
205 | ||
df92e5cf | 206 | SR_PRIV int mso_parse_serial(const char *iSerial, const char *iProduct, |
00b44ccb | 207 | struct dev_context *devc) |
df92e5cf | 208 | { |
209 | unsigned int u1, u2, u3, u4, u5, u6; | |
210 | ||
00b44ccb UH |
211 | iProduct = iProduct; |
212 | /* FIXME: This code is in the original app, but I think its | |
213 | * used only for the GUI */ | |
214 | /* if (strstr(iProduct, "REV_02") || strstr(iProduct, "REV_03")) | |
215 | devc->num_sample_rates = 0x16; | |
216 | else | |
217 | devc->num_sample_rates = 0x10; */ | |
df92e5cf | 218 | |
219 | /* parse iSerial */ | |
220 | if (iSerial[0] != '4' || sscanf(iSerial, "%5u%3u%3u%1u%1u%6u", | |
00b44ccb | 221 | &u1, &u2, &u3, &u4, &u5, &u6) != 6) |
df92e5cf | 222 | return SR_ERR; |
223 | devc->hwmodel = u4; | |
224 | devc->hwrev = u5; | |
df92e5cf | 225 | devc->vbit = u1 / 10000; |
226 | if (devc->vbit == 0) | |
227 | devc->vbit = 4.19195; | |
228 | devc->dac_offset = u2; | |
229 | if (devc->dac_offset == 0) | |
230 | devc->dac_offset = 0x1ff; | |
231 | devc->offset_range = u3; | |
232 | if (devc->offset_range == 0) | |
233 | devc->offset_range = 0x17d; | |
234 | ||
235 | /* | |
236 | * FIXME: There is more code on the original software to handle | |
237 | * bigger iSerial strings, but as I can't test on my device | |
238 | * I will not implement it yet | |
239 | */ | |
240 | ||
241 | return SR_OK; | |
242 | } | |
243 | ||
4db2aaff | 244 | SR_PRIV int mso_reset_adc(struct sr_dev_inst *sdi) |
df92e5cf | 245 | { |
4db2aaff | 246 | struct dev_context *devc = sdi->priv; |
247 | uint16_t ops[2]; | |
df92e5cf | 248 | |
4db2aaff | 249 | ops[0] = mso_trans(REG_CTL1, (devc->ctlbase1 | BIT_CTL1_RESETADC)); |
250 | ops[1] = mso_trans(REG_CTL1, devc->ctlbase1); | |
251 | devc->ctlbase1 |= BIT_CTL1_ADC_UNKNOWN4; | |
df92e5cf | 252 | |
4db2aaff | 253 | sr_dbg("Requesting ADC reset."); |
254 | return mso_send_control_message(devc->serial, ARRAY_AND_SIZE(ops)); | |
255 | } | |
df92e5cf | 256 | |
4db2aaff | 257 | SR_PRIV int mso_reset_fsm(struct sr_dev_inst *sdi) |
258 | { | |
259 | struct dev_context *devc = sdi->priv; | |
260 | uint16_t ops[1]; | |
df92e5cf | 261 | |
4db2aaff | 262 | devc->ctlbase1 |= BIT_CTL1_RESETFSM; |
263 | ops[0] = mso_trans(REG_CTL1, devc->ctlbase1); | |
df92e5cf | 264 | |
4db2aaff | 265 | sr_dbg("Requesting ADC reset."); |
266 | return mso_send_control_message(devc->serial, ARRAY_AND_SIZE(ops)); | |
df92e5cf | 267 | } |
268 | ||
4db2aaff | 269 | SR_PRIV int mso_toggle_led(struct sr_dev_inst *sdi, int state) |
df92e5cf | 270 | { |
271 | struct dev_context *devc = sdi->priv; | |
4db2aaff | 272 | uint16_t ops[1]; |
df92e5cf | 273 | |
4db2aaff | 274 | devc->ctlbase1 &= ~BIT_CTL1_LED; |
275 | if (state) | |
276 | devc->ctlbase1 |= BIT_CTL1_LED; | |
277 | ops[0] = mso_trans(REG_CTL1, devc->ctlbase1); | |
df92e5cf | 278 | |
4db2aaff | 279 | sr_dbg("Requesting LED toggle."); |
df92e5cf | 280 | return mso_send_control_message(devc->serial, ARRAY_AND_SIZE(ops)); |
281 | } | |
282 | ||
283 | SR_PRIV void stop_acquisition(const struct sr_dev_inst *sdi) | |
284 | { | |
285 | struct sr_datafeed_packet packet; | |
286 | struct dev_context *devc; | |
287 | ||
288 | devc = sdi->priv; | |
289 | sr_source_remove(devc->serial->fd); | |
290 | ||
291 | /* Terminate session */ | |
292 | packet.type = SR_DF_END; | |
293 | sr_session_send(sdi, &packet); | |
294 | } | |
295 | ||
296 | SR_PRIV int mso_clkrate_out(struct sr_serial_dev_inst *serial, uint16_t val) | |
297 | { | |
298 | uint16_t ops[] = { | |
299 | mso_trans(REG_CLKRATE1, (val >> 8) & 0xff), | |
300 | mso_trans(REG_CLKRATE2, val & 0xff), | |
301 | }; | |
302 | ||
303 | sr_dbg("Setting clkrate word to 0x%x.", val); | |
304 | return mso_send_control_message(serial, ARRAY_AND_SIZE(ops)); | |
305 | } | |
306 | ||
307 | SR_PRIV int mso_configure_rate(struct sr_dev_inst *sdi, uint32_t rate) | |
308 | { | |
309 | struct dev_context *devc = sdi->priv; | |
310 | unsigned int i; | |
311 | int ret = SR_ERR; | |
312 | ||
313 | for (i = 0; i < ARRAY_SIZE(rate_map); i++) { | |
314 | if (rate_map[i].rate == rate) { | |
315 | devc->ctlbase2 = rate_map[i].slowmode; | |
4b719338 | 316 | ret = mso_clkrate_out(devc->serial, rate_map[i].val); |
df92e5cf | 317 | if (ret == SR_OK) |
318 | devc->cur_rate = rate; | |
319 | return ret; | |
320 | } | |
321 | } | |
4db2aaff | 322 | |
00b44ccb | 323 | if (ret != SR_OK) |
4db2aaff | 324 | sr_err("Unsupported rate."); |
325 | ||
df92e5cf | 326 | return ret; |
327 | } | |
328 | ||
00b44ccb | 329 | SR_PRIV int mso_check_trigger(struct sr_serial_dev_inst *serial, uint8_t * info) |
df92e5cf | 330 | { |
331 | uint16_t ops[] = { mso_trans(REG_TRIGGER, 0) }; | |
332 | int ret; | |
333 | ||
334 | sr_dbg("Requesting trigger state."); | |
335 | ret = mso_send_control_message(serial, ARRAY_AND_SIZE(ops)); | |
336 | if (info == NULL || ret != SR_OK) | |
337 | return ret; | |
338 | ||
00b44ccb UH |
339 | uint8_t buf = 0; |
340 | if (serial_read(serial, &buf, 1) != 1) /* FIXME: Need timeout */ | |
df92e5cf | 341 | ret = SR_ERR; |
342 | *info = buf; | |
343 | ||
344 | sr_dbg("Trigger state is: 0x%x.", *info); | |
345 | return ret; | |
346 | } | |
347 | ||
348 | SR_PRIV int mso_receive_data(int fd, int revents, void *cb_data) | |
349 | { | |
df92e5cf | 350 | struct sr_datafeed_packet packet; |
351 | struct sr_datafeed_logic logic; | |
352 | struct sr_dev_inst *sdi; | |
df92e5cf | 353 | GSList *l; |
4db2aaff | 354 | int i; |
df92e5cf | 355 | |
4db2aaff | 356 | struct drv_context *drvc = di->priv; |
df92e5cf | 357 | |
358 | /* Find this device's devc struct by its fd. */ | |
4db2aaff | 359 | struct dev_context *devc = NULL; |
df92e5cf | 360 | for (l = drvc->instances; l; l = l->next) { |
361 | sdi = l->data; | |
362 | devc = sdi->priv; | |
363 | if (devc->serial->fd == fd) | |
364 | break; | |
365 | devc = NULL; | |
366 | } | |
367 | if (!devc) | |
368 | /* Shouldn't happen. */ | |
369 | return TRUE; | |
370 | ||
371 | (void)revents; | |
372 | ||
373 | uint8_t in[1024]; | |
374 | size_t s = serial_read(devc->serial, in, sizeof(in)); | |
5a24e89c | 375 | |
df92e5cf | 376 | if (s <= 0) |
377 | return FALSE; | |
00b44ccb UH |
378 | |
379 | /* Check if we triggered, then send a command that we are ready | |
380 | * to read the data */ | |
381 | if (devc->trigger_state != MSO_TRIGGER_DATAREADY) { | |
382 | devc->trigger_state = in[0]; | |
383 | if (devc->trigger_state == MSO_TRIGGER_DATAREADY) { | |
384 | mso_read_buffer(sdi); | |
385 | devc->buffer_n = 0; | |
386 | } else { | |
387 | mso_check_trigger(devc->serial, NULL); | |
388 | } | |
389 | return TRUE; | |
390 | } | |
df92e5cf | 391 | |
392 | /* the hardware always dumps 1024 samples, 24bits each */ | |
393 | if (devc->buffer_n < 3072) { | |
394 | memcpy(devc->buffer + devc->buffer_n, in, s); | |
395 | devc->buffer_n += s; | |
396 | } | |
397 | if (devc->buffer_n < 3072) | |
5a24e89c | 398 | return TRUE; |
df92e5cf | 399 | |
400 | /* do the conversion */ | |
401 | uint8_t logic_out[1024]; | |
402 | double analog_out[1024]; | |
403 | for (i = 0; i < 1024; i++) { | |
404 | /* FIXME: Need to do conversion to mV */ | |
405 | analog_out[i] = (devc->buffer[i * 3] & 0x3f) | | |
00b44ccb | 406 | ((devc->buffer[i * 3 + 1] & 0xf) << 6); |
df92e5cf | 407 | logic_out[i] = ((devc->buffer[i * 3 + 1] & 0x30) >> 4) | |
00b44ccb | 408 | ((devc->buffer[i * 3 + 2] & 0x3f) << 2); |
df92e5cf | 409 | } |
410 | ||
411 | packet.type = SR_DF_LOGIC; | |
412 | packet.payload = &logic; | |
413 | logic.length = 1024; | |
414 | logic.unitsize = 1; | |
415 | logic.data = logic_out; | |
416 | sr_session_send(cb_data, &packet); | |
417 | ||
00b44ccb | 418 | devc->num_samples += 1024; |
eb913174 | 419 | |
df92e5cf | 420 | // Dont bother fixing this yet, keep it "old style" |
421 | /* | |
00b44ccb UH |
422 | packet.type = SR_DF_ANALOG; |
423 | packet.length = 1024; | |
424 | packet.unitsize = sizeof(double); | |
425 | packet.payload = analog_out; | |
426 | sr_session_send(ctx->session_dev_id, &packet); | |
427 | */ | |
428 | ||
429 | if (devc->limit_samples && devc->num_samples >= devc->limit_samples) { | |
430 | sr_info("Requested number of samples reached."); | |
431 | sdi->driver->dev_acquisition_stop(sdi, cb_data); | |
432 | } | |
433 | ||
434 | return TRUE; | |
df92e5cf | 435 | } |
5a24e89c | 436 | |
437 | SR_PRIV int mso_configure_probes(const struct sr_dev_inst *sdi) | |
438 | { | |
5a24e89c | 439 | struct dev_context *devc; |
440 | struct sr_probe *probe; | |
441 | GSList *l; | |
442 | int probe_bit, stage, i; | |
443 | char *tc; | |
444 | ||
5a24e89c | 445 | devc = sdi->priv; |
5a24e89c | 446 | |
00b44ccb UH |
447 | devc->la_trigger_mask = 0xFF; //the mask for the LA_TRIGGER (bits set to 0 matter, those set to 1 are ignored). |
448 | devc->la_trigger = 0x00; //The value of the LA byte that generates a trigger event (in that mode). | |
449 | devc->dso_trigger_voltage = 3; | |
450 | devc->dso_probe_attn = 1; | |
451 | devc->trigger_outsrc = 0; | |
452 | devc->trigger_chan = 3; //LA combination trigger | |
453 | devc->use_trigger = FALSE; | |
087a9161 | 454 | |
5a24e89c | 455 | for (l = sdi->probes; l; l = l->next) { |
456 | probe = (struct sr_probe *)l->data; | |
457 | if (probe->enabled == FALSE) | |
458 | continue; | |
459 | ||
087a9161 | 460 | int probe_bit = 1 << (probe->index); |
5a24e89c | 461 | if (!(probe->trigger)) |
462 | continue; | |
463 | ||
00b44ccb | 464 | devc->use_trigger = TRUE; |
5a24e89c | 465 | //Configure trigger mask and value. |
5a24e89c | 466 | for (tc = probe->trigger; *tc; tc++) { |
087a9161 | 467 | devc->la_trigger_mask &= ~probe_bit; |
00b44ccb UH |
468 | if (*tc == '1') |
469 | devc->la_trigger |= probe_bit; | |
470 | } | |
471 | } | |
5a24e89c | 472 | |
473 | return SR_OK; | |
5a24e89c | 474 | } |